9 u_double condition
[2] = { {.bits
= { 0x3FF0000000000001ULL
, 0x3FF0000000000000ULL
,
10 0x00000000ffffffffULL
, 0x1234563388994400ULL
,
11 0x0000004412369801ULL
, 0x111111eeeeeee220ULL
,
12 0xAAAAABBBBBCCCDDDULL
, 0xaa55cc2266dd2200ULL
}}};
13 const double a
[] = { 0.5, 0.0, 0.8, 0.10, 0.128, 5.0, 8.15, 9.456 };
17 #define TEST(instruction, LID, FD, FS, FDval, condition) \
19 unsigned int result; \
21 ".set noreorder" "\n\t" \
22 "l.d $"#FD", %1" "\n\t" \
23 "l.d $"#FS", %2" "\n\t" \
24 "move $v0, $0" "\n\t" \
25 instruction " $"#FD", end21"instruction#LID "\n\t" \
26 "addiu $v0, 3" "\n\t" \
27 "addiu $v0, 11" "\n\t" \
28 "end12"instruction#LID":" "\n\t" \
29 "bal r_end"instruction#LID "\n\t" \
30 "addiu $v0, 19" "\n\t" \
31 "addiu $v0, 20" "\n\t" \
32 "end21"instruction#LID":" "\n\t" \
33 instruction" $"#FS", end12"instruction#LID "\n\t" \
34 "addiu $v0, 7" "\n\t" \
35 "addiu $v0, 1" "\n\t" \
36 "r_end"instruction#LID ":" "\n\t" \
37 "move %0, $v0" "\n\t" \
39 : "m" (FDval), "m" (condition), "r" (LID) \
40 : #FD, #FS, "$v0", "memory" \
42 printf(instruction":: result: %x\n", result); \
47 #if (__mips_isa_rev>=6)
49 TEST("bc1eqz", 0, f0
, f1
, a
[0], condition
[0]);
50 TEST("bc1eqz", 1, f1
, f2
, a
[0], condition
[1]);
51 TEST("bc1eqz", 3, f2
, f3
, a
[1], condition
[1]);
52 TEST("bc1eqz", 4, f3
, f4
, a
[1], condition
[2]);
53 TEST("bc1eqz", 6, f4
, f5
, a
[2], condition
[2]);
54 TEST("bc1eqz", 7, f5
, f6
, a
[2], condition
[3]);
55 TEST("bc1eqz", 8, f6
, f7
, a
[3], condition
[3]);
56 TEST("bc1eqz", 9, f7
, f8
, a
[3], condition
[4]);
57 TEST("bc1eqz", 10, f8
, f9
, a
[4], condition
[4]);
58 TEST("bc1eqz", 11, f9
, f10
, a
[4], condition
[5]);
59 TEST("bc1eqz", 12, f10
, f11
, a
[5], condition
[5]);
60 TEST("bc1eqz", 13, f11
, f12
, a
[6], condition
[5]);
61 TEST("bc1eqz", 14, f12
, f13
, a
[6], condition
[6]);
62 TEST("bc1eqz", 15, f13
, f14
, a
[6], condition
[7]);
63 TEST("bc1eqz", 16, f14
, f15
, a
[7], condition
[7]);
64 TEST("bc1eqz", 17, f15
, f16
, a
[7], condition
[8]);
65 TEST("bc1eqz", 18, f16
, f17
, a
[8], condition
[8]);
68 TEST("bc1nez", 0, f0
, f1
, a
[0], condition
[0]);
69 TEST("bc1nez", 1, f1
, f2
, a
[0], condition
[1]);
70 TEST("bc1nez", 3, f2
, f3
, a
[1], condition
[1]);
71 TEST("bc1nez", 4, f3
, f4
, a
[1], condition
[2]);
72 TEST("bc1nez", 6, f4
, f5
, a
[2], condition
[2]);
73 TEST("bc1nez", 7, f5
, f6
, a
[2], condition
[3]);
74 TEST("bc1nez", 8, f6
, f7
, a
[3], condition
[3]);
75 TEST("bc1nez", 9, f7
, f8
, a
[3], condition
[4]);
76 TEST("bc1nez", 10, f8
, f9
, a
[4], condition
[4]);
77 TEST("bc1nez", 11, f9
, f10
, a
[4], condition
[5]);
78 TEST("bc1nez", 12, f10
, f11
, a
[5], condition
[5]);
79 TEST("bc1nez", 13, f11
, f12
, a
[6], condition
[5]);
80 TEST("bc1nez", 14, f12
, f13
, a
[6], condition
[6]);
81 TEST("bc1nez", 15, f13
, f14
, a
[6], condition
[7]);
82 TEST("bc1nez", 16, f14
, f15
, a
[7], condition
[7]);
83 TEST("bc1nez", 17, f15
, f16
, a
[7], condition
[8]);
84 TEST("bc1nez", 18, f16
, f17
, a
[8], condition
[8]);