1 #if defined(__mips_hard_float)
10 printf("This test is testing mips32r2 instructions in fpu64 mode.\n");
12 * Bits 18 (NAN2008) and 19 (ABS2008) are preset by hardware and may differ
13 * between platforms. Hence a macro to clear them before printing FCSR
16 #define FCSR_NAN2008 1 << 18
17 #define FCSR_ABS2008 1 << 19
18 #define FLAGS_RM_MASK 0xFFFFFFFF & ~(FCSR_ABS2008 | FCSR_NAN2008)
19 #define CLEAR_PRESETBITS_FCSR(fcsr) (fcsr & FLAGS_RM_MASK)
22 CVTLS
, CVTLD
, ROUNDLS
, ROUNDLD
,
23 TRUNCLS
, TRUNCLD
, FLOORLS
, FLOORLD
,
27 const char *flt_round_op_names
[] = {
28 "cvt.l.s", "cvt.l.d", "round.l.s", "round.l.d",
29 "trunc.l.s", "trunc.l.d", "floor.l.s", "floor.l.d"
30 "ceil.l.s", "ceil.l.d"
34 TO_NEAREST
=0, TO_ZERO
, TO_PLUS_INFINITY
, TO_MINUS_INFINITY
} round_mode_t
;
35 char *round_mode_name
[] = { "near", "zero", "+inf", "-inf" };
37 const float fs_f
[] = {
39 1384.5, -7.25, 1000000000, -5786.25,
40 1752, 0.015625, 0.03125, -248562.75,
41 -45786.5, 456, 34.03125, 45786.75,
42 1752065, 107, -45667.25, -7,
43 -347856.5, 356047, -1.25, 23.0625
46 const double fs_d
[] = {
48 1384.5, -7.25, 1000000000, -5786.25,
49 1752, 0.015625, 0.03125, -24856226678933.75,
50 -45786.5, 456, 34.03125, 45786.75,
51 1752065, 107, -45667.25, -7,
52 -347856.5, 356047, -1.25, 23.0625
56 __asm__ __volatile__( \
58 "sdc1 $f0, 0(%1)" "\n\t" \
59 "cfc1 %0, $31" "\n\t" \
61 : "r"(&fd_l), "f"(fs_f[i]) \
66 __asm__ __volatile__( \
68 "sdc1 $f0, 0(%1)" "\n\t" \
69 "cfc1 %0, $31" "\n\t" \
71 : "r"(&fd_l), "f"(fs_d[i]) \
76 __asm__ __volatile__( \
77 "cvt.l.s $f0, $f0" "\n\t" \
83 #if (__mips==32) && (__mips_isa_rev>=2) && \
84 ((__mips_fpr==64) || (__mips_fpr==xx))
85 void set_rounding_mode(round_mode_t mode
)
89 __asm__
volatile("ctc1 $zero, $31" "\n\t");
92 __asm__
volatile("li $t0, 0x1" "\n\t"
93 "ctc1 $t0, $31" "\n\t");
95 case TO_PLUS_INFINITY
:
96 __asm__
volatile("li $t0, 0x2" "\n\t"
97 "ctc1 $t0, $31" "\n\t");
99 case TO_MINUS_INFINITY
:
100 __asm__
volatile("li $t0, 0x3" "\n\t"
101 "ctc1 $t0, $31" "\n\t");
112 static void handler(int sig
)
118 int FCSRRoundingMode(flt_round_op_t op
)
124 for (rm
= TO_NEAREST
; rm
<= TO_MINUS_INFINITY
; rm
++) {
125 printf("roundig mode: %s\n", round_mode_name
[rm
]);
126 for (i
= 0; i
< MAX_ARR
; i
++) {
127 set_rounding_mode(rm
);
131 printf("%s %lld %f\n",
132 flt_round_op_names
[op
], fd_l
, fs_f
[i
]);
133 printf("fcsr: 0x%x\n", CLEAR_PRESETBITS_FCSR(fcsr
));
137 printf("%s %lld %lf\n",
138 flt_round_op_names
[op
], fd_l
, fs_d
[i
]);
139 printf("fcsr: 0x%x\n", CLEAR_PRESETBITS_FCSR(fcsr
));
143 printf("%s %lld %f\n",
144 flt_round_op_names
[op
], fd_l
, fs_f
[i
]);
145 printf("fcsr: 0x%x\n", CLEAR_PRESETBITS_FCSR(fcsr
));
149 printf("%s %lld %lf\n",
150 flt_round_op_names
[op
], fd_l
, fs_d
[i
]);
151 printf("fcsr: 0x%x\n", CLEAR_PRESETBITS_FCSR(fcsr
));
155 printf("%s %lld %f\n",
156 flt_round_op_names
[op
], fd_l
, fs_f
[i
]);
157 printf("fcsr: 0x%x\n", CLEAR_PRESETBITS_FCSR(fcsr
));
161 printf("%s %lld %lf\n",
162 flt_round_op_names
[op
], fd_l
, fs_d
[i
]);
163 printf("fcsr: 0x%x\n", CLEAR_PRESETBITS_FCSR(fcsr
));
167 printf("%s %lld %f\n",
168 flt_round_op_names
[op
], fd_l
, fs_f
[i
]);
169 printf("fcsr: 0x%x\n", CLEAR_PRESETBITS_FCSR(fcsr
));
173 printf("%s %lld %lf\n",
174 flt_round_op_names
[op
], fd_l
, fs_d
[i
]);
175 printf("fcsr: 0x%x\n", CLEAR_PRESETBITS_FCSR(fcsr
));
179 printf("%s %lld %f\n",
180 flt_round_op_names
[op
], fd_l
, fs_f
[i
]);
181 printf("fcsr: 0x%x\n", CLEAR_PRESETBITS_FCSR(fcsr
));
185 printf("%s %lld %lf\n",
186 flt_round_op_names
[op
], fd_l
, fs_d
[i
]);
187 printf("fcsr: 0x%x\n", CLEAR_PRESETBITS_FCSR(fcsr
));
202 #if (__mips==32) && (__mips_isa_rev>=2) && \
203 ((__mips_fpr==64) || (__mips_fpr==xx))
205 signal(SIGILL
, handler
);
206 /* Test fpu64 mode. */
208 printf("-------------------------- %s --------------------------\n",
209 "test FPU Conversion Operations Using the FCSR Rounding Mode");
210 for (op
= CVTLS
; op
<= CEILLD
; op
++)
211 FCSRRoundingMode(op
);