none/tests/mips64/arithmetic_instruction.c

   1 #include <stdio.h>
   2 #include "const.h"
   3 #include "macro_int.h"
   4
   5 #if (__mips_isa_rev < 6)
   6 typedef enum {
   7    ADD=0,  ADDI,   ADDIU,  ADDU,
   8    CLO,    CLZ,    DADD,   DADDI,
   9    DADDIU, DADDU,  DCLO,   DCLZ,
  10    DDIV,   DDIVU,  DIV,    DIVU,
  11    DMULT,  DMULTU, DSUB,   DSUBU,
  12    MADD,   MADDU,  MSUB,   MSUBU,
  13    MUL,    MULT,   MULTU,  MOVN,
  14    MOVZ,   SEB,    SEH,    SLT,
  15    SLTI,   SLTIU,  SLTU,   SUB,
  16    SUBU
  17 } arithmetic_op;
  18 #else
  19 typedef enum {
  20    ADD=0,  ADDIU,  ADDU,
  21    CLO,    CLZ,    DCLO,   DCLZ,
  22    DADD,   DADDIU, DADDU,
  23    DSUB,   DSUBU,  SUB,    SUBU,
  24    SEB,    SEH,
  25    SLT,    SLTI,   SLTIU,  SLTU
  26 } arithmetic_op;
  27
  28 #endif
  29
  30 int main()
  31 {
  32    arithmetic_op op;
  33    int i;
  34    init_reg_val2();
  35
  36    for (op = ADD; op <= SUBU; op++) {
  37       for (i = 0; i < N; i++) {
  38          switch(op) {
  39             case ADD:
  40                /* If either GPR rt or GPR rs does not contain sign-extended
  41                   32-bit values (bits 63..31 equal), then the result of the
  42                   operation is UNPREDICTABLE. */
  43                TEST1("add $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
  44                                           t0, t1, t2);
  45                break;
  46
  47 #if (__mips_isa_rev < 6)
  48             case ADDI:
  49                /* If GPR rs does not contain a sign-extended 32-bit
  50                   value (bits 63..31 equal), then the result of the operation
  51                   is UNPREDICTABLE. */
  52                TEST2("addi $t0, $t1, 0xff",   reg_val1[i], 0xff,   t0, t1);
  53                TEST2("addi $t2, $t3, 0xffff", reg_val1[i], 0xffff, t2, t3);
  54                TEST2("addi $a0, $a1, 0x0",    reg_val1[i], 0x0,    a0, a1);
  55                TEST2("addi $s0, $s1, 0x23",   reg_val1[i], 0x23,   s0, s1);
  56                break;
  57 #endif
  58             case ADDIU:
  59                /* If GPR rs does not contain a sign-extended 32-bit
  60                   value (bits 63..31 equal), then the result of the operation
  61                   is UNPREDICTABLE. */
  62                TEST2("addiu $t0, $t1, 0xff",   reg_val1[i], 0xff,   t0, t1);
  63                TEST2("addiu $t2, $t3, 0xffff", reg_val1[i], 0xffff, t2, t3);
  64                TEST2("addiu $a0, $a1, 0x0",    reg_val1[i], 0x0,    a0, a1);
  65                TEST2("addiu $s0, $s1, 0x23",   reg_val1[i], 0x23,   s0, s1);
  66                break;
  67
  68             case ADDU:
  69                /* If either GPR rt or GPR rs does not contain sign-extended
  70                   32-bit values (bits 63..31 equal), then the result of the
  71                   operation is UNPREDICTABLE. */
  72                TEST1("addu $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
  73                                            t0, t1, t2);
  74                break;
  75
  76             case CLO:
  77                /* If GPR rs does not contain a sign-extended 32-bit
  78                   value (bits 63..31 equal), then the results of the operation
  79                   are UNPREDICTABLE. */
  80                TEST3("clo $t0, $t1", reg_val1[i], t0, t1);
  81                break;
  82
  83             case CLZ:
  84                /* If GPR rs does not contain a sign-extended 32-bit
  85                   value (bits 63..31 equal), then the results of the operation
  86                   are UNPREDICTABLE. */
  87                TEST3("clz $t0, $t1", reg_val1[i], t0, t1);
  88                break;
  89
  90             case DADD:
  91                /* If the addition results in 64-bit 2âs complement arithmetic
  92                   overflow, then the destination register is not modified and
  93                   an IntegerOverflow exception occurs. */
  94                TEST1("dadd $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
  95                                            t0, t1, t2);
  96                break;
  97 #if (__mips_isa_rev < 6)
  98             case DADDI:
  99                /* If the addition results in 64-bit 2âs complement arithmetic
 100                   overflow, then the destination register is not modified and
 101                   an Integer Overflow exception occurs. */
 102                TEST2("daddi $t0, $t1, 0xff",   reg_val1[i], 0xff,   t0, t1);
 103                TEST2("daddi $t2, $t3, 0xffff", reg_val1[i], 0xffff, t2, t3);
 104                TEST2("daddi $a0, $a1, 0x0",    reg_val1[i], 0x0,    a0, a1);
 105                TEST2("daddi $s0, $s1, 0x23",   reg_val1[i], 0x23,   s0, s1);
 106                TEST2("daddi $t0, $t1, 0xff",   reg_val2[i], 0xff,   t0, t1);
 107                TEST2("daddi $t2, $t3, 0xffff", reg_val2[i], 0xffff, t2, t3);
 108                TEST2("daddi $a0, $a1, 0x0",    reg_val2[i], 0x0,    a0, a1);
 109                TEST2("daddi $s0, $s1, 0x23",   reg_val2[i], 0x23,   s0, s1);
 110                break;
 111 #endif
 112             case DADDIU:
 113                /* No Integer Overflow exception occurs under any
 114                   circumstances. */
 115                TEST2("daddiu $t0, $t1, 0xff",   reg_val1[i], 0xff,   t0, t1);
 116                TEST2("daddiu $t2, $t3, 0xffff", reg_val1[i], 0xffff, t2, t3);
 117                TEST2("daddiu $a0, $a1, 0x0",    reg_val1[i], 0x0,    a0, a1);
 118                TEST2("daddiu $s0, $s1, 0x23",   reg_val1[i], 0x23,   s0, s1);
 119                TEST2("daddiu $t0, $t1, 0xff",   reg_val2[i], 0xff,   t0, t1);
 120                TEST2("daddiu $t2, $t3, 0xffff", reg_val2[i], 0xffff, t2, t3);
 121                TEST2("daddiu $a0, $a1, 0x0",    reg_val2[i], 0x0,    a0, a1);
 122                TEST2("daddiu $s0, $s1, 0x23",   reg_val2[i], 0x23,   s0, s1);
 123                break;
 124
 125             case DADDU:
 126                /* No Integer Overflow exception occurs under any
 127                   circumstances. */
 128                TEST1("daddu $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
 129                                             t0, t1, t2);
 130                TEST1("daddu $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1],
 131                                             s0, s1, s2);
 132                break;
 133
 134             case DCLO:
 135                /* No arithmetic exception occurs under any circumstances. */
 136                TEST3("dclo $t0, $t1", reg_val1[i], t0, t1);
 137                TEST3("dclo $v0, $v1", reg_val2[i], v0, v1);
 138                break;
 139
 140             case DCLZ:
 141                /* No arithmetic exception occurs under any circumstances. */
 142                TEST3("dclz $t0, $t1", reg_val1[i], t0, t1);
 143                TEST3("dclz $v0, $v1", reg_val2[i], v0, v1);
 144                break;
 145 #if (__mips_isa_rev < 6)
 146             case DDIV:
 147                /* If the divisor in GPR rt is zero, the arithmetic result value
 148                   is UNPREDICTABLE. */
 149                if (reg_val1[N-i-1] != 0)
 150                   TEST4("ddiv $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1);
 151
 152                if (reg_val2[N-i-1] != 0)
 153                   TEST4("ddiv $v0, $v1", reg_val2[i], reg_val2[N-i-1], v0, v1);
 154
 155                break;
 156
 157             case DDIVU:
 158                /* If the divisor in GPR rt is zero, the arithmetic result value
 159                   is UNPREDICTABLE. */
 160                if (reg_val1[N-i-1] != 0)
 161                   TEST4("ddivu $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1);
 162
 163                if (reg_val2[N-i-1] != 0)
 164                   TEST4("ddivu $v0, $v1", reg_val2[i], reg_val2[N-i-1], v0, v1);
 165
 166                break;
 167
 168             case DIV:
 169                /* If either GPR rt or GPR rs does not contain sign-extended
 170                   32-bit values (bits 63..31 equal), then the result of the
 171                   operation is UNPREDICTABLE.
 172                   If the divisor in GPR rt is zero, the arithmetic result
 173                   value is UNPREDICTABLE. */
 174                if (reg_val1[N-i-1] != 0)
 175                   TEST4("div $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1);
 176
 177                break;
 178
 179             case DIVU:
 180                /* If either GPR rt or GPR rs does not contain sign-extended
 181                   32-bit values (bits 63..31 equal), then the result of the
 182                   operation is UNPREDICTABLE.
 183                   If the divisor in GPR rt is zero, the arithmetic result
 184                   value is UNPREDICTABLE. */
 185                if (reg_val1[N-i-1] != 0)
 186                   TEST4("divu $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1);
 187
 188                break;
 189
 190             case DMULT:
 191                /* No arithmetic exception occurs under any circumstances. */
 192                TEST4("dmult $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1);
 193                TEST4("dmult $v0, $v1", reg_val2[i], reg_val2[N-i-1], v0, v1);
 194                break;
 195
 196             case DMULTU:
 197                /* No arithmetic exception occurs under any circumstances. */
 198                TEST4("dmultu $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1);
 199                TEST4("dmultu $v0, $v1", reg_val2[i], reg_val2[N-i-1], v0, v1);
 200                break;
 201 #endif
 202             case DSUB:
 203                /* If the subtraction results in 64-bit 2âs complement
 204                   arithmetic overflow, then the destination register is not
 205                   modified and an Integer Overflow exception occurs. */
 206                TEST1("dsub $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
 207                                            t0, t1, t2);
 208                break;
 209
 210             case DSUBU:
 211                /* No Integer Overflow exception occurs under any
 212                   circumstances. */
 213                TEST1("dsubu $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
 214                                             t0, t1, t2);
 215                TEST1("dsubu $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1],
 216                                             s0, s1, s2);
 217                break;
 218 #if (__mips_isa_rev < 6)
 219             case MADD:
 220                /* If GPRs rs or rt do not contain sign-extended 32-bit
 221                   values (bits 63..31 equal), then the results of the operation
 222                   are UNPREDICTABLE. */
 223                TEST5("madd $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1);
 224                break;
 225
 226             case MADDU:
 227                /* If GPRs rs or rt do not contain sign-extended 32-bit
 228                   values (bits 63..31 equal), then the results of the operation
 229                   are UNPREDICTABLE. */
 230                TEST5("maddu $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1);
 231                break;
 232
 233             case MSUB:
 234                /* If GPR rs or rt do not contain a sign-extended 32-bit
 235                   value (bits 63..31 equal), then the results of the operation
 236                   are UNPREDICTABLE. */
 237                TEST5("msub $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1);
 238                break;
 239
 240             case MSUBU:
 241                /* If GPRs rs or rt do not contain sign-extended 32-bit
 242                   values (bits 63..31 equal), then the results of the operation
 243                   are UNPREDICTABLE.
 244                   This instruction does not provide the capability of writing
 245                   directly to a target GPR. */
 246                TEST5("msubu $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1);
 247                break;
 248
 249             case MUL:
 250                /* On 64-bit processors, if either GPR rt or GPR rs does not
 251                   contain sign-extended 32-bit values (bits 63..31 equal), then
 252                   the result of the operation is UNPREDICTABLE. */
 253                TEST1("mul $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
 254                                           t0, t1, t2);
 255                break;
 256
 257             case MULT:
 258                /* On 64-bit processors, if either GPR rt or GPR rs does not
 259                   contain sign-extended 32-bit values (bits 63..31 equal), then
 260                   the result of the operation is UNPREDICTABLE. */
 261                TEST4("mult $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1);
 262                break;
 263
 264             case MULTU:
 265                /* On 64-bit processors, if either GPR rt or GPR rs does not
 266                   contain sign-extended 32-bit values (bits 63..31 equal), then
 267                   the result of the operation is UNPREDICTABLE. */
 268                TEST4("multu $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1);
 269                break;
 270
 271             case MOVN:
 272                /* The arithmetic comparison does not cause an Integer Overflow
 273                   exception. */
 274                TEST1("movn $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
 275                                            t0, t1, t2);
 276                TEST1("movn $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1],
 277                                            s0, s1, s2);
 278                break;
 279
 280             case MOVZ:
 281                /* The arithmetic comparison does not cause an Integer Overflow
 282                   exception. */
 283                TEST1("movz $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
 284                                            t0, t1, t2);
 285                TEST1("movz $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1],
 286                                            s0, s1, s2);
 287                break;
 288 #endif
 289             case SEB:
 290 #if (__mips==64) && (__mips_isa_rev>=2)
 291                /* If GPR rt does not contain a sign-extended 32-bit
 292                   value (bits 63..31 equal), then the result of the operation
 293                   is UNPREDICTABLE. */
 294                TEST3("seb $t0, $t1", reg_val1[i], t0, t1);
 295 #endif
 296                break;
 297
 298             case SEH:
 299 #if (__mips==64) && (__mips_isa_rev>=2)
 300                /* If GPR rt does not contain a sign-extended 32-bit
 301                   value (bits 63..31 equal), then the result of the operation
 302                   is UNPREDICTABLE. */
 303                TEST3("seh $t0, $t1", reg_val1[i], t0, t1);
 304 #endif
 305                break;
 306
 307             case SLT:
 308                /* The arithmetic comparison does not cause an Integer Overflow
 309                   exception. */
 310                TEST1("slt $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
 311                                           t0, t1, t2);
 312                break;
 313
 314             case SLTI:
 315                /* The arithmetic comparison does not cause an Integer Overflow
 316                   exception. */
 317                TEST2("slti $t0, $t1, 0xff",   reg_val1[i], 0xff,   t0, t1);
 318                TEST2("slti $t2, $t3, 0xffff", reg_val1[i], 0xffff, t2, t3);
 319                TEST2("slti $a0, $a1, 0x0",    reg_val1[i], 0x0,    a0, a1);
 320                TEST2("slti $s0, $s1, 0x23",   reg_val1[i], 0x23,   s0, s1);
 321                TEST2("slti $t0, $t1, 0xff",   reg_val2[i], 0xff,   t0, t1);
 322                TEST2("slti $t2, $t3, 0xffff", reg_val2[i], 0xffff, t2, t3);
 323                TEST2("slti $a0, $a1, 0x0",    reg_val2[i], 0x0,    a0, a1);
 324                TEST2("slti $s0, $s1, 0x23",   reg_val2[i], 0x23,   s0, s1);
 325                break;
 326
 327             case SLTIU:
 328                /* The arithmetic comparison does not cause an Integer Overflow
 329                   exception. */
 330                TEST2("sltiu $t0, $t1, 0xff",   reg_val1[i], 0xff,   t0, t1);
 331                TEST2("sltiu $t2, $t3, 0xffff", reg_val1[i], 0xffff, t2, t3);
 332                TEST2("sltiu $a0, $a1, 0x0",    reg_val1[i], 0x0,    a0, a1);
 333                TEST2("sltiu $s0, $s1, 0x23",   reg_val1[i], 0x23,   s0, s1);
 334                TEST2("sltiu $t0, $t1, 0xff",   reg_val2[i], 0xff,   t0, t1);
 335                TEST2("sltiu $t2, $t3, 0xffff", reg_val2[i], 0xffff, t2, t3);
 336                TEST2("sltiu $a0, $a1, 0x0",    reg_val2[i], 0x0,    a0, a1);
 337                TEST2("sltiu $s0, $s1, 0x23",   reg_val2[i], 0x23,   s0, s1);
 338                break;
 339
 340             case SLTU:
 341                /* The arithmetic comparison does not cause an Integer Overflow
 342                   exception. */
 343                TEST1("sltu $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
 344                                            t0, t1, t2);
 345                TEST1("sltu $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1],
 346                                            s0, s1, s2);
 347                break;
 348
 349             case SUB:
 350                /* On 64-bit processors, if either GPR rt or GPR rs does not
 351                   contain sign-extended 32-bit values (bits 63..31 equal), then
 352                   the result of the operation is UNPREDICTABLE. */
 353                if (i < 8 || (i > 15 && i < 22))
 354                   TEST1("sub $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
 355                                              t0, t1, t2);
 356                break;
 357
 358             case SUBU:
 359                /* On 64-bit processors, if either GPR rt or GPR rs does not
 360                   contain sign-extended 32-bit values (bits 63..31 equal), then
 361                   the result of the operation is UNPREDICTABLE. */
 362                TEST1("subu $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
 363                                            t0, t1, t2);
 364                break;
 365             default:
 366                printf("Error!\n");
 367                break;
 368          }
 369       }
 370    }
 371    return 0;
 372 }