coregrind/m_cache.c

   1 /* -*- mode: C; c-basic-offset: 3; -*- */
   2
   3 /*--------------------------------------------------------------------*/
   4 /*--- Cache-related stuff.                               m_cache.c ---*/
   5 /*--------------------------------------------------------------------*/
   6
   7 /*
   8    This file is part of Valgrind, a dynamic binary instrumentation
   9    framework.
  10
  11    Copyright (C) 2002-2017 Nicholas Nethercote
  12       njn@valgrind.org
  13
  14    This program is free software; you can redistribute it and/or
  15    modify it under the terms of the GNU General Public License as
  16    published by the Free Software Foundation; either version 2 of the
  17    License, or (at your option) any later version.
  18
  19    This program is distributed in the hope that it will be useful, but
  20    WITHOUT ANY WARRANTY; without even the implied warranty of
  21    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  22    General Public License for more details.
  23
  24    You should have received a copy of the GNU General Public License
  25    along with this program; if not, see <http://www.gnu.org/licenses/>.
  26
  27    The GNU General Public License is contained in the file COPYING.
  28 */
  29
  30 #include "pub_core_basics.h"
  31 #include "pub_core_libcbase.h"
  32 #include "pub_core_libcassert.h"
  33 #include "pub_core_libcprint.h"
  34 #include "pub_core_mallocfree.h"
  35 #include "pub_core_machine.h"
  36 #include "pub_core_debuglog.h"
  37 #include "libvex.h"
  38
  39 #if defined(VGA_x86) || defined(VGA_amd64)
  40
  41 #include "pub_core_cpuid.h"
  42
  43 // All CPUID info taken from sandpile.org/ia32/cpuid.htm */
  44 // Probably only works for Intel and AMD chips, and probably only for some of
  45 // them.
  46
  47 static void
  48 add_cache(VexCacheInfo *ci, VexCache cache)
  49 {
  50    static UInt num_allocated = 0;
  51
  52    if (ci->num_caches == num_allocated) {
  53       num_allocated += 6;
  54       ci->caches = VG_(realloc)("m_cache", ci->caches,
  55                                 num_allocated * sizeof *ci->caches);
  56    }
  57
  58    if (ci->num_levels < cache.level) ci->num_levels = cache.level;
  59    ci->caches[ci->num_caches++] = cache;
  60 }
  61
  62 /* Convenience macros */
  63 #define add_icache(level, size, assoc, linesize) \
  64    do { \
  65       add_cache(ci, \
  66                 VEX_CACHE_INIT(INSN_CACHE, level, size, linesize, assoc)); \
  67    } while (0)
  68
  69 #define add_dcache(level, size, assoc, linesize) \
  70    do { \
  71       add_cache(ci, \
  72                 VEX_CACHE_INIT(DATA_CACHE, level, size, linesize, assoc)); \
  73    } while (0)
  74
  75 #define add_ucache(level, size, assoc, linesize) \
  76    do { \
  77       add_cache(ci, \
  78                 VEX_CACHE_INIT(UNIFIED_CACHE, level, size, linesize, assoc)); \
  79    } while (0)
  80
  81 #define add_itcache(level, size, assoc) \
  82    do { \
  83       VexCache c = \
  84           VEX_CACHE_INIT(INSN_CACHE, level, size, 0, assoc); \
  85       c.is_trace_cache = True; \
  86       add_cache(ci, c); \
  87    } while (0)
  88
  89 #define add_I1(size, assoc, linesize) add_icache(1, size, assoc, linesize)
  90 #define add_D1(size, assoc, linesize) add_dcache(1, size, assoc, linesize)
  91 #define add_U1(size, assoc, linesize) add_ucache(1, size, assoc, linesize)
  92 #define add_I2(size, assoc, linesize) add_icache(2, size, assoc, linesize)
  93 #define add_D2(size, assoc, linesize) add_dcache(2, size, assoc, linesize)
  94 #define add_U2(size, assoc, linesize) add_ucache(2, size, assoc, linesize)
  95 #define add_I3(size, assoc, linesize) add_icache(3, size, assoc, linesize)
  96 #define add_D3(size, assoc, linesize) add_dcache(3, size, assoc, linesize)
  97 #define add_U3(size, assoc, linesize) add_ucache(3, size, assoc, linesize)
  98
  99 #define add_I1T(size, assoc) \
 100    add_itcache(1, size, assoc)
 101
 102 /* Intel method is truly wretched.  We have to do an insane indexing into an
 103  * array of pre-defined configurations for various parts of the memory
 104  * hierarchy.
 105  * According to Intel Processor Identification, App Note 485.
 106  *
 107  * If a L3 cache is found, then data for it rather than the L2
 108  * is returned via *LLc.
 109  */
 110 static Int
 111 Intel_cache_info(Int level, VexCacheInfo *ci)
 112 {
 113    UInt cpuid1_eax;
 114    UInt cpuid1_ignore;
 115    Int family;
 116    Int model;
 117    UChar info[16];
 118    Int   i, j, trials;
 119
 120    if (level < 2) {
 121       VG_(debugLog)(1, "cache", "warning: CPUID level < 2 for Intel "
 122                     "processor (%d)\n", level);
 123       return -1;
 124    }
 125
 126    /* family/model needed to distinguish code reuse (currently 0x49) */
 127    VG_(cpuid)(1, 0, &cpuid1_eax, &cpuid1_ignore,
 128               &cpuid1_ignore, &cpuid1_ignore);
 129    family = (((cpuid1_eax >> 20) & 0xff) << 4) + ((cpuid1_eax >> 8) & 0xf);
 130    model =  (((cpuid1_eax >> 16) & 0xf) << 4) + ((cpuid1_eax >> 4) & 0xf);
 131
 132    VG_(cpuid)(2, 0, (UInt*)&info[0], (UInt*)&info[4],
 133                     (UInt*)&info[8], (UInt*)&info[12]);
 134    trials  = info[0] - 1;   /* AL register - bits 0..7 of %eax */
 135    info[0] = 0x0;           /* reset AL */
 136
 137    if (0 != trials) {
 138       VG_(debugLog)(1, "cache", "warning: non-zero CPUID trials for Intel "
 139                     "processor (%d)\n", trials);
 140       return -1;
 141    }
 142
 143    ci->num_levels = 0;
 144    ci->num_caches = 0;
 145    ci->icaches_maintain_coherence = True;
 146    ci->caches = NULL;
 147
 148    for (i = 0; i < 16; i++) {
 149
 150       switch (info[i]) {
 151
 152       case 0x0:       /* ignore zeros */
 153           break;
 154
 155       /* TLB info, ignore */
 156       case 0x01: case 0x02: case 0x03: case 0x04: case 0x05:
 157       case 0x0b:
 158       case 0x4f: case 0x50: case 0x51: case 0x52: case 0x55:
 159       case 0x56: case 0x57: case 0x59:
 160       case 0x5a: case 0x5b: case 0x5c: case 0x5d:
 161       case 0x76:
 162       case 0xb0: case 0xb1: case 0xb2:
 163       case 0xb3: case 0xb4: case 0xba: case 0xc0:
 164       case 0xca:
 165           break;
 166
 167       case 0x06: add_I1( 8, 4, 32); break;
 168       case 0x08: add_I1(16, 4, 32); break;
 169       case 0x09: add_I1(32, 4, 64); break;
 170       case 0x30: add_I1(32, 8, 64); break;
 171
 172       case 0x0a: add_D1( 8, 2, 32); break;
 173       case 0x0c: add_D1(16, 4, 32); break;
 174       case 0x0d: add_D1(16, 4, 64); break;
 175       case 0x0e: add_D1(24, 6, 64); break;
 176       case 0x2c: add_D1(32, 8, 64); break;
 177
 178       /* IA-64 info -- panic! */
 179       case 0x10: case 0x15: case 0x1a:
 180       case 0x88: case 0x89: case 0x8a: case 0x8d:
 181       case 0x90: case 0x96: case 0x9b:
 182          VG_(core_panic)("IA-64 cache detected?!");
 183
 184       /* L3 cache info. */
 185       case 0x22: add_U3(512,    4, 64); break;
 186       case 0x23: add_U3(1024,   8, 64); break;
 187       case 0x25: add_U3(2048,   8, 64); break;
 188       case 0x29: add_U3(4096,   8, 64); break;
 189       case 0x46: add_U3(4096,   4, 64); break;
 190       case 0x47: add_U3(8192,   8, 64); break;
 191       case 0x4a: add_U3(6144,  12, 64); break;
 192       case 0x4b: add_U3(8192,  16, 64); break;
 193       case 0x4c: add_U3(12288, 12, 64); break;
 194       case 0x4d: add_U3(16384, 16, 64); break;
 195       case 0xd0: add_U3(512,    4, 64); break;
 196       case 0xd1: add_U3(1024,   4, 64); break;
 197       case 0xd2: add_U3(2048,   4, 64); break;
 198       case 0xd6: add_U3(1024,   8, 64); break;
 199       case 0xd7: add_U3(2048,   8, 64); break;
 200       case 0xd8: add_U3(4096,   8, 64); break;
 201       case 0xdc: add_U3(1536,  12, 64); break;
 202       case 0xdd: add_U3(3072,  12, 64); break;
 203       case 0xde: add_U3(6144,  12, 64); break;
 204       case 0xe2: add_U3(2048,  16, 64); break;
 205       case 0xe3: add_U3(4096,  16, 64); break;
 206       case 0xe4: add_U3(8192,  16, 64); break;
 207       case 0xea: add_U3(12288, 24, 64); break;
 208       case 0xeb: add_U3(18432, 24, 64); break;
 209       case 0xec: add_U3(24576, 24, 64); break;
 210
 211       /* Described as "MLC" in Intel documentation */
 212       case 0x21: add_U2(256, 8, 64); break;
 213
 214       /* These are sectored, whatever that means */
 215          // FIXME: I did not find these in the Intel docs
 216       case 0x39: add_U2(128, 4, 64); break;
 217       case 0x3c: add_U2(256, 4, 64); break;
 218
 219       /* If a P6 core, this means "no L2 cache".
 220          If a P4 core, this means "no L3 cache".
 221          We don't know what core it is, so don't issue a warning.  To detect
 222          a missing L2 cache, we use 'L2_found'. */
 223       case 0x40:
 224           break;
 225
 226       case 0x41: add_U2(  128,  4, 32); break;
 227       case 0x42: add_U2(  256,  4, 32); break;
 228       case 0x43: add_U2(  512,  4, 32); break;
 229       case 0x44: add_U2( 1024,  4, 32); break;
 230       case 0x45: add_U2( 2048,  4, 32); break;
 231       case 0x48: add_U2( 3072, 12, 64); break;
 232       case 0x4e: add_U2( 6144, 24, 64); break;
 233       case 0x49:
 234          if (family == 15 && model == 6) {
 235             /* On Xeon MP (family F, model 6), this is for L3 */
 236             add_U3(4096, 16, 64);
 237          } else {
 238             add_U2(4096, 16, 64);
 239          }
 240          break;
 241
 242       /* These are sectored, whatever that means */
 243       case 0x60: add_D1(16, 8, 64);  break;      /* sectored */
 244       case 0x66: add_D1( 8, 4, 64);  break;      /* sectored */
 245       case 0x67: add_D1(16, 4, 64);  break;      /* sectored */
 246       case 0x68: add_D1(32, 4, 64);  break;      /* sectored */
 247
 248       /* HACK ALERT: Instruction trace cache -- capacity is micro-ops based.
 249        * conversion to byte size is a total guess;  treat the 12K and 16K
 250        * cases the same since the cache byte size must be a power of two for
 251        * everything to work!.  Also guessing 32 bytes for the line size...
 252        */
 253       case 0x70:    /* 12K micro-ops, 8-way */
 254          add_I1T(12, 8);
 255          break;
 256       case 0x71:    /* 16K micro-ops, 8-way */
 257          add_I1T(16, 8);
 258          break;
 259       case 0x72:    /* 32K micro-ops, 8-way */
 260          add_I1T(32, 8);
 261          break;
 262
 263       /* not sectored, whatever that might mean */
 264       case 0x78: add_U2(1024, 4,  64);  break;
 265
 266       /* These are sectored, whatever that means */
 267       case 0x79: add_U2( 128, 8,  64);  break;
 268       case 0x7a: add_U2( 256, 8,  64);  break;
 269       case 0x7b: add_U2( 512, 8,  64);  break;
 270       case 0x7c: add_U2(1024, 8,  64);  break;
 271       case 0x7d: add_U2(2048, 8,  64);  break;
 272       case 0x7e: add_U2( 256, 8, 128);  break;
 273       case 0x7f: add_U2( 512, 2,  64);  break;
 274       case 0x80: add_U2( 512, 8,  64);  break;
 275       case 0x81: add_U2( 128, 8,  32);  break;
 276       case 0x82: add_U2( 256, 8,  32);  break;
 277       case 0x83: add_U2( 512, 8,  32);  break;
 278       case 0x84: add_U2(1024, 8,  32);  break;
 279       case 0x85: add_U2(2048, 8,  32);  break;
 280       case 0x86: add_U2( 512, 4,  64);  break;
 281       case 0x87: add_U2(1024, 8,  64);  break;
 282
 283       /* Ignore prefetch information */
 284       case 0xf0: case 0xf1:
 285          break;
 286
 287       case 0xff:
 288          j = 0;
 289          VG_(cpuid)(4, j++, (UInt*)&info[0], (UInt*)&info[4],
 290                             (UInt*)&info[8], (UInt*)&info[12]);
 291
 292          while ((info[0] & 0x1f) != 0) {
 293             UInt assoc = ((*(UInt *)&info[4] >> 22) & 0x3ff) + 1;
 294             UInt parts = ((*(UInt *)&info[4] >> 12) & 0x3ff) + 1;
 295             UInt line_size = (*(UInt *)&info[4] & 0x7ff) + 1;
 296             UInt sets = *(UInt *)&info[8] + 1;
 297
 298             UInt size = assoc * parts * line_size * sets / 1024;
 299
 300             switch ((info[0] & 0xe0) >> 5)
 301             {
 302             case 1:
 303                switch (info[0] & 0x1f)
 304                {
 305                case 1: add_D1(size, assoc, line_size); break;
 306                case 2: add_I1(size, assoc, line_size); break;
 307                case 3: add_U1(size, assoc, line_size); break;
 308                default:
 309                   VG_(debugLog)(1, "cache",
 310                                 "warning: L1 cache of unknown type ignored\n");
 311                   break;
 312                }
 313                break;
 314             case 2:
 315                switch (info[0] & 0x1f)
 316                {
 317                case 1: add_D2(size, assoc, line_size); break;
 318                case 2: add_I2(size, assoc, line_size); break;
 319                case 3: add_U2(size, assoc, line_size); break;
 320                default:
 321                   VG_(debugLog)(1, "cache",
 322                                 "warning: L2 cache of unknown type ignored\n");
 323                   break;
 324                }
 325                break;
 326             case 3:
 327                switch (info[0] & 0x1f)
 328                {
 329                case 1: add_D3(size, assoc, line_size); break;
 330                case 2: add_I3(size, assoc, line_size); break;
 331                case 3: add_U3(size, assoc, line_size); break;
 332                default:
 333                   VG_(debugLog)(1, "cache",
 334                                 "warning: L3 cache of unknown type ignored\n");
 335                   break;
 336                }
 337                break;
 338             default:
 339                VG_(debugLog)(1, "cache", "warning: L%u cache ignored\n",
 340                              (info[0] & 0xe0) >> 5);
 341                break;
 342             }
 343
 344             VG_(cpuid)(4, j++, (UInt*)&info[0], (UInt*)&info[4],
 345                                (UInt*)&info[8], (UInt*)&info[12]);
 346          }
 347          break;
 348
 349       default:
 350          VG_(debugLog)(1, "cache",
 351                        "warning: Unknown Intel cache config value (0x%x), "
 352                        "ignoring\n", info[i]);
 353          break;
 354       }
 355    }
 356
 357    return 0;
 358 }
 359
 360 /* AMD method is straightforward, just extract appropriate bits from the
 361  * result registers.
 362  *
 363  * Bits, for D1 and I1:
 364  *  31..24  data L1 cache size in KBs
 365  *  23..16  data L1 cache associativity (FFh=full)
 366  *  15.. 8  data L1 cache lines per tag
 367  *   7.. 0  data L1 cache line size in bytes
 368  *
 369  * Bits, for L2:
 370  *  31..16  unified L2 cache size in KBs
 371  *  15..12  unified L2 cache associativity (0=off, FFh=full)
 372  *  11.. 8  unified L2 cache lines per tag
 373  *   7.. 0  unified L2 cache line size in bytes
 374  *
 375  * #3  The AMD K7 processor's L2 cache must be configured prior to relying
 376  *     upon this information. (Whatever that means -- njn)
 377  *
 378  * Also, according to Cyrille Chepelov, Duron stepping A0 processors (model
 379  * 0x630) have a bug and misreport their L2 size as 1KB (it's really 64KB),
 380  * so we detect that.
 381  *
 382  * Returns 0 on success, non-zero on failure.  As with the Intel code
 383  * above, if a L3 cache is found, then data for it rather than the L2
 384  * is returned via *LLc.
 385  */
 386
 387 /* A small helper */
 388 static Int
 389 decode_AMD_cache_L2_L3_assoc ( Int bits_15_12 )
 390 {
 391    /* Decode a L2/L3 associativity indication.  It is encoded
 392       differently from the I1/D1 associativity.  Returns 1
 393       (direct-map) as a safe but suboptimal result for unknown
 394       encodings. */
 395    switch (bits_15_12 & 0xF) {
 396       case 1: return 1;    case 2: return 2;
 397       case 4: return 4;    case 6: return 8;
 398       case 8: return 16;   case 0xA: return 32;
 399       case 0xB: return 48; case 0xC: return 64;
 400       case 0xD: return 96; case 0xE: return 128;
 401       case 0xF: /* fully associative */
 402       case 0: /* L2/L3 cache or TLB is disabled */
 403       default:
 404         return 1;
 405    }
 406 }
 407
 408 static Int
 409 AMD_cache_info(VexCacheInfo *ci)
 410 {
 411    UInt ext_level;
 412    UInt dummy, model;
 413    UInt I1i, D1i, L2i, L3i;
 414    UInt size, line_size, assoc;
 415
 416    VG_(cpuid)(0x80000000, 0, &ext_level, &dummy, &dummy, &dummy);
 417
 418    if (0 == (ext_level & 0x80000000) || ext_level < 0x80000006) {
 419       VG_(debugLog)(1, "cache", "warning: ext_level < 0x80000006 for AMD "
 420                     "processor (0x%x)\n", ext_level);
 421       return -1;
 422    }
 423
 424    VG_(cpuid)(0x80000005, 0, &dummy, &dummy, &D1i, &I1i);
 425    VG_(cpuid)(0x80000006, 0, &dummy, &dummy, &L2i, &L3i);
 426
 427    VG_(cpuid)(0x1, 0, &model, &dummy, &dummy, &dummy);
 428
 429    /* Check for Duron bug */
 430    if (model == 0x630) {
 431       VG_(debugLog)(1, "cache", "warning: Buggy Duron stepping A0. "
 432                     "Assuming L2 size=65536 bytes\n");
 433       L2i = (64 << 16) | (L2i & 0xffff);
 434    }
 435
 436    ci->num_levels = 2;
 437    ci->num_caches = 3;
 438    ci->icaches_maintain_coherence = True;
 439
 440    /* Check for L3 cache */
 441    if (((L3i >> 18) & 0x3fff) > 0) {
 442       ci->num_levels = 3;
 443       ci->num_caches = 4;
 444    }
 445
 446    ci->caches = VG_(malloc)("m_cache", ci->num_caches * sizeof *ci->caches);
 447
 448    // D1
 449    size      = (D1i >> 24) & 0xff;
 450    assoc     = (D1i >> 16) & 0xff;
 451    line_size = (D1i >>  0) & 0xff;
 452    ci->caches[0] = VEX_CACHE_INIT(DATA_CACHE, 1, size, line_size, assoc);
 453
 454    // I1
 455    size      = (I1i >> 24) & 0xff;
 456    assoc     = (I1i >> 16) & 0xff;
 457    line_size = (I1i >>  0) & 0xff;
 458    ci->caches[1] = VEX_CACHE_INIT(INSN_CACHE, 1, size, line_size, assoc);
 459
 460    // L2    Nb: different bits used for L2
 461    size      = (L2i >> 16) & 0xffff;
 462    assoc     = decode_AMD_cache_L2_L3_assoc((L2i >> 12) & 0xf);
 463    line_size = (L2i >>  0) & 0xff;
 464    ci->caches[2] = VEX_CACHE_INIT(UNIFIED_CACHE, 2, size, line_size, assoc);
 465
 466    // L3, if any
 467    if (((L3i >> 18) & 0x3fff) > 0) {
 468       /* There's an L3 cache. */
 469       /* NB: the test in the if is "if L3 size > 0 ".  I don't know if
 470          this is the right way to test presence-vs-absence of L3.  I
 471          can't see any guidance on this in the AMD documentation. */
 472       size      = ((L3i >> 18) & 0x3fff) * 512;
 473       assoc     = decode_AMD_cache_L2_L3_assoc((L3i >> 12) & 0xf);
 474       line_size = (L3i >>  0) & 0xff;
 475       ci->caches[3] = VEX_CACHE_INIT(UNIFIED_CACHE, 3, size, line_size, assoc);
 476    }
 477
 478    return 0;
 479 }
 480
 481 static Int
 482 get_caches_from_CPUID(VexCacheInfo *ci)
 483 {
 484    Int  ret, i;
 485    UInt level;
 486    HChar vendor_id[13];
 487
 488    vg_assert(VG_(has_cpuid)());
 489
 490    VG_(cpuid)(0, 0, &level, (UInt*)&vendor_id[0],
 491               (UInt*)&vendor_id[8], (UInt*)&vendor_id[4]);
 492    vendor_id[12] = '\0';
 493
 494    if (0 == level) {    // CPUID level is 0, early Pentium?
 495       return -1;
 496    }
 497
 498    /* Only handling Intel and AMD chips... no Cyrix, Transmeta, etc */
 499    if (0 == VG_(strcmp)(vendor_id, "GenuineIntel")) {
 500       ret = Intel_cache_info(level, ci);
 501
 502    } else if (0 == VG_(strcmp)(vendor_id, "AuthenticAMD")) {
 503       ret = AMD_cache_info(ci);
 504
 505    } else if (0 == VG_(strcmp)(vendor_id, "CentaurHauls")) {
 506       /* Total kludge.  Pretend to be a VIA Nehemiah. */
 507       ci->num_levels = 2;
 508       ci->num_caches = 3;
 509       ci->icaches_maintain_coherence = True;
 510       ci->caches = VG_(malloc)("m_cache", ci->num_caches * sizeof *ci->caches);
 511       ci->caches[0] = VEX_CACHE_INIT(DATA_CACHE,    1, 64, 16, 16);
 512       ci->caches[1] = VEX_CACHE_INIT(INSN_CACHE,    1, 64, 16,  4);
 513       ci->caches[2] = VEX_CACHE_INIT(UNIFIED_CACHE, 2, 64, 16, 16);
 514
 515       ret = 0;
 516
 517    } else {
 518       VG_(debugLog)(1, "cache", "CPU vendor ID not recognised (%s)\n",
 519                     vendor_id);
 520       return -1;
 521    }
 522
 523    /* Successful!  Convert sizes from KB to bytes */
 524    for (i = 0; i < ci->num_caches; ++i) {
 525       ci->caches[i].sizeB *= 1024;
 526    }
 527
 528    return ret;
 529 }
 530
 531 static Bool
 532 get_cache_info(VexArchInfo *vai)
 533 {
 534    Int ret = get_caches_from_CPUID(&vai->hwcache_info);
 535
 536    return ret == 0 ? True : False;
 537 }
 538
 539 #elif defined(VGA_arm) || defined(VGA_ppc32)    || \
 540    defined(VGA_ppc64be) || defined(VGA_ppc64le) || \
 541    defined(VGA_mips32) || defined(VGA_mips64) || \
 542    defined(VGA_arm64) || defined(VGA_nanomips)
 543 static Bool
 544 get_cache_info(VexArchInfo *vai)
 545 {
 546 #if defined(VGA_arm64)
 547    unsigned long val;
 548    asm volatile("mrs %0, dczid_el0" : "=r" (val));
 549    val &= 0xf;
 550    // The ARM manual says that 4 bits are used but 9 is the maximum
 551    vg_assert(val <= 9);
 552    vai->arm64_cache_block_size = val;
 553 #endif
 554    vai->hwcache_info.icaches_maintain_coherence = False;
 555
 556    return False;   // not yet
 557 }
 558
 559 #elif defined(VGA_s390x)
 560
 561 static ULong
 562 ecag(UInt ai, UInt li, UInt ti)
 563 {
 564    register ULong result asm("2") = 0;
 565    register ULong input  asm("3") = (ai << 4) | (li << 1) | ti;
 566
 567    asm volatile(".short 0xeb20\n\t"
 568                 ".long  0x3000004c\n\t"
 569                  : "=d" (result) : "d" (input));
 570
 571    return result;
 572 }
 573
 574 static UInt
 575 get_cache_info_for_level(ULong topology, UInt level)
 576 {
 577    return (topology >> (56 - level * 8)) & 0xff;
 578 }
 579
 580 static ULong
 581 get_line_size(UInt level, Bool is_insn_cache)
 582 {
 583    return ecag(1, level, is_insn_cache);
 584 }
 585
 586 static ULong
 587 get_total_size(UInt level, Bool is_insn_cache)
 588 {
 589    return ecag(2, level, is_insn_cache);
 590 }
 591
 592 static ULong
 593 get_associativity(UInt level, Bool is_insn_cache)
 594 {
 595    return ecag(3, level, is_insn_cache);
 596 }
 597
 598 static VexCache
 599 get_cache(UInt level, VexCacheKind kind)
 600 {
 601    Bool is_insn_cache = kind == INSN_CACHE;
 602    UInt size = get_total_size(level, is_insn_cache);
 603    UInt line_size = get_line_size(level, is_insn_cache);
 604    UInt assoc = get_associativity(level, is_insn_cache);
 605
 606    return VEX_CACHE_INIT(kind, level + 1, size, line_size, assoc);
 607 }
 608
 609 static Bool
 610 get_cache_info(VexArchInfo *vai)
 611 {
 612    VexCacheInfo *ci = &vai->hwcache_info;
 613
 614    ci->icaches_maintain_coherence = True;
 615
 616    if (! (vai->hwcaps & VEX_HWCAPS_S390X_GIE)) {
 617       // ECAG is not available
 618       return False;
 619    }
 620
 621    UInt level, cache_kind, info, i;
 622    ULong topology = ecag(0, 0, 0);   // get summary
 623
 624    /* ECAG supports at most 8 levels of cache. Find out how many levels
 625       of cache and how many caches there are. */
 626    ci->num_levels = 0;
 627    ci->num_caches = 0;
 628    for (level = 0; level < 8; level++) {
 629       info = get_cache_info_for_level(topology, level);
 630
 631       if ((info & 0xc) == 0) break;  // cache does not exist at this level
 632       ++ci->num_levels;
 633
 634       cache_kind = info & 0x3;
 635       switch (cache_kind) {
 636       case 0:  ci->num_caches += 2; break; /* separate data and insn cache */
 637       case 1:  ci->num_caches += 1; break; /* only insn cache */
 638       case 2:  ci->num_caches += 1; break; /* only data cache */
 639       case 3:  ci->num_caches += 1; break; /* unified data and insn cache */
 640       }
 641    }
 642
 643    ci->caches = VG_(malloc)("m_cache", ci->num_caches * sizeof *ci->caches);
 644
 645    i = 0;
 646    for (level = 0; level < ci->num_levels; level++) {
 647       info = get_cache_info_for_level(topology, level);
 648       cache_kind = info & 0x3;
 649       switch (cache_kind) {
 650       case 0:   /* separate data and insn cache */
 651          ci->caches[i++] = get_cache(level, INSN_CACHE);
 652          ci->caches[i++] = get_cache(level, DATA_CACHE);
 653          break;
 654
 655       case 1:   /* only insn cache */
 656          ci->caches[i++] = get_cache(level, INSN_CACHE);
 657          break;
 658
 659       case 2:   /* only data cache */
 660          ci->caches[i++] = get_cache(level, DATA_CACHE);
 661          break;
 662
 663       case 3:   /* unified data and insn cache */
 664          ci->caches[i++] = get_cache(level, UNIFIED_CACHE);
 665          break;
 666       }
 667    }
 668    return True;
 669 }
 670
 671 #else
 672
 673 #error "Unknown arch"
 674
 675 #endif
 676
 677 /* Debug information */
 678 static void
 679 write_cache_info(const VexCacheInfo *ci)
 680 {
 681    UInt i;
 682
 683    VG_(debugLog)(1, "cache", "Cache info:\n");
 684    VG_(debugLog)(1, "cache", "  #levels = %u\n", ci->num_levels);
 685    VG_(debugLog)(1, "cache", "  #caches = %u\n", ci->num_caches);
 686    for (i = 0; i < ci->num_caches; ++i) {
 687       VexCache *c = ci->caches + i;
 688       const HChar *kind;
 689       VG_(debugLog)(1, "cache", "     cache #%u:\n", i);
 690       switch (c->kind) {
 691       case INSN_CACHE:    kind = "insn";    break;
 692       case DATA_CACHE:    kind = "data";    break;
 693       case UNIFIED_CACHE: kind = "unified"; break;
 694       default: kind = "unknown"; break;
 695       }
 696       VG_(debugLog)(1, "cache", "        kind = %s\n", kind);
 697       VG_(debugLog)(1, "cache", "        level = %u\n", c->level);
 698       VG_(debugLog)(1, "cache", "        size = %u bytes\n", c->sizeB);
 699       VG_(debugLog)(1, "cache", "        linesize = %u bytes\n", c->line_sizeB);
 700       VG_(debugLog)(1, "cache", "        assoc = %u\n", c->assoc);
 701    }
 702 }
 703
 704 static Bool
 705 cache_info_is_sensible(const VexCacheInfo *ci)
 706 {
 707    UInt level, i;
 708    Bool sensible = True;
 709
 710    /* There must be at most one cache of a given kind at the same level.
 711       If there is a unified cache at a given level, no other cache may
 712       exist at that level. */
 713    for (level = 1; level <= ci->num_levels; ++level) {
 714       UInt num_icache, num_dcache, num_ucache;
 715
 716       num_icache = num_dcache = num_ucache = 0;
 717       for (i = 0; i < ci->num_caches; ++i) {
 718          if (ci->caches[i].level == level) {
 719             switch (ci->caches[i].kind) {
 720             case INSN_CACHE:    ++num_icache; break;
 721             case DATA_CACHE:    ++num_dcache; break;
 722             case UNIFIED_CACHE: ++num_ucache; break;
 723             }
 724          }
 725       }
 726       if (num_icache == 0 && num_dcache == 0 && num_ucache == 0) {
 727          VG_(debugLog)(1, "cache", "warning: No caches at level %u\n", level);
 728          sensible = False;
 729       }
 730       if (num_icache > 1 || num_dcache > 1 || num_ucache > 1) {
 731          VG_(debugLog)(1, "cache", "warning: More than one cache of a given "
 732                        "kind at level %u\n", level);
 733          sensible = False;
 734       }
 735       if (num_ucache != 0 && (num_icache > 0 || num_dcache > 0)) {
 736          VG_(debugLog)(1, "cache", "warning: Unified cache and I/D cache "
 737                        "at level %u\n", level);
 738          sensible = False;
 739       }
 740    }
 741
 742    /* If there is a cache at level N > 1 there must be a cache at level N-1 */
 743    for (level = 2; level <= ci->num_levels; ++level) {
 744       Bool found = False;
 745       for (i = 0; i < ci->num_caches; ++i) {
 746          if (ci->caches[i].level == level - 1) {
 747             found = True;
 748             break;
 749          }
 750       }
 751       if (! found) {
 752          VG_(debugLog)(1, "cache", "warning: Cache at level %u but no cache "
 753                        "at level %u\n", level, level - 1);
 754          sensible = False;
 755       }
 756    }
 757
 758    return sensible;
 759 }
 760
 761
 762 /* Autodetect the cache information for this host and stuff it into
 763    VexArchInfo::hwcache_info. Return True if successful. */
 764 Bool
 765 VG_(machine_get_cache_info)(VexArchInfo *vai)
 766 {
 767    Bool ok = get_cache_info(vai);
 768
 769    VexCacheInfo *ci = &vai->hwcache_info;
 770
 771    if (! ok) {
 772       VG_(debugLog)(1, "cache", "Could not autodetect cache info\n");
 773    } else {
 774       ok = cache_info_is_sensible(ci);
 775
 776       if (! ok) {
 777          VG_(debugLog)(1, "cache",
 778                        "Autodetected cache info is not sensible\n");
 779       } else {
 780          VG_(debugLog)(1, "cache",
 781                        "Autodetected cache info is sensible\n");
 782       }
 783       write_cache_info(ci);  /* write out for debugging */
 784    }
 785
 786    if (! ok ) {
 787       /* Reset cache info */
 788       ci->num_levels = 0;
 789       ci->num_caches = 0;
 790       VG_(free)(ci->caches);
 791       ci->caches = NULL;
 792    }
 793
 794    return ok;
 795 }
 796
 797 /*--------------------------------------------------------------------*/
 798 /*--- end                                                          ---*/
 799 /*--------------------------------------------------------------------*/