8 ecag(int ai
, int li
, int ti
)
10 register uint64_t result
asm("2") = 0;
11 register uint64_t input
asm("3") = (ai
<< 4) | (li
<< 1) | ti
;
13 asm volatile( ECAG(2,0,3,000,00)
14 : "=d" (result
) : "d" (input
));
19 get_level_info(uint64_t topology
, unsigned level
)
21 return (topology
>> (56 - level
* 8)) & 0xff;
30 topology
= ecag(0, 0, 0); // get summary
32 /* ECAG supports at most 8 levels of cache. Iterate over all of them
33 ignoring those not present. */
34 for (level
= 0; level
< 8; level
++) {
35 unsigned info
= get_level_info(topology
, level
);
37 if ((info
& 0xc) == 0) continue; // cache does not exist at this level
39 unsigned cache_type
= info
& 0x3;
40 unsigned cache_scope
= (info
& 0xc) >> 2;
44 case 0: type
= "separate data and instruction"; break;
45 case 1: type
= "instruction"; break;
46 case 2: type
= "data"; break;
47 case 3: type
= "unified data and instruction"; break;
50 switch (cache_scope
) {
51 case 0: assert(0); // should never occur because cache exists
52 case 1: scope
= "private"; break;
53 case 2: scope
= "shared"; break;
54 case 3: scope
= "reserved"; break;
57 printf("L%u topology: %s; %s\n", level
+1, type
, scope
);
58 printf("L%u cache line size data: %"PRId64
"\n", level
+1,
60 printf("L%u cache line size insn: %"PRId64
"\n", level
+1,
62 printf("L%u total cachesize data: %"PRId64
"\n", level
+1,
64 printf("L%u total cachesize insn: %"PRId64
"\n", level
+1,
66 printf("L%u set. assoc. data: %"PRId64
"\n", level
+1,
68 printf("L%u set. assoc. insn: %"PRId64
"\n", level
+1,