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1 ;; @file
2 ; IPRT - X86 and AMD64 Structures and Definitions.
3 ;
4 ; Automatically generated by various.sed. DO NOT EDIT!
5 ;
7 ;
8 ; Copyright (C) 2006-2024 Oracle and/or its affiliates.
9 ;
10 ; This file is part of VirtualBox base platform packages, as
11 ; available from https://www.virtualbox.org.
12 ;
13 ; This program is free software; you can redistribute it and/or
14 ; modify it under the terms of the GNU General Public License
15 ; as published by the Free Software Foundation, in version 3 of the
16 ; License.
17 ;
18 ; This program is distributed in the hope that it will be useful, but
19 ; WITHOUT ANY WARRANTY; without even the implied warranty of
20 ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
21 ; General Public License for more details.
22 ;
23 ; You should have received a copy of the GNU General Public License
24 ; along with this program; if not, see <https://www.gnu.org/licenses>.
25 ;
26 ; The contents of this file may alternatively be used under the terms
27 ; of the Common Development and Distribution License Version 1.0
28 ; (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
29 ; in the VirtualBox distribution, in which case the provisions of the
30 ; CDDL are applicable instead of those of the GPL.
31 ;
32 ; You may elect to license modified versions of this file under the
33 ; terms and conditions of either the GPL or the CDDL or both.
34 ;
35 ; SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
36 ;
38 %ifndef IPRT_INCLUDED_x86_h
39 %define IPRT_INCLUDED_x86_h
40 %ifndef RT_WITHOUT_PRAGMA_ONCE
41 %endif
42 %ifndef VBOX_FOR_DTRACE_LIB
43 %ifndef __ASSEMBLER__
44 %else
45 %endif
46 %else
47 %endif
48 %ifdef RT_OS_SOLARIS
49 %endif
50 %ifndef __ASSEMBLER__
51 %ifndef VBOX_FOR_DTRACE_LIB
52 %endif
53 %ifndef VBOX_FOR_DTRACE_LIB
54 %endif
55 %ifndef VBOX_FOR_DTRACE_LIB
56 %endif
57 %endif
58 %define X86_EFL_CF RT_BIT_32(0)
59 %define X86_EFL_CF_BIT 0
60 %define X86_EFL_1 RT_BIT_32(1)
61 %define X86_EFL_PF RT_BIT_32(2)
62 %define X86_EFL_PF_BIT 2
63 %define X86_EFL_AF RT_BIT_32(4)
64 %define X86_EFL_AF_BIT 4
65 %define X86_EFL_ZF RT_BIT_32(6)
66 %define X86_EFL_ZF_BIT 6
67 %define X86_EFL_SF RT_BIT_32(7)
68 %define X86_EFL_SF_BIT 7
69 %define X86_EFL_TF RT_BIT_32(8)
70 %define X86_EFL_TF_BIT 8
71 %define X86_EFL_IF RT_BIT_32(9)
72 %define X86_EFL_IF_BIT 9
73 %define X86_EFL_DF RT_BIT_32(10)
74 %define X86_EFL_DF_BIT 10
75 %define X86_EFL_OF RT_BIT_32(11)
76 %define X86_EFL_OF_BIT 11
77 %define X86_EFL_IOPL (RT_BIT_32(12) | RT_BIT_32(13))
78 %define X86_EFL_NT RT_BIT_32(14)
79 %define X86_EFL_NT_BIT 14
80 %define X86_EFL_RF RT_BIT_32(16)
81 %define X86_EFL_RF_BIT 16
82 %define X86_EFL_VM RT_BIT_32(17)
83 %define X86_EFL_VM_BIT 17
84 %define X86_EFL_AC RT_BIT_32(18)
85 %define X86_EFL_AC_BIT 18
86 %define X86_EFL_VIF RT_BIT_32(19)
87 %define X86_EFL_VIF_BIT 19
88 %define X86_EFL_VIP RT_BIT_32(20)
89 %define X86_EFL_VIP_BIT 20
90 %define X86_EFL_ID RT_BIT_32(21)
91 %define X86_EFL_ID_BIT 21
92 %define X86_EFL_LIVE_MASK 0x003f7fd5
93 %define X86_EFL_RA1_MASK RT_BIT_32(1)
94 %define X86_EFL_RAZ_MASK 0xffc08028
95 %define X86_EFL_RAZ_LO_MASK 0x00008028
96 %define X86_EFL_IOPL_SHIFT 12
97 %define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
98 %define X86_EFL_POPF_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF \
99 | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT | X86_EFL_AC | X86_EFL_ID )
100 %define X86_EFL_POPF_BITS_386 ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF \
101 | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT )
102 %define X86_EFL_STATUS_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF )
103 %ifndef __ASSEMBLER__
104 %ifndef VBOX_FOR_DTRACE_LIB
105 %else
106 %endif
107 %ifndef VBOX_FOR_DTRACE_LIB
108 %else
109 %endif
110 %endif
111 %define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547
112 %define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e
113 %define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69
114 %define X86_CPUID_VENDOR_AMD_EBX 0x68747541
115 %define X86_CPUID_VENDOR_AMD_ECX 0x444d4163
116 %define X86_CPUID_VENDOR_AMD_EDX 0x69746e65
117 %define X86_CPUID_VENDOR_VIA_EBX 0x746e6543
118 %define X86_CPUID_VENDOR_VIA_ECX 0x736c7561
119 %define X86_CPUID_VENDOR_VIA_EDX 0x48727561
120 %define X86_CPUID_VENDOR_SHANGHAI_EBX 0x68532020
121 %define X86_CPUID_VENDOR_SHANGHAI_ECX 0x20206961
122 %define X86_CPUID_VENDOR_SHANGHAI_EDX 0x68676e61
123 %define X86_CPUID_VENDOR_HYGON_EBX 0x6f677948
124 %define X86_CPUID_VENDOR_HYGON_ECX 0x656e6975
125 %define X86_CPUID_VENDOR_HYGON_EDX 0x6e65476e
126 %define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT_32(0)
127 %define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT_32(1)
128 %define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT_32(2)
129 %define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT_32(3)
130 %define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT_32(4)
131 %define X86_CPUID_FEATURE_ECX_VMX RT_BIT_32(5)
132 %define X86_CPUID_FEATURE_ECX_SMX RT_BIT_32(6)
133 %define X86_CPUID_FEATURE_ECX_EST RT_BIT_32(7)
134 %define X86_CPUID_FEATURE_ECX_TM2 RT_BIT_32(8)
135 %define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT_32(9)
136 %define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT_32(10)
137 %define X86_CPUID_FEATURE_ECX_SDBG RT_BIT_32(11)
138 %define X86_CPUID_FEATURE_ECX_FMA RT_BIT_32(12)
139 %define X86_CPUID_FEATURE_ECX_CX16 RT_BIT_32(13)
140 %define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT_32(14)
141 %define X86_CPUID_FEATURE_ECX_PDCM RT_BIT_32(15)
142 %define X86_CPUID_FEATURE_ECX_PCID RT_BIT_32(17)
143 %define X86_CPUID_FEATURE_ECX_DCA RT_BIT_32(18)
144 %define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT_32(19)
145 %define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT_32(20)
146 %define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT_32(21)
147 %define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT_32(22)
148 %define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT_32(23)
149 %define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT_32(24)
150 %define X86_CPUID_FEATURE_ECX_AES RT_BIT_32(25)
151 %define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT_32(26)
152 %define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT_32(27)
153 %define X86_CPUID_FEATURE_ECX_AVX RT_BIT_32(28)
154 %define X86_CPUID_FEATURE_ECX_F16C RT_BIT_32(29)
155 %define X86_CPUID_FEATURE_ECX_RDRAND RT_BIT_32(30)
156 %define X86_CPUID_FEATURE_ECX_HVP RT_BIT_32(31)
157 %define X86_CPUID_FEATURE_EDX_FPU RT_BIT_32(0)
158 %define X86_CPUID_FEATURE_EDX_VME RT_BIT_32(1)
159 %define X86_CPUID_FEATURE_EDX_DE RT_BIT_32(2)
160 %define X86_CPUID_FEATURE_EDX_PSE RT_BIT_32(3)
161 %define X86_CPUID_FEATURE_EDX_PSE_BIT 3
162 %define X86_CPUID_FEATURE_EDX_TSC RT_BIT_32(4)
163 %define X86_CPUID_FEATURE_EDX_MSR RT_BIT_32(5)
164 %define X86_CPUID_FEATURE_EDX_PAE RT_BIT_32(6)
165 %define X86_CPUID_FEATURE_EDX_PAE_BIT 6
166 %define X86_CPUID_FEATURE_EDX_MCE RT_BIT_32(7)
167 %define X86_CPUID_FEATURE_EDX_CX8 RT_BIT_32(8)
168 %define X86_CPUID_FEATURE_EDX_APIC RT_BIT_32(9)
169 %define X86_CPUID_FEATURE_EDX_SEP RT_BIT_32(11)
170 %define X86_CPUID_FEATURE_EDX_MTRR RT_BIT_32(12)
171 %define X86_CPUID_FEATURE_EDX_PGE RT_BIT_32(13)
172 %define X86_CPUID_FEATURE_EDX_MCA RT_BIT_32(14)
173 %define X86_CPUID_FEATURE_EDX_CMOV RT_BIT_32(15)
174 %define X86_CPUID_FEATURE_EDX_PAT RT_BIT_32(16)
175 %define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT_32(17)
176 %define X86_CPUID_FEATURE_EDX_PSN RT_BIT_32(18)
177 %define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT_32(19)
178 %define X86_CPUID_FEATURE_EDX_DS RT_BIT_32(21)
179 %define X86_CPUID_FEATURE_EDX_ACPI RT_BIT_32(22)
180 %define X86_CPUID_FEATURE_EDX_MMX RT_BIT_32(23)
181 %define X86_CPUID_FEATURE_EDX_FXSR RT_BIT_32(24)
182 %define X86_CPUID_FEATURE_EDX_SSE RT_BIT_32(25)
183 %define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT_32(26)
184 %define X86_CPUID_FEATURE_EDX_SS RT_BIT_32(27)
185 %define X86_CPUID_FEATURE_EDX_HTT RT_BIT_32(28)
186 %define X86_CPUID_FEATURE_EDX_TM RT_BIT_32(29)
187 %define X86_CPUID_FEATURE_EDX_PBE RT_BIT_32(31)
188 %define X86_CPUID_MWAIT_ECX_EXT RT_BIT_32(0)
189 %define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT_32(1)
190 %define X86_CPUID_POWER_EAX_DTS RT_BIT_32(0)
191 %define X86_CPUID_POWER_EAX_TURBOBOOST RT_BIT_32(1)
192 %define X86_CPUID_POWER_EAX_ARAT RT_BIT_32(2)
193 %define X86_CPUID_POWER_EAX_PLN RT_BIT_32(4)
194 %define X86_CPUID_POWER_EAX_ECMD RT_BIT_32(5)
195 %define X86_CPUID_POWER_EAX_PTM RT_BIT_32(6)
196 %define X86_CPUID_POWER_EAX_HWP RT_BIT_32(7)
197 %define X86_CPUID_POWER_EAX_HWP_NOTIFY RT_BIT_32(8)
198 %define X86_CPUID_POWER_EAX_HWP_ACT_WIN RT_BIT_32(9)
199 %define X86_CPUID_POWER_EAX_HWP_NRG_PP RT_BIT_32(10)
200 %define X86_CPUID_POWER_EAX_HWP_PLR RT_BIT_32(11)
201 %define X86_CPUID_POWER_EAX_HDC RT_BIT_32(13)
202 %define X86_CPUID_POWER_EAX_TBM30 RT_BIT_32(14)
203 %define X86_CPUID_POWER_EAX_HWP_HPC RT_BIT_32(15)
204 %define X86_CPUID_POWER_EAX_HWP_PECI RT_BIT_32(16)
205 %define X86_CPUID_POWER_EAX_HWP_FLEX RT_BIT_32(17)
206 %define X86_CPUID_POWER_ECX_HCFC RT_BIT_32(0)
207 %define X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT_32(0)
208 %define X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT_32(1)
209 %define X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT_32(2)
210 %define X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT_32(3)
211 %define X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT_32(4)
212 %define X86_CPUID_STEXT_FEATURE_EBX_AVX2 RT_BIT_32(5)
213 %define X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY RT_BIT_32(6)
214 %define X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT_32(7)
215 %define X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT_32(8)
216 %define X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT_32(9)
217 %define X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT_32(10)
218 %define X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT_32(11)
219 %define X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT_32(12)
220 %define X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS RT_BIT_32(13)
221 %define X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT_32(14)
222 %define X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT_32(15)
223 %define X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT_32(16)
224 %define X86_CPUID_STEXT_FEATURE_EBX_RDSEED RT_BIT_32(18)
225 %define X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT_32(19)
226 %define X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT_32(20)
227 %define X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT RT_BIT_32(23)
228 %define X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT_32(25)
229 %define X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT_32(26)
230 %define X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT_32(27)
231 %define X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT_32(28)
232 %define X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT_32(29)
233 %define X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 RT_BIT_32(0)
234 %define X86_CPUID_STEXT_FEATURE_ECX_UMIP RT_BIT_32(2)
235 %define X86_CPUID_STEXT_FEATURE_ECX_PKU RT_BIT_32(3)
236 %define X86_CPUID_STEXT_FEATURE_ECX_OSPKE RT_BIT_32(4)
237 %define X86_CPUID_STEXT_FEATURE_ECX_CET_SS RT_BIT_32(7)
238 %define X86_CPUID_STEXT_FEATURE_ECX_MAWAU 0x003e0000
239 %define X86_CPUID_STEXT_FEATURE_ECX_RDPID RT_BIT_32(2)
240 %define X86_CPUID_STEXT_FEATURE_ECX_SGX_LC RT_BIT_32(30)
241 %define X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR RT_BIT_32(10)
242 %define X86_CPUID_STEXT_FEATURE_EDX_CET_IBT RT_BIT_32(20)
243 %define X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT_32(26)
244 %define X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT_32(27)
245 %define X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD RT_BIT_32(28)
246 %define X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP RT_BIT_32(29)
247 %define X86_CPUID_STEXT_FEATURE_EDX_CORECAP RT_BIT_32(30)
248 %define X86_CPUID_STEXT_FEATURE_EDX_SSBD RT_BIT_32(31)
249 %define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT_32(0)
250 %define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT_32(11)
251 %define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT_32(20)
252 %define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT_32(26)
253 %define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT_32(27)
254 %define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT_32(29)
255 %define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT_32(0)
256 %define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT_32(1)
257 %define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT_32(2)
258 %define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT_32(3)
259 %define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT_32(4)
260 %define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT_32(5)
261 %define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT_32(6)
262 %define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT_32(7)
263 %define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT_32(8)
264 %define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT_32(9)
265 %define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT_32(12)
266 %define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT_32(13)
267 %define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT_32(14)
268 %define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT_32(15)
269 %define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT_32(16)
270 %define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT_32(17)
271 %define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT_32(22)
272 %define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT_32(23)
273 %define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT_32(24)
274 %define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT_32(25)
275 %define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT_32(30)
276 %define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT_32(31)
277 %define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT_32(1)
278 %define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT_32(2)
279 %define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT_32(3)
280 %define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT_32(4)
281 %define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT_32(5)
282 %define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT_32(6)
283 %define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT_32(7)
284 %define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT_32(8)
285 %define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT_32(9)
286 %define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT_32(10)
287 %define X86_CPUID_AMD_FEATURE_ECX_XOP RT_BIT_32(11)
288 %define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT_32(12)
289 %define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT_32(13)
290 %define X86_CPUID_AMD_FEATURE_ECX_LWP RT_BIT_32(15)
291 %define X86_CPUID_AMD_FEATURE_ECX_FMA4 RT_BIT_32(16)
292 %define X86_CPUID_AMD_FEATURE_ECX_NODEID RT_BIT_32(19)
293 %define X86_CPUID_AMD_FEATURE_ECX_TBM RT_BIT_32(21)
294 %define X86_CPUID_AMD_FEATURE_ECX_TOPOEXT RT_BIT_32(22)
295 %define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT_32(0)
296 %define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT_32(1)
297 %define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT_32(2)
298 %define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT_32(3)
299 %define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT_32(4)
300 %define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT_32(5)
301 %define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT_32(6)
302 %define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT_32(7)
303 %define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT_32(8)
304 %define X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT_32(9)
305 %define X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT_32(10)
306 %define X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT_32(11)
307 %define X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT_32(12)
308 %define X86_CPUID_AMD_EFEID_EBX_CLZERO RT_BIT_32(0)
309 %define X86_CPUID_AMD_EFEID_EBX_IRPERF RT_BIT_32(1)
310 %define X86_CPUID_AMD_EFEID_EBX_XSAVE_ER_PTR RT_BIT_32(2)
311 %define X86_CPUID_AMD_EFEID_EBX_RDPRU RT_BIT_32(4)
312 %define X86_CPUID_AMD_EFEID_EBX_MCOMMIT RT_BIT_32(8)
313 %define X86_CPUID_AMD_EFEID_EBX_IBPB RT_BIT_32(12)
314 %define X86_CPUID_AMD_EFEID_EBX_IBRS RT_BIT_32(14)
315 %define X86_CPUID_AMD_EFEID_EBX_STIBP RT_BIT_32(15)
316 %define X86_CPUID_AMD_EFEID_EBX_IBRS_ALWAYS_ON RT_BIT_32(16)
317 %define X86_CPUID_AMD_EFEID_EBX_STIBP_ALWAYS_ON RT_BIT_32(17)
318 %define X86_CPUID_AMD_EFEID_EBX_IBRS_PREFERRED RT_BIT_32(18)
319 %define X86_CPUID_AMD_EFEID_EBX_SPEC_CTRL_SSBD RT_BIT_32(24)
320 %define X86_CPUID_AMD_EFEID_EBX_VIRT_SPEC_CTRL_SSBD RT_BIT_32(25)
321 %define X86_CPUID_AMD_EFEID_EBX_NO_SSBD_REQUIRED RT_BIT_32(26)
322 %define X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING RT_BIT(0)
323 %define X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT RT_BIT(1)
324 %define X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK RT_BIT(2)
325 %define X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE RT_BIT(3)
326 %define X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR RT_BIT(4)
327 %define X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN RT_BIT(5)
328 %define X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID RT_BIT(6)
329 %define X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS RT_BIT(7)
330 %define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER RT_BIT(10)
331 %define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD RT_BIT(12)
332 %define X86_CPUID_SVM_FEATURE_EDX_AVIC RT_BIT(13)
333 %define X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD RT_BIT(15)
334 %define X86_CPUID_SVM_FEATURE_EDX_VGIF RT_BIT(16)
335 %define X86_CPUID_SVM_FEATURE_EDX_GMET RT_BIT(17)
336 %define X86_CPUID_SVM_FEATURE_EDX_X2AVIC RT_BIT(18)
337 %define X86_CPUID_SVM_FEATURE_EDX_SSSCHECK RT_BIT(19)
338 %define X86_CPUID_SVM_FEATURE_EDX_SPEC_CTRL RT_BIT(20)
339 %define X86_CPUID_SVM_FEATURE_EDX_ROGPT RT_BIT(21)
340 %define X86_CPUID_SVM_FEATURE_EDX_HOST_MCE_OVERRIDE RT_BIT(23)
341 %define X86_CPUID_SVM_FEATURE_EDX_TLBICTL RT_BIT(24)
342 %define X86_CPUID_SVM_FEATURE_EDX_VNMI RT_BIT(25)
343 %define X86_CPUID_SVM_FEATURE_EDX_IBS_VIRT RT_BIT(26)
344 %define X86_CPUID_SVM_FEATURE_EDX_EXT_LVT_AVIC_ACCESS_CHG RT_BIT(27)
345 %define X86_CPUID_SVM_FEATURE_EDX_NST_VIRT_VMCB_ADDR_CHK RT_BIT(28)
346 %define X86_CPUID_SVM_FEATURE_EDX_BUS_LOCK_THRESHOLD RT_BIT(29)
347 %define X86_CR0_PE RT_BIT_32(0)
348 %define X86_CR0_PROTECTION_ENABLE RT_BIT_32(0)
349 %define X86_CR0_PE_BIT 0
350 %define X86_CR0_MP RT_BIT_32(1)
351 %define X86_CR0_MONITOR_COPROCESSOR RT_BIT_32(1)
352 %define X86_CR0_MP_BIT 1
353 %define X86_CR0_EM RT_BIT_32(2)
354 %define X86_CR0_EMULATE_FPU RT_BIT_32(2)
355 %define X86_CR0_EM_BIT 2
356 %define X86_CR0_TS RT_BIT_32(3)
357 %define X86_CR0_TASK_SWITCH RT_BIT_32(3)
358 %define X86_CR0_TS_BIT 3
359 %define X86_CR0_ET RT_BIT_32(4)
360 %define X86_CR0_EXTENSION_TYPE RT_BIT_32(4)
361 %define X86_CR0_ET_BIT 4
362 %define X86_CR0_NE RT_BIT_32(5)
363 %define X86_CR0_NUMERIC_ERROR RT_BIT_32(5)
364 %define X86_CR0_NE_BIT 5
365 %define X86_CR0_WP RT_BIT_32(16)
366 %define X86_CR0_WRITE_PROTECT RT_BIT_32(16)
367 %define X86_CR0_WP_BIT 16
368 %define X86_CR0_AM RT_BIT_32(18)
369 %define X86_CR0_ALIGNMENT_MASK RT_BIT_32(18)
370 %define X86_CR0_AM_BIT 18
371 %define X86_CR0_NW RT_BIT_32(29)
372 %define X86_CR0_NOT_WRITE_THROUGH RT_BIT_32(29)
373 %define X86_CR0_NW_BIT 29
374 %define X86_CR0_CD RT_BIT_32(30)
375 %define X86_CR0_CACHE_DISABLE RT_BIT_32(30)
376 %define X86_CR0_CD_BIT 30
377 %define X86_CR0_PG RT_BIT_32(31)
378 %define X86_CR0_PAGING RT_BIT_32(31)
379 %define X86_CR0_BIT_PG 31
380 %define X86_CR3_PWT RT_BIT_32(3)
381 %define X86_CR3_PWT_BIT 3
382 %define X86_CR3_PCD RT_BIT_32(4)
383 %define X86_CR3_PCD_BIT 4
384 %define X86_CR3_PAGE_MASK (0xfffff000)
385 %define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
386 %define X86_CR3_AMD64_PAGE_MASK 0x000ffffffffff000
387 %define X86_CR3_EPT_PAGE_MASK 0x000ffffffffff000
388 %define X86_CR4_VME RT_BIT_32(0)
389 %define X86_CR4_VME_BIT 0
390 %define X86_CR4_PVI RT_BIT_32(1)
391 %define X86_CR4_PVI_BIT 1
392 %define X86_CR4_TSD RT_BIT_32(2)
393 %define X86_CR4_TSD_BIT 2
394 %define X86_CR4_DE RT_BIT_32(3)
395 %define X86_CR4_DE_BIT 3
396 %define X86_CR4_PSE RT_BIT_32(4)
397 %define X86_CR4_PSE_BIT 4
398 %define X86_CR4_PAE RT_BIT_32(5)
399 %define X86_CR4_PAE_BIT 5
400 %define X86_CR4_MCE RT_BIT_32(6)
401 %define X86_CR4_MCE_BIT 6
402 %define X86_CR4_PGE RT_BIT_32(7)
403 %define X86_CR4_PGE_BIT 7
404 %define X86_CR4_PCE RT_BIT_32(8)
405 %define X86_CR4_PCE_BIT 8
406 %define X86_CR4_OSFXSR RT_BIT_32(9)
407 %define X86_CR4_OSFXSR_BIT 9
408 %define X86_CR4_OSXMMEEXCPT RT_BIT_32(10)
409 %define X86_CR4_OSXMMEEXCPT_BIT 10
410 %define X86_CR4_UMIP RT_BIT_32(11)
411 %define X86_CR4_UMIP_BIT 11
412 %define X86_CR4_VMXE RT_BIT_32(13)
413 %define X86_CR4_VMXE_BIT 13
414 %define X86_CR4_SMXE RT_BIT_32(14)
415 %define X86_CR4_SMXE_BIT 14
416 %define X86_CR4_FSGSBASE RT_BIT_32(16)
417 %define X86_CR4_FSGSBASE_BIT 16
418 %define X86_CR4_PCIDE RT_BIT_32(17)
419 %define X86_CR4_PCIDE_BIT 17
420 %define X86_CR4_OSXSAVE RT_BIT_32(18)
421 %define X86_CR4_OSXSAVE_BIT 18
422 %define X86_CR4_SMEP RT_BIT_32(20)
423 %define X86_CR4_SMEP_BIt 20
424 %define X86_CR4_SMAP RT_BIT_32(21)
425 %define X86_CR4_SMAP_BIT 21
426 %define X86_CR4_PKE RT_BIT_32(22)
427 %define X86_CR4_PKE_BIT 22
428 %define X86_CR4_CET RT_BIT_32(23)
429 %define X86_CR4_CET_BIT 23
430 %define X86_DR6_B0 RT_BIT_32(0)
431 %define X86_DR6_B1 RT_BIT_32(1)
432 %define X86_DR6_B2 RT_BIT_32(2)
433 %define X86_DR6_B3 RT_BIT_32(3)
434 %define X86_DR6_B_MASK 0x0000000f
435 %define X86_DR6_BD RT_BIT_32(13)
436 %define X86_DR6_BS RT_BIT_32(14)
437 %define X86_DR6_BT RT_BIT_32(15)
438 %define X86_DR6_RTM RT_BIT_32(16)
439 %define X86_DR6_INIT_VAL 0xffff0ff0
440 %define X86_DR6_RA1_MASK 0xffff0ff0
441 %define X86_DR6_RA1_MASK_RTM 0xfffe0ff0
442 %define X86_DR6_RAZ_MASK RT_BIT_64(12)
443 %define X86_DR6_MBZ_MASK 0xffffffff00000000
444 %define X86_DR6_B(iBp) RT_BIT_64(iBp)
445 %define X86_DR7_L0 RT_BIT_32(0)
446 %define X86_DR7_G0 RT_BIT_32(1)
447 %define X86_DR7_L1 RT_BIT_32(2)
448 %define X86_DR7_G1 RT_BIT_32(3)
449 %define X86_DR7_L2 RT_BIT_32(4)
450 %define X86_DR7_G2 RT_BIT_32(5)
451 %define X86_DR7_L3 RT_BIT_32(6)
452 %define X86_DR7_G3 RT_BIT_32(7)
453 %define X86_DR7_LE RT_BIT_32(8)
454 %define X86_DR7_GE RT_BIT_32(9)
455 %define X86_DR7_LE_ALL 0x0000000000000055
456 %define X86_DR7_GE_ALL 0x00000000000000aa
457 %define X86_DR7_RTM RT_BIT_32(11)
458 %define X86_DR7_ICE_IR RT_BIT_32(12)
459 %define X86_DR7_GD RT_BIT_32(13)
460 %define X86_DR7_ICE_TR1 RT_BIT_32(14)
461 %define X86_DR7_ICE_TR2 RT_BIT_32(15)
462 %define X86_DR7_RW0_MASK (3 << 16)
463 %define X86_DR7_LEN0_MASK (3 << 18)
464 %define X86_DR7_RW1_MASK (3 << 20)
465 %define X86_DR7_LEN1_MASK (3 << 22)
466 %define X86_DR7_RW2_MASK (3 << 24)
467 %define X86_DR7_LEN2_MASK (3 << 26)
468 %define X86_DR7_RW3_MASK (3 << 28)
469 %define X86_DR7_LEN3_MASK (3 << 30)
470 %define X86_DR7_RA1_MASK RT_BIT_32(10)
471 %define X86_DR7_RAZ_MASK 0x0000d800
472 %define X86_DR7_MBZ_MASK 0xffffffff00000000
473 %define X86_DR7_L(iBp) ( 1 << (iBp * 2) )
474 %define X86_DR7_G(iBp) ( 1 << (iBp * 2 + 1) )
475 %define X86_DR7_L_G(iBp) ( 3 << (iBp * 2) )
476 %define X86_DR7_RW_EO 0
477 %define X86_DR7_RW_WO 1
478 %define X86_DR7_RW_IO 2
479 %define X86_DR7_RW_RW 3
480 %define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
481 %define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & 3 )
482 %define X86_DR7_RW_ALL_MASKS 0x33330000
483 %ifndef VBOX_FOR_DTRACE_LIB
484 %define X86_DR7_IS_EO_CFG(a_uDR7, a_iBp) ( ((a_uDR7) & (0x000f0000 << ((a_iBp) * 4))) == 0 )
485 %define X86_DR7_IS_EO_ENABLED(a_uDR7, a_iBp) \
486 ( ((a_uDR7) & (0x03 << ((a_iBp) * 2))) != 0 && X86_DR7_IS_EO_CFG(a_uDR7, a_iBp) )
487 %define X86_DR7_ANY_EO_ENABLED(a_uDR7) \
488 ( (((a_uDR7) & 0x03) != 0 && ((a_uDR7) & UINT32_C(0x000f0000)) == 0) \
489 || (((a_uDR7) & UINT32_C(0x0c)) != 0 && ((a_uDR7) & UINT32_C(0x00f00000)) == 0) \
490 || (((a_uDR7) & UINT32_C(0x30)) != 0 && ((a_uDR7) & UINT32_C(0x0f000000)) == 0) \
491 || (((a_uDR7) & UINT32_C(0xc0)) != 0 && ((a_uDR7) & UINT32_C(0xf0000000)) == 0) )
492 %define X86_DR7_IS_RW_CFG(a_uDR7, a_iBp) ( ~((a_uDR7) & (0x00030000 << ((a_iBp) * 4))) == 0)
493 %define X86_DR7_ANY_RW_ENABLED(a_uDR7) \
494 ( (((a_uDR7) & 0x03) != 0 && ((a_uDR7) & UINT32_C(0x00030000)) == UINT32_C(0x00030000)) \
495 || (((a_uDR7) & UINT32_C(0x0c)) != 0 && ((a_uDR7) & UINT32_C(0x00300000)) == UINT32_C(0x00300000)) \
496 || (((a_uDR7) & UINT32_C(0x30)) != 0 && ((a_uDR7) & UINT32_C(0x03000000)) == UINT32_C(0x03000000)) \
497 || (((a_uDR7) & UINT32_C(0xc0)) != 0 && ((a_uDR7) & UINT32_C(0x30000000)) == UINT32_C(0x30000000)) )
498 %define X86_DR7_IS_W_CFG(a_uDR7, a_iBp) ( ((a_uDR7) & (0x00010000 << ((a_iBp) * 4))) != 0)
499 %define X86_DR7_ANY_W_ENABLED(a_uDR7) \
500 ( (((a_uDR7) & 0x03) != 0 && ((a_uDR7) & UINT32_C(0x00010000)) != 0) \
501 || (((a_uDR7) & UINT32_C(0x0c)) != 0 && ((a_uDR7) & UINT32_C(0x00100000)) != 0) \
502 || (((a_uDR7) & UINT32_C(0x30)) != 0 && ((a_uDR7) & UINT32_C(0x01000000)) != 0) \
503 || (((a_uDR7) & UINT32_C(0xc0)) != 0 && ((a_uDR7) & UINT32_C(0x10000000)) != 0) )
504 %define X86_DR7_ANY_RW_IO(uDR7) \
505 ( ( 0x22220000 & (uDR7) ) \
506 && ( ( (UINT32_C(0x22220000) & (uDR7) ) >> 1 ) & ~(uDR7) ) )
507 %endif
508 %define X86_DR7_LEN_BYTE 0
509 %define X86_DR7_LEN_WORD 1
510 %define X86_DR7_LEN_QWORD 2
511 %define X86_DR7_LEN_DWORD 3
512 %define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
513 %define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & 0x3 )
514 %define X86_DR7_ENABLED_MASK 0x000000ff
515 %define X86_DR7_LEN_ALL_MASKS 0xcccc0000
516 %define X86_DR7_RW_LEN_ALL_MASKS 0xffff0000
517 %define X86_DR7_INIT_VAL 0x400
518 %define MSR_P5_MC_ADDR 0x00000000
519 %define MSR_P5_MC_TYPE 0x00000001
520 %define MSR_IA32_TSC 0x10
521 %define MSR_IA32_CESR 0x00000011
522 %define MSR_IA32_CTR0 0x00000012
523 %define MSR_IA32_CTR1 0x00000013
524 %define MSR_IA32_PLATFORM_ID 0x17
525 %ifndef MSR_IA32_APICBASE
526 %define MSR_IA32_APICBASE 0x1b
527 %define MSR_IA32_APICBASE_EN RT_BIT_64(11)
528 %define MSR_IA32_APICBASE_EXTD RT_BIT_64(10)
529 %define MSR_IA32_APICBASE_BSP RT_BIT_64(8)
530 %define MSR_IA32_APICBASE_BASE_MIN 0x0000000ffffff000
531 %define MSR_IA32_APICBASE_ADDR 0x00000000fee00000
532 %define MSR_IA32_APICBASE_GET_ADDR(a_Msr) ((a_Msr) & X86_PAGE_4K_BASE_MASK)
533 %endif
534 %define MSR_MEMORY_CTRL 0x33
535 %define MSR_MEMORY_CTRL_UC_STORE_THROTTLE RT_BIT_64(27)
536 %define MSR_MEMORY_CTRL_UC_LOCK_DISABLE RT_BIT_64(28)
537 %define MSR_MEMORY_CTRL_SPLIT_LOCK_DISABLE RT_BIT_64(29)
538 %define MSR_CORE_THREAD_COUNT 0x35
539 %define MSR_IA32_FEATURE_CONTROL 0x3A
540 %define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT_64(0)
541 %define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT_64(1)
542 %define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT_64(2)
543 %define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0 RT_BIT_64(8)
544 %define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1 RT_BIT_64(9)
545 %define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2 RT_BIT_64(10)
546 %define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3 RT_BIT_64(11)
547 %define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4 RT_BIT_64(12)
548 %define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5 RT_BIT_64(13)
549 %define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6 RT_BIT_64(14)
550 %define MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN RT_BIT_64(15)
551 %define MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN RT_BIT_64(17)
552 %define MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN RT_BIT_64(18)
553 %define MSR_IA32_FEATURE_CONTROL_LMCE RT_BIT_64(20)
554 %define MSR_IA32_TSC_ADJUST 0x3B
555 %define MSR_IA32_SPEC_CTRL 0x48
556 %define MSR_IA32_SPEC_CTRL_F_IBRS RT_BIT_32(0)
557 %define MSR_IA32_SPEC_CTRL_F_STIBP RT_BIT_32(1)
558 %define MSR_IA32_SPEC_CTRL_F_SSBD RT_BIT_32(2)
559 %define MSR_IA32_PRED_CMD 0x49
560 %define MSR_IA32_PRED_CMD_F_IBPB RT_BIT_32(0)
561 %define MSR_IA32_BIOS_UPDT_TRIG 0x79
562 %define MSR_IA32_BIOS_SIGN_ID 0x8B
563 %define MSR_IA32_SMM_MONITOR_CTL 0x9B
564 %define MSR_IA32_SMM_MONITOR_VALID RT_BIT_64(0)
565 %define MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI RT_BIT_64(2)
566 %define MSR_IA32_SMM_MONITOR_MSGEG_PHYSADDR(a) (((a) >> 12) & 0xfffff)
567 %define MSR_IA32_SMBASE 0x9E
568 %define MSR_IA32_PMC0 0xC1
569 %define MSR_IA32_PMC1 0xC2
570 %define MSR_IA32_PMC2 0xC3
571 %define MSR_IA32_PMC3 0xC4
572 %define MSR_IA32_PMC4 0xC5
573 %define MSR_IA32_PMC5 0xC6
574 %define MSR_IA32_PMC6 0xC7
575 %define MSR_IA32_PMC7 0xC8
576 %define MSR_IA32_PLATFORM_INFO 0xCE
577 %define MSR_IA32_CORE_CAPABILITIES 0xCF
578 %define MSR_IA32_CORE_CAP_STLB_QOS RT_BIT_64(0)
579 %define MSR_IA32_CORE_CAP_FUSA RT_BIT_64(2)
580 %define MSR_IA32_CORE_CAP_RSM_CPL0 RT_BIT_64(3)
581 %define MSR_IA32_CORE_CAP_UC_LOCK_DISABLE RT_BIT_64(4)
582 %define MSR_IA32_CORE_CAP_SPLIT_LOCK_DISABLE RT_BIT_64(5)
583 %define MSR_IA32_CORE_CAP_SNOOP_FILTER_QOS RT_BIT_64(6)
584 %define MSR_IA32_CORE_CAP_UC_STORE_THROTTLE RT_BIT_64(7)
585 %define MSR_IA32_FSB_CLOCK_STS 0xCD
586 %define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2
587 %define MSR_IA32_MPERF 0xE7
588 %define MSR_IA32_APERF 0xE8
589 %define MSR_IA32_MTRR_CAP 0xFE
590 %define MSR_IA32_MTRR_CAP_VCNT_MASK 0x00000000000000ff
591 %define MSR_IA32_MTRR_CAP_FIX RT_BIT_64(8)
592 %define MSR_IA32_MTRR_CAP_WC RT_BIT_64(10)
593 %define MSR_IA32_MTRR_CAP_SMRR RT_BIT_64(11)
594 %define MSR_IA32_MTRR_CAP_PRMRR RT_BIT_64(12)
595 %ifndef __ASSEMBLER__
596 %ifndef VBOX_FOR_DTRACE_LIB
597 %endif
598 %endif
599 %define X86_MTRR_MT_UC 0
600 %define X86_MTRR_MT_WC 1
601 %define X86_MTRR_MT_WT 4
602 %define X86_MTRR_MT_WP 5
603 %define X86_MTRR_MT_WB 6
604 %define MSR_IA32_ARCH_CAPABILITIES 0x10a
605 %define MSR_IA32_ARCH_CAP_F_RDCL_NO RT_BIT_32(0)
606 %define MSR_IA32_ARCH_CAP_F_IBRS_ALL RT_BIT_32(1)
607 %define MSR_IA32_ARCH_CAP_F_RSBO RT_BIT_32(2)
608 %define MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D RT_BIT_32(3)
609 %define MSR_IA32_ARCH_CAP_F_SSB_NO RT_BIT_32(4)
610 %define MSR_IA32_ARCH_CAP_F_MDS_NO RT_BIT_32(5)
611 %define MSR_IA32_ARCH_CAP_F_IF_PSCHANGE_MC_NO RT_BIT_32(6)
612 %define MSR_IA32_ARCH_CAP_F_TSX_CTRL RT_BIT_32(7)
613 %define MSR_IA32_ARCH_CAP_F_TAA_NO RT_BIT_32(8)
614 %define MSR_IA32_ARCH_CAP_F_MISC_PACKAGE_CTRLS RT_BIT_32(10)
615 %define MSR_IA32_ARCH_CAP_F_ENERGY_FILTERING_CTL RT_BIT_32(11)
616 %define MSR_IA32_ARCH_CAP_F_DOITM RT_BIT_32(12)
617 %define MSR_IA32_ARCH_CAP_F_SBDR_SSDP_NO RT_BIT_32(13)
618 %define MSR_IA32_ARCH_CAP_F_FBSDP_NO RT_BIT_32(14)
619 %define MSR_IA32_ARCH_CAP_F_PSDP_NO RT_BIT_32(15)
620 %define MSR_IA32_ARCH_CAP_F_FB_CLEAR RT_BIT_32(17)
621 %define MSR_IA32_ARCH_CAP_F_FB_CLEAR_CTRL RT_BIT_32(18)
622 %define MSR_IA32_ARCH_CAP_F_RRSBA RT_BIT_32(19)
623 %define MSR_IA32_ARCH_CAP_F_BHI_NO RT_BIT_32(20)
624 %define MSR_IA32_ARCH_CAP_F_XAPIC_DISABLE_STATUS RT_BIT_32(21)
625 %define MSR_IA32_ARCH_CAP_F_OVERCLOCKING_STATUS RT_BIT_32(22)
626 %define MSR_IA32_ARCH_CAP_F_PBRSB_NO RT_BIT_32(23)
627 %define MSR_IA32_ARCH_CAP_F_GDS_CTRL RT_BIT_32(24)
628 %define MSR_IA32_ARCH_CAP_F_GDS_NO RT_BIT_32(25)
629 %define MSR_IA32_ARCH_CAP_F_RFDS_NO RT_BIT_32(26)
630 %define MSR_IA32_ARCH_CAP_F_RFDS_CLEAR RT_BIT_32(27)
631 %define MSR_IA32_FLUSH_CMD 0x10b
632 %define MSR_IA32_FLUSH_CMD_F_L1D RT_BIT_32(0)
633 %define MSR_BBL_CR_CTL3 0x11e
634 %ifndef MSR_IA32_SYSENTER_CS
635 %define MSR_IA32_SYSENTER_CS 0x174
636 %define MSR_IA32_SYSENTER_ESP 0x175
637 %define MSR_IA32_SYSENTER_EIP 0x176
638 %endif
639 %define MSR_IA32_MCG_CAP 0x179
640 %define MSR_IA32_MCG_STATUS 0x17A
641 %define MSR_IA32_MCG_CTRL 0x17B
642 %define MSR_IA32_CR_PAT 0x277
643 %define MSR_IA32_CR_PAT_INIT_VAL 0x0007040600070406
644 %define MSR_IA32_PAT_MT_UC 0
645 %define MSR_IA32_PAT_MT_WC 1
646 %define MSR_IA32_PAT_MT_RSVD_2 2
647 %define MSR_IA32_PAT_MT_RSVD_3 3
648 %define MSR_IA32_PAT_MT_WT 4
649 %define MSR_IA32_PAT_MT_WP 5
650 %define MSR_IA32_PAT_MT_WB 6
651 %define MSR_IA32_PAT_MT_UCD 7
652 %define MSR_IA32_PERFEVTSEL0 0x186
653 %define MSR_IA32_PERFEVTSEL1 0x187
654 %define MSR_IA32_PERFEVTSEL2 0x188
655 %define MSR_IA32_PERFEVTSEL3 0x189
656 %define MSR_FLEX_RATIO 0x194
657 %define MSR_IA32_PERF_STATUS 0x198
658 %define MSR_IA32_PERF_CTL 0x199
659 %define MSR_IA32_THERM_STATUS 0x19c
660 %define MSR_OFFCORE_RSP_0 0x1a6
661 %define MSR_OFFCORE_RSP_1 0x1a7
662 %define MSR_IA32_MISC_ENABLE 0x1A0
663 %define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0)
664 %define MSR_IA32_MISC_ENABLE_TCC RT_BIT_64(3)
665 %define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT_64(7)
666 %define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT_64(11)
667 %define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT_64(12)
668 %define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT_64(16)
669 %define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT_64(18)
670 %define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT_64(22)
671 %define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT_64(23)
672 %define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT_64(34)
673 %define MSR_IA32_DEBUGCTL 0x000001d9
674 %define MSR_IA32_DEBUGCTL_LBR RT_BIT_64(0)
675 %define MSR_IA32_DEBUGCTL_BTF RT_BIT_64(1)
676 %define MSR_IA32_DEBUGCTL_PB0 RT_BIT_64(2)
677 %define MSR_IA32_DEBUGCTL_PB1 RT_BIT_64(3)
678 %define MSR_IA32_DEBUGCTL_PB2 RT_BIT_64(4)
679 %define MSR_IA32_DEBUGCTL_PB3 RT_BIT_64(5)
680 %define MSR_IA32_DEBUGCTL_TR RT_BIT_64(6)
681 %define MSR_IA32_DEBUGCTL_BTS RT_BIT_64(7)
682 %define MSR_IA32_DEBUGCTL_BTINT RT_BIT_64(8)
683 %define MSR_IA32_DEBUGCTL_BTS_OFF_OS RT_BIT_64(9)
684 %define MSR_IA32_DEBUGCTL_BTS_OFF_USER RT_BIT_64(10)
685 %define MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI RT_BIT_64(11)
686 %define MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI RT_BIT_64(12)
687 %define MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM RT_BIT_64(14)
688 %define MSR_IA32_DEBUGCTL_RTM RT_BIT_64(15)
689 %define MSR_IA32_DEBUGCTL_VALID_MASK_INTEL ( MSR_IA32_DEBUGCTL_LBR | MSR_IA32_DEBUGCTL_BTF | MSR_IA32_DEBUGCTL_TR \
690 | MSR_IA32_DEBUGCTL_BTS | MSR_IA32_DEBUGCTL_BTINT | MSR_IA32_DEBUGCTL_BTS_OFF_OS \
691 | MSR_IA32_DEBUGCTL_BTS_OFF_USER | MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI \
692 | MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI | MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM \
693 | MSR_IA32_DEBUGCTL_RTM)
694 %define MSR_P4_LASTBRANCH_0 0x1db
695 %define MSR_P4_LASTBRANCH_1 0x1dc
696 %define MSR_P4_LASTBRANCH_2 0x1dd
697 %define MSR_P4_LASTBRANCH_3 0x1de
698 %define MSR_P4_LASTBRANCH_TOS 0x1da
699 %define MSR_CORE2_LASTBRANCH_0_FROM_IP 0x40
700 %define MSR_CORE2_LASTBRANCH_1_FROM_IP 0x41
701 %define MSR_CORE2_LASTBRANCH_2_FROM_IP 0x42
702 %define MSR_CORE2_LASTBRANCH_3_FROM_IP 0x43
703 %define MSR_CORE2_LASTBRANCH_0_TO_IP 0x60
704 %define MSR_CORE2_LASTBRANCH_1_TO_IP 0x61
705 %define MSR_CORE2_LASTBRANCH_2_TO_IP 0x62
706 %define MSR_CORE2_LASTBRANCH_3_TO_IP 0x63
707 %define MSR_CORE2_LASTBRANCH_TOS 0x1c9
708 %define MSR_LASTBRANCH_0_FROM_IP 0x680
709 %define MSR_LASTBRANCH_1_FROM_IP 0x681
710 %define MSR_LASTBRANCH_2_FROM_IP 0x682
711 %define MSR_LASTBRANCH_3_FROM_IP 0x683
712 %define MSR_LASTBRANCH_4_FROM_IP 0x684
713 %define MSR_LASTBRANCH_5_FROM_IP 0x685
714 %define MSR_LASTBRANCH_6_FROM_IP 0x686
715 %define MSR_LASTBRANCH_7_FROM_IP 0x687
716 %define MSR_LASTBRANCH_8_FROM_IP 0x688
717 %define MSR_LASTBRANCH_9_FROM_IP 0x689
718 %define MSR_LASTBRANCH_10_FROM_IP 0x68a
719 %define MSR_LASTBRANCH_11_FROM_IP 0x68b
720 %define MSR_LASTBRANCH_12_FROM_IP 0x68c
721 %define MSR_LASTBRANCH_13_FROM_IP 0x68d
722 %define MSR_LASTBRANCH_14_FROM_IP 0x68e
723 %define MSR_LASTBRANCH_15_FROM_IP 0x68f
724 %define MSR_LASTBRANCH_16_FROM_IP 0x690
725 %define MSR_LASTBRANCH_17_FROM_IP 0x691
726 %define MSR_LASTBRANCH_18_FROM_IP 0x692
727 %define MSR_LASTBRANCH_19_FROM_IP 0x693
728 %define MSR_LASTBRANCH_20_FROM_IP 0x694
729 %define MSR_LASTBRANCH_21_FROM_IP 0x695
730 %define MSR_LASTBRANCH_22_FROM_IP 0x696
731 %define MSR_LASTBRANCH_23_FROM_IP 0x697
732 %define MSR_LASTBRANCH_24_FROM_IP 0x698
733 %define MSR_LASTBRANCH_25_FROM_IP 0x699
734 %define MSR_LASTBRANCH_26_FROM_IP 0x69a
735 %define MSR_LASTBRANCH_27_FROM_IP 0x69b
736 %define MSR_LASTBRANCH_28_FROM_IP 0x69c
737 %define MSR_LASTBRANCH_29_FROM_IP 0x69d
738 %define MSR_LASTBRANCH_30_FROM_IP 0x69e
739 %define MSR_LASTBRANCH_31_FROM_IP 0x69f
740 %define MSR_LASTBRANCH_0_TO_IP 0x6c0
741 %define MSR_LASTBRANCH_1_TO_IP 0x6c1
742 %define MSR_LASTBRANCH_2_TO_IP 0x6c2
743 %define MSR_LASTBRANCH_3_TO_IP 0x6c3
744 %define MSR_LASTBRANCH_4_TO_IP 0x6c4
745 %define MSR_LASTBRANCH_5_TO_IP 0x6c5
746 %define MSR_LASTBRANCH_6_TO_IP 0x6c6
747 %define MSR_LASTBRANCH_7_TO_IP 0x6c7
748 %define MSR_LASTBRANCH_8_TO_IP 0x6c8
749 %define MSR_LASTBRANCH_9_TO_IP 0x6c9
750 %define MSR_LASTBRANCH_10_TO_IP 0x6ca
751 %define MSR_LASTBRANCH_11_TO_IP 0x6cb
752 %define MSR_LASTBRANCH_12_TO_IP 0x6cc
753 %define MSR_LASTBRANCH_13_TO_IP 0x6cd
754 %define MSR_LASTBRANCH_14_TO_IP 0x6ce
755 %define MSR_LASTBRANCH_15_TO_IP 0x6cf
756 %define MSR_LASTBRANCH_16_TO_IP 0x6d0
757 %define MSR_LASTBRANCH_17_TO_IP 0x6d1
758 %define MSR_LASTBRANCH_18_TO_IP 0x6d2
759 %define MSR_LASTBRANCH_19_TO_IP 0x6d3
760 %define MSR_LASTBRANCH_20_TO_IP 0x6d4
761 %define MSR_LASTBRANCH_21_TO_IP 0x6d5
762 %define MSR_LASTBRANCH_22_TO_IP 0x6d6
763 %define MSR_LASTBRANCH_23_TO_IP 0x6d7
764 %define MSR_LASTBRANCH_24_TO_IP 0x6d8
765 %define MSR_LASTBRANCH_25_TO_IP 0x6d9
766 %define MSR_LASTBRANCH_26_TO_IP 0x6da
767 %define MSR_LASTBRANCH_27_TO_IP 0x6db
768 %define MSR_LASTBRANCH_28_TO_IP 0x6dc
769 %define MSR_LASTBRANCH_29_TO_IP 0x6dd
770 %define MSR_LASTBRANCH_30_TO_IP 0x6de
771 %define MSR_LASTBRANCH_31_TO_IP 0x6df
772 %define MSR_LASTBRANCH_0_INFO 0xdc0
773 %define MSR_LASTBRANCH_1_INFO 0xdc1
774 %define MSR_LASTBRANCH_2_INFO 0xdc2
775 %define MSR_LASTBRANCH_3_INFO 0xdc3
776 %define MSR_LASTBRANCH_4_INFO 0xdc4
777 %define MSR_LASTBRANCH_5_INFO 0xdc5
778 %define MSR_LASTBRANCH_6_INFO 0xdc6
779 %define MSR_LASTBRANCH_7_INFO 0xdc7
780 %define MSR_LASTBRANCH_8_INFO 0xdc8
781 %define MSR_LASTBRANCH_9_INFO 0xdc9
782 %define MSR_LASTBRANCH_10_INFO 0xdca
783 %define MSR_LASTBRANCH_11_INFO 0xdcb
784 %define MSR_LASTBRANCH_12_INFO 0xdcc
785 %define MSR_LASTBRANCH_13_INFO 0xdcd
786 %define MSR_LASTBRANCH_14_INFO 0xdce
787 %define MSR_LASTBRANCH_15_INFO 0xdcf
788 %define MSR_LASTBRANCH_16_INFO 0xdd0
789 %define MSR_LASTBRANCH_17_INFO 0xdd1
790 %define MSR_LASTBRANCH_18_INFO 0xdd2
791 %define MSR_LASTBRANCH_19_INFO 0xdd3
792 %define MSR_LASTBRANCH_20_INFO 0xdd4
793 %define MSR_LASTBRANCH_21_INFO 0xdd5
794 %define MSR_LASTBRANCH_22_INFO 0xdd6
795 %define MSR_LASTBRANCH_23_INFO 0xdd7
796 %define MSR_LASTBRANCH_24_INFO 0xdd8
797 %define MSR_LASTBRANCH_25_INFO 0xdd9
798 %define MSR_LASTBRANCH_26_INFO 0xdda
799 %define MSR_LASTBRANCH_27_INFO 0xddb
800 %define MSR_LASTBRANCH_28_INFO 0xddc
801 %define MSR_LASTBRANCH_29_INFO 0xddd
802 %define MSR_LASTBRANCH_30_INFO 0xdde
803 %define MSR_LASTBRANCH_31_INFO 0xddf
804 %define MSR_LASTBRANCH_SELECT 0x1c8
805 %define MSR_LASTBRANCH_TOS 0x1c9
806 %define MSR_LER_FROM_IP 0x1dd
807 %define MSR_LER_TO_IP 0x1de
808 %define MSR_IA32_TSX_CTRL 0x122
809 %define MSR_IA32_MTRR_PHYSBASE0 0x200
810 %define MSR_IA32_MTRR_PHYSMASK0 0x201
811 %define MSR_IA32_MTRR_PHYSBASE1 0x202
812 %define MSR_IA32_MTRR_PHYSMASK1 0x203
813 %define MSR_IA32_MTRR_PHYSBASE2 0x204
814 %define MSR_IA32_MTRR_PHYSMASK2 0x205
815 %define MSR_IA32_MTRR_PHYSBASE3 0x206
816 %define MSR_IA32_MTRR_PHYSMASK3 0x207
817 %define MSR_IA32_MTRR_PHYSBASE4 0x208
818 %define MSR_IA32_MTRR_PHYSMASK4 0x209
819 %define MSR_IA32_MTRR_PHYSBASE5 0x20a
820 %define MSR_IA32_MTRR_PHYSMASK5 0x20b
821 %define MSR_IA32_MTRR_PHYSBASE6 0x20c
822 %define MSR_IA32_MTRR_PHYSMASK6 0x20d
823 %define MSR_IA32_MTRR_PHYSBASE7 0x20e
824 %define MSR_IA32_MTRR_PHYSMASK7 0x20f
825 %define MSR_IA32_MTRR_PHYSBASE8 0x210
826 %define MSR_IA32_MTRR_PHYSMASK8 0x211
827 %define MSR_IA32_MTRR_PHYSBASE9 0x212
828 %define MSR_IA32_MTRR_PHYSMASK9 0x213
829 %define MSR_IA32_MTRR_FIX64K_00000 0x250
830 %define MSR_IA32_MTRR_FIX16K_80000 0x258
831 %define MSR_IA32_MTRR_FIX16K_A0000 0x259
832 %define MSR_IA32_MTRR_FIX4K_C0000 0x268
833 %define MSR_IA32_MTRR_FIX4K_C8000 0x269
834 %define MSR_IA32_MTRR_FIX4K_D0000 0x26a
835 %define MSR_IA32_MTRR_FIX4K_D8000 0x26b
836 %define MSR_IA32_MTRR_FIX4K_E0000 0x26c
837 %define MSR_IA32_MTRR_FIX4K_E8000 0x26d
838 %define MSR_IA32_MTRR_FIX4K_F0000 0x26e
839 %define MSR_IA32_MTRR_FIX4K_F8000 0x26f
840 %define MSR_IA32_MTRR_DEF_TYPE 0x2FF
841 %define MSR_IA32_MTRR_DEF_TYPE_DEF_MT_MASK 0xFF
842 %define MSR_IA32_MTRR_DEF_TYPE_FIXED_EN RT_BIT_64(10)
843 %define MSR_IA32_MTRR_DEF_TYPE_MTRR_EN RT_BIT_64(11)
844 %define MSR_IA32_MTRR_DEF_TYPE_VALID_MASK ( MSR_IA32_MTRR_DEF_TYPE_DEF_MT_MASK \
845 | MSR_IA32_MTRR_DEF_TYPE_FIXED_EN \
846 | MSR_IA32_MTRR_DEF_TYPE_MTRR_EN)
847 %define MSR_IA32_MTRR_PHYSMASK_VALID RT_BIT_64(11)
848 %define MSR_IA32_MTRR_PHYSBASE_MT_MASK 0xff
849 %define MSR_IA32_PERF_GLOBAL_STATUS 0x38E
850 %define MSR_IA32_PERF_GLOBAL_CTRL 0x38F
851 %define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x390
852 %define MSR_IA32_PEBS_ENABLE 0x3F1
853 %define MSR_IA32_MC0_CTL 0x400
854 %define MSR_IA32_MC0_STATUS 0x401
855 %define MSR_IA32_VMX_BASIC 0x480
856 %define MSR_IA32_VMX_PINBASED_CTLS 0x481
857 %define MSR_IA32_VMX_PROCBASED_CTLS 0x482
858 %define MSR_IA32_VMX_EXIT_CTLS 0x483
859 %define MSR_IA32_VMX_ENTRY_CTLS 0x484
860 %define MSR_IA32_VMX_MISC 0x485
861 %define MSR_IA32_VMX_CR0_FIXED0 0x486
862 %define MSR_IA32_VMX_CR0_FIXED1 0x487
863 %define MSR_IA32_VMX_CR4_FIXED0 0x488
864 %define MSR_IA32_VMX_CR4_FIXED1 0x489
865 %define MSR_IA32_VMX_VMCS_ENUM 0x48A
866 %define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
867 %define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
868 %define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x48D
869 %define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48E
870 %define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x48F
871 %define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x490
872 %define MSR_IA32_VMX_VMFUNC 0x491
873 %define MSR_IA32_VMX_PROCBASED_CTLS3 0x492
874 %define MSR_IA32_VMX_EXIT_CTLS2 0x493
875 %define MSR_IA32_RTIT_CTL 0x570
876 %define MSR_IA32_DS_AREA 0x600
877 %define MSR_RAPL_POWER_UNIT 0x606
878 %define MSR_PKGC3_IRTL 0x60a
879 %define MSR_PKGC_IRTL1 0x60b
880 %define MSR_PKGC_IRTL2 0x60c
881 %define MSR_PKG_C2_RESIDENCY 0x60d
882 %define MSR_PKG_POWER_LIMIT 0x610
883 %define MSR_PKG_ENERGY_STATUS 0x611
884 %define MSR_PKG_PERF_STATUS 0x613
885 %define MSR_PKG_POWER_INFO 0x614
886 %define MSR_DRAM_POWER_LIMIT 0x618
887 %define MSR_DRAM_ENERGY_STATUS 0x619
888 %define MSR_DRAM_PERF_STATUS 0x61b
889 %define MSR_DRAM_POWER_INFO 0x61c
890 %define MSR_PKG_C10_RESIDENCY 0x632
891 %define MSR_PP0_ENERGY_STATUS 0x639
892 %define MSR_PP1_ENERGY_STATUS 0x641
893 %define MSR_TURBO_ACTIVATION_RATIO 0x64c
894 %define MSR_CORE_PERF_LIMIT_REASONS 0x64f
895 %define MSR_IA32_U_CET 0x6a0
896 %define MSR_IA32_S_CET 0x6a2
897 %define MSR_IA32_CET_SH_STK_EN RT_BIT_64(0)
898 %define MSR_IA32_CET_WR_SHSTK_EN RT_BIT_64(1)
899 %define MSR_IA32_CET_ENDBR_EN RT_BIT_64(2)
900 %define MSR_IA32_CET_LEG_IW_EN RT_BIT_64(3)
901 %define MSR_IA32_CET_NO_TRACK_EN RT_BIT_64(4)
902 %define MSR_IA32_CET_SUPPRESS_DIS RT_BIT_64(5)
903 %define MSR_IA32_CET_SUPPRESS RT_BIT_64(10)
904 %define MSR_IA32_CET_TRACKER RT_BIT_64(11)
905 %define MSR_IA32_CET_EB_LEG_BITMAP_BASE 0xfffffffffffff000
906 %define MSR_IA32_X2APIC_START 0x800
907 %define MSR_IA32_X2APIC_ID 0x802
908 %define MSR_IA32_X2APIC_VERSION 0x803
909 %define MSR_IA32_X2APIC_TPR 0x808
910 %define MSR_IA32_X2APIC_PPR 0x80A
911 %define MSR_IA32_X2APIC_EOI 0x80B
912 %define MSR_IA32_X2APIC_LDR 0x80D
913 %define MSR_IA32_X2APIC_SVR 0x80F
914 %define MSR_IA32_X2APIC_ISR0 0x810
915 %define MSR_IA32_X2APIC_ISR1 0x811
916 %define MSR_IA32_X2APIC_ISR2 0x812
917 %define MSR_IA32_X2APIC_ISR3 0x813
918 %define MSR_IA32_X2APIC_ISR4 0x814
919 %define MSR_IA32_X2APIC_ISR5 0x815
920 %define MSR_IA32_X2APIC_ISR6 0x816
921 %define MSR_IA32_X2APIC_ISR7 0x817
922 %define MSR_IA32_X2APIC_TMR0 0x818
923 %define MSR_IA32_X2APIC_TMR1 0x819
924 %define MSR_IA32_X2APIC_TMR2 0x81A
925 %define MSR_IA32_X2APIC_TMR3 0x81B
926 %define MSR_IA32_X2APIC_TMR4 0x81C
927 %define MSR_IA32_X2APIC_TMR5 0x81D
928 %define MSR_IA32_X2APIC_TMR6 0x81E
929 %define MSR_IA32_X2APIC_TMR7 0x81F
930 %define MSR_IA32_X2APIC_IRR0 0x820
931 %define MSR_IA32_X2APIC_IRR1 0x821
932 %define MSR_IA32_X2APIC_IRR2 0x822
933 %define MSR_IA32_X2APIC_IRR3 0x823
934 %define MSR_IA32_X2APIC_IRR4 0x824
935 %define MSR_IA32_X2APIC_IRR5 0x825
936 %define MSR_IA32_X2APIC_IRR6 0x826
937 %define MSR_IA32_X2APIC_IRR7 0x827
938 %define MSR_IA32_X2APIC_ESR 0x828
939 %define MSR_IA32_X2APIC_LVT_CMCI 0x82F
940 %define MSR_IA32_X2APIC_ICR 0x830
941 %define MSR_IA32_X2APIC_LVT_TIMER 0x832
942 %define MSR_IA32_X2APIC_LVT_THERMAL 0x833
943 %define MSR_IA32_X2APIC_LVT_PERF 0x834
944 %define MSR_IA32_X2APIC_LVT_LINT0 0x835
945 %define MSR_IA32_X2APIC_LVT_LINT1 0x836
946 %define MSR_IA32_X2APIC_LVT_ERROR 0x837
947 %define MSR_IA32_X2APIC_TIMER_ICR 0x838
948 %define MSR_IA32_X2APIC_TIMER_CCR 0x839
949 %define MSR_IA32_X2APIC_TIMER_DCR 0x83E
950 %define MSR_IA32_X2APIC_SELF_IPI 0x83F
951 %define MSR_IA32_X2APIC_END 0x8FF
952 %define MSR_IA32_X2APIC_LVT_START MSR_IA32_X2APIC_LVT_TIMER
953 %define MSR_IA32_X2APIC_LVT_END MSR_IA32_X2APIC_LVT_ERROR
954 %define MSR_K6_EFER 0xc0000080
955 %define MSR_K6_EFER_SCE RT_BIT_32(0)
956 %define MSR_K6_EFER_LME RT_BIT_32(8)
957 %define MSR_K6_EFER_BIT_LME 8
958 %define MSR_K6_EFER_LMA RT_BIT_32(10)
959 %define MSR_K6_EFER_BIT_LMA 10
960 %define MSR_K6_EFER_NXE RT_BIT_32(11)
961 %define MSR_K6_EFER_BIT_NXE 11
962 %define MSR_K6_EFER_SVME RT_BIT_32(12)
963 %define MSR_K6_EFER_LMSLE RT_BIT_32(13)
964 %define MSR_K6_EFER_FFXSR RT_BIT_32(14)
965 %define MSR_K6_EFER_TCE RT_BIT_32(15)
966 %define MSR_K6_EFER_MCOMMIT RT_BIT_32(17)
967 %define MSR_K6_STAR 0xc0000081
968 %define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
969 %define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
970 %define MSR_K6_STAR_SEL_MASK 0xffff
971 %define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
972 %define MSR_K6_WHCR 0xc0000082
973 %define MSR_K6_UWCCR 0xc0000085
974 %define MSR_K6_PSOR 0xc0000087
975 %define MSR_K6_PFIR 0xc0000088
976 %define MSR_K7_EVNTSEL0 0xc0010000
977 %define MSR_K7_EVNTSEL1 0xc0010001
978 %define MSR_K7_EVNTSEL2 0xc0010002
979 %define MSR_K7_EVNTSEL3 0xc0010003
980 %define MSR_K7_PERFCTR0 0xc0010004
981 %define MSR_K7_PERFCTR1 0xc0010005
982 %define MSR_K7_PERFCTR2 0xc0010006
983 %define MSR_K7_PERFCTR3 0xc0010007
984 %define MSR_K8_LSTAR 0xc0000082
985 %define MSR_K8_CSTAR 0xc0000083
986 %define MSR_K8_SF_MASK 0xc0000084
987 %define MSR_K8_FS_BASE 0xc0000100
988 %define MSR_K8_GS_BASE 0xc0000101
989 %define MSR_K8_KERNEL_GS_BASE 0xc0000102
990 %define MSR_K8_TSC_AUX 0xc0000103
991 %define MSR_K8_SYSCFG 0xc0010010
992 %define MSR_K8_HWCR 0xc0010015
993 %define MSR_K8_IORRBASE0 0xc0010016
994 %define MSR_K8_IORRMASK0 0xc0010017
995 %define MSR_K8_IORRBASE1 0xc0010018
996 %define MSR_K8_IORRMASK1 0xc0010019
997 %define MSR_K8_TOP_MEM1 0xc001001a
998 %define MSR_K8_TOP_MEM2 0xc001001d
999 %define MSR_K7_SMBASE 0xc0010111
1000 %define MSR_K7_SMM_ADDR 0xc0010112
1001 %define MSR_K7_SMM_MASK 0xc0010113
1002 %define MSR_K8_NB_CFG 0xc001001f
1003 %define MSR_K8_INT_PENDING 0xc0010055
1004 %define MSR_K8_VM_CR 0xc0010114
1005 %define MSR_K8_VM_CR_DPD RT_BIT_32(0)
1006 %define MSR_K8_VM_CR_R_INIT RT_BIT_32(1)
1007 %define MSR_K8_VM_CR_DIS_A20M RT_BIT_32(2)
1008 %define MSR_K8_VM_CR_LOCK RT_BIT_32(3)
1009 %define MSR_K8_VM_CR_SVM_DISABLE RT_BIT_32(4)
1010 %define MSR_K8_IGNNE 0xc0010115
1011 %define MSR_K8_SMM_CTL 0xc0010116
1012 %define MSR_K8_VM_HSAVE_PA 0xc0010117
1013 %define MSR_AMD_VIRT_SPEC_CTL 0xc001011f
1014 %define MSR_AMD_VIRT_SPEC_CTL_F_SSBD RT_BIT(2)
1015 %ifndef __ASSEMBLER__
1016 %endif
1017 %define X86_PG_ENTRIES 1024
1018 %ifndef __ASSEMBLER__
1019 %endif
1020 %define X86_PG_PAE_ENTRIES 512
1021 %define X86_PG_PAE_PDPE_ENTRIES 4
1022 %define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
1023 %define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
1024 %define X86_PAGE_SIZE X86_PAGE_4K_SIZE
1025 %define X86_PAGE_SHIFT X86_PAGE_4K_SHIFT
1026 %define X86_PAGE_OFFSET_MASK X86_PAGE_4K_OFFSET_MASK
1027 %define X86_PAGE_BASE_MASK X86_PAGE_4K_BASE_MASK
1028 %define X86_PAGE_BASE_MASK_32 X86_PAGE_4K_BASE_MASK_32
1029 %define X86_PAGE_4K_SIZE _4K
1030 %define X86_PAGE_4K_SHIFT 12
1031 %define X86_PAGE_4K_OFFSET_MASK 0xfff
1032 %define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000
1033 %define X86_PAGE_4K_BASE_MASK_32 0xfffff000
1034 %define X86_PAGE_2M_SIZE _2M
1035 %define X86_PAGE_2M_SHIFT 21
1036 %define X86_PAGE_2M_OFFSET_MASK 0x001fffff
1037 %define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000
1038 %define X86_PAGE_2M_BASE_MASK_32 0xffe00000
1039 %define X86_PAGE_4M_SIZE _4M
1040 %define X86_PAGE_4M_SHIFT 22
1041 %define X86_PAGE_4M_OFFSET_MASK 0x003fffff
1042 %define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000
1043 %define X86_PAGE_4M_BASE_MASK_32 0xffc00000
1044 %define X86_PAGE_1G_SIZE _1G
1045 %define X86_PAGE_1G_SHIFT 30
1046 %define X86_PAGE_1G_OFFSET_MASK 0x3fffffff
1047 %define X86_PAGE_1G_BASE_MASK 0xffffffffc0000000
1048 %define X86_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + 0x800000000000 < UINT64_C(0x1000000000000))
1049 %define X86_GET_PAGE_BASE_MASK(a_cShift) (0xffffffffffffffff << (a_cShift))
1050 %define X86_GET_PAGE_OFFSET_MASK(a_cShift) (~X86_GET_PAGE_BASE_MASK(a_cShift))
1051 %define X86_PTE_BIT_P 0
1052 %define X86_PTE_BIT_RW 1
1053 %define X86_PTE_BIT_US 2
1054 %define X86_PTE_BIT_PWT 3
1055 %define X86_PTE_BIT_PCD 4
1056 %define X86_PTE_BIT_A 5
1057 %define X86_PTE_BIT_D 6
1058 %define X86_PTE_BIT_PAT 7
1059 %define X86_PTE_BIT_G 8
1060 %define X86_PTE_PAE_BIT_NX 63
1061 %define X86_PTE_P RT_BIT_32(0)
1062 %define X86_PTE_RW RT_BIT_32(1)
1063 %define X86_PTE_US RT_BIT_32(2)
1064 %define X86_PTE_PWT RT_BIT_32(3)
1065 %define X86_PTE_PCD RT_BIT_32(4)
1066 %define X86_PTE_A RT_BIT_32(5)
1067 %define X86_PTE_D RT_BIT_32(6)
1068 %define X86_PTE_PAT RT_BIT_32(7)
1069 %define X86_PTE_G RT_BIT_32(8)
1070 %define X86_PTE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
1071 %define X86_PTE_PG_MASK ( 0xfffff000 )
1072 %define X86_PTE_PAE_PG_MASK 0x000ffffffffff000
1073 %define X86_PTE_PAE_NX RT_BIT_64(63)
1074 %define X86_PTE_PAE_MBZ_MASK_NX 0x7ff0000000000000
1075 %define X86_PTE_PAE_MBZ_MASK_NO_NX 0xfff0000000000000
1076 %define X86_PTE_LM_MBZ_MASK_NX 0x0000000000000000
1077 %define X86_PTE_LM_MBZ_MASK_NO_NX 0x8000000000000000
1078 %ifndef __ASSEMBLER__
1079 %ifndef VBOX_FOR_DTRACE_LIB
1080 %endif
1081 %ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
1082 %endif
1083 %ifndef VBOX_FOR_DTRACE_LIB
1084 %endif
1085 %ifndef VBOX_FOR_DTRACE_LIB
1086 %endif
1087 %ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
1088 %endif
1089 %ifndef VBOX_FOR_DTRACE_LIB
1090 %endif
1091 %ifndef VBOX_FOR_DTRACE_LIB
1092 %endif
1093 %endif
1094 %define X86_PT_SHIFT 12
1095 %define X86_PT_MASK 0x3ff
1096 %ifndef __ASSEMBLER__
1097 %ifndef VBOX_FOR_DTRACE_LIB
1098 %endif
1099 %endif
1100 %define X86_PT_PAE_SHIFT 12
1101 %define X86_PT_PAE_MASK 0x1ff
1102 %define X86_PDE_P RT_BIT_32(0)
1103 %define X86_PDE_RW RT_BIT_32(1)
1104 %define X86_PDE_US RT_BIT_32(2)
1105 %define X86_PDE_PWT RT_BIT_32(3)
1106 %define X86_PDE_PCD RT_BIT_32(4)
1107 %define X86_PDE_A RT_BIT_32(5)
1108 %define X86_PDE_PS RT_BIT_32(7)
1109 %define X86_PDE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
1110 %define X86_PDE_PG_MASK ( 0xfffff000 )
1111 %define X86_PDE_PAE_PG_MASK 0x000ffffffffff000
1112 %define X86_PDE_PAE_NX RT_BIT_64(63)
1113 %define X86_PDE_PAE_MBZ_MASK_NX 0x7ff0000000000080
1114 %define X86_PDE_PAE_MBZ_MASK_NO_NX 0xfff0000000000080
1115 %define X86_PDE_LM_MBZ_MASK_NX 0x0000000000000080
1116 %define X86_PDE_LM_MBZ_MASK_NO_NX 0x8000000000000080
1117 %ifndef __ASSEMBLER__
1118 %ifndef VBOX_FOR_DTRACE_LIB
1119 %endif
1120 %ifndef VBOX_FOR_DTRACE_LIB
1121 %endif
1122 %endif
1123 %define X86_PDE4M_P RT_BIT_32(0)
1124 %define X86_PDE4M_RW RT_BIT_32(1)
1125 %define X86_PDE4M_US RT_BIT_32(2)
1126 %define X86_PDE4M_PWT RT_BIT_32(3)
1127 %define X86_PDE4M_PCD RT_BIT_32(4)
1128 %define X86_PDE4M_A RT_BIT_32(5)
1129 %define X86_PDE4M_D RT_BIT_32(6)
1130 %define X86_PDE4M_PS RT_BIT_32(7)
1131 %define X86_PDE4M_G RT_BIT_32(8)
1132 %define X86_PDE4M_AVL (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
1133 %define X86_PDE4M_PAT RT_BIT_32(12)
1134 %define X86_PDE4M_PAT_SHIFT (12 - 7)
1135 %define X86_PDE4M_PG_MASK ( 0xffc00000 )
1136 %define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
1137 %define X86_PDE4M_PG_HIGH_SHIFT 19
1138 %define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
1139 %define X86_PDE2M_PAE_PG_MASK 0x000fffffffe00000
1140 %define X86_PDE2M_PAE_NX RT_BIT_64(63)
1141 %define X86_PDE2M_PAE_MBZ_MASK_NX 0x7ff00000001fe000
1142 %define X86_PDE2M_PAE_MBZ_MASK_NO_NX 0xfff00000001fe000
1143 %define X86_PDE2M_LM_MBZ_MASK_NX 0x00000000001fe000
1144 %define X86_PDE2M_LM_MBZ_MASK_NO_NX 0x80000000001fe000
1145 %ifndef __ASSEMBLER__
1146 %ifndef VBOX_FOR_DTRACE_LIB
1147 %endif
1148 %ifndef VBOX_FOR_DTRACE_LIB
1149 %endif
1150 %endif
1151 %ifndef __ASSEMBLER__
1152 %ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
1153 %endif
1154 %ifndef VBOX_FOR_DTRACE_LIB
1155 %endif
1156 %ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
1157 %endif
1158 %ifndef VBOX_FOR_DTRACE_LIB
1159 %endif
1160 %ifndef VBOX_FOR_DTRACE_LIB
1161 %endif
1162 %endif
1163 %define X86_PD_SHIFT 22
1164 %define X86_PD_MASK 0x3ff
1165 %ifndef __ASSEMBLER__
1166 %ifndef VBOX_FOR_DTRACE_LIB
1167 %endif
1168 %endif
1169 %define X86_PD_PAE_SHIFT 21
1170 %define X86_PD_PAE_MASK 0x1ff
1171 %define X86_PDPE_P RT_BIT_32(0)
1172 %define X86_PDPE_RW RT_BIT_32(1)
1173 %define X86_PDPE_US RT_BIT_32(2)
1174 %define X86_PDPE_PWT RT_BIT_32(3)
1175 %define X86_PDPE_PCD RT_BIT_32(4)
1176 %define X86_PDPE_A RT_BIT_32(5)
1177 %define X86_PDPE_LM_PS RT_BIT_32(7)
1178 %define X86_PDPE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
1179 %define X86_PDPE_PG_MASK 0x000ffffffffff000
1180 %define X86_PDPE1G_PG_MASK 0x000fffffc0000000
1181 %define X86_PDPE_PAE_MBZ_MASK 0xfff00000000001e6
1182 %define X86_PDPE_LM_NX RT_BIT_64(63)
1183 %define X86_PDPE_LM_MBZ_MASK_NX 0x0000000000000180
1184 %define X86_PDPE_LM_MBZ_MASK_NO_NX 0x8000000000000180
1185 %define X86_PDPE1G_LM_MBZ_MASK_NX 0x000000003fffe000
1186 %define X86_PDPE1G_LM_MBZ_MASK_NO_NX 0x800000003fffe000
1187 %ifndef __ASSEMBLER__
1188 %ifndef VBOX_FOR_DTRACE_LIB
1189 %endif
1190 %ifndef VBOX_FOR_DTRACE_LIB
1191 %endif
1192 %ifndef VBOX_FOR_DTRACE_LIB
1193 %endif
1194 %ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
1195 %endif
1196 %ifndef VBOX_FOR_DTRACE_LIB
1197 %endif
1198 %ifndef VBOX_FOR_DTRACE_LIB
1199 %endif
1200 %endif
1201 %define X86_PDPT_SHIFT 30
1202 %define X86_PDPT_MASK_PAE 0x3
1203 %define X86_PDPT_MASK_AMD64 0x1ff
1204 %define X86_PML4E_P RT_BIT_32(0)
1205 %define X86_PML4E_RW RT_BIT_32(1)
1206 %define X86_PML4E_US RT_BIT_32(2)
1207 %define X86_PML4E_PWT RT_BIT_32(3)
1208 %define X86_PML4E_PCD RT_BIT_32(4)
1209 %define X86_PML4E_A RT_BIT_32(5)
1210 %define X86_PML4E_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
1211 %define X86_PML4E_PG_MASK 0x000ffffffffff000
1212 %define X86_PML4E_MBZ_MASK_NX 0x0000000000000080
1213 %define X86_PML4E_MBZ_MASK_NO_NX 0x8000000000000080
1214 %define X86_PML4E_NX RT_BIT_64(63)
1215 %ifndef __ASSEMBLER__
1216 %ifndef VBOX_FOR_DTRACE_LIB
1217 %endif
1218 %ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
1219 %endif
1220 %ifndef VBOX_FOR_DTRACE_LIB
1221 %endif
1222 %ifndef VBOX_FOR_DTRACE_LIB
1223 %endif
1224 %endif
1225 %define X86_PML4_SHIFT 39
1226 %define X86_PML4_MASK 0x1ff
1227 %define X86_INVPCID_TYPE_INDV_ADDR 0
1228 %define X86_INVPCID_TYPE_SINGLE_CONTEXT 1
1229 %define X86_INVPCID_TYPE_ALL_CONTEXT_INCL_GLOBAL 2
1230 %define X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL 3
1231 %define X86_INVPCID_TYPE_MAX_VALID X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL
1232 %define X86_FPU_INT64_INDEFINITE INT64_MIN
1233 %define X86_FPU_INT32_INDEFINITE INT32_MIN
1234 %define X86_FPU_INT16_INDEFINITE INT16_MIN
1235 %ifndef __ASSEMBLER__
1236 %ifndef VBOX_FOR_DTRACE_LIB
1237 %endif
1238 %ifndef VBOX_FOR_DTRACE_LIB
1239 %endif
1240 %ifndef VBOX_FOR_DTRACE_LIB
1241 %endif
1242 %ifndef VBOX_FOR_DTRACE_LIB
1243 %endif
1244 %ifndef VBOX_FOR_DTRACE_LIB
1245 %endif
1246 %ifndef VBOX_FOR_DTRACE_LIB
1247 %endif
1248 %ifndef VBOX_FOR_DTRACE_LIB
1249 %endif
1250 %ifndef VBOX_FOR_DTRACE_LIB
1251 %endif
1252 %endif
1253 %define X86_OFF_FXSTATE_RSVD 0x1d0
1254 %define X86_FXSTATE_RSVD_32BIT_MAGIC 0x32b3232b
1255 %ifndef VBOX_FOR_DTRACE_LIB
1256 %endif
1257 %define X86_FSW_IE RT_BIT_32(0)
1258 %define X86_FSW_IE_BIT 0
1259 %define X86_FSW_DE RT_BIT_32(1)
1260 %define X86_FSW_DE_BIT 1
1261 %define X86_FSW_ZE RT_BIT_32(2)
1262 %define X86_FSW_ZE_BIT 2
1263 %define X86_FSW_OE RT_BIT_32(3)
1264 %define X86_FSW_OE_BIT 3
1265 %define X86_FSW_UE RT_BIT_32(4)
1266 %define X86_FSW_UE_BIT 4
1267 %define X86_FSW_PE RT_BIT_32(5)
1268 %define X86_FSW_PE_BIT 5
1269 %define X86_FSW_SF RT_BIT_32(6)
1270 %define X86_FSW_SF_BIT 6
1271 %define X86_FSW_ES RT_BIT_32(7)
1272 %define X86_FSW_ES_BIT 7
1273 %define X86_FSW_XCPT_MASK 0x007f
1274 %define X86_FSW_XCPT_ES_MASK 0x00ff
1275 %define X86_FSW_C0 RT_BIT_32(X86_FSW_C0_BIT)
1276 %define X86_FSW_C0_BIT 8
1277 %define X86_FSW_C1 RT_BIT_32(X86_FSW_C1_BIT)
1278 %define X86_FSW_C1_BIT 9
1279 %define X86_FSW_C2 RT_BIT_32(X86_FSW_C2_BIT)
1280 %define X86_FSW_C2_BIT 10
1281 %define X86_FSW_TOP_MASK 0x3800
1282 %define X86_FSW_TOP_SHIFT 11
1283 %define X86_FSW_TOP_SMASK 0x0007
1284 %define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
1285 %define X86_FSW_TOP_GET_ST(a_uFsw, a_iSt) ((((a_uFsw) >> X86_FSW_TOP_SHIFT) + (a_iSt)) & X86_FSW_TOP_SMASK)
1286 %define X86_FSW_C3 RT_BIT_32(X86_FSW_C3_BIT)
1287 %define X86_FSW_C3_BIT 14
1288 %define X86_FSW_C_MASK 0x4700
1289 %define X86_FSW_B RT_BIT_32(15)
1290 %define X86_FSW_CX_TO_QUOTIENT(a_fFsw) \
1291 ( (((a_fFsw) & X86_FSW_C1) >> (X86_FSW_C1_BIT - 0)) \
1292 | (((a_fFsw) & X86_FSW_C3) >> (X86_FSW_C3_BIT - 1)) \
1293 | (((a_fFsw) & X86_FSW_C0) >> (X86_FSW_C0_BIT - 2)) )
1294 %define X86_FSW_CX_FROM_QUOTIENT(a_uQuotient) \
1295 ( ((uint16_t)((a_uQuotient) & 1) << (X86_FSW_C1_BIT - 0)) \
1296 | ((uint16_t)((a_uQuotient) & 2) << (X86_FSW_C3_BIT - 1)) \
1297 | ((uint16_t)((a_uQuotient) & 4) << (X86_FSW_C0_BIT - 2)) )
1298 %define X86_FCW_IM RT_BIT_32(0)
1299 %define X86_FCW_IM_BIT 0
1300 %define X86_FCW_DM RT_BIT_32(1)
1301 %define X86_FCW_DM_BIT 1
1302 %define X86_FCW_ZM RT_BIT_32(2)
1303 %define X86_FCW_ZM_BIT 2
1304 %define X86_FCW_OM RT_BIT_32(3)
1305 %define X86_FCW_OM_BIT 3
1306 %define X86_FCW_UM RT_BIT_32(4)
1307 %define X86_FCW_UM_BIT 4
1308 %define X86_FCW_PM RT_BIT_32(5)
1309 %define X86_FCW_PM_BIT 5
1310 %define X86_FCW_MASK_ALL 0x007f
1311 %define X86_FCW_XCPT_MASK 0x003f
1312 %define X86_FCW_PC_MASK 0x0300
1313 %define X86_FCW_PC_SHIFT 8
1314 %define X86_FCW_PC_24 0x0000
1315 %define X86_FCW_PC_RSVD 0x0100
1316 %define X86_FCW_PC_53 0x0200
1317 %define X86_FCW_PC_64 0x0300
1318 %define X86_FCW_RC_MASK 0x0c00
1319 %define X86_FCW_RC_SHIFT 10
1320 %define X86_FCW_RC_NEAREST 0x0000
1321 %define X86_FCW_RC_DOWN 0x0400
1322 %define X86_FCW_RC_UP 0x0800
1323 %define X86_FCW_RC_ZERO 0x0c00
1324 %define X86_FCW_IC_MASK 0x1000
1325 %define X86_FCW_IC_AFFINE 0x1000
1326 %define X86_FCW_IC_PROJECTIVE 0x0000
1327 %define X86_FCW_ZERO_MASK 0xf080
1328 %define X86_MXCSR_IE RT_BIT_32(0)
1329 %define X86_MXCSR_IE_BIT 0
1330 %define X86_MXCSR_DE RT_BIT_32(1)
1331 %define X86_MXCSR_DE_BIT 1
1332 %define X86_MXCSR_ZE RT_BIT_32(2)
1333 %define X86_MXCSR_ZE_BIT 2
1334 %define X86_MXCSR_OE RT_BIT_32(3)
1335 %define X86_MXCSR_OE_BIT 3
1336 %define X86_MXCSR_UE RT_BIT_32(4)
1337 %define X86_MXCSR_UE_BIT 4
1338 %define X86_MXCSR_PE RT_BIT_32(5)
1339 %define X86_MXCSR_PE_BIT 5
1340 %define X86_MXCSR_XCPT_FLAGS 0x003f
1341 %define X86_MXCSR_DAZ RT_BIT_32(6)
1342 %define X86_MXCSR_DAZ_BIT 6
1343 %define X86_MXCSR_IM RT_BIT_32(7)
1344 %define X86_MXCSR_IM_BIT 7
1345 %define X86_MXCSR_DM RT_BIT_32(8)
1346 %define X86_MXCSR_DM_BIT 8
1347 %define X86_MXCSR_ZM RT_BIT_32(9)
1348 %define X86_MXCSR_ZM_BIT 9
1349 %define X86_MXCSR_OM RT_BIT_32(10)
1350 %define X86_MXCSR_OM_BIT 10
1351 %define X86_MXCSR_UM RT_BIT_32(11)
1352 %define X86_MXCSR_UM_BIT 11
1353 %define X86_MXCSR_PM RT_BIT_32(12)
1354 %define X86_MXCSR_PM_BIT 12
1355 %define X86_MXCSR_XCPT_MASK 0x1f80
1356 %define X86_MXCSR_XCPT_MASK_SHIFT 7
1357 %define X86_MXCSR_RC_MASK 0x6000
1358 %define X86_MXCSR_RC_SHIFT 13
1359 %define X86_MXCSR_RC_NEAREST 0x0000
1360 %define X86_MXCSR_RC_DOWN 0x2000
1361 %define X86_MXCSR_RC_UP 0x4000
1362 %define X86_MXCSR_RC_ZERO 0x6000
1363 %define X86_MXCSR_FZ RT_BIT_32(15)
1364 %define X86_MXCSR_FZ_BIT 15
1365 %define X86_MXCSR_MM RT_BIT_32(17)
1366 %define X86_MXCSR_MM_BIT 17
1367 %define X86_MXCSR_ZERO_MASK 0xfffd0000
1368 %ifndef __ASSEMBLER__
1369 %ifndef VBOX_FOR_DTRACE_LIB
1370 %endif
1371 %ifndef VBOX_FOR_DTRACE_LIB
1372 %endif
1373 %ifndef VBOX_FOR_DTRACE_LIB
1374 %endif
1375 %ifndef VBOX_FOR_DTRACE_LIB
1376 %endif
1377 %ifndef VBOX_FOR_DTRACE_LIB
1378 %endif
1379 %ifndef VBOX_FOR_DTRACE_LIB
1380 %endif
1381 %ifndef VBOX_FOR_DTRACE_LIB
1382 %endif
1383 %ifndef VBOX_FOR_DTRACE_LIB
1384 %endif
1385 %ifndef VBOX_FOR_DTRACE_LIB
1386 %endif
1387 %endif
1388 %define XSAVE_C_X87_BIT 0
1389 %define XSAVE_C_X87 RT_BIT_64(XSAVE_C_X87_BIT)
1390 %define XSAVE_C_SSE_BIT 1
1391 %define XSAVE_C_SSE RT_BIT_64(XSAVE_C_SSE_BIT)
1392 %define XSAVE_C_YMM_BIT 2
1393 %define XSAVE_C_YMM RT_BIT_64(XSAVE_C_YMM_BIT)
1394 %define XSAVE_C_BNDREGS_BIT 3
1395 %define XSAVE_C_BNDREGS RT_BIT_64(XSAVE_C_BNDREGS_BIT)
1396 %define XSAVE_C_BNDCSR_BIT 4
1397 %define XSAVE_C_BNDCSR RT_BIT_64(XSAVE_C_BNDCSR_BIT)
1398 %define XSAVE_C_OPMASK_BIT 5
1399 %define XSAVE_C_OPMASK RT_BIT_64(XSAVE_C_OPMASK_BIT)
1400 %define XSAVE_C_ZMM_HI256_BIT 6
1401 %define XSAVE_C_ZMM_HI256 RT_BIT_64(XSAVE_C_ZMM_HI256_BIT)
1402 %define XSAVE_C_ZMM_16HI_BIT 7
1403 %define XSAVE_C_ZMM_16HI RT_BIT_64(XSAVE_C_ZMM_16HI_BIT)
1404 %define XSAVE_C_PKRU_BIT 9
1405 %define XSAVE_C_PKRU RT_BIT_64(XSAVE_C_PKRU_BIT)
1406 %define XSAVE_C_LWP_BIT 62
1407 %define XSAVE_C_LWP RT_BIT_64(XSAVE_C_LWP_BIT)
1408 %define XSAVE_C_X_BIT 63
1409 %define XSAVE_C_X RT_BIT_64(XSAVE_C_X_BIT)
1410 %ifndef __ASSEMBLER__
1411 %ifndef VBOX_FOR_DTRACE_LIB
1412 %endif
1413 %endif
1414 %define X86DESCATTR_TYPE 0x0000000f
1415 %define X86DESCATTR_DT 0x00000010
1416 %define X86DESCATTR_DPL 0x00000060
1417 %define X86DESCATTR_DPL_SHIFT 5
1418 %define X86DESCATTR_P 0x00000080
1419 %define X86DESCATTR_LIMIT_HIGH 0x00000f00
1420 %define X86DESCATTR_AVL 0x00001000
1421 %define X86DESCATTR_L 0x00002000
1422 %define X86DESCATTR_D 0x00004000
1423 %define X86DESCATTR_G 0x00008000
1424 %define X86DESCATTR_UNUSABLE 0x00010000
1425 %ifndef __ASSEMBLER__
1426 %ifndef VBOX_FOR_DTRACE_LIB
1427 %endif
1428 %endif
1429 %ifndef VBOX_FOR_DTRACE_LIB
1430 %ifndef __ASSEMBLER__
1431 %endif
1432 %define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0)
1433 %define X86DESCGENERIC_BIT_OFF_BASE_LOW (16)
1434 %define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32)
1435 %define X86DESCGENERIC_BIT_OFF_TYPE (40)
1436 %define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44)
1437 %define X86DESCGENERIC_BIT_OFF_DPL (45)
1438 %define X86DESCGENERIC_BIT_OFF_PRESENT (47)
1439 %define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48)
1440 %define X86DESCGENERIC_BIT_OFF_AVAILABLE (52)
1441 %define X86DESCGENERIC_BIT_OFF_LONG (53)
1442 %define X86DESCGENERIC_BIT_OFF_DEF_BIG (54)
1443 %define X86DESCGENERIC_BIT_OFF_GRANULARITY (55)
1444 %define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56)
1445 %define X86LAR_F_TYPE 0x0f00
1446 %define X86LAR_F_DT 0x1000
1447 %define X86LAR_F_DPL 0x6000
1448 %define X86LAR_F_DPL_SHIFT 13
1449 %define X86LAR_F_P 0x8000
1450 %define X86LAR_F_AVL 0x00100000
1451 %define X86LAR_F_L 0x00200000
1452 %define X86LAR_F_D 0x00400000
1453 %define X86LAR_F_G 0x00800000
1454 %ifndef __ASSEMBLER__
1455 %endif
1456 %endif
1457 %ifndef __ASSEMBLER__
1458 %ifndef VBOX_FOR_DTRACE_LIB
1459 %endif
1460 %ifndef VBOX_FOR_DTRACE_LIB
1461 %endif
1462 %endif
1463 %ifndef __ASSEMBLER__
1464 %ifndef VBOX_FOR_DTRACE_LIB
1465 %endif
1466 %ifndef VBOX_FOR_DTRACE_LIB
1467 %endif
1468 %ifndef VBOX_FOR_DTRACE_LIB
1469 %endif
1470 %if HC_ARCH_BITS == 64
1471 %else
1472 %endif
1473 %if HC_ARCH_BITS == 64
1474 %else
1475 %endif
1476 %if HC_ARCH_BITS == 64
1477 %else
1478 %endif
1479 %endif
1480 %define X86_SEL_TYPE_CODE 8
1481 %define X86_SEL_TYPE_MEMORY RT_BIT_32(4)
1482 %define X86_SEL_TYPE_ACCESSED 1
1483 %define X86_SEL_TYPE_DOWN 4
1484 %define X86_SEL_TYPE_CONF 4
1485 %define X86_SEL_TYPE_WRITE 2
1486 %define X86_SEL_TYPE_READ 2
1487 %define X86_SEL_TYPE_READ_BIT 1
1488 %define X86_SEL_TYPE_RO 0
1489 %define X86_SEL_TYPE_RO_ACC (0 | X86_SEL_TYPE_ACCESSED)
1490 %define X86_SEL_TYPE_RW 2
1491 %define X86_SEL_TYPE_RW_ACC (2 | X86_SEL_TYPE_ACCESSED)
1492 %define X86_SEL_TYPE_RO_DOWN 4
1493 %define X86_SEL_TYPE_RO_DOWN_ACC (4 | X86_SEL_TYPE_ACCESSED)
1494 %define X86_SEL_TYPE_RW_DOWN 6
1495 %define X86_SEL_TYPE_RW_DOWN_ACC (6 | X86_SEL_TYPE_ACCESSED)
1496 %define X86_SEL_TYPE_EO (0 | X86_SEL_TYPE_CODE)
1497 %define X86_SEL_TYPE_EO_ACC (0 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
1498 %define X86_SEL_TYPE_ER (2 | X86_SEL_TYPE_CODE)
1499 %define X86_SEL_TYPE_ER_ACC (2 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
1500 %define X86_SEL_TYPE_EO_CONF (4 | X86_SEL_TYPE_CODE)
1501 %define X86_SEL_TYPE_EO_CONF_ACC (4 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
1502 %define X86_SEL_TYPE_ER_CONF (6 | X86_SEL_TYPE_CODE)
1503 %define X86_SEL_TYPE_ER_CONF_ACC (6 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
1504 %define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
1505 %define X86_SEL_TYPE_SYS_UNDEFINED 0
1506 %define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
1507 %define X86_SEL_TYPE_SYS_LDT 2
1508 %define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
1509 %define X86_SEL_TYPE_SYS_286_CALL_GATE 4
1510 %define X86_SEL_TYPE_SYS_TASK_GATE 5
1511 %define X86_SEL_TYPE_SYS_286_INT_GATE 6
1512 %define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
1513 %define X86_SEL_TYPE_SYS_UNDEFINED2 8
1514 %define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
1515 %define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
1516 %define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
1517 %define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
1518 %define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
1519 %define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
1520 %define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
1521 %define AMD64_SEL_TYPE_SYS_LDT 2
1522 %define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
1523 %define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
1524 %define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
1525 %define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
1526 %define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
1527 %define X86_DESC_TYPE_MASK (RT_BIT_32(8) | RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
1528 %define X86_DESC_S RT_BIT_32(12)
1529 %define X86_DESC_DPL (RT_BIT_32(13) | RT_BIT_32(14))
1530 %define X86_DESC_P RT_BIT_32(15)
1531 %define X86_DESC_AVL RT_BIT_32(20)
1532 %define X86_DESC_DB RT_BIT_32(22)
1533 %define X86_DESC_G RT_BIT_32(23)
1534 %define X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN 0x2b
1535 %define X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN 0x67
1536 %ifndef __ASSEMBLER__
1537 %ifndef VBOX_FOR_DTRACE_LIB
1538 %endif
1539 %ifndef VBOX_FOR_DTRACE_LIB
1540 %endif
1541 %ifndef VBOX_FOR_DTRACE_LIB
1542 %endif
1543 %endif
1544 %define X86_SEL_SHIFT 3
1545 %define X86_SEL_MASK 0xfff8
1546 %define X86_SEL_MASK_OFF_RPL 0xfffc
1547 %define X86_SEL_LDT 0x0004
1548 %define X86_SEL_RPL 0x0003
1549 %define X86_SEL_RPL_LDT 0x0007
1550 %ifndef __ASSEMBLER__
1551 %endif
1552 %define X86_XCPT_LAST 0x1f
1553 %define X86_TRAP_ERR_EXTERNAL 1
1554 %define X86_TRAP_ERR_IDT 2
1555 %define X86_TRAP_ERR_TI 4
1556 %define X86_TRAP_ERR_SEL_MASK 0xfff8
1557 %define X86_TRAP_ERR_SEL_SHIFT 3
1558 %define X86_TRAP_PF_P RT_BIT_32(0)
1559 %define X86_TRAP_PF_RW RT_BIT_32(1)
1560 %define X86_TRAP_PF_US RT_BIT_32(2)
1561 %define X86_TRAP_PF_RSVD RT_BIT_32(3)
1562 %define X86_TRAP_PF_ID RT_BIT_32(4)
1563 %define X86_TRAP_PF_PK RT_BIT_32(5)
1564 %ifndef __ASSEMBLER__
1565 %ifndef VBOX_FOR_DTRACE_LIB
1566 %else
1567 %endif
1568 %ifndef VBOX_FOR_DTRACE_LIB
1569 %else
1570 %endif
1571 %endif
1572 %define X86_MODRM_RM_MASK 0x07
1573 %define X86_MODRM_REG_MASK 0x38
1574 %define X86_MODRM_REG_SMASK 0x07
1575 %define X86_MODRM_REG_SHIFT 3
1576 %define X86_MODRM_MOD_MASK 0xc0
1577 %define X86_MODRM_MOD_SMASK 0x03
1578 %define X86_MODRM_MOD_SHIFT 6
1579 %define X86_MOD_MEM0 0
1580 %define X86_MOD_MEM1 1
1581 %define X86_MOD_MEM4 2
1582 %define X86_MOD_REG 3
1583 %ifndef VBOX_FOR_DTRACE_LIB
1584 %define X86_MODRM_MAKE(a_Mod, a_Reg, a_RegMem) (((a_Mod) << X86_MODRM_MOD_SHIFT) | ((a_Reg) << X86_MODRM_REG_SHIFT) | (a_RegMem))
1585 %endif
1586 %define X86_SIB_BASE_MASK 0x07
1587 %define X86_SIB_INDEX_MASK 0x38
1588 %define X86_SIB_INDEX_SMASK 0x07
1589 %define X86_SIB_INDEX_SHIFT 3
1590 %define X86_SIB_SCALE_MASK 0xc0
1591 %define X86_SIB_SCALE_SMASK 0x03
1592 %define X86_SIB_SCALE_SHIFT 6
1593 %ifndef VBOX_FOR_DTRACE_LIB
1594 %define X86_SIB_MAKE(a_BaseReg, a_IndexReg, a_Scale) \
1595 (((a_Scale) << X86_SIB_SCALE_SHIFT) | ((a_IndexReg) << X86_SIB_INDEX_SHIFT) | (a_BaseReg))
1596 %endif
1597 %define X86_GREG_xAX 0
1598 %define X86_GREG_xCX 1
1599 %define X86_GREG_xDX 2
1600 %define X86_GREG_xBX 3
1601 %define X86_GREG_xSP 4
1602 %define X86_GREG_xBP 5
1603 %define X86_GREG_xSI 6
1604 %define X86_GREG_xDI 7
1605 %define X86_GREG_x8 8
1606 %define X86_GREG_x9 9
1607 %define X86_GREG_x10 10
1608 %define X86_GREG_x11 11
1609 %define X86_GREG_x12 12
1610 %define X86_GREG_x13 13
1611 %define X86_GREG_x14 14
1612 %define X86_GREG_x15 15
1613 %define X86_GREG_COUNT 16
1614 %define X86_SREG_ES 0
1615 %define X86_SREG_CS 1
1616 %define X86_SREG_SS 2
1617 %define X86_SREG_DS 3
1618 %define X86_SREG_FS 4
1619 %define X86_SREG_GS 5
1620 %define X86_SREG_COUNT 6
1621 %define X86_OP_PRF_CS 0x2e
1622 %define X86_OP_PRF_SS 0x36
1623 %define X86_OP_PRF_DS 0x3e
1624 %define X86_OP_PRF_ES 0x26
1625 %define X86_OP_PRF_FS 0x64
1626 %define X86_OP_PRF_GS 0x65
1627 %define X86_OP_PRF_SIZE_OP 0x66
1628 %define X86_OP_PRF_SIZE_ADDR 0x67
1629 %define X86_OP_PRF_LOCK 0xf0
1630 %define X86_OP_PRF_REPZ 0xf3
1631 %define X86_OP_PRF_REPNZ 0xf2
1632 %define X86_OP_REX 0x40
1633 %define X86_OP_REX_B 0x41
1634 %define X86_OP_REX_X 0x42
1635 %define X86_OP_REX_R 0x44
1636 %define X86_OP_REX_W 0x48
1637 %define X86_OP_VEX3 0xc4
1638 %define X86_OP_VEX2 0xc5
1639 %define X86_OP_VEX2_BYTE1_P_MASK 0x3
1640 %define X86_OP_VEX2_BYTE1_P_NO_PRF 0
1641 %define X86_OP_VEX2_BYTE1_P_066H 1
1642 %define X86_OP_VEX2_BYTE1_P_0F3H 2
1643 %define X86_OP_VEX2_BYTE1_P_0F2H 3
1644 %define X86_OP_VEX2_BYTE1_L RT_BIT(2)
1645 %define X86_OP_VEX2_BYTE1_VVVV_MASK 0x78
1646 %define X86_OP_VEX2_BYTE1_VVVV_SHIFT 3
1647 %define X86_OP_VEX2_BYTE1_VVVV_NONE 15
1648 %define X86_OP_VEX2_BYTE1_R RT_BIT(7)
1649 %define X86_OP_VEX2_BYTE1_MAKE(a_fRegW, a_iSrcReg, a_f256BitAvx, a_fPrf) \
1650 ( ((a_fRegW) ? 0 : X86_OP_VEX2_BYTE1_R) \
1651 | (~((uint8_t)(a_iSrcReg) & 0xf) << X86_OP_VEX2_BYTE1_VVVV_SHIFT) \
1652 | ((a_f256BitAvx) ? X86_OP_VEX2_BYTE1_L : 0) \
1653 | ((a_fPrf) & X86_OP_VEX2_BYTE1_P_MASK))
1654 %define X86_OP_VEX2_BYTE1_MAKE_NO_VVVV(a_fRegW, a_f256BitAvx, a_fPrf) \
1655 ( ((a_fRegW) ? 0 : X86_OP_VEX2_BYTE1_R) \
1656 | (X86_OP_VEX2_BYTE1_VVVV_NONE << X86_OP_VEX2_BYTE1_VVVV_SHIFT) \
1657 | ((a_f256BitAvx) ? X86_OP_VEX2_BYTE1_L : 0) \
1658 | ((a_fPrf) & X86_OP_VEX2_BYTE1_P_MASK))
1659 %define X86_OP_VEX3_BYTE1_MAP_MASK 0x1f
1660 %define X86_OP_VEX3_BYTE1_B RT_BIT(5)
1661 %define X86_OP_VEX3_BYTE1_X RT_BIT(6)
1662 %define X86_OP_VEX3_BYTE1_R RT_BIT(7)
1663 %define X86_OP_VEX3_BYTE1_MAKE(a_idxMap, a_B, a_X, a_R) \
1664 ( (uint8_t)(a_idxMap) \
1665 | ((a_B) ? 0 : X86_OP_VEX3_BYTE1_B) \
1666 | ((a_X) ? 0 : X86_OP_VEX3_BYTE1_X) \
1667 | ((a_R) ? 0 : X86_OP_VEX3_BYTE1_R))
1668 %define X86_OP_VEX3_BYTE2_P_MASK 0x3
1669 %define X86_OP_VEX3_BYTE2_P_NO_PRF 0
1670 %define X86_OP_VEX3_BYTE2_P_066H 1
1671 %define X86_OP_VEX3_BYTE2_P_0F3H 2
1672 %define X86_OP_VEX3_BYTE2_P_0F2H 3
1673 %define X86_OP_VEX3_BYTE2_L RT_BIT(2)
1674 %define X86_OP_VEX3_BYTE2_VVVV_MASK 0x78
1675 %define X86_OP_VEX3_BYTE2_VVVV_SHIFT 3
1676 %define X86_OP_VEX3_BYTE2_VVVV_NONE 15
1677 %define X86_OP_VEX3_BYTE2_W RT_BIT(7)
1678 %define X86_OP_VEX3_BYTE2_MAKE(a_f64BitOpSize, a_iSrcReg, a_f256BitAvx, a_fPrf) \
1679 ( ((a_f64BitOpSize) ? X86_OP_VEX3_BYTE2_W : 0) \
1680 | ((~((uint8_t)(a_iSrcReg) & 0xf) << X86_OP_VEX3_BYTE2_VVVV_SHIFT) & X86_OP_VEX3_BYTE2_VVVV_MASK) \
1681 | ((a_f256BitAvx) ? X86_OP_VEX3_BYTE2_L : 0) \
1682 | ((a_fPrf) & X86_OP_VEX3_BYTE2_P_MASK))
1683 %define X86_OP_VEX3_BYTE2_MAKE_NO_VVVV(a_f64BitOpSize, a_f256BitAvx, a_fPrf) \
1684 ( ((a_f64BitOpSize) ? X86_OP_VEX3_BYTE2_W : 0) \
1685 | (X86_OP_VEX3_BYTE2_VVVV_NONE << X86_OP_VEX3_BYTE2_VVVV_SHIFT) \
1686 | ((a_f256BitAvx) ? X86_OP_VEX3_BYTE2_L : 0) \
1687 | ((a_fPrf) & X86_OP_VEX3_BYTE2_P_MASK))
1688 %endif
1689 %include "iprt/x86extra.mac"