counter.vhd

   1 library ieee;
   2     use ieee.std_logic_1164.all;
   3     use ieee.numeric_std.all;
   4
   5 entity counter is
   6     generic (
   7         width : in natural := 32
   8         );
   9     port (
  10         rst   : in std_logic;
  11         clk   : in std_logic;
  12         load  : in std_logic;
  13         d     : in std_logic_vector(width-1 downto 0);
  14         q     : out std_logic_vector(width-1 downto 0)
  15         );
  16 end entity counter;
  17
  18 architecture rtl of counter is
  19
  20 begin
  21     process(all) is
  22     begin
  23         if rst then
  24             q <= (others => '0');
  25         elsif rising_edge(clk) then
  26             if load then
  27                 q <= d;
  28             else
  29                 q <= std_logic_vector(unsigned(q) + 1);
  30             end if;
  31         end if;
  32     end process;
  33
  34 end architecture rtl;