add ram dual and single port
[vhdl_digital_base_blocks.git] / debouncer.vhd
blob639d2bef2b025d9a3ef7680db3c97a1df2193c2b
1 library ieee;
2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.ALL;
4 use work.debounce_pkg.ALL;
6 entity debouncer is
8 port
10 clk : in std_logic;
11 rst : in std_logic;
13 pbutton : in std_logic;
14 pb_deb : out std_logic
17 end entity;
19 architecture rtl of debouncer is
21 signal cnt_deb : unsigned(DIV_DEB_W-1 downto 0);
22 signal clk_en : std_logic;
23 signal cnt_threshold : unsigned(DEB_LEN_W-1 downto 0);
24 signal pb_deb_i : std_logic;
25 signal pbutton_s : std_logic;
27 begin
29 -- downcounter for input clock freq. division
30 process (rst, clk)
31 begin
32 if (rst = '1') then
33 cnt_deb <= (others => '0');
34 clk_en <= '0';
35 elsif (rising_edge(clk)) then
36 if (cnt_deb = 0) then
37 cnt_deb <= to_unsigned(DIV_DEB, cnt_deb'length);
38 clk_en <= '1';
39 else
40 cnt_deb <= cnt_deb-1;
41 clk_en <= '0';
42 end if;
43 end if;
44 end process;
46 -- sample pushbutton and debounce
47 process (rst, clk)
48 begin
49 if (rst = '1') then
50 cnt_threshold <= (others => '0');
51 pbutton_s <= '0';
52 pb_deb_i <= '0';
53 elsif (rising_edge(clk)) then
54 pbutton_s <= pbutton;
55 if (pbutton_s = '1' and clk_en = '1') then
56 if (cnt_threshold < (DEB_LEN-1) ) then
57 cnt_threshold <= cnt_threshold + 1;
58 end if;
59 end if;
60 if (pbutton_s = '0' and clk_en = '1') then
61 if (cnt_threshold > 0 ) then
62 cnt_threshold <= cnt_threshold - 1;
63 end if;
64 end if;
66 -- Activate output with hysteresis
67 if (pb_deb_i = '0' and (cnt_threshold > DEB_THRES_HI)) then
68 pb_deb_i <= '1';
69 end if;
70 if (pb_deb_i = '1' and (cnt_threshold < DEB_THRES_LO)) then
71 pb_deb_i <= '0';
72 end if;
74 end if;
75 end process;
77 pb_deb <= pb_deb_i;
78 end rtl;