mux2to1.vhd

   1 -- 2 to 1 mux
   2
   3 library ieee;
   4     use ieee.std_logic_1164.all;
   5     use ieee.std_logic_arith.all;
   6     use ieee.std_logic_unsigned.all;
   7
   8 entity mux2to1 is
   9     port (
  10         a : in std_logic;
  11         b : in std_logic;
  12         s : in std_logic;
  13         y : out std_logic
  14         );
  15 end mux2to1;
  16
  17 architecture behav1 of mux2to1 is
  18 begin
  19     process(a, b, s)
  20     begin
  21     if (s = '1') then
  22         y <= a;
  23     else
  24         y <= b;
  25     end if;
  26     end process;
  27 end behav1;
  28
  29 architecture behav2 of mux2to1 is
  30 begin
  31     process(a, b, s)
  32     begin
  33     case s is
  34         when '1' =>
  35             y <= a;
  36         when others=>
  37             y <= b;
  38     end case;
  39     end process;
  40 end behav2;
  41
  42 architecture behav3 of mux2to1 is
  43 begin
  44     y <= a when (s = '1') else b;
  45 end behav3;
  46
  47 architecture behav4 of mux2to1 is
  48 begin
  49     with s select
  50         y <= a when '1', b when others;
  51 end behav4;