amd/gcn/pm4/regs.h

   1 #ifndef REGS_H
   2 #define REGS_H
   3 /*****************************************************************************/
   4 /* GFX6 */
   5 /*
   6  * ABBREVIATIONS:
   7  *
   8  * AA : AntiAliasing (MultiSample AntiAliasing, MSAA)
   9  * ADDR : ADDRess
  10  * ADJ : ADJus
  11  * BARYC : BARYCentric
  12  * BR : Bottom Right
  13  * CB : Color Block
  14  * CL : CLipper
  15  * CNTL: CoNTroL
  16  * COL : COLor
  17  * CONFIG : CONFIGuration
  18  * DB : Depth Block
  19  * DISC : DISCard
  20  * EN/ENA : ENAble
  21  * GB : Guard Band
  22  * GS : Geometry Shader
  23  * HI : HIgh ("high 32 bits of a 64 bits word)
  24  * HORZ : HORiZontal
  25  * IB : Indirect Buffer
  26  * IN : INput
  27  * INFO : INFOrmation
  28  * INTERP : INTERPolator
  29  * LO : LOw ("low 32 bits" of a 64 bits word)
  30  * LOCS : LOCationS
  31  * OFF : OFFset
  32  * PA : Primitive Assembler
  33  * PGM : ProGraM
  34  * POS : POSition
  35  * PRIM : PRIMitive
  36  * PS : Pixel Shader
  37  * RECT : RECTangle
  38  * RSRC : ReSouRCe
  39  * SC : Scan Converter
  40  * SPI : Shader Processor Interpolator
  41  * SU : Setup Unit
  42  * TE : Transform/Tesselation Engine
  43  * TL : Top Left
  44  * TMP : TeMPorary
  45  * VERT : VERTical
  46  * VGT : Vertex Grouper Tesselator
  47  * VPORT : ViewPORT
  48  * VS : Vertex Shader
  49  * VTE : Vertex Transform Engine
  50  * VTX : VerTeX
  51  * UCP: User Clip Plane
  52  */
  53 /*****************************************************************************/
  54 constant {
  55         reg_blk_lo = 0,
  56         reg_blk_cfg = 1, /* only 1 unlike ctxs */
  57         reg_blk_sh = 2,
  58         reg_blk_ctx = 3 /* there are N (depends on GFX) ctxs */
  59 };
  60
  61 /*
  62  * gfx[6-10]
  63  * 64KiB reg space:
  64  * low 32KiB, use PKT0:
  65  *   0x00000000-0x00007ffff byte ofts
  66  *   0x00000000-0x00001ffff w ofts
  67  * hi 32KiB, use PKT3 with the right SET_* opcode
  68  *   0x00008000-0x0000fffff byte ofts
  69  *   0x00002000-0x00003ffff w ofts
  70  */
  71 u64 reg_blk_w_ofts[] = {
  72         [reg_blk_lo]    = 0,
  73         /*-------------------------------------------------------------------*/
  74         [reg_blk_cfg]   = 0x0000000000002000,
  75         [reg_blk_sh]    = 0x0000000000002c00,
  76         [reg_blk_ctx]   = 0x000000000000a000,
  77 };
  78
  79 struct reg_desc {
  80         u8 blk;
  81         u64 w_oft;
  82         u8 *name;
  83 };
  84
  85 /* may add a gfx blk version mask, gfx6 for now */
  86 struct reg_desc reg_descs[] = {
  87         {
  88                 reg_blk_cfg,
  89                 0x256,
  90                 "VGT_PRIMITIVE_TYPE"
  91         },
  92         /*-------------------------------------------------------------------*/
  93         {
  94                 reg_blk_sh,
  95                 0x8,
  96                 "SPI_SHADER_PGM_LO_PS"
  97         },
  98         {
  99                 reg_blk_sh,
 100                 0x9,
 101                 "SPI_SHADER_PGM_HI_PS"
 102         },
 103         {
 104                 reg_blk_sh,
 105                 0xa,
 106                 "SPI_SHADER_PGM_RSRC1_PS"
 107         },
 108         {
 109                 reg_blk_sh,
 110                 0xb,
 111                 "SPI_SHADER_PGM_RSRC2_PS"
 112         },
 113         {
 114                 reg_blk_sh,
 115                 0xe,
 116                 "SPI_SHADER_USER_DATA_PS_2"
 117         },
 118         {
 119                 reg_blk_sh,
 120                 0xf,
 121                 "SPI_SHADER_USER_DATA_PS_3"
 122         },
 123         {
 124                 reg_blk_sh,
 125                 0x48,
 126                 "SPI_SHADER_PGM_LO_VS"
 127         },
 128         {
 129                 reg_blk_sh,
 130                 0x49,
 131                 "SPI_SHADER_PGM_HI_VS"
 132         },
 133         {
 134                 reg_blk_sh,
 135                 0x4a,
 136                 "SPI_SHADER_PGM_RSRC1_VS"
 137         },
 138         {
 139                 reg_blk_sh,
 140                 0x4b,
 141                 "SPI_SHADER_PGM_RSRC2_VS"
 142         },
 143         {
 144                 reg_blk_sh,
 145                 0x4e,
 146                 "SPI_SHADER_USER_DATA_VS_2"
 147         },
 148         {
 149                 reg_blk_sh,
 150                 0x4f,
 151                 "SPI_SHADER_USER_DATA_VS_3"
 152         },
 153         {
 154                 reg_blk_sh,
 155                 0x50,
 156                 "SPI_SHADER_USER_DATA_VS_4"
 157         },
 158         {
 159                 reg_blk_sh,
 160                 0x51,
 161                 "SPI_SHADER_USER_DATA_VS_5"
 162         },
 163         {
 164                 reg_blk_sh,
 165                 0x52,
 166                 "SPI_SHADER_USER_DATA_VS_6"
 167         },
 168         {
 169                 reg_blk_sh,
 170                 0x53,
 171                 "SPI_SHADER_USER_DATA_VS_7"
 172         },
 173         /*-------------------------------------------------------------------*/
 174         {
 175                 reg_blk_ctx,
 176                 0x0,
 177                 "DB_RENDER_CONTROL"
 178         },
 179         {
 180                 reg_blk_ctx,
 181                 0x3,
 182                 "DB_RENDER_OVERRIDE"
 183         },
 184         {
 185                 reg_blk_ctx,
 186                 0x4,
 187                 "DB_RENDER_OVERRIDE2"
 188         },
 189         {
 190                 reg_blk_ctx,
 191                 0x10,
 192                 "DB_Z_INFO"
 193         },
 194         {
 195                 reg_blk_ctx,
 196                 0x11,
 197                 "DB_STENCIL_INFO"
 198         },
 199         {
 200                 reg_blk_ctx,
 201                 0x82,
 202                 "PA_SC_WINDOW_SCISSOR_BR"
 203         },
 204         {
 205                 reg_blk_ctx,
 206                 0x8e,
 207                 "CB_TARGET_MASK"
 208         },
 209         {
 210                 reg_blk_ctx,
 211                 0x83,
 212                 "PA_SC_CLIPRECT_RULE"
 213         },
 214         {
 215                 reg_blk_ctx,
 216                 0x8f,
 217                 "CB_SHADER_MASK"
 218         },
 219         {
 220                 reg_blk_ctx,
 221                 0x94,
 222                 "PA_SC_VPORT_SCISSOR_0_TL"
 223         },
 224         {
 225                 reg_blk_ctx,
 226                 0x95,
 227                 "PA_SC_VPORT_SCISSOR_0_BR"
 228         },
 229         {
 230                 reg_blk_ctx,
 231                 0xb4,
 232                 "PA_SC_VPORT_ZMIN_0"
 233         },
 234         {
 235                 reg_blk_ctx,
 236                 0xb5,
 237                 "PA_SC_VPORT_ZMAX_0"
 238         },
 239         {
 240                 reg_blk_ctx,
 241                 0x10b,
 242                 "DB_STENCIL_CONTROL"
 243         },
 244         {
 245                 reg_blk_ctx,
 246                 0x10f,
 247                 "PA_CL_VPORT_XSCALE"
 248         },
 249         {
 250                 reg_blk_ctx,
 251                 0x110,
 252                 "PA_CL_VPORT_XOFFSET"
 253         },
 254         {
 255                 reg_blk_ctx,
 256                 0x111,
 257                 "PA_CL_VPORT_YSCALE"
 258         },
 259         {
 260                 reg_blk_ctx,
 261                 0x112,
 262                 "PA_CL_VPORT_YOFFSET"
 263         },
 264         {
 265                 reg_blk_ctx,
 266                 0x113,
 267                 "PA_CL_VPORT_ZSCALE"
 268         },
 269         {
 270                 reg_blk_ctx,
 271                 0x114,
 272                 "PA_CL_VPORT_ZOFFSET"
 273         },
 274         {
 275                 reg_blk_ctx,
 276                 0x191,
 277                 "SPI_PS_INPUT_CNTL_0"
 278         },
 279         {
 280                 reg_blk_ctx,
 281                 0x1b1,
 282                 "SPI_VS_OUT_CONFIG"
 283         },
 284         {
 285                 reg_blk_ctx,
 286                 0x1b3,
 287                 "SPI_PS_INPUT_ENA"
 288         },
 289         {
 290                 reg_blk_ctx,
 291                 0x1b4,
 292                 "SPI_PS_INPUT_ADDR"
 293         },
 294         {
 295                 reg_blk_ctx,
 296                 0x1b5,
 297                 "SPI_INTERP_CONTROL_0"
 298         },
 299         {
 300                 reg_blk_ctx,
 301                 0x1b6,
 302                 "SPI_PS_IN_CONTROL"
 303         },
 304         {
 305                 reg_blk_ctx,
 306                 0x1b8,
 307                 "SPI_BARYC_CNTL"
 308         },
 309         {
 310                 reg_blk_ctx,
 311                 0x1ba,
 312                 "SPI_TMPRING_SIZE"
 313         },
 314         {
 315                 reg_blk_ctx,
 316                 0x1c3,
 317                 "SPI_SHADER_POS_FORMAT"
 318         },
 319         {
 320                 reg_blk_ctx,
 321                 0x1c4,
 322                 "SPI_SHADER_Z_FORMAT"
 323         },
 324         {
 325                 reg_blk_ctx,
 326                 0x1c5,
 327                 "SPI_SHADER_COL_FORMAT"
 328         },
 329         {
 330                 reg_blk_ctx,
 331                 0x1e0,
 332                 "CB_BLEND0_CONTROL"
 333         },
 334         {
 335                 reg_blk_ctx,
 336                 0x1e1,
 337                 "CB_BLEND1_CONTROL"
 338         },
 339         {
 340                 reg_blk_ctx,
 341                 0x1e2,
 342                 "CB_BLEND2_CONTROL"
 343         },
 344         {
 345                 reg_blk_ctx,
 346                 0x1e3,
 347                 "CB_BLEND3_CONTROL"
 348         },
 349         {
 350                 reg_blk_ctx,
 351                 0x1e4,
 352                 "CB_BLEND4_CONTROL"
 353         },
 354         {
 355                 reg_blk_ctx,
 356                 0x1e5,
 357                 "CB_BLEND5_CONTROL"
 358         },
 359         {
 360                 reg_blk_ctx,
 361                 0x1e6,
 362                 "CB_BLEND6_CONTROL"
 363         },
 364         {
 365                 reg_blk_ctx,
 366                 0x1e7,
 367                 "CB_BLEND7_CONTROL"
 368         },
 369         {
 370                 reg_blk_ctx,
 371                 0x200,
 372                 "DB_DEPTH_CONTROL"
 373         },
 374         {
 375                 reg_blk_ctx,
 376                 0x201,
 377                 "DB_EQAA"
 378         },
 379         {
 380                 reg_blk_ctx,
 381                 0x202,
 382                 "CB_COLOR_CONTROL"
 383         },
 384         {
 385                 reg_blk_ctx,
 386                 0x203,
 387                 "DB_SHADER_CONTROL"
 388         },
 389         {
 390                 reg_blk_ctx,
 391                 0x204,
 392                 "PA_CL_CLIP_CNTL"
 393         },
 394         {
 395                 reg_blk_ctx,
 396                 0x205,
 397                 "PA_SU_SC_MODE_CNTL"
 398         },
 399         {
 400                 reg_blk_ctx,
 401                 0x206,
 402                 "PA_CL_VTE_CNTL"
 403         },
 404         {
 405                 reg_blk_ctx,
 406                 0x207,
 407                 "PA_CL_VS_OUT_CNTL"
 408         },
 409         {
 410                 reg_blk_ctx,
 411                 0x20b,
 412                 "PA_SU_PRIM_FILTER_CNTL"
 413         },
 414         {
 415                 reg_blk_ctx,
 416                 0x290,
 417                 "VGT_GS_MODE"
 418         },
 419         {
 420                 reg_blk_ctx,
 421                 0x292,
 422                 "PA_SC_MODE_CNTL_0"
 423         },
 424         {
 425                 reg_blk_ctx,
 426                 0x293,
 427                 "PA_SC_MODE_CNTL_1"
 428         },
 429         {
 430                 reg_blk_ctx,
 431                 0x29b,
 432                 "VGT_GS_OUT_PRIM_TYPE"
 433         },
 434         {
 435                 reg_blk_ctx,
 436                 0x2a1,
 437                 "VGT_PRIMITIVEID_EN"
 438         },
 439         {
 440                 reg_blk_ctx,
 441                 0x2a5,
 442                 "VGT_MULTI_PRIM_IB_RESET_EN"
 443         },
 444         {
 445                 reg_blk_ctx,
 446                 0x2aa,
 447                 "IA_MULTI_VGT_PARAM"
 448         },
 449         {
 450                 reg_blk_ctx,
 451                 0x2ad,
 452                 "VGT_REUSE_OFF"
 453         },
 454         {
 455                 reg_blk_ctx,
 456                 0x2d5,
 457                 "VGT_SHADER_STAGES_EN"
 458         },
 459         {
 460                 reg_blk_ctx,
 461                 0x2dc,
 462                 "DB_ALPHA_TO_MASK"
 463         },
 464         {
 465                 reg_blk_ctx,
 466                 0x2f5,
 467                 "PA_SC_CENTROID_PRIORITY_0"
 468         },
 469         {
 470                 reg_blk_ctx,
 471                 0x2f6,
 472                 "PA_SC_CENTROID_PRIORITY_1"
 473         },
 474         {
 475                 reg_blk_ctx,
 476                 0x2f7,
 477                 "PA_SC_LINE_CNTL"
 478         },
 479         {
 480                 reg_blk_ctx,
 481                 0x2f8,
 482                 "PA_SC_AA_CONFIG"
 483         },
 484         {
 485                 reg_blk_ctx,
 486                 0x2f9,
 487                 "PA_SU_VTX_CNTL"
 488         },
 489         {
 490                 reg_blk_ctx,
 491                 0x2fa,
 492                 "PA_CL_GB_VERT_CLIP_ADJ"
 493         },
 494         {
 495                 reg_blk_ctx,
 496                 0x2fb,
 497                 "PA_CL_GB_VERT_DISC_ADJ"
 498         },
 499         {
 500                 reg_blk_ctx,
 501                 0x2fc,
 502                 "PA_CL_GB_HORZ_CLIP_ADJ"
 503         },
 504         {
 505                 reg_blk_ctx,
 506                 0x2fd,
 507                 "PA_CL_GB_HORZ_DISC_ADJ"
 508         },
 509         {
 510                 reg_blk_ctx,
 511                 0x2fe,
 512                 "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0"
 513         },
 514         {
 515                 reg_blk_ctx,
 516                 0x302,
 517                 "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0"
 518         },
 519         {
 520                 reg_blk_ctx,
 521                 0x306,
 522                 "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0"
 523         },
 524         {
 525                 reg_blk_ctx,
 526                 0x30a,
 527                 "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0"
 528         },
 529         {
 530                 reg_blk_ctx,
 531                 0x30e,
 532                 "PA_SC_AA_MASK_X0Y0_X1Y0"
 533         },
 534         {
 535                 reg_blk_ctx,
 536                 0x30f,
 537                 "PA_SC_AA_MASK_X0Y1_X1Y1"
 538         },
 539         {
 540                 reg_blk_ctx,
 541                 0x313,
 542                 "PA_SC_CONSERVATIVE_RASTERIZATION_CNTL"
 543         },
 544         {
 545                 reg_blk_ctx,
 546                 0x318,
 547                 "CB_COLOR0_BASE"
 548         },
 549         {
 550                 reg_blk_ctx,
 551                 0x319,
 552                 "CB_COLOR0_PITCH"
 553         },
 554         {
 555                 reg_blk_ctx,
 556                 0x31a,
 557                 "CB_COLOR0_SLICE"
 558         },
 559         {
 560                 reg_blk_ctx,
 561                 0x31b,
 562                 "CB_COLOR0_VIEW"
 563         },
 564         {
 565                 reg_blk_ctx,
 566                 0x31c,
 567                 "CB_COLOR0_INFO"
 568         },
 569         {
 570                 reg_blk_ctx,
 571                 0x31d,
 572                 "CB_COLOR0_ATTRIB"
 573         },
 574         {
 575                 reg_blk_ctx,
 576                 0x31e,
 577                 "CB_COLOR0_DCC_CONTROL"
 578         },
 579         {
 580                 reg_blk_ctx,
 581                 0x31f,
 582                 "CB_COLOR0_CMASK"
 583         },
 584         {
 585                 reg_blk_ctx,
 586                 0x320,
 587                 "CB_COLOR0_CMASK_SLICE"
 588         },
 589         {
 590                 reg_blk_ctx,
 591                 0x321,
 592                 "CB_COLOR0_FMASK"
 593         },
 594         {
 595                 reg_blk_ctx,
 596                 0x322,
 597                 "CB_COLOR0_FMASK_SLICE"
 598         },
 599         {
 600                 reg_blk_ctx,
 601                 0x32b,
 602                 "CB_COLOR1_INFO"
 603         },
 604         {
 605                 reg_blk_ctx,
 606                 0x33a,
 607                 "CB_COLOR2_INFO"
 608         },
 609         {
 610                 reg_blk_ctx,
 611                 0x349,
 612                 "CB_COLOR3_INFO"
 613         },
 614         {
 615                 reg_blk_ctx,
 616                 0x358,
 617                 "CB_COLOR4_INFO"
 618         },
 619         {
 620                 reg_blk_ctx,
 621                 0x367,
 622                 "CB_COLOR5_INFO"
 623         },
 624         {
 625                 reg_blk_ctx,
 626                 0x376,
 627                 "CB_COLOR6_INFO"
 628         },
 629         {
 630                 reg_blk_ctx,
 631                 0x385,
 632                 "CB_COLOR7_INFO"
 633         },
 634 };
 635 #endif