2 # -*- coding: utf-8 -*-
4 =======================================
5 module_name: vut_analyser
6 ---------------------------------------
7 Author: Rodrigo Peixoto
9 ---------------------------------------
11 - This moludes fetchs the data from
12 the waveform to generate the Module
13 Skeleton and the UnitTest Module
14 =======================================
17 from elementtree
.ElementTree
import *
18 from vut_generator
import *
25 def __init__(self
, xml_source
):
26 self
.vut
= ElementTree(file=xml_source
)
27 self
.root
= self
.vut
.getroot()
28 self
.vmodule
= VerilogModule(self
.root
.get("module_name"))
31 print "Initing parser to %s..." % xml_source
33 def clear_comments(self
, dlist
):
34 for i
in dlist
:# removing commets
36 dlist
[dlist
.index(i
)] = i
[:i
.index("#")]
37 return map(str.strip
, dlist
)
40 def parse_waveform(self
, *args
):
41 print "--> parsing waveform..."
42 waves
= map(str.strip
, args
[0].text
.splitlines())
43 waves
= [x
for x
in waves
if((x
!= "") and ("-" not in x
) and ("=" not in x
))]
46 t
= re
.findall(r
'(^[a-zA-z]\w*( )*\[)|(^[a-zA-z]\w*( )*[io]\@)', signal
)[0]
47 sig_name
= [x
for x
in t
if x
!=""][0].split()[0].replace('[', '') #Cleaning all once!
48 slice = re
.findall(r
'\[\d+\:\d+\]', signal
)
51 port
= (sig_name
, tuple(map(int, re
.findall(r
'\d+', slice[0]))))
52 else: port
= (sig_name
,)
54 if re
.match(r
'.*i@.*', signal
):
55 self
.vmodule
.in_ports
.append(port
)
57 self
.vmodule
.out_ports
.append(port
)
60 waves
= map(lambda a
: a
.replace(" ", ""), waves
)
61 self
.parse_signal_values(waves
)
63 def parse_gen_with(self
, *args
):
69 print " parsing gen_with..."
70 ran
= map(str.strip
, args
[0].text
.splitlines())
71 ran
= [x
for x
in ran
if((x
!= "") and (x
[0]!="#"))]
72 #ran = self.clear_comments(ran)
74 self
.vmodule
.ran_range
[re
.findall(r
'R\d+', i
)[0]] = (int(re
.findall(r
'[0-9A-Fa-f]+\,', i
)[0][:-1],16), int(re
.findall(r
'[0-9A-Fa-f]+\s*\)', i
)[0][:-1],16))
75 print self
.vmodule
.ran_range
76 for code
in args
[0].getchildren():
78 assert var
, """Var not defined in python_code tag.\nUsage <python_code var="var_name">...code...</python_code>!"""
79 assert re
.match(r
'[a-zA-Z][a-zA-Z0-9_]*$', var
)
80 self
.python_code_parser(code
.text
)
83 def parse_time_scale(self
, *args
):
88 print " parsing time_scale..."
89 t_div
= args
[0].get("t_div")
90 unit
= args
[0].get("unit")
91 assert t_div
, """Time division not defined in time_scale tag.\n
92 Usage <time_scale t_div='val_integer' unit="unit{(ump)s}"/>!"""
93 assert unit
, "Unit not defined in time_scale tag!"
95 def parse_signal_values(self
, pwaves
):
96 print "--> creating memories..."
100 sig_name
= re
.sub("\[\d+:\d+\]", '', wav
[:wav
.index('@')-1])
101 values
= wav
[wav
.index('@')+1:].split('|')[1:-1]
102 if wav
[wav
.index('@')-1] == 'i':
103 mem
= MemoryIO("i_%s"% sig_name
, values
)
105 #exec ("imem_%s = %s" % (sig_name, values)) #wav[wav.index('@')+1:].split('|')[1:-1]))
106 list_imem
.append(mem
)
108 mem
= MemoryIO("o_%s"% sig_name
, values
)
109 #exec ("omem_%s = %s"% (sig_name, values)) #wav[wav.index('@')+1:].split('|')[1:-1]))
110 #exec("list_omem.append(omem_%s)"% sig_name)
111 list_omem
.append(mem
)
114 self
.vmodule
.set_in_ports_behavior(list_imem
)
115 self
.vmodule
.set_out_ports_behavior(list_omem
)
121 root_children
= self
.root
.getchildren()
122 switch
= {"waveform": self
.parse_waveform
,
123 "gen_with": self
.parse_gen_with
,
124 "time_scale": self
.parse_time_scale
}
126 for item
in root_children
:
128 switch
[item
.tag
](item
)
130 raise InvalidTagException(e
)
131 print "Parse complete successful!!!"
134 def python_code_parser(self
, pycode
):
135 #TODO: Ajsutar isso aqui!!!
136 print "checking python code..."
138 code
= self
.clear_comments(pycode
.splitlines())
139 code
= [x
for x
in code
if(x
!= "")]
142 if re
.match(r
"\s*include_python_file\(\"(((\
/\w
+)+|\
.)\
/)?\w
+.py
[oc
]?
\"\
)\s
*$
",pycode):
145 exec("\n".join(code))
146 print "Fetching reference model
: ", "\n".join(code)
148 print "Python reference model code error
: ", sys.exc_info()
149 if __name__ == '__main__':
150 test = VUTParser("teste
.vut
")
151 vm = test.parse_all()
152 VUTGenerator(vm).gen()