src/utils.py

   1 #!/usr/bin/python
   2 # -*- coding: utf-8 -*-
   3 """
   4 =======================================
   5 module_name: utils
   6 ---------------------------------------
   7 Author: Rodrigo Peixoto
   8 Data: 11/02/2008
   9 ---------------------------------------
  10 Description:
  11  - This moludes contains the basics
  12  tools.
  13 =======================================
  14 """
  15 from random import randrange
  16 import re
  17
  18 SYSTEM_DELAY=5
  19
  20 class VerilogModule(object):
  21     def __init__(self, module_name=""):
  22         self.name=module_name #It must respect the regexp [a-zA-Z]\w*
  23         self.in_ports=[] #Can be a bit (a) or vector ex.: (a,(7,0))
  24         self.out_ports=[] #Can be a bit (a) or vector ex.: (a,(7,0))
  25         self.time_slice=() #Must be ((division, unit) ,(precision, unit))
  26         self.in_ports_behavior=[]
  27         self.out_ports_behavior=[]
  28         self.ran_range = {}
  29         self.ref_functions = {}
  30
  31     def set_in_ports_behavior(self, behav):
  32         self.in_ports_behavior=behav
  33
  34     def set_out_ports_behavior(self, behav):
  35         self.out_ports_behavior=behav
  36
  37     def gen_random_values(self):
  38         regexp = re.compile("R\d+")
  39         for beh in self.in_ports_behavior:
  40             for val in beh.content:
  41                 if regexp.match(val):
  42                     try:
  43                         ri,ro = self.ran_range[val]
  44                         beh.content[beh.content.index(val)] = hex(randrange(ri,ro))[2:]
  45                     except KeyError:
  46                         #print sys.exc_info()
  47                         print "!Error: The random range to %s value is not defined in vut file!" % val
  48         print self.in_ports_behavior
  49
  50     def resolve_reference_functions(self):
  51         for kref in self.ref_functions:
  52             print self.ref_functions[kref]
  53
  54     def __repr__(self):
  55         return "============================\nModule: %s\n----------------------------\nIn_ports: %s\
  56 \nOut_ports: %s\n============================" % (self.name, self.in_ports, self.out_ports)
  57
  58
  59 class MemoryIO(object):
  60     def __init__(self, pname="", pcontent=[]):
  61         self.name = pname
  62         self.content = pcontent
  63
  64     def get_content(self):
  65         return self.content
  66
  67     def __repr__(self):
  68         return "Memory name: %s || Content: %s\n" % (self.name, self.content)
  69
  70
  71 BASIC_SKELETON=\
  72 """
  73 /*
  74 @The skeleton was generated by VUTGenerator@
  75 =======================================
  76 module_name: %(module_name)s
  77 ---------------------------------------
  78 Author: <author>
  79 Data: <date>
  80 ---------------------------------------
  81 Description: <description>
  82 =======================================
  83 */
  84
  85 module %(module_name)s(%(ports)s);
  86 //Inputs
  87 %(inputs)s
  88
  89 //Outputs
  90 %(outputs)s
  91
  92 //Wires
  93 %(wires)s
  94
  95 //Regs
  96 %(regs)s
  97
  98 //Behavior
  99
 100 %(behavior)s
 101
 102 endmodule
 103 """
 104
 105
 106
 107 BASIC_VUT_BEHAVIOR=\
 108 """
 109 %(memories)s
 110 %(tmpmem)s
 111     integer k;
 112     event send, ready;
 113
 114 %(module)s
 115
 116 %(initialmems)s
 117
 118     initial begin
 119         $dumpfile ("waveform.vcd");
 120         $dumpvars;
 121         #1;
 122 %(initregs)s
 123         k = -1;
 124         #4 -> ready;
 125     end
 126
 127
 128     always @ ready begin
 129         k = k + 1;
 130 %(mematt)s
 131         if (k >= %(memlen)s) begin
 132             $display("|VUT_OK| > All the signals are right-right!\\n\\n By Rodrigo Peixoto\\n");
 133             #5 $finish;
 134         end //if
 135         else #%(delay)s -> send;
 136     end
 137
 138
 139     always @ send begin
 140 %(iferrors)s
 141         #3 -> ready;
 142     end
 143
 144 """
 145
 146 BASIC_IF=\
 147 """        if (%(port)s !== tmp_%(port)s) begin
 148             $display("|VUT_FAIL|> Error in %(port)s value at time %%0dns!!!",$time);
 149             $finish;
 150         end //if"""