src/vut_generator.py

   1 #!/usr/bin/python
   2 # -*- coding: utf-8 -*-
   3 """
   4 =======================================
   5 module_name: vut_generator
   6 ---------------------------------------
   7 Author: Rodrigo Peixoto
   8 Data: 11/02/2008
   9 ---------------------------------------
  10 Description:
  11  - This modules generates the Verilog
  12  module skeleton, based in the vut
  13  file.
  14 =======================================
  15 """
  16
  17 from utils import *
  18 import re
  19
  20 DEST_GEN_FILES="./gen/"
  21
  22 class VUTGenerator:
  23     def __init__(self, vmodule, flags={}):
  24         self.flags=flags
  25         self.vmodule = vmodule
  26         self.vmodule.gen_random_values()
  27         self.vmodule.resolve_reference_functions()
  28         print "Code generation stars"
  29
  30     def get_(self, items=[], string_label=""):
  31         for sig in items:
  32             if len(sig) > 1:
  33                 yield "    %s [%d:%d] %s;" % (string_label, sig[1][0], sig[1][1], sig[0])
  34             else:
  35                 yield "    %s %s;" % (string_label, sig[0])
  36
  37     def get_memories(self):
  38         items = self.vmodule.in_ports + self.vmodule.out_ports
  39         verf_items = self.vmodule.in_ports_behavior + self.vmodule.out_ports_behavior
  40         #print items
  41         #print verf_items
  42         for sig in items:
  43             mem_len = len(verf_items[items.index(sig)].get_content()) -1
  44             if len(sig) > 1:
  45                 yield "    reg [%d:%d] mem_%s [0:%d];" % (sig[1][0], sig[1][1], sig[0], mem_len)
  46             else:
  47                 yield "    reg mem_%s [0:%d];" % (sig[0], mem_len)
  48
  49     def gen_module_skeleton(self):
  50         inputs = list(self.get_(self.vmodule.in_ports, "input"))
  51         inputs.sort()
  52         outputs = list(self.get_(self.vmodule.out_ports, "output"))
  53         outputs.sort()
  54         wires = list(self.get_(self.vmodule.in_ports, "wire"))
  55         wires.sort()
  56         regs = list(self.get_(self.vmodule.out_ports, "reg"))
  57         regs.sort()
  58         verilog_code = BASIC_SKELETON % {'module_name':self.vmodule.name,
  59                                 'ports':','.join([x[0] for x in self.vmodule.in_ports] + [x[0] for x in self.vmodule.out_ports]),
  60                                 'inputs':"\n".join(inputs),
  61                                 'outputs':"\n".join(outputs),
  62                                 'wires':"\n".join(wires),
  63                                 'regs':"\n".join(regs),
  64                                 'behavior': ""}
  65         file = open(DEST_GEN_FILES + "%s.v" % self.vmodule.name, "w")
  66         file.writelines(verilog_code)
  67         file.close()
  68
  69     def gen_vut(self):
  70
  71         regs = list(self.get_(self.vmodule.in_ports, "reg"))
  72         regs.sort()
  73         wires = list(self.get_(self.vmodule.out_ports, "wire"))
  74         wires.sort()
  75         memos = list(self.get_memories())
  76         memos.sort()
  77
  78         def gen_module_inst():
  79             ret="    %(module)s test(\n%(cons)s);"
  80             cons = []
  81             for p in self.vmodule.in_ports + self.vmodule.out_ports:
  82                 cons.append("        .%(port)s(%(port)s)" % {'port':p[0]})
  83             return ret % {'module':self.vmodule.name,
  84                           'cons':',\n'.join(cons)}
  85         def gen_tmp_mem():
  86             ret=[]
  87
  88             for p in self.vmodule.out_ports:
  89                  if len(p) > 1:
  90                      ret.append("    reg [%d:%d] tmp_%s;" % (p[1][0], p[1][1], p[0]))
  91                  else:
  92                      ret.append("    reg tmp_%s;" % p[0])
  93             return '\n'.join(ret)
  94
  95         def gen_initial_mems():
  96             ret = []
  97             for p in self.vmodule.in_ports:
  98                 ret.append('    initial $readmemh("i_%(port)s.mem",mem_%(port)s);' % {'port':p[0]})
  99             for p in self.vmodule.out_ports:
 100                 ret.append('    initial $readmemh("o_%(port)s.mem",mem_%(port)s);' % {'port':p[0]})
 101             return '\n'.join(ret)
 102
 103         def gen_init_regs():
 104             ret = []
 105             for p in self.vmodule.in_ports:
 106                 ret.append("        %s = 0;" % p[0])
 107             return '\n'.join(ret)
 108
 109         def gen_set_regs():
 110             ret = []
 111             for p in self.vmodule.in_ports:
 112                 ret.append(8*" " + "%(p)s = mem_%(p)s[k];" % {'p':p[0]})
 113             for p in self.vmodule.out_ports:
 114                 ret.append(8*" " + "tmp_%(p)s = mem_%(p)s[k];" % {'p':p[0]})
 115             return '\n'.join(ret)
 116
 117         def gen_sens_list():
 118             ret = []
 119             for p in self.vmodule.out_ports:
 120                 ret.append(p[0])
 121             return ' or '.join(ret)
 122
 123         def gen_if_errors():
 124             ret = []
 125             for p in self.vmodule.out_ports:
 126                 ret.append(BASIC_IF % {'port': p[0]})
 127             return '\n'.join(ret)
 128
 129         behavior_code = BASIC_VUT_BEHAVIOR % {'memories':'\n'.join(memos),
 130                                               'tmpmem': gen_tmp_mem(),
 131                                               'module': gen_module_inst(),
 132                                               'initialmems': gen_initial_mems(),
 133                                               'initregs': gen_init_regs(),
 134                                               'memlen': len(self.vmodule.in_ports_behavior[0].content),
 135                                               'delay': 2,
 136                                               'mematt': gen_set_regs(),
 137                                               'outlist':gen_sens_list(),
 138                                               'iferrors': gen_if_errors(),
 139                                               'tofin': len(self.vmodule.in_ports_behavior[0].content) * 10
 140                                               }
 141
 142         verilog_code = BASIC_SKELETON % {'module_name':"vut_" + self.vmodule.name,
 143                                 'ports': "",
 144                                 'inputs':"",
 145                                 'outputs':"",
 146                                 'wires':"\n".join(wires),
 147                                 'regs':"\n".join(regs),
 148                                 'behavior': behavior_code}
 149
 150
 151         file = open(DEST_GEN_FILES + "vut_%s.v" % self.vmodule.name, "w")
 152         file.writelines(verilog_code)
 153         file.close()
 154
 155         for in_p in self.vmodule.in_ports_behavior:
 156             f = open(DEST_GEN_FILES + in_p.name + ".mem", "w")
 157
 158             f.write("\n".join(in_p.content) + '\n')
 159             f.close()
 160 #            self.gen_random_values(in_p)
 161
 162         for out_p in self.vmodule.out_ports_behavior:
 163             f = open(DEST_GEN_FILES + out_p.name + ".mem", "w")
 164             f.write("\n".join(out_p.content) + '\n')
 165             f.close()
 166
 167 #    def gen_random_values(self, cont):
 168 #        regexp = re.compile("R\d+")
 169 #        for val in cont:
 170 #            if regexp.match(val):
 171 #                regexp.findall(val)
 172 #                cont[cont.index(val)] = hex(randrange(0,255))[2:]
 173 #                print cont
 174 #
 175     def gen(self):
 176         if 'skel' in self.flags:
 177             self.gen_module_skeleton()
 178             print "--> code generated %s.v" % self.vmodule.name
 179         self.gen_vut()
 180         print "--> code generated vut_%s.v" % self.vmodule.name
 181
 182 if __name__ == '__main__':
 183     vm = VerilogModule("Teste_de_geracao")
 184     vm.in_ports.append(('a', (3, 0)))
 185     vm.in_ports.append(('c',))
 186     vm.in_ports.append(('d', (3, 0)))
 187     vm.in_ports_behavior.append( MemoryIO('a',['R1','F','R2','9','4','R3','R2','R1','R2','R3','R4']))
 188     vm.in_ports_behavior.append( MemoryIO('c',['4','R3','A','R4','R1','R2','R3','R4','R3','R2','R1']))
 189     vm.in_ports_behavior.append( MemoryIO('d',['4','F','A','9']))
 190     vm.out_ports.append(('e', (3, 0)))
 191     vm.out_ports.append(('f', (3, 0)))
 192     vm.out_ports.append(('g', (3, 0)))
 193     vm.out_ports_behavior.append( MemoryIO('e',['4','F','A','9']))
 194     vm.out_ports_behavior.append( MemoryIO('f',['4','F','A','9','c','6']))
 195     vm.out_ports_behavior.append( MemoryIO('g',['4','F','A','9']))
 196     vm.ran_range['R1'] = (0,24)
 197     vm.ran_range['R2'] = (25,49)
 198     vm.ran_range['R3'] = (50,74)
 199     vm.ran_range['R4'] = (75,100)
 200     vm.ref_functions['o_e'] = "lambda a,c:a+c"
 201     test = VUTGenerator(vm)
 202     test.gen()