src/vut_parser.py

   1 #!/usr/bin/python
   2 # -*- coding: utf-8 -*-
   3 """
   4 =======================================
   5 module_name: vut_analyser
   6 ---------------------------------------
   7 Author: Rodrigo Peixoto
   8 Data: 10/02/2008
   9 ---------------------------------------
  10 Description:
  11  - This moludes fetchs the data from
  12  the waveform to generate the Module
  13  Skeleton and the UnitTest Module
  14 =======================================
  15 """
  16
  17 from elementtree.ElementTree import *
  18 from vut_generator import *
  19 from utils import *
  20 import re
  21 import sys
  22
  23 class VUTParser:
  24
  25     def __init__(self, xml_source):
  26         self.vut = ElementTree(file=xml_source)
  27         self.root = self.vut.getroot()
  28         self.vmodule = VerilogModule(self.root.get("module_name"))
  29         #print self.vmodule
  30         #self.ran_range = {}
  31         print "Initing parser to %s..." % xml_source
  32
  33     def clear_comments(self, dlist):
  34         for i in dlist:# removing commets
  35             if "#" in i:
  36                 dlist[dlist.index(i)] = i[:i.index("#")]
  37         return map(str.strip, dlist)
  38
  39
  40     def parse_waveform(self, *args):
  41             print "--> parsing waveform..."
  42             waves = map(str.strip, args[0].text.splitlines())
  43             waves = [x for x in waves if((x!= "") and ("-" not in x) and ("=" not in x))]
  44             for signal in waves:
  45                 t = re.findall(r'(^[a-zA-z]\w*( )*\[)|(^[a-zA-z]\w*( )*[io]\@)', signal)[0]
  46                 sig_name = [x for x in t if x!=""][0].split()[0].replace('[', '') #Cleaning all once!
  47                 slice = re.findall(r'\[\d+\:\d+\]', signal)
  48                 port = None
  49                 if slice:
  50                     port = (sig_name, tuple(map(int, re.findall(r'\d+', slice[0]))))
  51                 else: port = (sig_name,)
  52
  53                 if re.match(r'.*i@.*', signal):
  54                     self.vmodule.in_ports.append(port)
  55                 else:
  56                     self.vmodule.out_ports.append(port)
  57                     ref = re.findall(r"ref_function\(.*\)",signal)
  58                     sigs = []
  59                     if ref:
  60                         print "Found reference_function to %s: %s" % (sig_name, ref[0])
  61                         sigs.append(re.findall(r"(\.*\))",ref[0])[0][1:-1])
  62                         print sigs
  63             #print self.vmodule
  64
  65             waves = map(lambda a : a.replace(" ", ""), waves)
  66             self.parse_signal_values(waves)
  67
  68     def parse_gen_with(self, *args):
  69         '''
  70         @param *args:
  71         '''
  72         print "    parsing gen_with..."
  73         ran = map(str.strip, args[0].text.splitlines())
  74         ran = [x for x in ran if((x!= "") and (x[0]!="#"))]
  75         #ran = self.clear_comments(ran)
  76         for i in ran:
  77             self.vmodule.ran_range[re.findall(r'R\d+', i)[0]] = (int(re.findall(r'[0-9A-Fa-f]+\,', i)[0][:-1],16), int(re.findall(r'[0-9A-Fa-f]+\s*\)', i)[0][:-1],16))
  78         print self.vmodule.ran_range
  79         for code in args[0].getchildren():
  80             var = code.get("output")
  81             assert var, """Output not defined into python_code tag.\nUsage <python_code output="port_name">...code...</python_code>!"""
  82             port_name = re.findall(r'[a-zA-Z][a-zA-Z0-9_]*$', var)[0]
  83             assert port_name, ""
  84             self.python_code_parser(port_name, code.text)
  85         #print ran
  86
  87     def parse_time_scale(self, *args):
  88         '''
  89         @param *args:
  90         '''
  91
  92         print "    parsing time_scale..."
  93         t_div = args[0].get("t_div")
  94         unit = args[0].get("unit")
  95         assert t_div, """Time division not defined in time_scale tag.\n
  96 Usage <time_scale t_div='val_integer' unit="unit{(ump)s}"/>!"""
  97         assert unit, "Unit not defined in time_scale tag!"
  98
  99     def parse_signal_values(self, pwaves):
 100         print "--> creating memories..."
 101         list_imem = []
 102         list_omem = []
 103         for wav in pwaves:
 104             sig_name = re.sub("\[\d+:\d+\]", '', wav[:wav.index('@')-1])
 105             values = wav[wav.index('@')+1:].split('|')[1:-1]
 106             if wav[wav.index('@')-1] == 'i':
 107                 mem = MemoryIO("i_%s"% sig_name, values)
 108                 #print mem
 109                 #exec ("imem_%s = %s" % (sig_name, values)) #wav[wav.index('@')+1:].split('|')[1:-1]))
 110                 list_imem.append(mem)
 111             else:
 112                 mem = MemoryIO("o_%s"% sig_name, values)
 113                 #exec ("omem_%s = %s"% (sig_name, values)) #wav[wav.index('@')+1:].split('|')[1:-1]))
 114                 #exec("list_omem.append(omem_%s)"% sig_name)
 115                 list_omem.append(mem)
 116         #print list_imem
 117         #print list_omem
 118         self.vmodule.set_in_ports_behavior(list_imem)
 119         self.vmodule.set_out_ports_behavior(list_omem)
 120
 121
 122     def parse_all(self):
 123         '''
 124         '''
 125         root_children = self.root.getchildren()
 126         switch = {"waveform": self.parse_waveform,
 127                   "gen_with": self.parse_gen_with,
 128                   "time_scale": self.parse_time_scale}
 129
 130         for item in root_children:
 131             try:
 132                 switch[item.tag](item)
 133             except KeyError, e:
 134                 raise InvalidTagException(e)
 135         print "Parse complete successful!!!"
 136         return self.vmodule
 137
 138     def python_code_parser(self, port_name, pycode):
 139         #TODO: Ajsutar isso aqui!!!
 140         print "checking python code..."
 141
 142         code = self.clear_comments(pycode.splitlines())
 143         code = [x for x in code if(x!= "")]
 144
 145         try:
 146             ref_function = None
 147             if re.match(r"\s*include_python_file\(\"(((\/\w+)+|\.)\/)?\w+.py[oc]?\"\)\s*$",pycode):
 148                 print pycode.strip()
 149                 function_file = re.findall(r"\"(((\/\w+)+|\.)\/)?\w+.py[oc]?\"", pycode)[0]
 150                 exec """import %(file)s;ref_function = %(file)s.reference_function""" % {'file':port_name}
 151                 #DEBUG: print "test ref_function: ", ref_function(10,20)
 152             else:
 153                 exec("ref_function = " + "\n".join(code))
 154                 print "Fetching reference model: ", "\n".join(code)
 155                 #DEBUG: print "test ref_function: ", ref_function(10,20)
 156             self.vmodule.ref_functions[port_name] = ref_function
 157             print self.vmodule.ref_functions
 158         except:
 159             print "Python reference model code error: ", sys.exc_info()
 160 if __name__ == '__main__':
 161     test = VUTParser("teste.vut")
 162     vm = test.parse_all()
 163     VUTGenerator(vm).gen()
 164
 165