teste
[vutg.git] / src / example3.vut
blob8dd393b79ba1ddc0c9bf08da4ef27d0eb21b9e5e
1 <?xml version="1.0" encoding="UTF-8"?>
2 <vut module_name="register1bit">
3 <waveform>
4 ========================
5 clk i@|1|0|1|0|1|0|
6 ------------------------
7 data_in i@|1|1|1|1|1|1|
8 ------------------------
9 enable i@|1|1|1|1|1|1|
10 ------------------------
11 reset i@|0|0|0|0|0|0|
12 ========================
13 data_out o@|1|1|1|1|1|1|
14 ========================
15 </waveform>
16 </vut>