teste
[vutg.git] / src / gen / vut_fulladder_1bit.v
blob2d5b56888e59f521d3eb3fcde691d5a5768990fe
2 /*
3 @The skeleton was generated by VUTGenerator@
4 =======================================
5 module_name: vut_fulladder_1bit
6 ---------------------------------------
7 Author: <author>
8 Data: <date>
9 ---------------------------------------
10 Description: <description>
11 =======================================
14 module vut_fulladder_1bit();
15 //Inputs
18 //Outputs
21 //Wires
22 wire overflow;
23 wire result;
25 //Regs
26 reg a;
27 reg b;
29 //Behavior
32 reg mem_a [0:3];
33 reg mem_b [0:3];
34 reg mem_overflow [0:3];
35 reg mem_result [0:3];
36 reg tmp_result;
37 reg tmp_overflow;
38 integer k;
39 event send, ready;
41 fulladder_1bit test(
42 .a(a),
43 .b(b),
44 .result(result),
45 .overflow(overflow));
47 initial $readmemh("i_a.mem",mem_a);
48 initial $readmemh("i_b.mem",mem_b);
49 initial $readmemh("o_result.mem",mem_result);
50 initial $readmemh("o_overflow.mem",mem_overflow);
52 initial begin
53 $dumpfile ("waveform.vcd");
54 $dumpvars;
55 #1;
56 a = 0;
57 b = 0;
58 k = -1;
59 #4 -> ready;
60 end
63 always @ ready begin
64 k = k + 1;
65 a = mem_a[k];
66 b = mem_b[k];
67 tmp_result = mem_result[k];
68 tmp_overflow = mem_overflow[k];
69 if (k >= 4) begin
70 $display("|VUT_OK| > All the signals are right-right!\n\n By Rodrigo Peixoto\n");
71 #5 $finish;
72 end //if
73 else #2 -> send;
74 end
77 always @ send begin
78 if (result !== tmp_result) begin
79 $display("|VUT_FAIL|> Error in result value at time %0dns!!!",$time);
80 $finish;
81 end //if
82 if (overflow !== tmp_overflow) begin
83 $display("|VUT_FAIL|> Error in overflow value at time %0dns!!!",$time);
84 $finish;
85 end //if
86 #3 -> ready;
87 end
91 endmodule