1 <?xml version="1.0" encoding="UTF-8"?>
2 <vut module_name="fulladder_8bits">
4 ============================================
\r
5 a [7:0] i@|00|00|00|00|00|00|00|00|00|
6 --------------------------------------------
\r
7 b[7:0] i@|01|02|03|04|05|06|07|08|09|
\r
8 ============================================
\r
9 result[7:0] o@|01|02|03|04|05|06|07|08|09|
\r
10 --------------------------------------------
\r
11 overflow o@|0 |0 |0 |0 |0 |0 |0 |0 |0 |
\r
12 ============================================
\r