src/vut_generator.py

   1 #!/usr/bin/python
   2 # -*- coding: utf-8 -*-
   3 """
   4 =======================================
   5 module_name: vut_generator
   6 ---------------------------------------
   7 Author: Rodrigo Peixoto
   8 Data: 11/02/2008
   9 ---------------------------------------
  10 Description:
  11  - This modules generates the Verilog
  12  module skeleton, based in the vut
  13  file.
  14 =======================================
  15 """
  16
  17 from utils import *
  18
  19 DEST_GEN_FILES="./gen/"
  20
  21 class VUTGenerator:
  22     def __init__(self, vmodule, flags={}):
  23         self.flags=flags
  24         self.vmodule = vmodule
  25         print "Code generation stars"
  26
  27     def get_(self, items=[], string_label=""):
  28         for sig in items:
  29             if len(sig) > 1:
  30                 yield "    %s [%d:%d] %s;" % (string_label, sig[1][0], sig[1][1], sig[0])
  31             else:
  32                 yield "    %s %s;" % (string_label, sig[0])
  33
  34     def get_memories(self):
  35         items = self.vmodule.in_ports + self.vmodule.out_ports
  36         verf_items = self.vmodule.in_ports_behavior + self.vmodule.out_ports_behavior
  37         #print items
  38         #print verf_items
  39         for sig in items:
  40             mem_len = len(verf_items[items.index(sig)].get_content()) -1
  41             if len(sig) > 1:
  42                 yield "    reg [%d:%d] mem_%s [0:%d];" % (sig[1][0], sig[1][1], sig[0], mem_len)
  43             else:
  44                 yield "    reg mem_%s [0:%d];" % (sig[0], mem_len)
  45
  46     def gen_module_skeleton(self):
  47         inputs = list(self.get_(self.vmodule.in_ports, "input"))
  48         inputs.sort()
  49         outputs = list(self.get_(self.vmodule.out_ports, "output"))
  50         outputs.sort()
  51         wires = list(self.get_(self.vmodule.in_ports, "wire"))
  52         wires.sort()
  53         regs = list(self.get_(self.vmodule.out_ports, "reg"))
  54         regs.sort()
  55         verilog_code = BASIC_SKELETON % {'module_name':self.vmodule.name,
  56                                 'ports':','.join([x[0] for x in self.vmodule.in_ports] + [x[0] for x in self.vmodule.out_ports]),
  57                                 'inputs':"\n".join(inputs),
  58                                 'outputs':"\n".join(outputs),
  59                                 'wires':"\n".join(wires),
  60                                 'regs':"\n".join(regs),
  61                                 'behavior': ""}
  62         file = open(DEST_GEN_FILES + "%s.v" % self.vmodule.name, "w")
  63         file.writelines(verilog_code)
  64         file.close()
  65
  66     def gen_vut(self):
  67
  68         regs = list(self.get_(self.vmodule.in_ports, "reg"))
  69         regs.sort()
  70         wires = list(self.get_(self.vmodule.out_ports, "wire"))
  71         wires.sort()
  72         memos = list(self.get_memories())
  73         memos.sort()
  74
  75         def gen_module_inst():
  76             ret="    %(module)s test(\n%(cons)s);"
  77             cons = []
  78             for p in self.vmodule.in_ports + self.vmodule.out_ports:
  79                 cons.append("        .%(port)s(%(port)s)" % {'port':p[0]})
  80             return ret % {'module':self.vmodule.name,
  81                           'cons':',\n'.join(cons)}
  82         def gen_tmp_mem():
  83             ret=[]
  84
  85             for p in self.vmodule.out_ports:
  86                  if len(p) > 1:
  87                      ret.append("    reg [%d:%d] tmp_%s;" % (p[1][0], p[1][1], p[0]))
  88                  else:
  89                      ret.append("    reg tmp_%s;" % p[0])
  90             return '\n'.join(ret)
  91
  92         def gen_initial_mems():
  93             ret = []
  94             for p in self.vmodule.in_ports:
  95                 ret.append('    initial $readmemh("i_%(port)s.mem",mem_%(port)s);' % {'port':p[0]})
  96             for p in self.vmodule.out_ports:
  97                 ret.append('    initial $readmemh("o_%(port)s.mem",mem_%(port)s);' % {'port':p[0]})
  98             return '\n'.join(ret)
  99
 100         def gen_init_regs():
 101             ret = []
 102             for p in self.vmodule.in_ports:
 103                 ret.append("        %s = 0;" % p[0])
 104             return '\n'.join(ret)
 105
 106         def gen_set_regs():
 107             ret = []
 108             for p in self.vmodule.in_ports:
 109                 ret.append(8*" " + "%(p)s = mem_%(p)s[k];" % {'p':p[0]})
 110             for p in self.vmodule.out_ports:
 111                 ret.append(8*" " + "tmp_%(p)s = mem_%(p)s[k];" % {'p':p[0]})
 112             return '\n'.join(ret)
 113
 114         def gen_sens_list():
 115             ret = []
 116             for p in self.vmodule.out_ports:
 117                 ret.append(p[0])
 118             return ' or '.join(ret)
 119
 120         def gen_if_errors():
 121             ret = []
 122             for p in self.vmodule.out_ports:
 123                 ret.append(BASIC_IF % {'port': p[0]})
 124             return '\n'.join(ret)
 125
 126         behavior_code = BASIC_VUT_BEHAVIOR % {'memories':'\n'.join(memos),
 127                                               'tmpmem': gen_tmp_mem(),
 128                                               'module': gen_module_inst(),
 129                                               'initialmems': gen_initial_mems(),
 130                                               'initregs': gen_init_regs(),
 131                                               'memlen': len(self.vmodule.in_ports_behavior[0].content),
 132                                               'delay': 2,
 133                                               'mematt': gen_set_regs(),
 134                                               'outlist':gen_sens_list(),
 135                                               'iferrors': gen_if_errors(),
 136                                               'tofin': len(self.vmodule.in_ports_behavior[0].content) * 10
 137                                               }
 138
 139         verilog_code = BASIC_SKELETON % {'module_name':"vut_" + self.vmodule.name,
 140                                 'ports': "",
 141                                 'inputs':"",
 142                                 'outputs':"",
 143                                 'wires':"\n".join(wires),
 144                                 'regs':"\n".join(regs),
 145                                 'behavior': behavior_code}
 146
 147
 148         file = open(DEST_GEN_FILES + "vut_%s.v" % self.vmodule.name, "w")
 149         file.writelines(verilog_code)
 150         file.close()
 151
 152         for in_p in self.vmodule.in_ports_behavior:
 153             f = open(DEST_GEN_FILES + in_p.name + ".mem", "w")
 154             f.write("\n".join(in_p.content) + '\n')
 155             f.close()
 156
 157         for out_p in self.vmodule.out_ports_behavior:
 158             f = open(DEST_GEN_FILES + out_p.name + ".mem", "w")
 159             f.write("\n".join(out_p.content) + '\n')
 160             f.close()
 161
 162     def gen(self):
 163         if 'skel' in self.flags:
 164             self.gen_module_skeleton()
 165             print "--> code generated %s.v" % self.vmodule.name
 166         self.gen_vut()
 167         print "--> code generated vut_%s.v" % self.vmodule.name
 168
 169 if __name__ == '__main__':
 170     vm = VerilogModule("Teste_de_geracao")
 171     vm.in_ports.append(('a', (3, 0)))
 172     vm.in_ports.append(('c',))
 173     vm.in_ports.append(('d', (3, 0)))
 174     vm.in_ports_behavior.append( MemoryIO('a',['4','F','A','9','4']))
 175     vm.in_ports_behavior.append( MemoryIO('c',['4','F','A','9']))
 176     vm.in_ports_behavior.append( MemoryIO('d',['4','F','A','9']))
 177     vm.out_ports.append(('e', (3, 0)))
 178     vm.out_ports.append(('f', (3, 0)))
 179     vm.out_ports.append(('g', (3, 0)))
 180     vm.in_ports_behavior.append( MemoryIO('e',['4','F','A','9']))
 181     vm.in_ports_behavior.append( MemoryIO('f',['4','F','A','9','','6']))
 182     vm.in_ports_behavior.append( MemoryIO('g',['4','F','A','9']))
 183
 184     test = VUTGenerator(vm)
 185     test.gen()