src/gen/fulladder_1bit.v

   1
   2 /*
   3 @The skeleton was generated by VUTGenerator@
   4 =======================================
   5 module_name: fulladder_1bit
   6 ---------------------------------------
   7 Author: <author>
   8 Data: <date>
   9 ---------------------------------------
  10 Description: <description>
  11 =======================================
  12 */
  13
  14 module fulladder_1bit(a,b,result,overflow);
  15 //Inputs
  16     input a;
  17     input b;
  18
  19 //Outputs
  20     output overflow;
  21     output result;
  22
  23 //Wires
  24     wire a;
  25     wire b;
  26
  27 //Regs
  28     reg overflow;
  29     reg result;
  30
  31 //Behavior
  32
  33
  34
  35 endmodule