src/utils.py

   1 #!/usr/bin/python
   2 # -*- coding: utf-8 -*-
   3 """
   4 =======================================
   5 module_name: utils
   6 ---------------------------------------
   7 Author: Rodrigo Peixoto
   8 Data: 11/02/2008
   9 ---------------------------------------
  10 Description:
  11  - This moludes contains the basics
  12  tools.
  13 =======================================
  14 """
  15 from random import randrange
  16 import re
  17 import sys
  18
  19 SYSTEM_DELAY=5
  20
  21 class VerilogModule(object):
  22     def __init__(self, module_name=""):
  23         self.name=module_name #It must respect the regexp [a-zA-Z]\w*
  24         self.in_ports=[] #Can be a bit (a) or vector ex.: (a,(7,0))
  25         self.out_ports=[] #Can be a bit (a) or vector ex.: (a,(7,0))
  26         self.time_slice=() #Must be ((division, unit) ,(precision, unit))
  27         self.in_ports_behavior=[]
  28         self.out_ports_behavior=[]
  29         self.out_ports_dep = {}
  30         self.ran_range = {}
  31         self.ref_functions = {}
  32         self.random_alloc = {} # 'sig_name': ([R1,R2,R3,...,R2], n)signal name list that contains RA
  33
  34     def set_in_ports_behavior(self, behav):
  35         self.in_ports_behavior=behav
  36
  37     def get_port_behav(self, name):
  38         ret = None
  39         for i in self.in_ports_behavior+self.out_ports_behavior:
  40             if i.name == name: ret = i;break
  41         return ret
  42
  43     def set_out_ports_behavior(self, behav):
  44         self.out_ports_behavior=behav
  45
  46     def alloc_random_values():
  47         pass
  48
  49     def gen_random_values(self):
  50         regexp = re.compile("R\d+")
  51         for beh in self.in_ports_behavior:
  52             for val in beh.content:
  53                 if regexp.match(val):
  54                     try:
  55                         ri,ro = self.ran_range[val]
  56                         #TODO: Verificar o [2:-1] da linha abaixo
  57                         beh.content[beh.content.index(val)] = hex(randrange(ri,ro))[2:].replace("L","")
  58                     except KeyError:
  59                         #print sys.exc_info()
  60                         print "!Error: The random range to %s value is not defined in vut file!" % val
  61                         sys.exit(1)
  62                     except ValueError:
  63                         print "!Error: Check the random range to %s value it is wrong!" % val
  64                         sys.exit(1)
  65         print self.in_ports_behavior
  66
  67     def resolve_reference_functions(self):
  68         for kref in self.ref_functions:
  69             params = self.out_ports_dep[kref]
  70             reff = self.ref_functions[kref]
  71             #reff = None
  72             #exec "reff = "+ref
  73             print reff
  74             mem = []
  75             for i in params:
  76                 mem.append(self.get_port_behav(i))
  77             tmp = []
  78             for x in mem:
  79                 tmp.append(str([int(m,16) for m in x.content]))
  80             aux = []
  81             exec "aux = zip(%s)" % ",".join(tmp)
  82             res = None
  83             out = []
  84             for y in aux:
  85                 exec "res = reff%s" % str(y)
  86                 out.append(res)
  87             result = [hex(x)[2:].replace("L","") for x in out]
  88
  89             tmp = self.out_ports_behavior[self.out_ports_behavior.index(self.get_port_behav(kref))].content
  90             tmp.pop()
  91             if len(tmp):
  92                 tmp+=result[(len(tmp)):]
  93             else:
  94                 tmp+=result
  95
  96
  97
  98     def __repr__(self):
  99         return "============================\nModule: %s\n----------------------------\nIn_ports: %s\
 100 \nOut_ports: %s\n============================" % (self.name, self.in_ports, self.out_ports)
 101
 102
 103 class MemoryIO(object):
 104     def __init__(self, pname="", pcontent=[]):
 105         self.name = pname
 106         self.content = pcontent
 107
 108     def get_content(self):
 109         return self.content
 110
 111     def __repr__(self):
 112         return "Memory name: %s || Content: %s\n" % (self.name, self.content)
 113
 114
 115 BASIC_SKELETON=\
 116 """
 117 /*
 118 @The skeleton was generated by VUTGenerator@
 119 =======================================
 120 module_name: %(module_name)s
 121 ---------------------------------------
 122 Author: <author>
 123 Data: <date>
 124 ---------------------------------------
 125 Description: <description>
 126 =======================================
 127 */
 128
 129 module %(module_name)s(%(ports)s);
 130 //Inputs
 131 %(inputs)s
 132
 133 //Outputs
 134 %(outputs)s
 135
 136 //Wires
 137 %(wires)s
 138
 139 //Regs
 140 %(regs)s
 141
 142 //Behavior
 143
 144 %(behavior)s
 145
 146 endmodule
 147 """
 148
 149
 150
 151 BASIC_VUT_BEHAVIOR=\
 152 """
 153 %(memories)s
 154 %(tmpmem)s
 155     integer k;
 156     event send, ready;
 157
 158 %(module)s
 159
 160 %(initialmems)s
 161
 162     initial begin
 163         $dumpfile ("waveform.vcd");
 164         $dumpvars;
 165         #1;
 166 %(initregs)s
 167         k = -1;
 168         #4 -> ready;
 169     end
 170
 171
 172     always @ ready begin
 173         k = k + 1;
 174 %(mematt)s
 175         if (k >= %(memlen)s) begin
 176             $display("|VUT_OK| > All the signals are right-right!\\n\\n By Rodrigo Peixoto\\n");
 177             #5 $finish;
 178         end //if
 179         else #%(delay)s -> send;
 180     end
 181
 182
 183     always @ send begin
 184 %(iferrors)s
 185         #3 -> ready;
 186     end
 187
 188 """
 189
 190 BASIC_IF=\
 191 """        if (%(port)s !== tmp_%(port)s) begin
 192             $display("|VUT_FAIL|> Error in %(port)s value at time %%0dns!!!",$time);
 193             $finish;
 194         end //if"""