src/vut_parser.py

   1 #!/usr/bin/python
   2 # -*- coding: utf-8 -*-
   3 """
   4 =======================================
   5 module_name: vut_analyser
   6 ---------------------------------------
   7 Author: Rodrigo Peixoto
   8 Data: 10/02/2008
   9 ---------------------------------------
  10 Description:
  11  - This moludes fetchs the data from
  12  the waveform to generate the Module
  13  Skeleton and the UnitTest Module
  14 =======================================
  15 """
  16
  17 from elementtree.ElementTree import *
  18 from vut_generator import *
  19 from utils import *
  20 import re
  21 import sys
  22 import random
  23
  24 class VUTParser:
  25
  26     def __init__(self, xml_source):
  27         self.vut = ElementTree(file=xml_source)
  28         self.root = self.vut.getroot()
  29         self.vmodule = VerilogModule(self.root.get("module_name"))
  30         print "Initing parser to %s..." % xml_source
  31
  32     def clear_comments(self, dlist):
  33         for i in dlist:# removing commets
  34             if "#" in i:
  35                 dlist[dlist.index(i)] = i[:i.index("#")]
  36         return map(str.strip, dlist)
  37
  38
  39     def parse_waveform(self, *args):
  40         print "--> parsing waveform..."
  41         waves = map(str.strip, args[0].text.splitlines())
  42         waves = [x for x in waves if((x!= "") and ("-" not in x) and ("=" not in x))]
  43         for signal in waves:
  44             t = re.findall(r'(^[a-zA-z]\w*( )*\[)|(^[a-zA-z]\w*( )*[io]\@)', signal)[0]
  45             sig_name = [x for x in t if x!=""][0].split()[0].replace('[', '') #Cleaning all once!
  46             slice = re.findall(r'\[\d+\:\d+\]', signal)
  47             port = None
  48             if slice:
  49                 port = (sig_name, tuple(map(int, re.findall(r'\d+', slice[0]))))
  50             else: port = (sig_name,)
  51
  52             if re.match(r'.*i@.*', signal):
  53                 self.vmodule.in_ports.append(port)
  54                 ref = re.findall(r"random_alloc\(.*\)",signal)
  55                 if ref:
  56                     print "Found random_alloc to %s: %s" % (sig_name,ref[0])
  57                     rs = re.findall(r"R\d+",ref[0])
  58                     n = int(re.findall(r"\,\d+",ref[0])[0][1:])
  59                     self.vmodule.random_alloc[sig_name] = (rs,n)
  60                     print self.vmodule.random_alloc
  61
  62
  63             else:
  64                 self.vmodule.out_ports.append(port)
  65                 ref = re.findall(r"ref_function\(.*\)",signal)
  66                 sigs = []
  67                 if ref:
  68                     print "Found reference_function to %s: %s" % (sig_name, ref[0])
  69                     sigs = re.findall(r"\(.*\)",ref[0])[0][1:-1].split(',')
  70                     self.vmodule.out_ports_dep[sig_name] = sigs
  71
  72         print self.vmodule.out_ports_dep
  73         waves = map(lambda a : a.replace(" ", ""), waves)
  74         self.parse_signal_values(waves)
  75
  76     def parse_gen_with(self, *args):
  77         '''
  78         @param *args:
  79         '''
  80         print "    parsing gen_with..."
  81         ran = map(str.strip, args[0].text.splitlines())
  82         ran = [x for x in ran if((x!= "") and (x[0]!="#"))]
  83         #ran = self.clear_comments(ran)
  84         for i in ran:
  85             self.vmodule.ran_range[re.findall(r'R\d+', i)[0]] =\
  86              (int(re.findall(r'[0-9A-Fa-f]+\s*\,', i)[0][:-1],16),\
  87               int(re.findall(r'[0-9A-Fa-f]+\s*\)', i)[0][:-1],16))
  88         print self.vmodule.ran_range
  89         for code in args[0].getchildren():
  90             var = code.get("output")
  91             assert var, "Output not defined into python_code tag.\n"\
  92                         'Usage <python_code output="port_name">...code...</python_code>!'
  93             port_name = re.findall(r'[a-zA-Z][a-zA-Z0-9_]*$', var)[0]
  94             assert port_name, ""
  95             self.python_code_parser(port_name, code.text)
  96
  97     def parse_time_scale(self, *args):
  98         '''
  99         @param *args:
 100         '''
 101         print "    parsing time_scale..."
 102         t_div = args[0].get("t_div")
 103         unit = args[0].get("unit")
 104         assert t_div, 'Time division not defined in time_scale tag.\n'\
 105                       'Usage <time_scale t_div="val_integer" unit="unit{(ump)s}"/>!'
 106         assert unit, "Unit not defined in time_scale tag!"
 107
 108     def parse_signal_values(self, pwaves):
 109         print "--> creating memories..."
 110         list_imem = []
 111         list_omem = []
 112         for wav in pwaves:
 113             sig_name = re.sub("\[\d+:\d+\]", '', wav[:wav.index('@')-1])
 114             #Random alloc values
 115             if sig_name in self.vmodule.random_alloc:
 116                 ran_val = []
 117                 tmp_val,n = self.vmodule.random_alloc[sig_name]
 118                 for i in range(n):
 119                     ran_val.append(tmp_val[random.randrange(len(tmp_val))])
 120                 wav = re.sub(r"random_alloc\(.*\)","|".join(ran_val),wav)
 121                 print "TESTE DE RANDOMALLOC",wav
 122
 123             values = wav[wav.index('@')+1:].split('|')[1:-1]
 124             if wav[wav.index('@')-1] == 'i':
 125                 mem = MemoryIO("%s"% sig_name, values)
 126                 #print mem
 127                 #exec ("imem_%s = %s" % (sig_name, values)) #wav[wav.index('@')+1:].split('|')[1:-1]))
 128                 list_imem.append(mem)
 129             else:
 130                 mem = MemoryIO("%s"% sig_name, values)
 131                 #exec ("omem_%s = %s"% (sig_name, values)) #wav[wav.index('@')+1:].split('|')[1:-1]))
 132                 #exec("list_omem.append(omem_%s)"% sig_name)
 133                 list_omem.append(mem)
 134         #print list_imem
 135         #print list_omem
 136         self.vmodule.set_in_ports_behavior(list_imem)
 137         self.vmodule.set_out_ports_behavior(list_omem)
 138
 139
 140     def parse_all(self):
 141         '''
 142         '''
 143         root_children = self.root.getchildren()
 144         switch = {"waveform": self.parse_waveform,
 145                   "gen_with": self.parse_gen_with,
 146                   "time_scale": self.parse_time_scale}
 147
 148         for item in root_children:
 149             try:
 150                 switch[item.tag](item)
 151             except KeyError, e:
 152                 raise InvalidTagException(e)
 153         print "Parse complete successful!!!"
 154         return self.vmodule
 155
 156     def python_code_parser(self, port_name, pycode):
 157         #TODO: Ajsutar isso aqui!!!
 158         print "checking python code..."
 159
 160         code = self.clear_comments(pycode.splitlines())
 161         code = [x for x in code if(x!= "")]
 162
 163         try:
 164             ref_function = None
 165             if re.match(r"\s*include_python_file\(\"(((\/\w+)+|\.)\/)?\w+.py[oc]?\"\)\s*$",pycode):
 166                 print pycode.strip()
 167                 function_file = re.findall(r"\"(((\/\w+)+|\.)\/)?\w+.py[oc]?\"", pycode)[0]
 168                 exec """import %(file)s;ref_function = %(file)s.reference_function""" % {'file':port_name}
 169                 #DEBUG: print "test ref_function: ", ref_function(10,20)
 170             else:
 171                 exec("ref_function = " + "\n".join(code))
 172                 print "Fetching reference model: ", "\n".join(code)
 173                 #DEBUG: print "test ref_function: ", ref_function(10,20)
 174             self.vmodule.ref_functions[port_name] = ref_function
 175             print self.vmodule.ref_functions
 176         except:
 177             print "Python reference model code error: ", sys.exc_info()
 178 if __name__ == '__main__':
 179     test = VUTParser("example5.vut")
 180     vm = test.parse_all()
 181     #VUTGenerator(vm).gen()
 182
 183