examples insertion.
[vutg.git] / src / examples / register / out_data.py
blob1e3136e7ea5d05b84432a315d114cca6c30e2cfe
1 # -*- coding: utf-8 -*-
2 """
3 clk i@|0|1|0|1|0|1|0|1|0|1|0|1|0|1|0|1|0|1|0|1|0|1|0|1|0|1|0|1|0|1|
4 ------------------------------------------------------------------------
5 in_data i@|random_alloc([R1,R2,R3],15)|
6 ------------------------------------------------
7 clear i@|random_alloc([R4],30)|
8 ------------------------------------------------
9 load i@|random_alloc([R4],30)|
10 """
11 def max_lenght(signals):
12 return min(map(len,signals.itervalues()))
14 def reference_function(signals):
15 #ret = [0]
16 def add_nop(l):
17 try:
18 tmp = l[-1]
19 l.append(tmp)
20 except:
21 l.append(0)
23 ret = []
24 print signals
25 for step in range(max_lenght(signals)):
26 if signals['clk'][step]:
27 if signals['clear'][step]:
28 ret.append(0)
29 elif signals['load'][step]:
30 ret.append(signals['in_data'][step])
31 else:
32 add_nop(ret)
33 print ret
34 return ret