examples insertion.
[vutg.git] / src / gen / vut_fulladder.v
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2 /*
3 @The skeleton was generated by VUTGenerator@
4 =======================================
5 module_name: vut_fulladder
6 ---------------------------------------
7 Author: <author>
8 Data: <date>
9 ---------------------------------------
10 Description: <description>
11 =======================================
14 module vut_fulladder();
15 //Inputs
18 //Outputs
21 //Wires
22 wire [7:0] result;
23 wire overflow;
25 //Regs
26 reg [7:0] a;
27 reg [7:0] b;
29 //Behavior
32 reg [7:0] mem_a [0:2003];
33 reg [7:0] mem_b [0:2003];
34 reg [7:0] mem_result [0:2003];
35 reg mem_overflow [0:2003];
36 reg [7:0] tmp_result;
37 reg tmp_overflow;
38 integer k;
39 event send, ready;
41 fulladder test(
42 .a(a),
43 .b(b),
44 .result(result),
45 .overflow(overflow));
47 initial $display("|VUT INFO| > Load memories... ");
49 initial $readmemh("a.mem",mem_a);
50 initial $readmemh("b.mem",mem_b);
51 initial $readmemh("result.mem",mem_result);
52 initial $readmemh("overflow.mem",mem_overflow);
54 initial begin
55 $dumpfile ("waveform.vcd");
56 $dumpvars;
57 $display("|VUT INFO| > Init Simulation.");
58 #1;
59 a = 0;
60 b = 0;
61 k = -1;
62 #4 -> ready;
63 end
66 always @ ready begin
67 k = k + 1;
68 a = mem_a[k];
69 b = mem_b[k];
70 tmp_result = mem_result[k];
71 tmp_overflow = mem_overflow[k];
72 if (k >= 2004) begin
73 $display("|VUT OK| > All the signals are right-right!\n\n By Rodrigo Peixoto\n");
74 #5 $finish;
75 end //if
76 else #2 -> send;
77 end
80 always @ send begin
81 if (result !== tmp_result) begin
82 $display("|VUT FAIL|> Error in result value at time %0dns!!!",$time);
83 $finish;
84 end //if
85 if (overflow !== tmp_overflow) begin
86 $display("|VUT FAIL|> Error in overflow value at time %0dns!!!",$time);
87 $finish;
88 end //if
89 #3 -> ready;
90 end
94 endmodule