kernel/suspend.c

   1 /*
   2  * mahatma - a simple kernel framework
   3  * Copyright (c) 2008, 2009 Daniel Mack <daniel@caiaq.de>
   4  *
   5  * This program is free software: you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation, either version 3 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include "types.h"
  20 #include "regs.h"
  21 #include "wikireader.h"
  22 #include "irq.h"
  23 #include "diskio.h"
  24 #include "tff.h"
  25 #include "suspend.h"
  26
  27
  28 #include "msg.h"
  29
  30 #define SUSPEND_SDRAM 1
  31
  32 void system_suspend(void)
  33 {
  34         register int card_state = check_card_power();
  35
  36         disable_card_power();
  37         SDCARD_CS_HI();
  38         EEPROM_CS_HI();
  39
  40         DISABLE_IRQ();
  41         // no more function calls after this point
  42         // all code must be in-line
  43
  44 #if SUSPEND_SDRAM
  45
  46         REG_CMU_PROTECT = CMU_PROTECT_OFF;
  47         REG_CMU_OPT |= WAKEUPWT;
  48         REG_CMU_PROTECT = CMU_PROTECT_ON;
  49
  50         // SDRAM to self-refresh mode (disables clock)
  51         REG_SDRAMC_REF =
  52                 //SELDO |
  53                 //SCKON |
  54                 SELEN |
  55                 (0x7f << SELCO_SHIFT) |
  56                 (0 << AURCO_SHIFT) |
  57                 0;
  58
  59         BUSY_WAIT_FOR(REG_SDRAMC_REF & SELDO);
  60
  61         // SDRAMC controller off
  62         REG_SDRAMC_APP &= ~(
  63                 ARBON |
  64                 //DBF |
  65                 //INCR |
  66                 //CAS1 |
  67                 //CAS0 |
  68                 APPON |
  69                 //IQB |
  70                 0);
  71
  72         REG_CMU_PROTECT = CMU_PROTECT_OFF;
  73         REG_CMU_GATEDCLK0 &= ~(
  74                 //USBSAPB_CKE |
  75                 //USB_CKE |
  76                 //SDAPCPU_HCKE |
  77                 SDAPCPU_CKE |
  78                 SDAPLCDC_CKE |
  79                 SDSAPB_CKE |
  80                 //DSTRAM_CKE |
  81                 //LCDCAHBIF_CKE |
  82                 //LCDCSAPB_CKE |
  83                 //LCDC_CKE |
  84                 0);
  85         REG_CMU_PROTECT = CMU_PROTECT_ON;
  86
  87         // release the SDRAMC pin functions
  88         REG_P2_P2D = ~0;
  89         REG_P2_03_CFP = 0x01;
  90         REG_P2_47_CFP = 0x00;
  91 #endif
  92
  93         // adjust baud rate for lower clock frequency
  94         //REG_EFSIF0_BRTRDL = 12 & 0xff;
  95         //REG_EFSIF0_BRTRDM = 12 >> 8;
  96
  97         SET_BRTRD(0, CALC_BAUD(MCLK / 4, DIV, 57600));
  98         SET_BRTRD(1, CALC_BAUD(MCLK / 4, DIV, 38400));
  99
 100         // turn off un necessary clocks
 101         REG_CMU_PROTECT = CMU_PROTECT_OFF;
 102         REG_CMU_GATEDCLK0 &= ~(
 103                 USBSAPB_CKE |
 104                 USB_CKE |
 105                 SDAPCPU_HCKE |
 106                 SDAPCPU_CKE |
 107                 SDAPLCDC_CKE |
 108                 SDSAPB_CKE |
 109                 //DSTRAM_CKE |
 110                 //LCDCAHBIF_CKE |
 111                 //LCDCSAPB_CKE |
 112                 //LCDC_CKE |
 113                 0);
 114         REG_CMU_GATEDCLK1 =
 115                 CPUAHB_HCKE |
 116                 LCDCAHB_HCKE |
 117                 GPIONSTP_HCKE |
 118                 SRAMC_HCKE |
 119                 EFSIOBR_HCKE |
 120                 MISC_HCKE |
 121
 122                 IVRAMARB_CKE |
 123                 //TM5_CKE |
 124                 //TM4_CKE |
 125                 //TM3_CKE |
 126                 //TM2_CKE |
 127                 //TM1_CKE |
 128                 //TM0_CKE |
 129                 //EGPIO_MISC_CK |
 130                 //I2S_CKE |
 131                 //DCSIO_CKE |
 132                 //WDT_CKE |
 133                 //GPIO_CKE |
 134                 //SRAMSAPB_CKE |
 135                 //SPI_CKE |
 136                 EFSIOSAPB_CKE |
 137                 //CARD_CKE |
 138                 //ADC_CKE |
 139                 ITC_CKE |
 140                 //DMA_CKE |
 141                 //RTCSAPB_CKE |
 142                 0;
 143
 144         REG_CMU_CLKCNTL =
 145                 CMU_CLK_SEL_OSC3_DIV_32 |
 146                 //CMU_CLK_SEL_OSC3_DIV_16 |
 147                 //CMU_CLK_SEL_OSC3_DIV_8 |
 148                 //CMU_CLK_SEL_OSC3_DIV_4 |
 149                 //CMU_CLK_SEL_OSC3_DIV_2 |
 150                 //CMU_CLK_SEL_OSC3_DIV_1 |
 151                 //CMU_CLK_SEL_LCDC_CLK |
 152                 //CMU_CLK_SEL_MCLK |
 153                 //CMU_CLK_SEL_PLL |
 154                 //CMU_CLK_SEL_OSC1 |
 155                 //CMU_CLK_SEL_OSC3 |
 156
 157                 PLLINDIV_10 |
 158                 //PLLINDIV_9 |
 159                 //PLLINDIV_8 |
 160                 //PLLINDIV_7 |
 161                 //PLLINDIV_6 |
 162                 //PLLINDIV_5 |
 163                 //PLLINDIV_4 |
 164                 //PLLINDIV_3 |
 165                 //PLLINDIV_2 |
 166                 //PLLINDIV_1 |
 167
 168                 //LCDCDIV_16 |
 169                 //LCDCDIV_15 |
 170                 //LCDCDIV_14 |
 171                 //LCDCDIV_13 |
 172                 //LCDCDIV_12 |
 173                 //LCDCDIV_11 |
 174                 LCDCDIV_10 |
 175                 //LCDCDIV_9 |
 176                 //LCDCDIV_8 |
 177                 //LCDCDIV_7 |
 178                 //LCDCDIV_6 |
 179                 //LCDCDIV_5 |
 180                 //LCDCDIV_4 |
 181                 //LCDCDIV_3 |
 182                 //LCDCDIV_2 |
 183                 //LCDCDIV_1 |
 184
 185                 //MCLKDIV |
 186
 187                 //OSC3DIV_32 |
 188                 //OSC3DIV_16 |
 189                 //OSC3DIV_8 |
 190                 OSC3DIV_4 |
 191                 //OSC3DIV_2 |
 192                 //OSC3DIV_1 |
 193
 194
 195                 //OSCSEL_PLL |
 196                 //OSCSEL_OSC3 |
 197                 //OSCSEL_OSC1 |
 198                 OSCSEL_OSC3 |
 199
 200                 SOSC3 |
 201                 //SOSC1 |
 202                 0;
 203         REG_CMU_PROTECT = CMU_PROTECT_ON;
 204
 205         // end of suspend, wait for interrupt
 206         asm volatile ("halt");
 207         // interrupt is on hold until end of resume
 208
 209         // restore baud rate
 210
 211         SET_BRTRD(0, CALC_BAUD(MCLK, DIV, 57600));
 212         SET_BRTRD(1, CALC_BAUD(MCLK, DIV, 38400));
 213
 214         REG_CMU_PROTECT = CMU_PROTECT_OFF;
 215
 216         REG_CMU_CLKCNTL =
 217                 //CMU_CLK_SEL_OSC3_DIV_32 |
 218                 //CMU_CLK_SEL_OSC3_DIV_16 |
 219                 //CMU_CLK_SEL_OSC3_DIV_8 |
 220                 //CMU_CLK_SEL_OSC3_DIV_4 |
 221                 //CMU_CLK_SEL_OSC3_DIV_2 |
 222                 //CMU_CLK_SEL_OSC3_DIV_1 |
 223                 //CMU_CLK_SEL_LCDC_CLK |
 224                 //CMU_CLK_SEL_MCLK |
 225                 //CMU_CLK_SEL_PLL |
 226                 //CMU_CLK_SEL_OSC1 |
 227                 CMU_CLK_SEL_OSC3 |
 228
 229                 //PLLINDIV_10 |
 230                 //PLLINDIV_9 |
 231                 PLLINDIV_8 |
 232                 //PLLINDIV_7 |
 233                 //PLLINDIV_6 |
 234                 //PLLINDIV_5 |
 235                 //PLLINDIV_4 |
 236                 //PLLINDIV_3 |
 237                 //PLLINDIV_2 |
 238                 //PLLINDIV_1 |
 239
 240                 //LCDCDIV_16 |
 241                 //LCDCDIV_15 |
 242                 //LCDCDIV_14 |
 243                 //LCDCDIV_13 |
 244                 //LCDCDIV_12 |
 245                 //LCDCDIV_11 |
 246                 //LCDCDIV_10 |
 247                 //LCDCDIV_9 |
 248                 LCDCDIV_8 |
 249                 //LCDCDIV_7 |
 250                 //LCDCDIV_6 |
 251                 //LCDCDIV_5 |
 252                 //LCDCDIV_4 |
 253                 //LCDCDIV_3 |
 254                 //LCDCDIV_2 |
 255                 //LCDCDIV_1 |
 256
 257                 //MCLKDIV |
 258
 259                 //OSC3DIV_32 |
 260                 //OSC3DIV_16 |
 261                 //OSC3DIV_8 |
 262                 //OSC3DIV_4 |
 263                 //OSC3DIV_2 |
 264                 OSC3DIV_1 |
 265
 266
 267                 //OSCSEL_PLL |
 268                 //OSCSEL_OSC3 |
 269                 //OSCSEL_OSC1 |
 270                 OSCSEL_OSC3 |
 271
 272                 SOSC3 |
 273                 //SOSC1 |
 274                 0;
 275         REG_CMU_PROTECT = CMU_PROTECT_ON;
 276
 277         {
 278                 register unsigned int i = 0;
 279                 for (i = 0; i < 10000; i++) {
 280                         asm volatile ("nop");
 281                 }
 282         }
 283
 284         REG_CMU_PROTECT = CMU_PROTECT_OFF;
 285         REG_CMU_GATEDCLK0 =
 286                 //USBSAPB_CKE |
 287                 //USB_CKE |
 288                 //SDAPCPU_HCKE |
 289                 SDAPCPU_CKE |
 290                 SDAPLCDC_CKE |
 291                 SDSAPB_CKE |
 292                 DSTRAM_CKE |
 293                 LCDCAHBIF_CKE |
 294                 LCDCSAPB_CKE |
 295                 LCDC_CKE |
 296                 0;
 297         REG_CMU_GATEDCLK1 =
 298                 CPUAHB_HCKE |
 299                 LCDCAHB_HCKE |
 300                 GPIONSTP_HCKE |
 301                 SRAMC_HCKE |
 302                 EFSIOBR_HCKE |
 303                 MISC_HCKE |
 304                 IVRAMARB_CKE |
 305                 //TM5_CKE |
 306                 //TM4_CKE |
 307                 //TM3_CKE |
 308                 //TM2_CKE |
 309                 //TM1_CKE |
 310                 //TM0_CKE |
 311                 EGPIO_MISC_CK |
 312                 //I2S_CKE |
 313                 DCSIO_CKE |
 314                 WDT_CKE |
 315                 GPIO_CKE |
 316                 SRAMSAPB_CKE |
 317                 SPI_CKE |
 318                 EFSIOSAPB_CKE |
 319                 //CARD_CKE |
 320                 ADC_CKE |
 321                 ITC_CKE |
 322                 //DMA_CKE |
 323                 //RTCSAPB_CKE |
 324                 0;
 325         REG_CMU_PROTECT = CMU_PROTECT_ON;
 326
 327
 328 #if SUSPEND_SDRAM
 329         /* re-enable the SDRAMC pin functions */
 330         REG_P2_03_CFP = 0x55;
 331         REG_P2_47_CFP = 0x55;
 332
 333         // enable RAM and self-refresh
 334         REG_SDRAMC_APP |=
 335                 ARBON |
 336                 //DBF |
 337                 //INCR |
 338                 //CAS1 |
 339                 //CAS0 |
 340                 APPON |
 341                 IQB |
 342                 0;
 343         REG_SDRAMC_REF =
 344                 //SELDO |
 345                 SCKON |
 346                 SELEN |
 347                 (0x7f << SELCO_SHIFT) |
 348                 (0x8c << AURCO_SHIFT) |
 349                 0;
 350 #endif
 351
 352         ENABLE_IRQ();
 353         // it is now possible to call other functions
 354         // as SDRAM is operational again
 355
 356         // resume SD card
 357         if (card_state) {
 358                 disk_initialize(0);
 359         }
 360 }