3 Copyright (c) 2008 Daniel Mack <daniel@caiaq.de>
4 Copyright (c) 2009 Holger Hans Peter Freyther <zecke@openmoko.org>
6 This program is free software: you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation, either version 3 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program. If not, see <http://www.gnu.org/licenses/>.
22 #include "wikireader.h"
28 #define KERNEL "/KERNEL"
30 //#define POWER_MANAGEMENT 1
31 #define FAILED_BOOT_IMAGE_ADDR 0xc000
33 #ifdef POWER_MANAGEMENT
34 static void power_tests();
37 __attribute__((noreturn
))
47 /* value of default data area is hard-coded in this case */
48 asm("xld.w %r15, __dp");
50 /* enable SPI: master mode, no DMA, 8 bit transfers */
51 REG_SPI_CTL1
= 0x03 | (7 << 10) | (1 << 4);
54 #ifndef POWER_MANAGEMENT
55 print_u32(elf_exec(KERNEL
) * -1);
58 /* load the 'could not boot from SD card' image */
60 eeprom_load(FAILED_BOOT_IMAGE_ADDR
, (u8
*) LCD_VRAM
, LCD_VRAM_SIZE
);
65 for (i
= LCD_VRAM
; i
< LCD_VRAM
+ LCD_VRAM_SIZE
; ++i
)
70 /* if we get here, boot_from_sdcard() failed to find a kernel on the
71 * inserted media or there is no media. Thus, we register an
72 * interrupt handler for the SD card insert switch and try again as
73 * soon as a media switch is detected. */
76 #ifdef POWER_MANAGEMENT
85 #define READ_AND_CLEAR_CAUSE(REG) \
90 #define WAIT_FOR_CONDITION(cond) \
91 do { asm("nop"); } while(!(cond))
93 static void power_tests()
98 REG_CMU_PROTECT
= 0x96;
99 // REG_CMU_OPT |= 0x1;
102 /* wakeup sources, turn keyboard control 0 to wakeup */
103 REG_KINTCOMP_SCPK0
= 0x1f;
104 REG_KINTCOMP_SMPK0
= 0x10;
105 REG_KINTSEL_SPPK01
= 0x40;
106 REG_INT_EK01_EP0_3
= 0x10;
116 READ_AND_CLEAR_CAUSE(REG_INT_FSIF01
);
117 READ_AND_CLEAR_CAUSE(REG_INT_F16T01
);
118 READ_AND_CLEAR_CAUSE(REG_INT_FDMA
);
119 READ_AND_CLEAR_CAUSE(REG_INT_F16T23
);
120 READ_AND_CLEAR_CAUSE(REG_INT_F16T45
);
121 READ_AND_CLEAR_CAUSE(REG_INT_FP47_FRTC_FAD
);
122 READ_AND_CLEAR_CAUSE(REG_INT_FLCDC
);
123 READ_AND_CLEAR_CAUSE(REG_INT_FSIF2_FSPI
);
125 READ_AND_CLEAR_CAUSE(REG_INT_FK01_FP03
);
127 /* enable write access to clock control registers */
128 REG_CMU_PROTECT
= 0x96;
130 /* send the SDRAM to its self-refresh mode (which disables the clock) */
131 REG_SDRAMC_REF
= (1 << 23) | (0x7f << 16);
133 /* wait for the SELDO bit to be asserted */
134 WAIT_FOR_CONDITION(REG_SDRAMC_REF
& (1 << 25));
136 /* switch off the SDRAMC application core */
138 REG_CMU_GATEDCLK0
&= ~0x70;
140 /* release the SDRAMC pin functions */
141 REG_P2_03_CFP
= 0x01;
142 REG_P2_47_CFP
= 0x00;
144 //REG_CMU_GATEDCLK1 = (1 << 29) | (1 << 28) | (1 << 27) | (1 << 19) | (1 << 8);
145 REG_CMU_GATEDCLK1
= 0x3f08002f;
146 REG_CMU_GATEDCLK0
&= ~(1 << 1);
148 /* disable clocks we don't need in HALT mode */
149 REG_CMU_CLKCNTL
= (0xa << 24) | (8 << 16) | (1 << 12) | (1 << 1);
151 /* write protect CMU registers */
154 /*********************************************************/
156 /*********************************************************/
158 REG_CMU_PROTECT
= 0x96;
160 /* restore clock setup */
161 REG_CMU_CLKCNTL
= 0x00770002;
163 /* re-enable the SDRAMC pin functions */
164 REG_P2_03_CFP
= 0x55;
165 REG_P2_47_CFP
= 0x55;
167 /* re-enable all the clocks */
168 REG_CMU_GATEDCLK1
= 0x3f0fffff;
169 REG_CMU_GATEDCLK0
|= (1 << 1);