2 * Emulation of processor ioports.
4 * Copyright 1995 Morten Welinder
5 * Copyright 1998 Andreas Mohr, Ove Kaaven
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA
23 - only a few ports are emulated.
24 - real-time clock in "cmos" is bogus. A nifty alarm() setup could
40 #include "wine/unicode.h"
41 #include "wine/debug.h"
43 WINE_DEFAULT_DEBUG_CHANNEL(int);
45 #if defined(linux) && defined(__i386__)
46 # define DIRECT_IO_ACCESS
48 # undef DIRECT_IO_ACCESS
49 #endif /* linux && __i386__ */
58 {0xFFFF, 0, 0x36, 0, 0},
59 {0x0012, 0, 0x74, 0, 0},
60 {0x0001, 0, 0xB6, 0, 0},
62 /* two byte read in progress */
63 #define TMR_RTOGGLE 0x01
64 /* two byte write in progress */
65 #define TMR_WTOGGLE 0x02
66 /* latch contains data */
67 #define TMR_LATCHED 0x04
68 /* counter is in update phase */
69 #define TMR_UPDATE 0x08
70 /* readback status request */
71 #define TMR_STATUS 0x10
74 static BYTE parport_8255
[4] = {0x4f, 0x20, 0xff, 0xff};
76 static BYTE cmosaddress
;
78 static int cmos_image_initialized
= 0;
80 static BYTE cmosimage
[64] =
82 0x27, /* 0x00: seconds */
83 0x34, /* 0X01: seconds alarm */
84 0x31, /* 0x02: minutes */
85 0x47, /* 0x03: minutes alarm */
86 0x16, /* 0x04: hour */
87 0x15, /* 0x05: hour alarm */
88 0x00, /* 0x06: week day */
89 0x01, /* 0x07: month day */
90 0x04, /* 0x08: month */
91 0x94, /* 0x09: year */
92 0x26, /* 0x0a: state A */
93 0x02, /* 0x0b: state B */
94 0x50, /* 0x0c: state C */
95 0x80, /* 0x0d: state D */
96 0x00, /* 0x0e: state diagnostic */
97 0x00, /* 0x0f: state state shutdown */
98 0x40, /* 0x10: floppy type */
99 0xb1, /* 0x11: reserved */
100 0x00, /* 0x12: HD type */
101 0x9c, /* 0x13: reserved */
102 0x01, /* 0x14: equipment */
103 0x80, /* 0x15: low base memory */
104 0x02, /* 0x16: high base memory (0x280 => 640KB) */
105 0x00, /* 0x17: low extended memory */
106 0x3b, /* 0x18: high extended memory (0x3b00 => 15MB) */
107 0x00, /* 0x19: HD 1 extended type byte */
108 0x00, /* 0x1a: HD 2 extended type byte */
109 0xad, /* 0x1b: reserved */
110 0x02, /* 0x1c: reserved */
111 0x10, /* 0x1d: reserved */
112 0x00, /* 0x1e: reserved */
113 0x00, /* 0x1f: installed features */
114 0x08, /* 0x20: HD 1 low cylinder number */
115 0x00, /* 0x21: HD 1 high cylinder number */
116 0x00, /* 0x22: HD 1 heads */
117 0x26, /* 0x23: HD 1 low pre-compensation start */
118 0x00, /* 0x24: HD 1 high pre-compensation start */
119 0x00, /* 0x25: HD 1 low landing zone */
120 0x00, /* 0x26: HD 1 high landing zone */
121 0x00, /* 0x27: HD 1 sectors */
122 0x00, /* 0x28: options 1 */
123 0x00, /* 0x29: reserved */
124 0x00, /* 0x2a: reserved */
125 0x00, /* 0x2b: options 2 */
126 0x00, /* 0x2c: options 3 */
127 0x3f, /* 0x2d: reserved */
128 0xcc, /* 0x2e: low CMOS ram checksum (computed automatically) */
129 0xcc, /* 0x2f: high CMOS ram checksum (computed automatically) */
130 0x00, /* 0x30: low extended memory byte */
131 0x1c, /* 0x31: high extended memory byte */
132 0x19, /* 0x32: century byte */
133 0x81, /* 0x33: setup information */
134 0x00, /* 0x34: CPU speed */
135 0x0e, /* 0x35: HD 2 low cylinder number */
136 0x00, /* 0x36: HD 2 high cylinder number */
137 0x80, /* 0x37: HD 2 heads */
138 0x1b, /* 0x38: HD 2 low pre-compensation start */
139 0x7b, /* 0x39: HD 2 high pre-compensation start */
140 0x21, /* 0x3a: HD 2 low landing zone */
141 0x00, /* 0x3b: HD 2 high landing zone */
142 0x00, /* 0x3c: HD 2 sectors */
143 0x00, /* 0x3d: reserved */
144 0x05, /* 0x3e: reserved */
145 0x5f /* 0x3f: reserved */
148 static void IO_FixCMOSCheckSum(void)
153 for (i
=0x10; i
< 0x2d; i
++)
155 cmosimage
[0x2e] = sum
>> 8; /* yes, this IS hi byte !! */
156 cmosimage
[0x2f] = sum
& 0xff;
157 TRACE("calculated hi %02x, lo %02x\n", cmosimage
[0x2e], cmosimage
[0x2f]);
160 #ifdef DIRECT_IO_ACCESS
162 extern int iopl(int level
);
163 static char do_direct_port_access
= -1;
164 static char port_permissions
[0x10000];
169 #endif /* DIRECT_IO_ACCESS */
172 static int do_pp_port_access
= -1; /* -1: uninitialized, 1: not available
177 ((a)%10 + ((a)>>4)%10*10 + ((a)>>8)%10*100 + ((a)>>12)%10*1000)
179 ((a)%10 | (a)/10%10<<4 | (a)/100%10<<8 | (a)/1000%10<<12)
182 static void set_timer(unsigned timer
)
184 DWORD val
= tmr_8253
[timer
].countmax
;
186 if (tmr_8253
[timer
].ctrlbyte_ch
& 0x01)
189 tmr_8253
[timer
].flags
&= ~TMR_UPDATE
;
190 if (!QueryPerformanceCounter((LARGE_INTEGER
*)&tmr_8253
[timer
].start_time
))
191 WARN("QueryPerformanceCounter should not fail!\n");
194 case 0: /* System timer counter divisor */
197 case 1: /* RAM refresh */
198 FIXME("RAM refresh counter handling not implemented !\n");
200 case 2: /* cassette & speaker */
202 if ((parport_8255
[1] & 3) == 3)
204 TRACE("Beep (freq: %d) !\n", 1193180 / val
);
205 Beep(1193180 / val
, 20);
212 static WORD
get_timer_val(unsigned timer
)
215 WORD maxval
, val
= tmr_8253
[timer
].countmax
;
216 BYTE mode
= tmr_8253
[timer
].ctrlbyte_ch
>> 1 & 0x07;
218 /* This is not strictly correct. In most cases the old countdown should
219 * finish normally (by counting down to 0) or halt and not jump to 0.
220 * But we are calculating and not countig, so this seems to be a good
221 * solution and should work well with most (all?) programs
223 if (tmr_8253
[timer
].flags
& TMR_UPDATE
)
226 if (!QueryPerformanceCounter(&time
))
227 WARN("QueryPerformanceCounter should not fail!\n");
229 time
.QuadPart
-= tmr_8253
[timer
].start_time
;
230 if (tmr_8253
[timer
].ctrlbyte_ch
& 0x01)
239 maxval
= tmr_8253
[timer
].ctrlbyte_ch
& 0x01 ? 9999 : 0xFFFF;
246 ERR("Invalid PIT mode: %d\n", mode
);
250 val
= (val
- time
.QuadPart
) % (maxval
+ 1);
251 if (tmr_8253
[timer
].ctrlbyte_ch
& 0x01)
258 /**********************************************************************
262 /* set_IO_permissions(int val1, int val)
263 * Helper function for IO_port_init
265 #ifdef DIRECT_IO_ACCESS
266 static void set_IO_permissions(int val1
, int val
, char rw
)
270 if (val
== -1) val
= 0x3ff;
271 for (j
= val1
; j
<= val
; j
++)
272 port_permissions
[j
] |= rw
;
274 do_direct_port_access
= 1;
277 } else if (val
!= -1) {
278 do_direct_port_access
= 1;
280 port_permissions
[val
] |= rw
;
285 /* do_IO_port_init_read_or_write(char* temp, char rw)
286 * Helper function for IO_port_init
289 static void do_IO_port_init_read_or_write(const WCHAR
*str
, char rw
)
294 static const WCHAR allW
[] = {'a','l','l',0};
296 if (!strcmpiW(str
, allW
))
298 for (i
=0; i
< sizeof(port_permissions
); i
++)
299 port_permissions
[i
] |= rw
;
312 set_IO_permissions(val1
, val
, rw
);
319 if (val1
== -1) val1
= 0;
325 val
= strtoulW( str
, &end
, 0 );
336 set_IO_permissions(val1
, val
, rw
);
340 static inline BYTE
inb( WORD port
)
343 __asm__
__volatile__( "inb %w1,%0" : "=a" (b
) : "d" (port
) );
347 static inline WORD
inw( WORD port
)
350 __asm__
__volatile__( "inw %w1,%0" : "=a" (w
) : "d" (port
) );
354 static inline DWORD
inl( WORD port
)
357 __asm__
__volatile__( "inl %w1,%0" : "=a" (dw
) : "d" (port
) );
361 static inline void outb( BYTE value
, WORD port
)
363 __asm__
__volatile__( "outb %b0,%w1" : : "a" (value
), "d" (port
) );
366 static inline void outw( WORD value
, WORD port
)
368 __asm__
__volatile__( "outw %w0,%w1" : : "a" (value
), "d" (port
) );
371 static inline void outl( DWORD value
, WORD port
)
373 __asm__
__volatile__( "outl %0,%w1" : : "a" (value
), "d" (port
) );
376 static void IO_port_init(void)
381 OBJECT_ATTRIBUTES attr
;
382 UNICODE_STRING nameW
;
384 static const WCHAR portsW
[] = {'S','o','f','t','w','a','r','e','\\',
385 'W','i','n','e','\\','V','D','M','\\','P','o','r','t','s',0};
386 static const WCHAR readW
[] = {'r','e','a','d',0};
387 static const WCHAR writeW
[] = {'w','r','i','t','e',0};
389 do_direct_port_access
= 0;
390 /* Can we do that? */
395 RtlOpenCurrentUser( KEY_ALL_ACCESS
, &root
);
396 attr
.Length
= sizeof(attr
);
397 attr
.RootDirectory
= root
;
398 attr
.ObjectName
= &nameW
;
400 attr
.SecurityDescriptor
= NULL
;
401 attr
.SecurityQualityOfService
= NULL
;
402 RtlInitUnicodeString( &nameW
, portsW
);
404 /* @@ Wine registry key: HKCU\Software\Wine\VDM\Ports */
405 if (!NtOpenKey( &hkey
, KEY_ALL_ACCESS
, &attr
))
407 RtlInitUnicodeString( &nameW
, readW
);
408 if (!NtQueryValueKey( hkey
, &nameW
, KeyValuePartialInformation
, tmp
, sizeof(tmp
), &dummy
))
410 WCHAR
*str
= (WCHAR
*)((KEY_VALUE_PARTIAL_INFORMATION
*)tmp
)->Data
;
411 do_IO_port_init_read_or_write(str
, IO_READ
);
413 RtlInitUnicodeString( &nameW
, writeW
);
414 if (!NtQueryValueKey( hkey
, &nameW
, KeyValuePartialInformation
, tmp
, sizeof(tmp
), &dummy
))
416 WCHAR
*str
= (WCHAR
*)((KEY_VALUE_PARTIAL_INFORMATION
*)tmp
)->Data
;
417 do_IO_port_init_read_or_write(str
, IO_WRITE
);
425 #endif /* DIRECT_IO_ACCESS */
428 /**********************************************************************
431 * Note: The size argument has to be handled correctly _externally_
432 * (as we always return a DWORD)
434 DWORD WINAPI
DOSVM_inport( int port
, int size
)
438 TRACE("%d-byte value from port 0x%04x\n", size
, port
);
441 if (do_pp_port_access
== -1) do_pp_port_access
=IO_pp_init();
442 if ((do_pp_port_access
== 0 ) && (size
== 1))
444 if (!IO_pp_inp(port
,&res
)) return res
;
448 #ifdef DIRECT_IO_ACCESS
449 if (do_direct_port_access
== -1) IO_port_init();
450 if ((do_direct_port_access
)
451 /* Make sure we have access to the port */
452 && (port_permissions
[port
] & IO_READ
))
457 case 1: res
= inb( port
); break;
458 case 2: res
= inw( port
); break;
459 case 4: res
= inl( port
); break;
472 BYTE chan
= port
& 3;
473 WORD tempval
= tmr_8253
[chan
].flags
& TMR_LATCHED
474 ? tmr_8253
[chan
].latch
: get_timer_val(chan
);
476 if (tmr_8253
[chan
].flags
& TMR_STATUS
)
478 WARN("Read-back status\n");
479 /* We differ slightly from the spec:
480 * - TMR_UPDATE is already set with the first write
481 * of a two byte counter update
482 * - 0x80 should be set if OUT signal is 1 (high)
484 tmr_8253
[chan
].flags
&= ~TMR_STATUS
;
485 res
= (tmr_8253
[chan
].ctrlbyte_ch
& 0x3F) |
486 (tmr_8253
[chan
].flags
& TMR_UPDATE
? 0x40 : 0x00);
489 switch ((tmr_8253
[chan
].ctrlbyte_ch
& 0x30) >> 4)
492 res
= 0; /* shouldn't happen? */
494 case 1: /* read lo byte */
496 tmr_8253
[chan
].flags
&= ~TMR_LATCHED
;
498 case 3: /* read lo byte, then hi byte */
499 tmr_8253
[chan
].flags
^= TMR_RTOGGLE
; /* toggle */
500 if (tmr_8253
[chan
].flags
& TMR_RTOGGLE
)
505 /* else [fall through if read hi byte !] */
506 case 2: /* read hi byte */
507 res
= (BYTE
)(tempval
>> 8);
508 tmr_8253
[chan
].flags
&= ~TMR_LATCHED
;
514 res
= DOSVM_Int09ReadScan(NULL
);
517 res
= (DWORD
)parport_8255
[1];
520 res
= (DWORD
)parport_8255
[2];
523 res
= (DWORD
)cmosaddress
;
526 if (!cmos_image_initialized
)
528 IO_FixCMOSCheckSum();
529 cmos_image_initialized
= 1;
531 res
= (DWORD
)cmosimage
[cmosaddress
& 0x3f];
535 res
= ~0U; /* no joystick */
540 res
= (DWORD
)SB_ioport_in( port
);
542 /* VGA read registers */
543 case 0x3b4: /* CRT Controller Register - Index (MDA) */
544 case 0x3b5: /* CRT Controller Register - Other (MDA) */
545 case 0x3ba: /* General Register - Input status 1 (MDA) */
546 case 0x3c0: /* Attribute Controller - Address */
547 case 0x3c1: /* Attribute Controller - Other */
548 case 0x3c2: /* General Register - Input status 0 */
549 case 0x3c3: /* General Register - Video subsystem enable */
550 case 0x3c4: /* Sequencer Register - Address */
551 case 0x3c5: /* Sequencer Register - Other */
553 case 0x3c7: /* General Register - DAC State */
556 case 0x3ca: /* General Register - Feature control */
558 case 0x3cc: /* General Register - Misc output */
560 case 0x3ce: /* Graphics Controller Register - Address */
561 case 0x3cf: /* Graphics Controller Register - Other */
566 case 0x3d4: /* CRT Controller Register - Index (CGA) */
567 case 0x3d5: /* CRT Controller Register - Other (CGA) */
579 FIXME("Trying to read more than one byte from VGA!\n");
580 res
= (DWORD
)VGA_ioport_in( port
);
616 res
= (DWORD
)DMA_ioport_in( port
);
619 WARN("Direct I/O read attempted from port %x\n", port
);
626 /**********************************************************************
627 * outport (WINEDOS.@)
629 void WINAPI
DOSVM_outport( int port
, int size
, DWORD value
)
631 TRACE("IO: 0x%x (%d-byte value) to port 0x%04x\n", value
, size
, port
);
634 if (do_pp_port_access
== -1) do_pp_port_access
= IO_pp_init();
635 if ((do_pp_port_access
== 0) && (size
== 1))
637 if (!IO_pp_outp(port
,&value
)) return;
641 #ifdef DIRECT_IO_ACCESS
643 if (do_direct_port_access
== -1) IO_port_init();
644 if ((do_direct_port_access
)
645 /* Make sure we have access to the port */
646 && (port_permissions
[port
] & IO_WRITE
))
651 case 1: outb( LOBYTE(value
), port
); break;
652 case 2: outw( LOWORD(value
), port
); break;
653 case 4: outl( value
, port
); break;
663 DOSVM_PIC_ioport_out( port
, (BYTE
)value
);
669 BYTE chan
= port
& 3;
671 tmr_8253
[chan
].flags
|= TMR_UPDATE
;
672 switch ((tmr_8253
[chan
].ctrlbyte_ch
& 0x30) >> 4)
675 break; /* shouldn't happen? */
676 case 1: /* write lo byte */
677 tmr_8253
[chan
].countmax
=
678 (tmr_8253
[chan
].countmax
& 0xff00) | (BYTE
)value
;
680 case 3: /* write lo byte, then hi byte */
681 tmr_8253
[chan
].flags
^= TMR_WTOGGLE
; /* toggle */
682 if (tmr_8253
[chan
].flags
& TMR_WTOGGLE
)
684 tmr_8253
[chan
].countmax
=
685 (tmr_8253
[chan
].countmax
& 0xff00) | (BYTE
)value
;
688 /* else [fall through if write hi byte !] */
689 case 2: /* write hi byte */
690 tmr_8253
[chan
].countmax
=
691 (tmr_8253
[chan
].countmax
& 0x00ff) | ((BYTE
)value
<< 8);
694 /* if programming is finished, update to new value */
695 if ((tmr_8253
[chan
].ctrlbyte_ch
& 0x30) &&
696 !(tmr_8253
[chan
].flags
& TMR_WTOGGLE
))
702 BYTE chan
= ((BYTE
)value
& 0xc0) >> 6;
703 /* ctrl byte for specific timer channel */
706 if ( !(value
& 0x20) )
708 if (value
& 0x02 && !(tmr_8253
[0].flags
& TMR_LATCHED
))
710 tmr_8253
[0].flags
|= TMR_LATCHED
;
711 tmr_8253
[0].latch
= get_timer_val(0);
713 if (value
& 0x04 && !(tmr_8253
[1].flags
& TMR_LATCHED
))
715 tmr_8253
[1].flags
|= TMR_LATCHED
;
716 tmr_8253
[1].latch
= get_timer_val(1);
718 if (value
& 0x08 && !(tmr_8253
[2].flags
& TMR_LATCHED
))
720 tmr_8253
[2].flags
|= TMR_LATCHED
;
721 tmr_8253
[2].latch
= get_timer_val(2);
725 if ( !(value
& 0x10) )
728 tmr_8253
[0].flags
|= TMR_STATUS
;
730 tmr_8253
[1].flags
|= TMR_STATUS
;
732 tmr_8253
[2].flags
|= TMR_STATUS
;
736 switch (((BYTE
)value
& 0x30) >> 4)
738 case 0: /* latch timer */
739 if ( !(tmr_8253
[chan
].flags
& TMR_LATCHED
) )
741 tmr_8253
[chan
].flags
|= TMR_LATCHED
;
742 tmr_8253
[chan
].latch
= get_timer_val(chan
);
745 case 1: /* write lo byte only */
746 case 2: /* write hi byte only */
747 case 3: /* write lo byte, then hi byte */
748 tmr_8253
[chan
].ctrlbyte_ch
= (BYTE
)value
;
749 tmr_8253
[chan
].countmax
= 0;
750 tmr_8253
[chan
].flags
= TMR_UPDATE
;
756 parport_8255
[1] = (BYTE
)value
;
757 if (((parport_8255
[1] & 3) == 3) && (tmr_8253
[2].countmax
!= 1))
759 TRACE("Beep (freq: %d) !\n", 1193180 / tmr_8253
[2].countmax
);
760 Beep(1193180 / tmr_8253
[2].countmax
, 20);
764 cmosaddress
= (BYTE
)value
& 0x7f;
767 if (!cmos_image_initialized
)
769 IO_FixCMOSCheckSum();
770 cmos_image_initialized
= 1;
772 cmosimage
[cmosaddress
& 0x3f] = (BYTE
)value
;
776 SB_ioport_out( port
, (BYTE
)value
);
778 /* VGA Write registers */
779 case 0x3b4: /* CRT Controller Register - Index (MDA) */
780 case 0x3b5: /* CRT Controller Register - Other (MDA) */
781 case 0x3ba: /* General Register - Feature Control */
782 case 0x3c0: /* Attribute Controller - Address/Other */
784 case 0x3c2: /* General Register - Misc output */
785 case 0x3c3: /* General Register - Video subsystem enable */
786 case 0x3c4: /* Sequencer Register - Address */
787 case 0x3c5: /* Sequencer Register - Other */
796 case 0x3ce: /* Graphics Controller Register - Address */
797 case 0x3cf: /* Graphics Controller Register - Other */
802 case 0x3d4: /* CRT Controller Register - Index (CGA) */
803 case 0x3d5: /* CRT Controller Register - Other (CGA) */
814 VGA_ioport_out( port
, LOBYTE(value
) );
816 VGA_ioport_out( port
+1, HIBYTE(value
) );
818 VGA_ioport_out( port
+2, LOBYTE(HIWORD(value
)) );
819 VGA_ioport_out( port
+3, HIBYTE(HIWORD(value
)) );
869 DMA_ioport_out( port
, (BYTE
)value
);
872 WARN("Direct I/O write attempted to port %x\n", port
);