programs/winedbg/be_arm64.c

   1 /*
   2  * Debugger ARM64 specific functions
   3  *
   4  * Copyright 2010-2013 André Hentschel
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA
  19  */
  20
  21 #include "debugger.h"
  22
  23 #if defined(__aarch64__) && !defined(__AARCH64EB__)
  24
  25 static BOOL be_arm64_get_addr(HANDLE hThread, const dbg_ctx_t *ctx,
  26                               enum be_cpu_addr bca, ADDRESS64* addr)
  27 {
  28     switch (bca)
  29     {
  30     case be_cpu_addr_pc:
  31         return be_cpu_build_addr(hThread, ctx, addr, 0, ctx->ctx.Pc);
  32     case be_cpu_addr_stack:
  33         return be_cpu_build_addr(hThread, ctx, addr, 0, ctx->ctx.Sp);
  34     case be_cpu_addr_frame:
  35         return be_cpu_build_addr(hThread, ctx, addr, 0, ctx->ctx.u.s.Fp);
  36         break;
  37     }
  38     return FALSE;
  39 }
  40
  41 static BOOL be_arm64_get_register_info(int regno, enum be_cpu_addr* kind)
  42 {
  43     switch (regno)
  44     {
  45     case CV_ARM64_PC:      *kind = be_cpu_addr_pc;    return TRUE;
  46     case CV_ARM64_SP:      *kind = be_cpu_addr_stack; return TRUE;
  47     case CV_ARM64_FP:      *kind = be_cpu_addr_frame; return TRUE;
  48     }
  49     return FALSE;
  50 }
  51
  52 static void be_arm64_single_step(dbg_ctx_t *ctx, BOOL enable)
  53 {
  54     dbg_printf("be_arm64_single_step: not done\n");
  55 }
  56
  57 static void be_arm64_print_context(HANDLE hThread, const dbg_ctx_t *ctx, int all_regs)
  58 {
  59     static const char condflags[] = "NZCV";
  60     int i;
  61     char        buf[8];
  62
  63     switch (ctx->ctx.Cpsr & 0x0f)
  64     {
  65     case 0:  strcpy(buf, "EL0t"); break;
  66     case 4:  strcpy(buf, "EL1t"); break;
  67     case 5:  strcpy(buf, "EL1t"); break;
  68     case 8:  strcpy(buf, "EL2t"); break;
  69     case 9:  strcpy(buf, "EL2t"); break;
  70     case 12: strcpy(buf, "EL3t"); break;
  71     case 13: strcpy(buf, "EL3t"); break;
  72     default: strcpy(buf, "UNKNWN"); break;
  73     }
  74
  75     dbg_printf("Register dump:\n");
  76     dbg_printf("%s %s Mode\n", (ctx->ctx.Cpsr & 0x10) ? "ARM" : "ARM64", buf);
  77
  78     strcpy(buf, condflags);
  79     for (i = 0; buf[i]; i++)
  80         if (!((ctx->ctx.Cpsr >> 26) & (1 << (sizeof(condflags) - i))))
  81             buf[i] = '-';
  82
  83     dbg_printf(" Pc:%016lx Sp:%016lx Lr:%016lx Cpsr:%08x(%s)\n",
  84                ctx->ctx.Pc, ctx->ctx.Sp, ctx->ctx.u.s.Lr, ctx->ctx.Cpsr, buf);
  85     dbg_printf(" x0: %016lx x1: %016lx x2: %016lx x3: %016lx x4: %016lx\n",
  86                ctx->ctx.u.s.X0, ctx->ctx.u.s.X1, ctx->ctx.u.s.X2, ctx->ctx.u.s.X3, ctx->ctx.u.s.X4);
  87     dbg_printf(" x5: %016lx x6: %016lx x7: %016lx x8: %016lx x9: %016lx\n",
  88                ctx->ctx.u.s.X5, ctx->ctx.u.s.X6, ctx->ctx.u.s.X7, ctx->ctx.u.s.X8, ctx->ctx.u.s.X9);
  89     dbg_printf(" x10:%016lx x11:%016lx x12:%016lx x13:%016lx x14:%016lx\n",
  90                ctx->ctx.u.s.X10, ctx->ctx.u.s.X11, ctx->ctx.u.s.X12, ctx->ctx.u.s.X13, ctx->ctx.u.s.X14);
  91     dbg_printf(" x15:%016lx ip0:%016lx ip1:%016lx x18:%016lx x19:%016lx\n",
  92                ctx->ctx.u.s.X15, ctx->ctx.u.s.X16, ctx->ctx.u.s.X17, ctx->ctx.u.s.X18, ctx->ctx.u.s.X19);
  93     dbg_printf(" x20:%016lx x21:%016lx x22:%016lx x23:%016lx x24:%016lx\n",
  94                ctx->ctx.u.s.X20, ctx->ctx.u.s.X21, ctx->ctx.u.s.X22, ctx->ctx.u.s.X23, ctx->ctx.u.s.X24);
  95     dbg_printf(" x25:%016lx x26:%016lx x27:%016lx x28:%016lx Fp:%016lx\n",
  96                ctx->ctx.u.s.X25, ctx->ctx.u.s.X26, ctx->ctx.u.s.X27, ctx->ctx.u.s.X28, ctx->ctx.u.s.Fp);
  97
  98     if (all_regs) dbg_printf( "Floating point ARM64 dump not implemented\n" );
  99 }
 100
 101 static void be_arm64_print_segment_info(HANDLE hThread, const dbg_ctx_t *ctx)
 102 {
 103 }
 104
 105 static struct dbg_internal_var be_arm64_ctx[] =
 106 {
 107     {CV_ARM64_PSTATE,     "cpsr",   (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Cpsr),    dbg_itype_unsigned_int},
 108     {CV_ARM64_X0 +  0,    "x0",     (DWORD_PTR*)FIELD_OFFSET(CONTEXT, u.s.X0),  dbg_itype_unsigned_long_int},
 109     {CV_ARM64_X0 +  1,    "x1",     (DWORD_PTR*)FIELD_OFFSET(CONTEXT, u.s.X1),  dbg_itype_unsigned_long_int},
 110     {CV_ARM64_X0 +  2,    "x2",     (DWORD_PTR*)FIELD_OFFSET(CONTEXT, u.s.X2),  dbg_itype_unsigned_long_int},
 111     {CV_ARM64_X0 +  3,    "x3",     (DWORD_PTR*)FIELD_OFFSET(CONTEXT, u.s.X3),  dbg_itype_unsigned_long_int},
 112     {CV_ARM64_X0 +  4,    "x4",     (DWORD_PTR*)FIELD_OFFSET(CONTEXT, u.s.X4),  dbg_itype_unsigned_long_int},
 113     {CV_ARM64_X0 +  5,    "x5",     (DWORD_PTR*)FIELD_OFFSET(CONTEXT, u.s.X5),  dbg_itype_unsigned_long_int},
 114     {CV_ARM64_X0 +  6,    "x6",     (DWORD_PTR*)FIELD_OFFSET(CONTEXT, u.s.X6),  dbg_itype_unsigned_long_int},
 115     {CV_ARM64_X0 +  7,    "x7",     (DWORD_PTR*)FIELD_OFFSET(CONTEXT, u.s.X7),  dbg_itype_unsigned_long_int},
 116     {CV_ARM64_X0 +  8,    "x8",     (DWORD_PTR*)FIELD_OFFSET(CONTEXT, u.s.X8),  dbg_itype_unsigned_long_int},
 117     {CV_ARM64_X0 +  9,    "x9",     (DWORD_PTR*)FIELD_OFFSET(CONTEXT, u.s.X9),  dbg_itype_unsigned_long_int},
 118     {CV_ARM64_X0 +  10,   "x10",    (DWORD_PTR*)FIELD_OFFSET(CONTEXT, u.s.X10), dbg_itype_unsigned_long_int},
 119     {CV_ARM64_X0 +  11,   "x11",    (DWORD_PTR*)FIELD_OFFSET(CONTEXT, u.s.X11), dbg_itype_unsigned_long_int},
 120     {CV_ARM64_X0 +  12,   "x12",    (DWORD_PTR*)FIELD_OFFSET(CONTEXT, u.s.X12), dbg_itype_unsigned_long_int},
 121     {CV_ARM64_X0 +  13,   "x13",    (DWORD_PTR*)FIELD_OFFSET(CONTEXT, u.s.X13), dbg_itype_unsigned_long_int},
 122     {CV_ARM64_X0 +  14,   "x14",    (DWORD_PTR*)FIELD_OFFSET(CONTEXT, u.s.X14), dbg_itype_unsigned_long_int},
 123     {CV_ARM64_X0 +  15,   "x15",    (DWORD_PTR*)FIELD_OFFSET(CONTEXT, u.s.X15), dbg_itype_unsigned_long_int},
 124     {CV_ARM64_X0 +  16,   "x16",    (DWORD_PTR*)FIELD_OFFSET(CONTEXT, u.s.X16), dbg_itype_unsigned_long_int},
 125     {CV_ARM64_X0 +  17,   "x17",    (DWORD_PTR*)FIELD_OFFSET(CONTEXT, u.s.X17), dbg_itype_unsigned_long_int},
 126     {CV_ARM64_X0 +  18,   "x18",    (DWORD_PTR*)FIELD_OFFSET(CONTEXT, u.s.X18), dbg_itype_unsigned_long_int},
 127     {CV_ARM64_X0 +  19,   "x19",    (DWORD_PTR*)FIELD_OFFSET(CONTEXT, u.s.X19), dbg_itype_unsigned_long_int},
 128     {CV_ARM64_X0 +  20,   "x20",    (DWORD_PTR*)FIELD_OFFSET(CONTEXT, u.s.X20), dbg_itype_unsigned_long_int},
 129     {CV_ARM64_X0 +  21,   "x21",    (DWORD_PTR*)FIELD_OFFSET(CONTEXT, u.s.X21), dbg_itype_unsigned_long_int},
 130     {CV_ARM64_X0 +  22,   "x22",    (DWORD_PTR*)FIELD_OFFSET(CONTEXT, u.s.X22), dbg_itype_unsigned_long_int},
 131     {CV_ARM64_X0 +  23,   "x23",    (DWORD_PTR*)FIELD_OFFSET(CONTEXT, u.s.X23), dbg_itype_unsigned_long_int},
 132     {CV_ARM64_X0 +  24,   "x24",    (DWORD_PTR*)FIELD_OFFSET(CONTEXT, u.s.X24), dbg_itype_unsigned_long_int},
 133     {CV_ARM64_X0 +  25,   "x25",    (DWORD_PTR*)FIELD_OFFSET(CONTEXT, u.s.X25), dbg_itype_unsigned_long_int},
 134     {CV_ARM64_X0 +  26,   "x26",    (DWORD_PTR*)FIELD_OFFSET(CONTEXT, u.s.X26), dbg_itype_unsigned_long_int},
 135     {CV_ARM64_X0 +  27,   "x27",    (DWORD_PTR*)FIELD_OFFSET(CONTEXT, u.s.X27), dbg_itype_unsigned_long_int},
 136     {CV_ARM64_X0 +  28,   "x28",    (DWORD_PTR*)FIELD_OFFSET(CONTEXT, u.s.X28), dbg_itype_unsigned_long_int},
 137     {CV_ARM64_FP,         "fp",     (DWORD_PTR*)FIELD_OFFSET(CONTEXT, u.s.Fp),  dbg_itype_unsigned_long_int},
 138     {CV_ARM64_LR,         "lr",     (DWORD_PTR*)FIELD_OFFSET(CONTEXT, u.s.Lr),  dbg_itype_unsigned_long_int},
 139     {CV_ARM64_SP,         "sp",     (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Sp),      dbg_itype_unsigned_long_int},
 140     {CV_ARM64_PC,         "pc",     (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Pc),      dbg_itype_unsigned_long_int},
 141     {0,                   NULL,     0,                                          dbg_itype_none}
 142 };
 143
 144 static BOOL be_arm64_is_step_over_insn(const void* insn)
 145 {
 146     dbg_printf("be_arm64_is_step_over_insn: not done\n");
 147     return FALSE;
 148 }
 149
 150 static BOOL be_arm64_is_function_return(const void* insn)
 151 {
 152     dbg_printf("be_arm64_is_function_return: not done\n");
 153     return FALSE;
 154 }
 155
 156 static BOOL be_arm64_is_break_insn(const void* insn)
 157 {
 158     dbg_printf("be_arm64_is_break_insn: not done\n");
 159     return FALSE;
 160 }
 161
 162 static BOOL be_arm64_is_func_call(const void* insn, ADDRESS64* callee)
 163 {
 164     return FALSE;
 165 }
 166
 167 static BOOL be_arm64_is_jump(const void* insn, ADDRESS64* jumpee)
 168 {
 169     return FALSE;
 170 }
 171
 172 static BOOL be_arm64_insert_Xpoint(HANDLE hProcess, const struct be_process_io* pio,
 173                                    dbg_ctx_t *ctx, enum be_xpoint_type type,
 174                                    void* addr, unsigned long* val, unsigned size)
 175 {
 176     SIZE_T              sz;
 177
 178     switch (type)
 179     {
 180     case be_xpoint_break:
 181         if (!size) return FALSE;
 182         if (!pio->read(hProcess, addr, val, 4, &sz) || sz != 4) return FALSE;
 183     default:
 184         dbg_printf("Unknown/unsupported bp type %c\n", type);
 185         return FALSE;
 186     }
 187     return TRUE;
 188 }
 189
 190 static BOOL be_arm64_remove_Xpoint(HANDLE hProcess, const struct be_process_io* pio,
 191                                    dbg_ctx_t *ctx, enum be_xpoint_type type,
 192                                    void* addr, unsigned long val, unsigned size)
 193 {
 194     SIZE_T              sz;
 195
 196     switch (type)
 197     {
 198     case be_xpoint_break:
 199         if (!size) return FALSE;
 200         if (!pio->write(hProcess, addr, &val, 4, &sz) || sz == 4) return FALSE;
 201         break;
 202     default:
 203         dbg_printf("Unknown/unsupported bp type %c\n", type);
 204         return FALSE;
 205     }
 206     return TRUE;
 207 }
 208
 209 static BOOL be_arm64_is_watchpoint_set(const dbg_ctx_t *ctx, unsigned idx)
 210 {
 211     dbg_printf("be_arm64_is_watchpoint_set: not done\n");
 212     return FALSE;
 213 }
 214
 215 static void be_arm64_clear_watchpoint(dbg_ctx_t *ctx, unsigned idx)
 216 {
 217     dbg_printf("be_arm64_clear_watchpoint: not done\n");
 218 }
 219
 220 static int be_arm64_adjust_pc_for_break(dbg_ctx_t *ctx, BOOL way)
 221 {
 222     if (way)
 223     {
 224         ctx->ctx.Pc -= 4;
 225         return -4;
 226     }
 227     ctx->ctx.Pc += 4;
 228     return 4;
 229 }
 230
 231 static BOOL be_arm64_fetch_integer(const struct dbg_lvalue* lvalue, unsigned size,
 232                                    BOOL is_signed, LONGLONG* ret)
 233 {
 234     if (size != 1 && size != 2 && size != 4 && size != 8) return FALSE;
 235
 236     memset(ret, 0, sizeof(*ret)); /* clear unread bytes */
 237     /* FIXME: this assumes that debuggee and debugger use the same
 238      * integral representation
 239      */
 240     if (!memory_read_value(lvalue, size, ret)) return FALSE;
 241
 242     /* propagate sign information */
 243     if (is_signed && size < 8 && (*ret >> (size * 8 - 1)) != 0)
 244     {
 245         ULONGLONG neg = -1;
 246         *ret |= neg << (size * 8);
 247     }
 248     return TRUE;
 249 }
 250
 251 static BOOL be_arm64_fetch_float(const struct dbg_lvalue* lvalue, unsigned size,
 252                                  long double* ret)
 253 {
 254     char tmp[sizeof(long double)];
 255
 256     /* FIXME: this assumes that debuggee and debugger use the same
 257      * representation for reals
 258      */
 259     if (!memory_read_value(lvalue, size, tmp)) return FALSE;
 260
 261     if (size == sizeof(float)) *ret = *(float*)tmp;
 262     else if (size == sizeof(double)) *ret = *(double*)tmp;
 263     else if (size == sizeof(long double)) *ret = *(long double*)tmp;
 264     else return FALSE;
 265
 266     return TRUE;
 267 }
 268
 269 static BOOL be_arm64_store_integer(const struct dbg_lvalue* lvalue, unsigned size,
 270                                    BOOL is_signed, LONGLONG val)
 271 {
 272     /* this is simple if we're on a little endian CPU */
 273     return memory_write_value(lvalue, size, &val);
 274 }
 275
 276 void be_arm64_disasm_one_insn(ADDRESS64 *addr, int display)
 277 {
 278     dbg_printf("be_arm64_disasm_one_insn: not done\n");
 279 }
 280
 281 static BOOL be_arm64_get_context(HANDLE thread, dbg_ctx_t *ctx)
 282 {
 283     ctx->ctx.ContextFlags = CONTEXT_ALL;
 284     return GetThreadContext(thread, &ctx->ctx);
 285 }
 286
 287 static BOOL be_arm64_set_context(HANDLE thread, const dbg_ctx_t *ctx)
 288 {
 289     return SetThreadContext(thread, &ctx->ctx);
 290 }
 291
 292 #define REG(f,n,t,r)  {f, n, t, FIELD_OFFSET(CONTEXT, r), sizeof(((CONTEXT*)NULL)->r)}
 293
 294 static struct gdb_register be_arm64_gdb_register_map[] = {
 295     REG("core", "x0",   NULL,         u.s.X0),
 296     REG(NULL,   "x1",   NULL,         u.s.X1),
 297     REG(NULL,   "x2",   NULL,         u.s.X2),
 298     REG(NULL,   "x3",   NULL,         u.s.X3),
 299     REG(NULL,   "x4",   NULL,         u.s.X4),
 300     REG(NULL,   "x5",   NULL,         u.s.X5),
 301     REG(NULL,   "x6",   NULL,         u.s.X6),
 302     REG(NULL,   "x7",   NULL,         u.s.X7),
 303     REG(NULL,   "x8",   NULL,         u.s.X8),
 304     REG(NULL,   "x9",   NULL,         u.s.X9),
 305     REG(NULL,   "x10",  NULL,         u.s.X10),
 306     REG(NULL,   "x11",  NULL,         u.s.X11),
 307     REG(NULL,   "x12",  NULL,         u.s.X12),
 308     REG(NULL,   "x13",  NULL,         u.s.X13),
 309     REG(NULL,   "x14",  NULL,         u.s.X14),
 310     REG(NULL,   "x15",  NULL,         u.s.X15),
 311     REG(NULL,   "x16",  NULL,         u.s.X16),
 312     REG(NULL,   "x17",  NULL,         u.s.X17),
 313     REG(NULL,   "x18",  NULL,         u.s.X18),
 314     REG(NULL,   "x19",  NULL,         u.s.X19),
 315     REG(NULL,   "x20",  NULL,         u.s.X20),
 316     REG(NULL,   "x21",  NULL,         u.s.X21),
 317     REG(NULL,   "x22",  NULL,         u.s.X22),
 318     REG(NULL,   "x23",  NULL,         u.s.X23),
 319     REG(NULL,   "x24",  NULL,         u.s.X24),
 320     REG(NULL,   "x25",  NULL,         u.s.X25),
 321     REG(NULL,   "x26",  NULL,         u.s.X26),
 322     REG(NULL,   "x27",  NULL,         u.s.X27),
 323     REG(NULL,   "x28",  NULL,         u.s.X28),
 324     REG(NULL,   "x29",  NULL,         u.s.Fp),
 325     REG(NULL,   "x30",  NULL,         u.s.Lr),
 326     REG(NULL,   "sp",   "data_ptr",   Sp),
 327     REG(NULL,   "pc",   "code_ptr",   Pc),
 328     REG(NULL,   "cpsr", "cpsr_flags", Cpsr),
 329 };
 330
 331 struct backend_cpu be_arm64 =
 332 {
 333     IMAGE_FILE_MACHINE_ARM64,
 334     8,
 335     be_cpu_linearize,
 336     be_cpu_build_addr,
 337     be_arm64_get_addr,
 338     be_arm64_get_register_info,
 339     be_arm64_single_step,
 340     be_arm64_print_context,
 341     be_arm64_print_segment_info,
 342     be_arm64_ctx,
 343     be_arm64_is_step_over_insn,
 344     be_arm64_is_function_return,
 345     be_arm64_is_break_insn,
 346     be_arm64_is_func_call,
 347     be_arm64_is_jump,
 348     be_arm64_disasm_one_insn,
 349     be_arm64_insert_Xpoint,
 350     be_arm64_remove_Xpoint,
 351     be_arm64_is_watchpoint_set,
 352     be_arm64_clear_watchpoint,
 353     be_arm64_adjust_pc_for_break,
 354     be_arm64_fetch_integer,
 355     be_arm64_fetch_float,
 356     be_arm64_store_integer,
 357     be_arm64_get_context,
 358     be_arm64_set_context,
 359     be_arm64_gdb_register_map,
 360     ARRAY_SIZE(be_arm64_gdb_register_map),
 361 };
 362 #endif