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epan/dissectors/pidl/samr/samr.cnf cnf_dissect_lsa_BinaryString => lsarpc_dissect_str...
[wireshark-sm.git] / epan / dissectors / packet-ubertooth.c
blobf3987033f97f1893753a224d9f7f4c98c7957ef7
1 /* packet-ubertooth.c
2 * Routines for Ubertooth USB dissection
3 *
4 * Copyright 2013, Michal Labedzki for Tieto Corporation
5 *
6 * Wireshark - Network traffic analyzer
7 * By Gerald Combs <gerald@wireshark.org>
8 * Copyright 1998 Gerald Combs
9 *
10 * SPDX-License-Identifier: GPL-2.0-or-later
11 */
12
13 #include "config.h"
14
15 #include <epan/packet.h>
16 #include <epan/prefs.h>
17 #include <epan/expert.h>
18 #include <epan/addr_resolv.h>
19
20 #include "packet-bluetooth.h"
21 #include "packet-ubertooth.h"
22
23 static int proto_ubertooth;
24
25 static int hf_command;
26 static int hf_response;
27 static int hf_argument_0;
28 static int hf_argument_1;
29 static int hf_estimated_length;
30 static int hf_board_id;
31 static int hf_reserved;
32 static int hf_length;
33 static int hf_firmware_revision;
34 static int hf_firmware_compile_info;
35 static int hf_user_led;
36 static int hf_rx_led;
37 static int hf_tx_led;
38 static int hf_1v8_led;
39 static int hf_channel;
40 static int hf_status;
41 static int hf_serial_number;
42 static int hf_part_number;
43 static int hf_packet_type;
44 static int hf_chip_status_dma_overflow;
45 static int hf_chip_status_dma_error;
46 static int hf_chip_status_cs_trigger;
47 static int hf_chip_status_fifo_overflow;
48 static int hf_chip_status_rssi_trigger;
49 static int hf_chip_status_reserved;
50 static int hf_clock_ns;
51 static int hf_clock_100ns;
52 static int hf_rssi_min;
53 static int hf_rssi_max;
54 static int hf_rssi_avg;
55 static int hf_rssi_count;
56 static int hf_data;
57 static int hf_crc_verify;
58 static int hf_paen;
59 static int hf_hgm;
60 static int hf_modulation;
61 static int hf_power_amplifier_reserved;
62 static int hf_power_amplifier_level;
63 static int hf_range_test_valid;
64 static int hf_range_test_request_power_amplifier;
65 static int hf_range_test_request_number;
66 static int hf_range_test_reply_power_amplifier;
67 static int hf_range_test_reply_number;
68 static int hf_squelch;
69 static int hf_register;
70 static int hf_register_value;
71 static int hf_access_address;
72 static int hf_high_frequency;
73 static int hf_low_frequency;
74 static int hf_rx_packets;
75 static int hf_rssi_threshold;
76 static int hf_clock_offset;
77 static int hf_afh_map;
78 static int hf_bdaddr;
79 static int hf_usb_rx_packet;
80 static int hf_state;
81 static int hf_crc_init;
82 static int hf_hop_interval;
83 static int hf_hop_increment;
84 static int hf_usb_rx_packet_channel;
85 static int hf_spectrum_entry;
86 static int hf_frequency;
87 static int hf_rssi;
88 static int hf_jam_mode;
89 static int hf_ego_mode;
90 static int hf_cc2400_value;
91 static int hf_cc2400_main_resetn;
92 static int hf_cc2400_main_reserved_14_10;
93 static int hf_cc2400_main_fs_force_en;
94 static int hf_cc2400_main_rxn_tx;
95 static int hf_cc2400_main_reserved_7_4;
96 static int hf_cc2400_main_reserved_3;
97 static int hf_cc2400_main_reserved_2;
98 static int hf_cc2400_main_xosc16m_bypass;
99 static int hf_cc2400_main_xosc16m_en;
100 static int hf_cc2400_fsctrl_reserved;
101 static int hf_cc2400_fsctrl_lock_threshold;
102 static int hf_cc2400_fsctrl_cal_done;
103 static int hf_cc2400_fsctrl_cal_running;
104 static int hf_cc2400_fsctrl_lock_length;
105 static int hf_cc2400_fsctrl_lock_status;
106 static int hf_cc2400_fsdiv_reserved;
107 static int hf_cc2400_fsdiv_frequency;
108 static int hf_cc2400_fsdiv_freq_high;
109 static int hf_cc2400_fsdiv_freq;
110 static int hf_cc2400_mdmctrl_reserved;
111 static int hf_cc2400_mdmctrl_mod_offset;
112 static int hf_cc2400_mdmctrl_mod_dev;
113 static int hf_cc2400_agcctrl_vga_gain;
114 static int hf_cc2400_agcctrl_reserved;
115 static int hf_cc2400_agcctrl_agc_locked;
116 static int hf_cc2400_agcctrl_agc_lock;
117 static int hf_cc2400_agcctrl_agc_sync_lock;
118 static int hf_cc2400_agcctrl_vga_gain_oe;
119 static int hf_cc2400_frend_reserved_15_4;
120 static int hf_cc2400_frend_reserved_3;
121 static int hf_cc2400_frend_pa_level;
122 static int hf_cc2400_rssi_rssi_val;
123 static int hf_cc2400_rssi_rssi_cs_thres;
124 static int hf_cc2400_rssi_rssi_filt;
125 static int hf_cc2400_freqest_rx_freq_offset;
126 static int hf_cc2400_freqest_reserved;
127 static int hf_cc2400_iocfg_reserved;
128 static int hf_cc2400_iocfg_gio6_cfg;
129 static int hf_cc2400_iocfg_gio1_cfg;
130 static int hf_cc2400_iocfg_hssd_src;
131 static int hf_cc2400_fsmtc_tc_rxon2agcen;
132 static int hf_cc2400_fsmtc_tc_paon2switch;
133 static int hf_cc2400_fsmtc_res;
134 static int hf_cc2400_fsmtc_tc_txend2switch;
135 static int hf_cc2400_fsmtc_tc_txend2paoff;
136 static int hf_cc2400_reserved_0x0C_res_15_5;
137 static int hf_cc2400_reserved_0x0C_res_4_0;
138 static int hf_cc2400_manand_vga_reset_n;
139 static int hf_cc2400_manand_lock_status;
140 static int hf_cc2400_manand_balun_ctrl;
141 static int hf_cc2400_manand_rxtx;
142 static int hf_cc2400_manand_pre_pd;
143 static int hf_cc2400_manand_pa_n_pd;
144 static int hf_cc2400_manand_pa_p_pd;
145 static int hf_cc2400_manand_dac_lpf_pd;
146 static int hf_cc2400_manand_bias_pd;
147 static int hf_cc2400_manand_xosc16m_pd;
148 static int hf_cc2400_manand_chp_pd;
149 static int hf_cc2400_manand_fs_pd;
150 static int hf_cc2400_manand_adc_pd;
151 static int hf_cc2400_manand_vga_pd;
152 static int hf_cc2400_manand_rxbpf_pd;
153 static int hf_cc2400_manand_lnamix_pd;
154 static int hf_cc2400_fsmstate_reserved_15_13;
155 static int hf_cc2400_fsmstate_fsm_state_bkpt;
156 static int hf_cc2400_fsmstate_reserved_7_5;
157 static int hf_cc2400_fsmstate_fsm_cur_state;
158 static int hf_cc2400_adctst_reserved_15;
159 static int hf_cc2400_adctst_adc_i;
160 static int hf_cc2400_adctst_reserved_7;
161 static int hf_cc2400_adctst_adc_q;
162 static int hf_cc2400_rxbpftst_reserved;
163 static int hf_cc2400_rxbpftst_rxbpf_cap_oe;
164 static int hf_cc2400_rxbpftst_rxbpf_cap_o;
165 static int hf_cc2400_rxbpftst_rxbpf_cap_res;
166 static int hf_cc2400_pamtst_reserved_15_13;
167 static int hf_cc2400_pamtst_vc_in_test_en;
168 static int hf_cc2400_pamtst_atestmod_pd;
169 static int hf_cc2400_pamtst_atestmod_mode;
170 static int hf_cc2400_pamtst_reserved_7;
171 static int hf_cc2400_pamtst_txmix_cap_array;
172 static int hf_cc2400_pamtst_txmix_current;
173 static int hf_cc2400_pamtst_pa_current;
174 static int hf_cc2400_lmtst_reserved;
175 static int hf_cc2400_lmtst_rxmix_hgm;
176 static int hf_cc2400_lmtst_rxmix_tail;
177 static int hf_cc2400_lmtst_rxmix_vcm;
178 static int hf_cc2400_lmtst_rxmix_current;
179 static int hf_cc2400_lmtst_lna_cap_array;
180 static int hf_cc2400_lmtst_lna_lowgain;
181 static int hf_cc2400_lmtst_lna_gain;
182 static int hf_cc2400_lmtst_lna_current;
183 static int hf_cc2400_manor_vga_reset_n;
184 static int hf_cc2400_manor_lock_status;
185 static int hf_cc2400_manor_balun_ctrl;
186 static int hf_cc2400_manor_rxtx;
187 static int hf_cc2400_manor_pre_pd;
188 static int hf_cc2400_manor_pa_n_pd;
189 static int hf_cc2400_manor_pa_p_pd;
190 static int hf_cc2400_manor_dac_lpf_pd;
191 static int hf_cc2400_manor_bias_pd;
192 static int hf_cc2400_manor_xosc16m_pd;
193 static int hf_cc2400_manor_chp_pd;
194 static int hf_cc2400_manor_fs_pd;
195 static int hf_cc2400_manor_adc_pd;
196 static int hf_cc2400_manor_vga_pd;
197 static int hf_cc2400_manor_rxbpf_pd;
198 static int hf_cc2400_manor_lnamix_pd;
199 static int hf_cc2400_mdmtst0_reserved;
200 static int hf_cc2400_mdmtst0_tx_prng;
201 static int hf_cc2400_mdmtst0_tx_1mhz_offset_n;
202 static int hf_cc2400_mdmtst0_invert_data;
203 static int hf_cc2400_mdmtst0_afc_adjust_on_packet;
204 static int hf_cc2400_mdmtst0_afc_settling;
205 static int hf_cc2400_mdmtst0_afc_delta;
206 static int hf_cc2400_mdmtst1_reserved;
207 static int hf_cc2400_mdmtst1_bsync_threshold;
208 static int hf_cc2400_dactst_reserved;
209 static int hf_cc2400_dactst_dac_src;
210 static int hf_cc2400_dactst_dac_i_o;
211 static int hf_cc2400_dactst_dac_q_o;
212 static int hf_cc2400_agctst0_agc_settle_blank_dn;
213 static int hf_cc2400_agctst0_agc_win_size;
214 static int hf_cc2400_agctst0_agc_settle_peak;
215 static int hf_cc2400_agctst0_agc_settle_adc;
216 static int hf_cc2400_agctst0_agc_attempts;
217 static int hf_cc2400_agctst1_reserved;
218 static int hf_cc2400_agctst1_agc_var_gain_sat;
219 static int hf_cc2400_agctst1_agc_settle_blank_up;
220 static int hf_cc2400_agctst1_peakdet_cur_boost;
221 static int hf_cc2400_agctst1_agc_mult_slow;
222 static int hf_cc2400_agctst1_agc_settle_fixed;
223 static int hf_cc2400_agctst1_agc_settle_var;
224 static int hf_cc2400_agctst2_reserved;
225 static int hf_cc2400_agctst2_agc_backend_blanking;
226 static int hf_cc2400_agctst2_agc_adjust_m3db;
227 static int hf_cc2400_agctst2_agc_adjust_m1db;
228 static int hf_cc2400_agctst2_agc_adjust_p3db;
229 static int hf_cc2400_agctst2_agc_adjust_p1db;
230 static int hf_cc2400_fstst0_rxmixbuf_cur;
231 static int hf_cc2400_fstst0_txmixbuf_cur;
232 static int hf_cc2400_fstst0_vco_array_settle_long;
233 static int hf_cc2400_fstst0_vco_array_oe;
234 static int hf_cc2400_fstst0_vco_array_o;
235 static int hf_cc2400_fstst0_vco_array_res;
236 static int hf_cc2400_fstst1_rxbpf_locur;
237 static int hf_cc2400_fstst1_rxbpf_midcur;
238 static int hf_cc2400_fstst1_vco_current_ref;
239 static int hf_cc2400_fstst1_vco_current_k;
240 static int hf_cc2400_fstst1_vc_dac_en;
241 static int hf_cc2400_fstst1_vc_dac_val;
242 static int hf_cc2400_fstst2_reserved;
243 static int hf_cc2400_fstst2_vco_curcal_speed;
244 static int hf_cc2400_fstst2_vco_current_oe;
245 static int hf_cc2400_fstst2_vco_current_o;
246 static int hf_cc2400_fstst2_vco_current_res;
247 static int hf_cc2400_fstst3_reserved;
248 static int hf_cc2400_fstst3_chp_test_up;
249 static int hf_cc2400_fstst3_chp_test_dn;
250 static int hf_cc2400_fstst3_chp_disable;
251 static int hf_cc2400_fstst3_pd_delay;
252 static int hf_cc2400_fstst3_chp_step_period;
253 static int hf_cc2400_fstst3_stop_chp_current;
254 static int hf_cc2400_fstst3_start_chp_current;
255 static int hf_cc2400_manfidl_partnum;
256 static int hf_cc2400_manfidl_manfid;
257 static int hf_cc2400_manfidh_version;
258 static int hf_cc2400_manfidh_partnum;
259 static int hf_cc2400_grmdm_reserved;
260 static int hf_cc2400_grmdm_sync_errbits_allowed;
261 static int hf_cc2400_grmdm_pin_mode;
262 static int hf_cc2400_grmdm_packet_mode;
263 static int hf_cc2400_grmdm_pre_bytes;
264 static int hf_cc2400_grmdm_sync_word_size;
265 static int hf_cc2400_grmdm_crc_on;
266 static int hf_cc2400_grmdm_data_format;
267 static int hf_cc2400_grmdm_modulation_format;
268 static int hf_cc2400_grmdm_tx_gaussian_filter;
269 static int hf_cc2400_grdec_reserved;
270 static int hf_cc2400_grdec_ind_saturation;
271 static int hf_cc2400_grdec_dec_shift;
272 static int hf_cc2400_grdec_channel_dec;
273 static int hf_cc2400_grdec_dec_val;
274 static int hf_cc2400_pktstatus_reserved_15_11;
275 static int hf_cc2400_pktstatus_sync_word_received;
276 static int hf_cc2400_pktstatus_crc_ok;
277 static int hf_cc2400_pktstatus_reserved_8;
278 static int hf_cc2400_pktstatus_reserved_7_0;
279 static int hf_cc2400_int_reserved_15_8;
280 static int hf_cc2400_int_reserved_7;
281 static int hf_cc2400_int_pkt_polarity;
282 static int hf_cc2400_int_fifo_polarity;
283 static int hf_cc2400_int_fifo_threshold;
284 static int hf_cc2400_reserved_0x24_res_15_14;
285 static int hf_cc2400_reserved_0x24_res_13_10;
286 static int hf_cc2400_reserved_0x24_res_9_7;
287 static int hf_cc2400_reserved_0x24_res_6_0;
288 static int hf_cc2400_reserved_0x25_res_15_12;
289 static int hf_cc2400_reserved_0x25_res_11_0;
290 static int hf_cc2400_reserved_0x26_res_15_10;
291 static int hf_cc2400_reserved_0x26_res_9_0;
292 static int hf_cc2400_reserved_0x27_res_15_8;
293 static int hf_cc2400_reserved_0x27_res_7_3;
294 static int hf_cc2400_reserved_0x27_res_2_0;
295 static int hf_cc2400_reserved_0x28_res_15;
296 static int hf_cc2400_reserved_0x28_res_14_13;
297 static int hf_cc2400_reserved_0x28_res_12_7;
298 static int hf_cc2400_reserved_0x28_res_6_0;
299 static int hf_cc2400_reserved_0x29_res_15_8;
300 static int hf_cc2400_reserved_0x29_res_7_3;
301 static int hf_cc2400_reserved_0x29_res_2_0;
302 static int hf_cc2400_reserved_0x2A_res_15_11;
303 static int hf_cc2400_reserved_0x2A_res_10;
304 static int hf_cc2400_reserved_0x2A_res_9_0;
305 static int hf_cc2400_reserved_0x2B_res_15_14;
306 static int hf_cc2400_reserved_0x2B_res_13;
307 static int hf_cc2400_reserved_0x2B_res_12;
308 static int hf_cc2400_reserved_0x2B_res_11_0;
309 static int hf_cc2400_syncl;
310 static int hf_cc2400_synch;
311
312 static int ett_ubertooth;
313 static int ett_command;
314 static int ett_usb_rx_packet;
315 static int ett_usb_rx_packet_data;
316 static int ett_entry;
317 static int ett_register_value;
318 static int ett_fsdiv_frequency;
319
320 static expert_field ei_unexpected_response;
321 static expert_field ei_unknown_data;
322 static expert_field ei_unexpected_data;
323
324 static dissector_handle_t ubertooth_handle;
325 static dissector_handle_t bluetooth_ubertooth_handle;
326
327 static wmem_tree_t *command_info;
328
329 typedef struct _command_data {
330 uint32_t bus_id;
331 uint32_t device_address;
332
333 uint8_t command;
334 uint32_t command_frame_number;
335 int32_t register_id;
336 } command_data_t;
337
338
339 static const value_string command_vals[] = {
340 { 0, "Ping" },
341 { 1, "Rx Symbols" },
342 { 2, "Tx Symbols" },
343 { 3, "Get User LED" },
344 { 4, "Set User LED" },
345 { 5, "Get Rx LED" },
346 { 6, "Set Rx LED" },
347 { 7, "Get Tx LED" },
348 { 8, "Set Tx LED" },
349 { 9, "Get 1V8" },
350 { 10, "Set 1V8" },
351 { 11, "Get Channel" },
352 { 12, "Set Channel" },
353 { 13, "Reset" },
354 { 14, "Get Microcontroller Serial Number" },
355 { 15, "Get Microcontroller Part Number" },
356 { 16, "Get PAEN" },
357 { 17, "Set PAEN" },
358 { 18, "Get HGM" },
359 { 19, "Set HGM" },
360 { 20, "Tx Test" },
361 { 21, "Stop" },
362 { 22, "Get Modulation" },
363 { 23, "Set Modulation" },
364 { 24, "Set ISP" },
365 { 25, "Flash" },
366 { 26, "Bootloader Flash" },
367 { 27, "Spectrum Analyzer" },
368 { 28, "Get Power Amplifier Level" },
369 { 29, "Set Power Amplifier Level" },
370 { 30, "Repeater" },
371 { 31, "Range Test" },
372 { 32, "Range Check" },
373 { 33, "Get Firmware Revision Number" },
374 { 34, "LED Spectrum Analyzer" },
375 { 35, "Get Hardware Board ID" },
376 { 36, "Set Squelch" },
377 { 37, "Get Squelch" },
378 { 38, "Set BDADDR" },
379 { 39, "Start Hopping" },
380 { 40, "Set Clock" },
381 { 41, "Get Clock" },
382 { 42, "BTLE Sniffing" },
383 { 43, "Get Access Address" },
384 { 44, "Set Access Address" },
385 { 45, "Do Something" },
386 { 46, "Do Something Reply" },
387 { 47, "Get CRC Verify" },
388 { 48, "Set CRC Verify" },
389 { 49, "Poll" },
390 { 50, "BTLE Promiscuous Mode" },
391 { 51, "Set AFH Map" },
392 { 52, "Clear AFH Map" },
393 { 53, "Read Register" },
394 { 54, "BTLE Slave" },
395 { 55, "Get Compile Info" },
396 { 56, "BTLE Set Target" },
397 { 57, "BTLE Phy" },
398 { 58, "Write Register" },
399 { 59, "Jam Mode" },
400 { 60, "Ego" },
401 { 0x00, NULL }
402 };
403 static value_string_ext(command_vals_ext) = VALUE_STRING_EXT_INIT(command_vals);
404
405 static const value_string board_id_vals[] = {
406 { 0x00, "Ubertooth Zero" },
407 { 0x01, "Ubertooth One" },
408 { 0x02, "ToorCon 13 Badge" },
409 { 0x00, NULL }
410 };
411 static value_string_ext(board_id_vals_ext) = VALUE_STRING_EXT_INIT(board_id_vals);
412
413 static const value_string led_state_vals[] = {
414 { 0x00, "Off" },
415 { 0x01, "On" },
416 { 0x00, NULL }
417 };
418 static value_string_ext(led_state_vals_ext) = VALUE_STRING_EXT_INIT(led_state_vals);
419
420 static const value_string state_vals[] = {
421 { 0x00, "False" },
422 { 0x01, "True" },
423 { 0x00, NULL }
424 };
425 static value_string_ext(state_vals_ext) = VALUE_STRING_EXT_INIT(state_vals);
426
427 static const value_string packet_type_vals[] = {
428 { 0x00, "BR/EDR" },
429 { 0x01, "LE" },
430 { 0x02, "Message" },
431 { 0x03, "Keep Alive" },
432 { 0x04, "Spectrum Analyze"},
433 { 0x05, "LE Promiscuous" },
434 { 0x06, "Ego Packet" },
435 { 0x00, NULL }
436 };
437 static value_string_ext(packet_type_vals_ext) = VALUE_STRING_EXT_INIT(packet_type_vals);
438
439 static const value_string usb_rx_packet_state_vals[] = {
440 { 0x00, "Access Address" },
441 { 0x01, "CRC Init" },
442 { 0x02, "Hop Interval" },
443 { 0x03, "Hop Increment" },
444 { 0x00, NULL }
445 };
446
447 static const value_string modulation_vals[] = {
448 { 0x00, "Basic Rate" },
449 { 0x01, "Low Energy" },
450 { 0x02, "802.11 FHSS" },
451 { 0x00, NULL }
452 };
453 static value_string_ext(modulation_vals_ext) = VALUE_STRING_EXT_INIT(modulation_vals);
454
455
456 static const value_string jam_mode_vals[] = {
457 { 0x00, "None" },
458 { 0x01, "Once" },
459 { 0x02, "Continuous" },
460 { 0x00, NULL }
461 };
462
463
464 static const value_string ego_mode_vals[] = {
465 { 0x00, "Follow" },
466 { 0x01, "Continuous Rx" },
467 { 0x02, "Jam" },
468 { 0x00, NULL }
469 };
470
471 static const value_string register_vals[] = {
472 { 0x00, "MAIN" },
473 { 0x01, "FSCTRL" },
474 { 0x02, "FSDIV" },
475 { 0x03, "MDMCTRL" },
476 { 0x04, "AGCCTRL" },
477 { 0x05, "FREND" },
478 { 0x06, "RSSI" },
479 { 0x07, "FREQEST" },
480 { 0x08, "IOCFG" },
481 { 0x0B, "FSMTC" },
482 { 0x0C, "RESERVED 0x0C" },
483 { 0x0D, "MANAND" },
484 { 0x0E, "FSMSTATE" },
485 { 0x0F, "ADCTST" },
486 { 0x10, "RXBPFTST" },
487 { 0x11, "PAMTST" },
488 { 0x12, "LMTST" },
489 { 0x13, "MANOR" },
490 { 0x14, "MDMTST0" },
491 { 0x15, "MDMTST1" },
492 { 0x16, "DACTST" },
493 { 0x17, "AGCTST0" },
494 { 0x18, "AGCTST1" },
495 { 0x19, "AGCTST2" },
496 { 0x1A, "FSTST0" },
497 { 0x1B, "FSTST1" },
498 { 0x1C, "FSTST2" },
499 { 0x1D, "FSTST3" },
500 { 0x1E, "MANFIDL" },
501 { 0x1F, "MANFIDH" },
502 { 0x20, "GRMDM" },
503 { 0x21, "GRDEC" },
504 { 0x22, "PKTSTATUS" },
505 { 0x23, "INT" },
506 { 0x24, "RESERVED 0x24" },
507 { 0x25, "RESERVED 0x25" },
508 { 0x26, "RESERVED 0x26" },
509 { 0x27, "RESERVED 0x27" },
510 { 0x28, "RESERVED 0x28" },
511 { 0x29, "RESERVED 0x29" },
512 { 0x2A, "RESERVED 0x2A" },
513 { 0x2B, "RESERVED 0x2B" },
514 { 0x2C, "SYNCL" },
515 { 0x2D, "SYNCH" },
516 { 0x60, "SXOSCON" },
517 { 0x61, "SFSON" },
518 { 0x62, "SRX" },
519 { 0x63, "STX" },
520 { 0x64, "SRFOFF" },
521 { 0x65, "SXOSCOFF" },
522 { 0x70, "FIFOREG" },
523 { 0x00, NULL }
524 };
525 static value_string_ext(register_vals_ext) = VALUE_STRING_EXT_INIT(register_vals);
526
527 static const value_string register_description_vals[] = {
528 { 0x00, "Main Control Register" },
529 { 0x01, "Frequency Synthesiser Control and Status" },
530 { 0x02, "Frequency Synthesiser Frequency Division Control" },
531 { 0x03, "Modem Control and Status" },
532 { 0x04, "Automatic Gain Control and Status" },
533 { 0x05, "Front-end Control Register" },
534 { 0x06, "Received Signal Strength Indicator Status and Control Register" },
535 { 0x07, "Received Frequency Offset Estimation" },
536 { 0x08, "IO Configuration Register" },
537 { 0x0B, "Finite State Machine Time Constants" },
538 { 0x0C, "Reserved Register Containing Spare Control and Status Bits" },
539 { 0x0D, "Manual Signal and Override Register" },
540 { 0x0E, "Finite State Machine Information and Breakpoint" },
541 { 0x0F, "Analog-to-Digital Converter Test Register" },
542 { 0x10, "Receiver Band-pass Filters Test Register" },
543 { 0x11, "Power Amplifier and Transmit Mixers Test Register" },
544 { 0x12, "Low Noise Amplifier and Receive Mixers Test Register" },
545 { 0x13, "Manual Signal or Override Register" },
546 { 0x14, "Modem Test Register 0" },
547 { 0x15, "Modem Test Register 1" },
548 { 0x16, "Digital-to-Analog Converter Test Register" },
549 { 0x17, "Automatic Gain Control Test Register 0" },
550 { 0x18, "Automatic Gain Control Test Register 1" },
551 { 0x19, "Automatic Gain Control Test Register 2" },
552 { 0x1A, "Frequency Synthesiser Test Register 0" },
553 { 0x1B, "Frequency Synthesiser Test Register 1" },
554 { 0x1C, "Frequency Synthesiser Test Register 2" },
555 { 0x1D, "Frequency Synthesiser Test Register 3" },
556 { 0x1E, "Manufacturer ID, Lower 16 Bit" },
557 { 0x1F, "Manufacturer ID, Upper 16 Bit" },
558 { 0x20, "Generic Radio Modem Control and Status" },
559 { 0x21, "Generic Radio Decimation Control and Status" },
560 { 0x22, "Packet Mode Status" },
561 { 0x23, "Interrupt Register" },
562 { 0x24, "Reserved 0x24" },
563 { 0x25, "Reserved 0x25" },
564 { 0x26, "Reserved 0x26" },
565 { 0x27, "Reserved 0x27" },
566 { 0x28, "Reserved 0x28" },
567 { 0x29, "Reserved 0x29" },
568 { 0x2A, "Reserved 0x2A" },
569 { 0x2B, "Reserved 0x2B" },
570 { 0x2C, "Sync Word, Lower 16 Bit" },
571 { 0x2D, "Sync Word, Upper 16 Bit" },
572 { 0x60, "Command Strobe Register: Turn on XOSC" },
573 { 0x61, "Command Strobe register: Start and calibrate Frequency Synthesizer and go from RX/TX to a wait mode where the Frequency Synthesizer is running" },
574 { 0x62, "Command Strobe register: Start RX" },
575 { 0x63, "Command Strobe register: Start TX (turn on Power Amplifier)" },
576 { 0x64, "Command Strobe register: Turn off RX/TX and Frequency Synthesizer" },
577 { 0x65, "Command Strobe register: Turn off XOSC" },
578 { 0x70, "Used to write data to and read data from the 8-bit wide 32 bytes FIFO used to buffer outgoing TX data and incoming RX data in buffered RF mode" },
579 { 0x00, NULL }
580 };
581 static value_string_ext(register_description_vals_ext) = VALUE_STRING_EXT_INIT(register_description_vals);
582
583 static const value_string cc2400_grdec_dec_shift_vals[] = {
584 { 0x00, "0" },
585 { 0x01, "1" },
586 { 0x02, "-2" },
587 { 0x03, "-1" },
588 { 0x00, NULL }
589 };
590 static value_string_ext(cc2400_grdec_dec_shift_vals_ext) = VALUE_STRING_EXT_INIT(cc2400_grdec_dec_shift_vals);
591
592 static const value_string cc2400_grdec_channel_dec_vals[] = {
593 { 0x00, "1 MHz (used for 1Mbps and 250 kbps datarates)" },
594 { 0x01, "500 kHz (used for 10 kbps data rate)" },
595 { 0x02, "250 kHz" },
596 { 0x03, "125 kHz" },
597 { 0x00, NULL }
598 };
599 static value_string_ext(cc2400_grdec_channel_dec_vals_ext) = VALUE_STRING_EXT_INIT(cc2400_grdec_channel_dec_vals);
600
601 static const value_string cc2400_grmdm_pin_mode_vals[] = {
602 { 0x00, "Unbuffered Mode" },
603 { 0x01, "Buffered Mode" },
604 { 0x02, "HSSD Test Mode" },
605 { 0x03, "Unused" },
606 { 0x00, NULL }
607 };
608 static value_string_ext(cc2400_grmdm_pin_mode_vals_ext) = VALUE_STRING_EXT_INIT(cc2400_grmdm_pin_mode_vals);
609
610 static const value_string cc2400_grmdm_pre_bytes_vals[] = {
611 { 0x00, "0" },
612 { 0x01, "1" },
613 { 0x02, "2" },
614 { 0x03, "4" },
615 { 0x04, "8" },
616 { 0x05, "16" },
617 { 0x06, "32" },
618 { 0x07, "Infinitely On" },
619 { 0x00, NULL }
620 };
621 static value_string_ext(cc2400_grmdm_pre_bytes_vals_ext) = VALUE_STRING_EXT_INIT(cc2400_grmdm_pre_bytes_vals);
622
623 static const value_string cc2400_grmdm_sync_word_size_vals[] = {
624 { 0x00, "The 8 MSB bits of SYNC_WORD" },
625 { 0x01, "The 16 MSB bits of SYNC_WORD" },
626 { 0x02, "The 24 MSB bits of SYNC_WORD" },
627 { 0x03, "The 32 MSB bits of SYNC_WORD" },
628 { 0x00, NULL }
629 };
630 static value_string_ext(cc2400_grmdm_sync_word_size_vals_ext) = VALUE_STRING_EXT_INIT(cc2400_grmdm_sync_word_size_vals);
631
632 static const value_string cc2400_grmdm_data_format_vals[] = {
633 { 0x00, "NRZ" },
634 { 0x01, "Manchester" },
635 { 0x02, "8/10 line-coding (Not applied to preambles or sync words)" },
636 { 0x03, "Reserved" },
637 { 0x00, NULL }
638 };
639 static value_string_ext(cc2400_grmdm_data_format_vals_ext) = VALUE_STRING_EXT_INIT(cc2400_grmdm_data_format_vals);
640
641 static const value_string cc2400_grmdm_modulation_format_vals[] = {
642 { 0x00, "FSK/GFSK" },
643 { 0x01, "Reserved" },
644 { 0x00, NULL }
645 };
646 static value_string_ext(cc2400_grmdm_modulation_format_vals_ext) = VALUE_STRING_EXT_INIT(cc2400_grmdm_modulation_format_vals);
647
648 static const value_string cc2400_fstst3_pd_delay_vals[] = {
649 { 0x00, "Short Reset Delay" },
650 { 0x01, "Long Reset Delay" },
651 { 0x00, NULL }
652 };
653 static value_string_ext(cc2400_fstst3_pd_delay_vals_ext) = VALUE_STRING_EXT_INIT(cc2400_fstst3_pd_delay_vals);
654
655 static const value_string cc2400_fstst3_chp_step_period_vals[] = {
656 { 0x00, "0.25 us" },
657 { 0x01, "0.5 us" },
658 { 0x02, "1 us" },
659 { 0x03, "4 us" },
660 { 0x00, NULL }
661 };
662 static value_string_ext(cc2400_fstst3_chp_step_period_vals_ext) = VALUE_STRING_EXT_INIT(cc2400_fstst3_chp_step_period_vals);
663
664 static const value_string cc2400_fstst2_vco_curcal_speed_vals[] = {
665 { 0x00, "Normal" },
666 { 0x01, "Undefined" },
667 { 0x02, "Half Speed" },
668 { 0x03, "Undefined" },
669 { 0x00, NULL }
670 };
671 static value_string_ext(cc2400_fstst2_vco_curcal_speed_vals_ext) = VALUE_STRING_EXT_INIT(cc2400_fstst2_vco_curcal_speed_vals);
672
673 static const value_string cc2400_fstst1_rxbpf_locur_vals[] = {
674 { 0x00, "4 uA (nominal)" },
675 { 0x01, "3 uA" },
676 { 0x00, NULL }
677 };
678 static value_string_ext(cc2400_fstst1_rxbpf_locur_vals_ext) = VALUE_STRING_EXT_INIT(cc2400_fstst1_rxbpf_locur_vals);
679
680 static const value_string cc2400_fstst1_rxbpf_midcur_vals[] = {
681 { 0x00, "4 uA (nominal)" },
682 { 0x01, "3.5 uA" },
683 { 0x00, NULL }
684 };
685 static value_string_ext(cc2400_fstst1_rxbpf_midcur_vals_ext) = VALUE_STRING_EXT_INIT(cc2400_fstst1_rxbpf_midcur_vals);
686
687 static const value_string cc2400_fstst1_vc_dac_en_vals[] = {
688 { 0x00, "Loop filter (closed loop PLL)" },
689 { 0x01, "VC DAC(open loop PLL)" },
690 { 0x00, NULL }
691 };
692 static value_string_ext(cc2400_fstst1_vc_dac_en_vals_ext) = VALUE_STRING_EXT_INIT(cc2400_fstst1_vc_dac_en_vals);
693
694 static const value_string cc2400_fstst0_rxtxmixbuf_cur_vals[] = {
695 { 0x00, "690 uA" },
696 { 0x01, "980 uA" },
697 { 0x02, "1.16 mA (nominal)" },
698 { 0x03, "1.44 mA" },
699 { 0x00, NULL }
700 };
701 static value_string_ext(cc2400_fstst0_rxtxmixbuf_cur_vals_ext) = VALUE_STRING_EXT_INIT(cc2400_fstst0_rxtxmixbuf_cur_vals);
702
703
704 static const value_string cc2400_agctst1_agc_var_gain_sat_vals[] = {
705 { 0x00, "-1/-3 gain steps" },
706 { 0x01, "-3/-5 gain steps" },
707 { 0x00, NULL }
708 };
709 static value_string_ext(cc2400_agctst1_agc_var_gain_sat_vals_ext) = VALUE_STRING_EXT_INIT(cc2400_agctst1_agc_var_gain_sat_vals);
710
711 static const value_string cc2400_dactst_dac_src_vals[] = {
712 { 0x00, "Normal Operation (from Modulator)" },
713 { 0x01, "The DAC_I_O and DAC_Q_O override values below" },
714 { 0x02, "From ADC" },
715 { 0x03, "I/Q after digital down-mixing and channel filtering" },
716 { 0x04, "Full-spectrum White Noise (from PRNG)" },
717 { 0x05, "RX signal magnitude / frequency filtered (from demodulator)" },
718 { 0x06, "RSSI/RX frequency offset estimation" },
719 { 0x07, "HSSD module" },
720 { 0x00, NULL }
721 };
722 static value_string_ext(cc2400_dactst_dac_src_vals_ext) = VALUE_STRING_EXT_INIT(cc2400_dactst_dac_src_vals);
723
724 static const value_string cc2400_mdmtst0_afc_settling_vals[] = {
725 { 0x00, "1 pair" },
726 { 0x01, "2 pairs" },
727 { 0x02, "4 pairs" },
728 { 0x03, "8 pairs" },
729 { 0x00, NULL }
730 };
731 static value_string_ext(cc2400_mdmtst0_afc_settling_vals_ext) = VALUE_STRING_EXT_INIT(cc2400_mdmtst0_afc_settling_vals);
732
733 static const value_string cc2400_lmtst_rxmix_tail_vals[] = {
734 { 0x00, "12 uA" },
735 { 0x01, "16 uA (Nominal)" },
736 { 0x02, "20 uA" },
737 { 0x03, "24 uA" },
738 { 0x00, NULL }
739 };
740 static value_string_ext(cc2400_lmtst_rxmix_tail_vals_ext) = VALUE_STRING_EXT_INIT(cc2400_lmtst_rxmix_tail_vals);
741
742 static const value_string cc2400_lmtst_rxmix_vcm_vals[] = {
743 { 0x00, "8 uA mixer current" },
744 { 0x01, "12 uA mixer current (Nominal)" },
745 { 0x02, "16 uA mixer current" },
746 { 0x03, "20 uA mixer current" },
747 { 0x00, NULL }
748 };
749 static value_string_ext(cc2400_lmtst_rxmix_vcm_vals_ext) = VALUE_STRING_EXT_INIT(cc2400_lmtst_rxmix_vcm_vals);
750
751 static const value_string cc2400_lmtst_rxmix_current_vals[] = {
752 { 0x00, "360 uA mixer current (x2)" },
753 { 0x01, "720 uA mixer current (x2)" },
754 { 0x02, "900 uA mixer current (x2) (Nominal)" },
755 { 0x03, "1260 uA mixer current (x2)" },
756 { 0x00, NULL }
757 };
758 static value_string_ext(cc2400_lmtst_rxmix_current_vals_ext) = VALUE_STRING_EXT_INIT(cc2400_lmtst_rxmix_current_vals);
759
760 static const value_string cc2400_lmtst_lna_cap_array_vals[] = {
761 { 0x00, "Off" },
762 { 0x01, "0.1pF (x2) (Nominal)" },
763 { 0x02, "0.2pF (x2)" },
764 { 0x03, "0.3pF (x2)" },
765 { 0x00, NULL }
766 };
767 static value_string_ext(cc2400_lmtst_lna_cap_array_vals_ext) = VALUE_STRING_EXT_INIT(cc2400_lmtst_lna_cap_array_vals);
768
769 static const value_string cc2400_lmtst_lna_lowgain_vals[] = {
770 { 0x00, "19 dB (Nominal)" },
771 { 0x01, "7 dB" },
772 { 0x00, NULL }
773 };
774 static value_string_ext(cc2400_lmtst_lna_lowgain_vals_ext) = VALUE_STRING_EXT_INIT(cc2400_lmtst_lna_lowgain_vals);
775
776 static const value_string cc2400_lmtst_lna_gain_vals[] = {
777 { 0x00, "Off (Nominal)" },
778 { 0x01, "100 uA LNA current" },
779 { 0x02, "300 uA LNA current" },
780 { 0x03, "1000 uA LNA current" },
781 { 0x00, NULL }
782 };
783 static value_string_ext(cc2400_lmtst_lna_gain_vals_ext) = VALUE_STRING_EXT_INIT(cc2400_lmtst_lna_gain_vals);
784
785 static const value_string cc2400_lmtst_lna_current_vals[] = {
786 { 0x00, "240 uA LNA current (x2)" },
787 { 0x01, "480 uA LNA current (x2)" },
788 { 0x02, "640 uA LNA current (x2) (Nominal)" },
789 { 0x03, "1280 uA LNA current (x2)" },
790 { 0x00, NULL }
791 };
792 static value_string_ext(cc2400_lmtst_lna_current_vals_ext) = VALUE_STRING_EXT_INIT(cc2400_lmtst_lna_current_vals);
793
794 static const value_string cc2400_pamtst_atestmod_mode_vals[] = {
795 { 0x00, "Outputs I (ATEST2) and Q (ATEST1) from RxMIX" },
796 { 0x01, "Inputs I (ATEST2) and Q (ATEST1) to BPF" },
797 { 0x02, "Outputs I (ATEST2) and Q (ATEST1) from VGA" },
798 { 0x03, "Inputs I (ATEST2) and Q (ATEST1) to ADC" },
799 { 0x04, "Outputs I (ATEST2) and Q (ATEST1) from LPF" },
800 { 0x05, "Inputs I (ATEST2) and Q (ATEST1) to TxMIX" },
801 { 0x06, "Outputs P (ATEST2) and N (ATEST1) from Prescaler" },
802 { 0x07, "Connects TX IF to RX IF and simultaneously the ATEST1 pin to the internal VC node" },
803 { 0x00, NULL }
804 };
805 static value_string_ext(cc2400_pamtst_atestmod_mode_vals_ext) = VALUE_STRING_EXT_INIT(cc2400_pamtst_atestmod_mode_vals);
806
807 static const value_string cc2400_pamtst_txmix_current_vals[] = {
808 { 0x00, "1.72 mA" },
809 { 0x01, "1.88 mA" },
810 { 0x02, "2.05 mA" },
811 { 0x03, "2.21 mA" },
812 { 0x00, NULL }
813 };
814 static value_string_ext(cc2400_pamtst_txmix_current_vals_ext) = VALUE_STRING_EXT_INIT(cc2400_pamtst_txmix_current_vals);
815
816 static const value_string cc2400_pamtst_pa_current_vals[] = {
817 { 0x00, "-3 current adjustment" },
818 { 0x01, "-2 current adjustment" },
819 { 0x02, "-1 current adjustment" },
820 { 0x03, "Nominal Setting" },
821 { 0x04, "+1 current adjustment" },
822 { 0x05, "+2 current adjustment" },
823 { 0x06, "+3 current adjustment" },
824 { 0x07, "+4 current adjustment" },
825 { 0x00, NULL }
826 };
827 static value_string_ext(cc2400_pamtst_pa_current_vals_ext) = VALUE_STRING_EXT_INIT(cc2400_pamtst_pa_current_vals);
828
829 static const value_string cc2400_iocfg_hssd_src_vals[] = {
830 { 0x00, "Off" },
831 { 0x01, "Output AGC status (gain setting / peak detector status / accumulator value)" },
832 { 0x02, "Output ADC I and Q values" },
833 { 0x03, "Output I/Q after digital down-mixing and channel filtering" },
834 { 0x04, "Output RX signal magnitude / frequency unfiltered (from demodulator)" },
835 { 0x05, "Output RX signal magnitude / frequency filtered (from demodulator)" },
836 { 0x06, "Output RSSI / RX frequency offset estimation" },
837 { 0x07, "Input DAC values" },
838 { 0x00, NULL }
839 };
840 static value_string_ext(cc2400_iocfg_hssd_src_vals_ext) = VALUE_STRING_EXT_INIT(cc2400_iocfg_hssd_src_vals);
841
842 static const value_string cc2400_rssi_rssi_filt_vals[] = {
843 { 0x00, "0 bits (no filtering)" },
844 { 0x01, "1 bit" },
845 { 0x02, "4 bits" },
846 { 0x03, "8 bits" },
847 { 0x00, NULL }
848 };
849 static value_string_ext(cc2400_rssi_rssi_filt_vals_ext) = VALUE_STRING_EXT_INIT(cc2400_rssi_rssi_filt_vals);
850
851 static const value_string cc2400_fsctlr_lock_threshold_vals[] = {
852 { 0x00, "64" },
853 { 0x01, "128" },
854 { 0x02, "256" },
855 { 0x03, "512" },
856 { 0x00, NULL }
857 };
858 static value_string_ext(cc2400_fsctlr_lock_threshold_vals_ext) = VALUE_STRING_EXT_INIT(cc2400_fsctlr_lock_threshold_vals);
859
860 static const value_string cc2400_fsctlr_lock_length_vals[] = {
861 { 0x00, "2 CLK_PRE Periods" },
862 { 0x01, "4 CLK_PRE Periods" },
863 { 0x00, NULL }
864 };
865 static value_string_ext(cc2400_fsctlr_lock_length_vals_ext) = VALUE_STRING_EXT_INIT(cc2400_fsctlr_lock_length_vals);
866
867 void proto_register_ubertooth(void);
868 void proto_reg_handoff_ubertooth(void);
869
870
871 /* TODO: rewrite to use e.g. proto_tree_add_bitmask() ? */
872 static void
873 dissect_cc2400_register(proto_tree *tree, tvbuff_t *tvb, int offset, uint8_t register_id)
874 {
875 proto_item *sub_item;
876 proto_item *sub_tree;
877
878 switch (register_id) {
879 case 0x00: /* MAIN */
880 proto_tree_add_item(tree, hf_cc2400_main_resetn, tvb, offset, 2, ENC_BIG_ENDIAN);
881 proto_tree_add_item(tree, hf_cc2400_main_reserved_14_10, tvb, offset, 2, ENC_BIG_ENDIAN);
882 proto_tree_add_item(tree, hf_cc2400_main_fs_force_en, tvb, offset, 2, ENC_BIG_ENDIAN);
883 proto_tree_add_item(tree, hf_cc2400_main_rxn_tx, tvb, offset, 2, ENC_BIG_ENDIAN);
884 proto_tree_add_item(tree, hf_cc2400_main_reserved_7_4, tvb, offset, 2, ENC_BIG_ENDIAN);
885 proto_tree_add_item(tree, hf_cc2400_main_reserved_3, tvb, offset, 2, ENC_BIG_ENDIAN);
886 proto_tree_add_item(tree, hf_cc2400_main_reserved_2, tvb, offset, 2, ENC_BIG_ENDIAN);
887 proto_tree_add_item(tree, hf_cc2400_main_xosc16m_bypass, tvb, offset, 2, ENC_BIG_ENDIAN);
888 proto_tree_add_item(tree, hf_cc2400_main_xosc16m_en, tvb, offset, 2, ENC_BIG_ENDIAN);
889 break;
890 case 0x01: /* FSCTRL */
891 proto_tree_add_item(tree, hf_cc2400_fsctrl_reserved, tvb, offset, 2, ENC_BIG_ENDIAN);
892 proto_tree_add_item(tree, hf_cc2400_fsctrl_lock_threshold, tvb, offset, 2, ENC_BIG_ENDIAN);
893 proto_tree_add_item(tree, hf_cc2400_fsctrl_cal_done, tvb, offset, 2, ENC_BIG_ENDIAN);
894 proto_tree_add_item(tree, hf_cc2400_fsctrl_cal_running, tvb, offset, 2, ENC_BIG_ENDIAN);
895 proto_tree_add_item(tree, hf_cc2400_fsctrl_lock_length, tvb, offset, 2, ENC_BIG_ENDIAN);
896 proto_tree_add_item(tree, hf_cc2400_fsctrl_lock_status, tvb, offset, 2, ENC_BIG_ENDIAN);
897 break;
898 case 0x02: /* FSDIV */
899 proto_tree_add_item(tree, hf_cc2400_fsdiv_reserved, tvb, offset, 2, ENC_BIG_ENDIAN);
900 sub_item = proto_tree_add_item(tree, hf_cc2400_fsdiv_frequency, tvb, offset, 2, ENC_BIG_ENDIAN);
901 sub_tree = proto_item_add_subtree(sub_item, ett_fsdiv_frequency);
902
903 proto_tree_add_item(sub_tree, hf_cc2400_fsdiv_freq_high, tvb, offset, 2, ENC_BIG_ENDIAN);
904 proto_tree_add_item(sub_tree, hf_cc2400_fsdiv_freq, tvb, offset, 2, ENC_BIG_ENDIAN);
905 break;
906 case 0x03: /* MDMCTRL */
907 proto_tree_add_item(tree, hf_cc2400_mdmctrl_reserved, tvb, offset, 2, ENC_BIG_ENDIAN);
908 proto_tree_add_item(tree, hf_cc2400_mdmctrl_mod_offset, tvb, offset, 2, ENC_BIG_ENDIAN);
909 proto_tree_add_item(tree, hf_cc2400_mdmctrl_mod_dev, tvb, offset, 2, ENC_BIG_ENDIAN);
910 break;
911 case 0x04: /* AGCCTRL */
912 proto_tree_add_item(tree, hf_cc2400_agcctrl_vga_gain, tvb, offset, 2, ENC_BIG_ENDIAN);
913 proto_tree_add_item(tree, hf_cc2400_agcctrl_reserved, tvb, offset, 2, ENC_BIG_ENDIAN);
914 proto_tree_add_item(tree, hf_cc2400_agcctrl_agc_locked, tvb, offset, 2, ENC_BIG_ENDIAN);
915 proto_tree_add_item(tree, hf_cc2400_agcctrl_agc_lock, tvb, offset, 2, ENC_BIG_ENDIAN);
916 proto_tree_add_item(tree, hf_cc2400_agcctrl_agc_sync_lock, tvb, offset, 2, ENC_BIG_ENDIAN);
917 proto_tree_add_item(tree, hf_cc2400_agcctrl_vga_gain_oe, tvb, offset, 2, ENC_BIG_ENDIAN);
918 break;
919 case 0x05: /* FREND */
920 proto_tree_add_item(tree, hf_cc2400_frend_reserved_15_4, tvb, offset, 2, ENC_BIG_ENDIAN);
921 proto_tree_add_item(tree, hf_cc2400_frend_reserved_3, tvb, offset, 2, ENC_BIG_ENDIAN);
922 proto_tree_add_item(tree, hf_cc2400_frend_pa_level, tvb, offset, 2, ENC_BIG_ENDIAN);
923 break;
924 case 0x06: /* RSSI */
925 proto_tree_add_item(tree, hf_cc2400_rssi_rssi_val, tvb, offset, 2, ENC_BIG_ENDIAN);
926 proto_tree_add_item(tree, hf_cc2400_rssi_rssi_cs_thres, tvb, offset, 2, ENC_BIG_ENDIAN);
927 proto_tree_add_item(tree, hf_cc2400_rssi_rssi_filt, tvb, offset, 2, ENC_BIG_ENDIAN);
928 break;
929 case 0x07: /* FREQEST */
930 proto_tree_add_item(tree, hf_cc2400_freqest_rx_freq_offset, tvb, offset, 2, ENC_BIG_ENDIAN);
931 proto_tree_add_item(tree, hf_cc2400_freqest_reserved, tvb, offset, 2, ENC_BIG_ENDIAN);
932 break;
933 case 0x08: /* IOCFG */
934 proto_tree_add_item(tree, hf_cc2400_iocfg_reserved, tvb, offset, 2, ENC_BIG_ENDIAN);
935 proto_tree_add_item(tree, hf_cc2400_iocfg_gio6_cfg, tvb, offset, 2, ENC_BIG_ENDIAN);
936 proto_tree_add_item(tree, hf_cc2400_iocfg_gio1_cfg, tvb, offset, 2, ENC_BIG_ENDIAN);
937 proto_tree_add_item(tree, hf_cc2400_iocfg_hssd_src, tvb, offset, 2, ENC_BIG_ENDIAN);
938 break;
939 case 0x0B: /* FSMTC */
940 proto_tree_add_item(tree, hf_cc2400_fsmtc_tc_rxon2agcen, tvb, offset, 2, ENC_BIG_ENDIAN);
941 proto_tree_add_item(tree, hf_cc2400_fsmtc_tc_paon2switch, tvb, offset, 2, ENC_BIG_ENDIAN);
942 proto_tree_add_item(tree, hf_cc2400_fsmtc_res, tvb, offset, 2, ENC_BIG_ENDIAN);
943 proto_tree_add_item(tree, hf_cc2400_fsmtc_tc_txend2switch, tvb, offset, 2, ENC_BIG_ENDIAN);
944 proto_tree_add_item(tree, hf_cc2400_fsmtc_tc_txend2paoff, tvb, offset, 2, ENC_BIG_ENDIAN);
945 break;
946 case 0x0C: /* Reserved */
947 proto_tree_add_item(tree, hf_cc2400_reserved_0x0C_res_15_5, tvb, offset, 2, ENC_BIG_ENDIAN);
948 proto_tree_add_item(tree, hf_cc2400_reserved_0x0C_res_4_0, tvb, offset, 2, ENC_BIG_ENDIAN);
949 break;
950 case 0x0D: /* MANAND */
951 proto_tree_add_item(tree, hf_cc2400_manand_vga_reset_n, tvb, offset, 2, ENC_BIG_ENDIAN);
952 proto_tree_add_item(tree, hf_cc2400_manand_lock_status, tvb, offset, 2, ENC_BIG_ENDIAN);
953 proto_tree_add_item(tree, hf_cc2400_manand_balun_ctrl, tvb, offset, 2, ENC_BIG_ENDIAN);
954 proto_tree_add_item(tree, hf_cc2400_manand_rxtx, tvb, offset, 2, ENC_BIG_ENDIAN);
955 proto_tree_add_item(tree, hf_cc2400_manand_pre_pd, tvb, offset, 2, ENC_BIG_ENDIAN);
956 proto_tree_add_item(tree, hf_cc2400_manand_pa_n_pd, tvb, offset, 2, ENC_BIG_ENDIAN);
957 proto_tree_add_item(tree, hf_cc2400_manand_pa_p_pd, tvb, offset, 2, ENC_BIG_ENDIAN);
958 proto_tree_add_item(tree, hf_cc2400_manand_dac_lpf_pd, tvb, offset, 2, ENC_BIG_ENDIAN);
959 proto_tree_add_item(tree, hf_cc2400_manand_bias_pd, tvb, offset, 2, ENC_BIG_ENDIAN);
960 proto_tree_add_item(tree, hf_cc2400_manand_xosc16m_pd, tvb, offset, 2, ENC_BIG_ENDIAN);
961 proto_tree_add_item(tree, hf_cc2400_manand_chp_pd, tvb, offset, 2, ENC_BIG_ENDIAN);
962 proto_tree_add_item(tree, hf_cc2400_manand_fs_pd, tvb, offset, 2, ENC_BIG_ENDIAN);
963 proto_tree_add_item(tree, hf_cc2400_manand_adc_pd, tvb, offset, 2, ENC_BIG_ENDIAN);
964 proto_tree_add_item(tree, hf_cc2400_manand_vga_pd, tvb, offset, 2, ENC_BIG_ENDIAN);
965 proto_tree_add_item(tree, hf_cc2400_manand_rxbpf_pd, tvb, offset, 2, ENC_BIG_ENDIAN);
966 proto_tree_add_item(tree, hf_cc2400_manand_lnamix_pd, tvb, offset, 2, ENC_BIG_ENDIAN);
967 break;
968 case 0x0E: /* FSMSTATE */
969 proto_tree_add_item(tree, hf_cc2400_fsmstate_reserved_15_13, tvb, offset, 2, ENC_BIG_ENDIAN);
970 proto_tree_add_item(tree, hf_cc2400_fsmstate_fsm_state_bkpt, tvb, offset, 2, ENC_BIG_ENDIAN);
971 proto_tree_add_item(tree, hf_cc2400_fsmstate_reserved_7_5, tvb, offset, 2, ENC_BIG_ENDIAN);
972 proto_tree_add_item(tree, hf_cc2400_fsmstate_fsm_cur_state, tvb, offset, 2, ENC_BIG_ENDIAN);
973 break;
974 case 0x0F: /* ADCTST */
975 proto_tree_add_item(tree, hf_cc2400_adctst_reserved_15, tvb, offset, 2, ENC_BIG_ENDIAN);
976 proto_tree_add_item(tree, hf_cc2400_adctst_adc_i, tvb, offset, 2, ENC_BIG_ENDIAN);
977 proto_tree_add_item(tree, hf_cc2400_adctst_reserved_7, tvb, offset, 2, ENC_BIG_ENDIAN);
978 proto_tree_add_item(tree, hf_cc2400_adctst_adc_q, tvb, offset, 2, ENC_BIG_ENDIAN);
979 break;
980 case 0x10: /* RXBPFTST */
981 proto_tree_add_item(tree, hf_cc2400_rxbpftst_reserved, tvb, offset, 2, ENC_BIG_ENDIAN);
982 proto_tree_add_item(tree, hf_cc2400_rxbpftst_rxbpf_cap_oe, tvb, offset, 2, ENC_BIG_ENDIAN);
983 proto_tree_add_item(tree, hf_cc2400_rxbpftst_rxbpf_cap_o, tvb, offset, 2, ENC_BIG_ENDIAN);
984 proto_tree_add_item(tree, hf_cc2400_rxbpftst_rxbpf_cap_res, tvb, offset, 2, ENC_BIG_ENDIAN);
985 break;
986 case 0x11: /* PAMTST */
987 proto_tree_add_item(tree, hf_cc2400_pamtst_reserved_15_13, tvb, offset, 2, ENC_BIG_ENDIAN);
988 proto_tree_add_item(tree, hf_cc2400_pamtst_vc_in_test_en, tvb, offset, 2, ENC_BIG_ENDIAN);
989 proto_tree_add_item(tree, hf_cc2400_pamtst_atestmod_pd, tvb, offset, 2, ENC_BIG_ENDIAN);
990 proto_tree_add_item(tree, hf_cc2400_pamtst_atestmod_mode, tvb, offset, 2, ENC_BIG_ENDIAN);
991 proto_tree_add_item(tree, hf_cc2400_pamtst_reserved_7, tvb, offset, 2, ENC_BIG_ENDIAN);
992 proto_tree_add_item(tree, hf_cc2400_pamtst_txmix_cap_array, tvb, offset, 2, ENC_BIG_ENDIAN);
993 proto_tree_add_item(tree, hf_cc2400_pamtst_txmix_current, tvb, offset, 2, ENC_BIG_ENDIAN);
994 proto_tree_add_item(tree, hf_cc2400_pamtst_pa_current, tvb, offset, 2, ENC_BIG_ENDIAN);
995 break;
996 case 0x12: /* LMTST */
997 proto_tree_add_item(tree, hf_cc2400_lmtst_reserved, tvb, offset, 2, ENC_BIG_ENDIAN);
998 proto_tree_add_item(tree, hf_cc2400_lmtst_rxmix_hgm, tvb, offset, 2, ENC_BIG_ENDIAN);
999 proto_tree_add_item(tree, hf_cc2400_lmtst_rxmix_tail, tvb, offset, 2, ENC_BIG_ENDIAN);
1000 proto_tree_add_item(tree, hf_cc2400_lmtst_rxmix_vcm, tvb, offset, 2, ENC_BIG_ENDIAN);
1001 proto_tree_add_item(tree, hf_cc2400_lmtst_rxmix_current, tvb, offset, 2, ENC_BIG_ENDIAN);
1002 proto_tree_add_item(tree, hf_cc2400_lmtst_lna_cap_array, tvb, offset, 2, ENC_BIG_ENDIAN);
1003 proto_tree_add_item(tree, hf_cc2400_lmtst_lna_lowgain, tvb, offset, 2, ENC_BIG_ENDIAN);
1004 proto_tree_add_item(tree, hf_cc2400_lmtst_lna_gain, tvb, offset, 2, ENC_BIG_ENDIAN);
1005 proto_tree_add_item(tree, hf_cc2400_lmtst_lna_current, tvb, offset, 2, ENC_BIG_ENDIAN);
1006 break;
1007 case 0x13: /* MANOR */
1008 proto_tree_add_item(tree, hf_cc2400_manor_vga_reset_n, tvb, offset, 2, ENC_BIG_ENDIAN);
1009 proto_tree_add_item(tree, hf_cc2400_manor_lock_status, tvb, offset, 2, ENC_BIG_ENDIAN);
1010 proto_tree_add_item(tree, hf_cc2400_manor_balun_ctrl, tvb, offset, 2, ENC_BIG_ENDIAN);
1011 proto_tree_add_item(tree, hf_cc2400_manor_rxtx, tvb, offset, 2, ENC_BIG_ENDIAN);
1012 proto_tree_add_item(tree, hf_cc2400_manor_pre_pd, tvb, offset, 2, ENC_BIG_ENDIAN);
1013 proto_tree_add_item(tree, hf_cc2400_manor_pa_n_pd, tvb, offset, 2, ENC_BIG_ENDIAN);
1014 proto_tree_add_item(tree, hf_cc2400_manor_pa_p_pd, tvb, offset, 2, ENC_BIG_ENDIAN);
1015 proto_tree_add_item(tree, hf_cc2400_manor_dac_lpf_pd, tvb, offset, 2, ENC_BIG_ENDIAN);
1016 proto_tree_add_item(tree, hf_cc2400_manor_bias_pd, tvb, offset, 2, ENC_BIG_ENDIAN);
1017 proto_tree_add_item(tree, hf_cc2400_manor_xosc16m_pd, tvb, offset, 2, ENC_BIG_ENDIAN);
1018 proto_tree_add_item(tree, hf_cc2400_manor_chp_pd, tvb, offset, 2, ENC_BIG_ENDIAN);
1019 proto_tree_add_item(tree, hf_cc2400_manor_fs_pd, tvb, offset, 2, ENC_BIG_ENDIAN);
1020 proto_tree_add_item(tree, hf_cc2400_manor_adc_pd, tvb, offset, 2, ENC_BIG_ENDIAN);
1021 proto_tree_add_item(tree, hf_cc2400_manor_vga_pd, tvb, offset, 2, ENC_BIG_ENDIAN);
1022 proto_tree_add_item(tree, hf_cc2400_manor_rxbpf_pd, tvb, offset, 2, ENC_BIG_ENDIAN);
1023 proto_tree_add_item(tree, hf_cc2400_manor_lnamix_pd, tvb, offset, 2, ENC_BIG_ENDIAN);
1024 break;
1025 case 0x14: /* MDMTST0 */
1026 proto_tree_add_item(tree, hf_cc2400_mdmtst0_reserved, tvb, offset, 2, ENC_BIG_ENDIAN);
1027 proto_tree_add_item(tree, hf_cc2400_mdmtst0_tx_prng, tvb, offset, 2, ENC_BIG_ENDIAN);
1028 proto_tree_add_item(tree, hf_cc2400_mdmtst0_tx_1mhz_offset_n, tvb, offset, 2, ENC_BIG_ENDIAN);
1029 proto_tree_add_item(tree, hf_cc2400_mdmtst0_invert_data, tvb, offset, 2, ENC_BIG_ENDIAN);
1030 proto_tree_add_item(tree, hf_cc2400_mdmtst0_afc_adjust_on_packet, tvb, offset, 2, ENC_BIG_ENDIAN);
1031 proto_tree_add_item(tree, hf_cc2400_mdmtst0_afc_settling, tvb, offset, 2, ENC_BIG_ENDIAN);
1032 proto_tree_add_item(tree, hf_cc2400_mdmtst0_afc_delta, tvb, offset, 2, ENC_BIG_ENDIAN);
1033 break;
1034 case 0x15: /* MDMTST1 */
1035 proto_tree_add_item(tree, hf_cc2400_mdmtst1_reserved, tvb, offset, 2, ENC_BIG_ENDIAN);
1036 proto_tree_add_item(tree, hf_cc2400_mdmtst1_bsync_threshold, tvb, offset, 2, ENC_BIG_ENDIAN);
1037 break;
1038 case 0x16: /* DACTST */
1039 proto_tree_add_item(tree, hf_cc2400_dactst_reserved, tvb, offset, 2, ENC_BIG_ENDIAN);
1040 proto_tree_add_item(tree, hf_cc2400_dactst_dac_src, tvb, offset, 2, ENC_BIG_ENDIAN);
1041 proto_tree_add_item(tree, hf_cc2400_dactst_dac_i_o, tvb, offset, 2, ENC_BIG_ENDIAN);
1042 proto_tree_add_item(tree, hf_cc2400_dactst_dac_q_o, tvb, offset, 2, ENC_BIG_ENDIAN);
1043 break;
1044 case 0x17: /* AGCTST0 */
1045 proto_tree_add_item(tree, hf_cc2400_agctst0_agc_settle_blank_dn, tvb, offset, 2, ENC_BIG_ENDIAN);
1046 proto_tree_add_item(tree, hf_cc2400_agctst0_agc_win_size, tvb, offset, 2, ENC_BIG_ENDIAN);
1047 proto_tree_add_item(tree, hf_cc2400_agctst0_agc_settle_peak, tvb, offset, 2, ENC_BIG_ENDIAN);
1048 proto_tree_add_item(tree, hf_cc2400_agctst0_agc_settle_adc, tvb, offset, 2, ENC_BIG_ENDIAN);
1049 proto_tree_add_item(tree, hf_cc2400_agctst0_agc_attempts, tvb, offset, 2, ENC_BIG_ENDIAN);
1050 break;
1051 case 0x18: /* AGCTST1 */
1052 proto_tree_add_item(tree, hf_cc2400_agctst1_reserved, tvb, offset, 2, ENC_BIG_ENDIAN);
1053 proto_tree_add_item(tree, hf_cc2400_agctst1_agc_var_gain_sat, tvb, offset, 2, ENC_BIG_ENDIAN);
1054 proto_tree_add_item(tree, hf_cc2400_agctst1_agc_settle_blank_up, tvb, offset, 2, ENC_BIG_ENDIAN);
1055 proto_tree_add_item(tree, hf_cc2400_agctst1_peakdet_cur_boost, tvb, offset, 2, ENC_BIG_ENDIAN);
1056 proto_tree_add_item(tree, hf_cc2400_agctst1_agc_mult_slow, tvb, offset, 2, ENC_BIG_ENDIAN);
1057 proto_tree_add_item(tree, hf_cc2400_agctst1_agc_settle_fixed, tvb, offset, 2, ENC_BIG_ENDIAN);
1058 proto_tree_add_item(tree, hf_cc2400_agctst1_agc_settle_var, tvb, offset, 2, ENC_BIG_ENDIAN);
1059 break;
1060 case 0x19: /* AGCTST2 */
1061 proto_tree_add_item(tree, hf_cc2400_agctst2_reserved, tvb, offset, 2, ENC_BIG_ENDIAN);
1062 proto_tree_add_item(tree, hf_cc2400_agctst2_agc_backend_blanking, tvb, offset, 2, ENC_BIG_ENDIAN);
1063 proto_tree_add_item(tree, hf_cc2400_agctst2_agc_adjust_m3db, tvb, offset, 2, ENC_BIG_ENDIAN);
1064 proto_tree_add_item(tree, hf_cc2400_agctst2_agc_adjust_m1db, tvb, offset, 2, ENC_BIG_ENDIAN);
1065 proto_tree_add_item(tree, hf_cc2400_agctst2_agc_adjust_p3db, tvb, offset, 2, ENC_BIG_ENDIAN);
1066 proto_tree_add_item(tree, hf_cc2400_agctst2_agc_adjust_p1db, tvb, offset, 2, ENC_BIG_ENDIAN);
1067 break;
1068 case 0x1A: /* FSTST0 */
1069 proto_tree_add_item(tree, hf_cc2400_fstst0_rxmixbuf_cur, tvb, offset, 2, ENC_BIG_ENDIAN);
1070 proto_tree_add_item(tree, hf_cc2400_fstst0_txmixbuf_cur, tvb, offset, 2, ENC_BIG_ENDIAN);
1071 proto_tree_add_item(tree, hf_cc2400_fstst0_vco_array_settle_long, tvb, offset, 2, ENC_BIG_ENDIAN);
1072 proto_tree_add_item(tree, hf_cc2400_fstst0_vco_array_oe, tvb, offset, 2, ENC_BIG_ENDIAN);
1073 proto_tree_add_item(tree, hf_cc2400_fstst0_vco_array_o, tvb, offset, 2, ENC_BIG_ENDIAN);
1074 proto_tree_add_item(tree, hf_cc2400_fstst0_vco_array_res, tvb, offset, 2, ENC_BIG_ENDIAN);
1075 break;
1076 case 0x1B: /* FSTST1 */
1077 proto_tree_add_item(tree, hf_cc2400_fstst1_rxbpf_locur, tvb, offset, 2, ENC_BIG_ENDIAN);
1078 proto_tree_add_item(tree, hf_cc2400_fstst1_rxbpf_midcur, tvb, offset, 2, ENC_BIG_ENDIAN);
1079 proto_tree_add_item(tree, hf_cc2400_fstst1_vco_current_ref, tvb, offset, 2, ENC_BIG_ENDIAN);
1080 proto_tree_add_item(tree, hf_cc2400_fstst1_vco_current_k, tvb, offset, 2, ENC_BIG_ENDIAN);
1081 proto_tree_add_item(tree, hf_cc2400_fstst1_vc_dac_en, tvb, offset, 2, ENC_BIG_ENDIAN);
1082 proto_tree_add_item(tree, hf_cc2400_fstst1_vc_dac_val, tvb, offset, 2, ENC_BIG_ENDIAN);
1083 break;
1084 case 0x1C: /* FSTST2 */
1085 proto_tree_add_item(tree, hf_cc2400_fstst2_reserved, tvb, offset, 2, ENC_BIG_ENDIAN);
1086 proto_tree_add_item(tree, hf_cc2400_fstst2_vco_curcal_speed, tvb, offset, 2, ENC_BIG_ENDIAN);
1087 proto_tree_add_item(tree, hf_cc2400_fstst2_vco_current_oe, tvb, offset, 2, ENC_BIG_ENDIAN);
1088 proto_tree_add_item(tree, hf_cc2400_fstst2_vco_current_o, tvb, offset, 2, ENC_BIG_ENDIAN);
1089 proto_tree_add_item(tree, hf_cc2400_fstst2_vco_current_res, tvb, offset, 2, ENC_BIG_ENDIAN);
1090 break;
1091 case 0x1D: /* FSTST3 */
1092 proto_tree_add_item(tree, hf_cc2400_fstst3_reserved, tvb, offset, 2, ENC_BIG_ENDIAN);
1093 proto_tree_add_item(tree, hf_cc2400_fstst3_chp_test_up, tvb, offset, 2, ENC_BIG_ENDIAN);
1094 proto_tree_add_item(tree, hf_cc2400_fstst3_chp_test_dn, tvb, offset, 2, ENC_BIG_ENDIAN);
1095 proto_tree_add_item(tree, hf_cc2400_fstst3_chp_disable, tvb, offset, 2, ENC_BIG_ENDIAN);
1096 proto_tree_add_item(tree, hf_cc2400_fstst3_pd_delay, tvb, offset, 2, ENC_BIG_ENDIAN);
1097 proto_tree_add_item(tree, hf_cc2400_fstst3_chp_step_period, tvb, offset, 2, ENC_BIG_ENDIAN);
1098 proto_tree_add_item(tree, hf_cc2400_fstst3_stop_chp_current, tvb, offset, 2, ENC_BIG_ENDIAN);
1099 proto_tree_add_item(tree, hf_cc2400_fstst3_start_chp_current, tvb, offset, 2, ENC_BIG_ENDIAN);
1100 break;
1101 case 0x1E: /* MANFIDL */
1102 proto_tree_add_item(tree, hf_cc2400_manfidl_partnum, tvb, offset, 2, ENC_BIG_ENDIAN);
1103 proto_tree_add_item(tree, hf_cc2400_manfidl_manfid, tvb, offset, 2, ENC_BIG_ENDIAN);
1104 break;
1105 case 0x1F: /* MANFIDH */
1106 proto_tree_add_item(tree, hf_cc2400_manfidh_version, tvb, offset, 2, ENC_BIG_ENDIAN);
1107 proto_tree_add_item(tree, hf_cc2400_manfidh_partnum, tvb, offset, 2, ENC_BIG_ENDIAN);
1108 break;
1109 case 0x20: /* GRMDM */
1110 proto_tree_add_item(tree, hf_cc2400_grmdm_reserved, tvb, offset, 2, ENC_BIG_ENDIAN);
1111 proto_tree_add_item(tree, hf_cc2400_grmdm_sync_errbits_allowed, tvb, offset, 2, ENC_BIG_ENDIAN);
1112 proto_tree_add_item(tree, hf_cc2400_grmdm_pin_mode, tvb, offset, 2, ENC_BIG_ENDIAN);
1113 proto_tree_add_item(tree, hf_cc2400_grmdm_packet_mode, tvb, offset, 2, ENC_BIG_ENDIAN);
1114 proto_tree_add_item(tree, hf_cc2400_grmdm_pre_bytes, tvb, offset, 2, ENC_BIG_ENDIAN);
1115 proto_tree_add_item(tree, hf_cc2400_grmdm_sync_word_size, tvb, offset, 2, ENC_BIG_ENDIAN);
1116 proto_tree_add_item(tree, hf_cc2400_grmdm_crc_on, tvb, offset, 2, ENC_BIG_ENDIAN);
1117 proto_tree_add_item(tree, hf_cc2400_grmdm_data_format, tvb, offset, 2, ENC_BIG_ENDIAN);
1118 proto_tree_add_item(tree, hf_cc2400_grmdm_modulation_format, tvb, offset, 2, ENC_BIG_ENDIAN);
1119 proto_tree_add_item(tree, hf_cc2400_grmdm_tx_gaussian_filter, tvb, offset, 2, ENC_BIG_ENDIAN);
1120 break;
1121 case 0x21: /* GRDEC */
1122 proto_tree_add_item(tree, hf_cc2400_grdec_reserved, tvb, offset, 2, ENC_BIG_ENDIAN);
1123 proto_tree_add_item(tree, hf_cc2400_grdec_ind_saturation, tvb, offset, 2, ENC_BIG_ENDIAN);
1124 proto_tree_add_item(tree, hf_cc2400_grdec_dec_shift, tvb, offset, 2, ENC_BIG_ENDIAN);
1125 proto_tree_add_item(tree, hf_cc2400_grdec_channel_dec, tvb, offset, 2, ENC_BIG_ENDIAN);
1126 proto_tree_add_item(tree, hf_cc2400_grdec_dec_val, tvb, offset, 2, ENC_BIG_ENDIAN);
1127 break;
1128 case 0x22: /* PKTSTATUS */
1129 proto_tree_add_item(tree, hf_cc2400_pktstatus_reserved_15_11, tvb, offset, 2, ENC_BIG_ENDIAN);
1130 proto_tree_add_item(tree, hf_cc2400_pktstatus_sync_word_received, tvb, offset, 2, ENC_BIG_ENDIAN);
1131 proto_tree_add_item(tree, hf_cc2400_pktstatus_crc_ok, tvb, offset, 2, ENC_BIG_ENDIAN);
1132 proto_tree_add_item(tree, hf_cc2400_pktstatus_reserved_8, tvb, offset, 2, ENC_BIG_ENDIAN);
1133 proto_tree_add_item(tree, hf_cc2400_pktstatus_reserved_7_0, tvb, offset, 2, ENC_BIG_ENDIAN);
1134 break;
1135 case 0x23: /* INT */
1136 proto_tree_add_item(tree, hf_cc2400_int_reserved_15_8, tvb, offset, 2, ENC_BIG_ENDIAN);
1137 proto_tree_add_item(tree, hf_cc2400_int_reserved_7, tvb, offset, 2, ENC_BIG_ENDIAN);
1138 proto_tree_add_item(tree, hf_cc2400_int_pkt_polarity, tvb, offset, 2, ENC_BIG_ENDIAN);
1139 proto_tree_add_item(tree, hf_cc2400_int_fifo_polarity, tvb, offset, 2, ENC_BIG_ENDIAN);
1140 proto_tree_add_item(tree, hf_cc2400_int_fifo_threshold, tvb, offset, 2, ENC_BIG_ENDIAN);
1141 break;
1142 case 0x24: /* Reserved */
1143 proto_tree_add_item(tree, hf_cc2400_reserved_0x24_res_15_14, tvb, offset, 2, ENC_BIG_ENDIAN);
1144 proto_tree_add_item(tree, hf_cc2400_reserved_0x24_res_13_10, tvb, offset, 2, ENC_BIG_ENDIAN);
1145 proto_tree_add_item(tree, hf_cc2400_reserved_0x24_res_9_7, tvb, offset, 2, ENC_BIG_ENDIAN);
1146 proto_tree_add_item(tree, hf_cc2400_reserved_0x24_res_6_0, tvb, offset, 2, ENC_BIG_ENDIAN);
1147 break;
1148 case 0x25: /* Reserved */
1149 proto_tree_add_item(tree, hf_cc2400_reserved_0x25_res_15_12, tvb, offset, 2, ENC_BIG_ENDIAN);
1150 proto_tree_add_item(tree, hf_cc2400_reserved_0x25_res_11_0, tvb, offset, 2, ENC_BIG_ENDIAN);
1151 break;
1152 case 0x26: /* Reserved */
1153 proto_tree_add_item(tree, hf_cc2400_reserved_0x26_res_15_10, tvb, offset, 2, ENC_BIG_ENDIAN);
1154 proto_tree_add_item(tree, hf_cc2400_reserved_0x26_res_9_0, tvb, offset, 2, ENC_BIG_ENDIAN);
1155 break;
1156 case 0x27: /* Reserved */
1157 proto_tree_add_item(tree, hf_cc2400_reserved_0x27_res_15_8, tvb, offset, 2, ENC_BIG_ENDIAN);
1158 proto_tree_add_item(tree, hf_cc2400_reserved_0x27_res_7_3, tvb, offset, 2, ENC_BIG_ENDIAN);
1159 proto_tree_add_item(tree, hf_cc2400_reserved_0x27_res_2_0, tvb, offset, 2, ENC_BIG_ENDIAN);
1160 break;
1161 case 0x28: /* Reserved */
1162 proto_tree_add_item(tree, hf_cc2400_reserved_0x28_res_15, tvb, offset, 2, ENC_BIG_ENDIAN);
1163 proto_tree_add_item(tree, hf_cc2400_reserved_0x28_res_14_13, tvb, offset, 2, ENC_BIG_ENDIAN);
1164 proto_tree_add_item(tree, hf_cc2400_reserved_0x28_res_12_7, tvb, offset, 2, ENC_BIG_ENDIAN);
1165 proto_tree_add_item(tree, hf_cc2400_reserved_0x28_res_6_0, tvb, offset, 2, ENC_BIG_ENDIAN);
1166 break;
1167 case 0x29: /* Reserved */
1168 proto_tree_add_item(tree, hf_cc2400_reserved_0x29_res_15_8, tvb, offset, 2, ENC_BIG_ENDIAN);
1169 proto_tree_add_item(tree, hf_cc2400_reserved_0x29_res_7_3, tvb, offset, 2, ENC_BIG_ENDIAN);
1170 proto_tree_add_item(tree, hf_cc2400_reserved_0x29_res_2_0, tvb, offset, 2, ENC_BIG_ENDIAN);
1171 break;
1172 case 0x2A: /* Reserved */
1173 proto_tree_add_item(tree, hf_cc2400_reserved_0x2A_res_15_11, tvb, offset, 2, ENC_BIG_ENDIAN);
1174 proto_tree_add_item(tree, hf_cc2400_reserved_0x2A_res_10, tvb, offset, 2, ENC_BIG_ENDIAN);
1175 proto_tree_add_item(tree, hf_cc2400_reserved_0x2A_res_9_0, tvb, offset, 2, ENC_BIG_ENDIAN);
1176 break;
1177 case 0x2B: /* Reserved */
1178 proto_tree_add_item(tree, hf_cc2400_reserved_0x2B_res_15_14, tvb, offset, 2, ENC_BIG_ENDIAN);
1179 proto_tree_add_item(tree, hf_cc2400_reserved_0x2B_res_13, tvb, offset, 2, ENC_BIG_ENDIAN);
1180 proto_tree_add_item(tree, hf_cc2400_reserved_0x2B_res_12, tvb, offset, 2, ENC_BIG_ENDIAN);
1181 proto_tree_add_item(tree, hf_cc2400_reserved_0x2B_res_11_0, tvb, offset, 2, ENC_BIG_ENDIAN);
1182 break;
1183 case 0x2C: /* SYNCL */
1184 proto_tree_add_item(tree, hf_cc2400_syncl, tvb, offset, 2, ENC_BIG_ENDIAN);
1185 break;
1186 case 0x2D: /* SYNCH */
1187 proto_tree_add_item(tree, hf_cc2400_synch, tvb, offset, 2, ENC_BIG_ENDIAN);
1188 break;
1189 default:
1190 proto_tree_add_item(tree, hf_cc2400_value, tvb, offset, 2, ENC_BIG_ENDIAN);
1191 }
1192 }
1193
1194 static int
1195 dissect_usb_rx_packet(proto_tree *main_tree, proto_tree *tree, packet_info *pinfo,
1196 tvbuff_t *tvb, int offset, int16_t command, urb_info_t *urb)
1197 {
1198 proto_item *sub_item;
1199 proto_tree *sub_tree;
1200 proto_item *p_item;
1201 proto_item *data_item;
1202 proto_tree *data_tree;
1203 proto_item *entry_item;
1204 proto_tree *entry_tree;
1205 int i_spec;
1206 int length;
1207 tvbuff_t *next_tvb;
1208 uint8_t packet_type;
1209 uint32_t start_offset;
1210 uint32_t clock_100ns;
1211 uint8_t channel;
1212 ubertooth_data_t *ubertooth_data;
1213
1214 sub_item = proto_tree_add_item(tree, hf_usb_rx_packet, tvb, offset, 64, ENC_NA);
1215 sub_tree = proto_item_add_subtree(sub_item, ett_usb_rx_packet);
1216
1217 start_offset = offset;
1218
1219 proto_tree_add_item(sub_tree, hf_packet_type, tvb, offset, 1, ENC_NA);
1220 packet_type = tvb_get_uint8(tvb, offset);
1221 offset += 1;
1222
1223 if (packet_type == 0x05) { /* LE_PROMISC */
1224 uint8_t state;
1225
1226 proto_tree_add_item(sub_tree, hf_state, tvb, offset, 1, ENC_NA);
1227 state = tvb_get_uint8(tvb, offset);
1228 col_append_fstr(pinfo->cinfo, COL_INFO, " LE Promiscuous - %s", val_to_str_const(state, usb_rx_packet_state_vals, "Unknown"));
1229 offset += 1;
1230
1231 switch (state) {
1232 case 0: /* Access Address */
1233 proto_tree_add_item(sub_tree, hf_access_address, tvb, offset, 4, ENC_LITTLE_ENDIAN);
1234 col_append_fstr(pinfo->cinfo, COL_INFO, " 0x%04x", tvb_get_letohl(tvb, offset));
1235 offset += 4;
1236 break;
1237 case 1: /* CRC Init */
1238 proto_tree_add_item(sub_tree, hf_crc_init, tvb, offset, 3, ENC_LITTLE_ENDIAN);
1239 col_append_fstr(pinfo->cinfo, COL_INFO, " 0x%06x", tvb_get_letoh24(tvb, offset));
1240 offset += 3;
1241 break;
1242 case 2: /* Hop Interval */
1243 p_item = proto_tree_add_item(sub_tree, hf_hop_interval, tvb, offset, 2, ENC_LITTLE_ENDIAN);
1244 proto_item_append_text(p_item, " (%f ms), ", tvb_get_letohs(tvb, offset) * 1.25);
1245 col_append_fstr(pinfo->cinfo, COL_INFO, " %f ms", tvb_get_letohs(tvb, offset) * 1.25);
1246 offset += 2;
1247 break;
1248 case 3: /* Hop Increment */
1249 proto_tree_add_item(sub_tree, hf_hop_increment, tvb, offset, 1, ENC_NA);
1250 col_append_fstr(pinfo->cinfo, COL_INFO, " %u", tvb_get_uint8(tvb, offset));
1251 offset += 1;
1252 break;
1253 }
1254
1255 proto_tree_add_item(sub_tree, hf_reserved, tvb, offset, 64 - (offset - start_offset), ENC_NA);
1256 offset += 64 - (offset - start_offset);
1257
1258 return offset;
1259 }
1260
1261 proto_tree_add_item(sub_tree, hf_chip_status_reserved, tvb, offset, 1, ENC_NA);
1262 proto_tree_add_item(sub_tree, hf_chip_status_rssi_trigger, tvb, offset, 1, ENC_NA);
1263 proto_tree_add_item(sub_tree, hf_chip_status_cs_trigger, tvb, offset, 1, ENC_NA);
1264 proto_tree_add_item(sub_tree, hf_chip_status_fifo_overflow, tvb, offset, 1, ENC_NA);
1265 proto_tree_add_item(sub_tree, hf_chip_status_dma_error, tvb, offset, 1, ENC_NA);
1266 proto_tree_add_item(sub_tree, hf_chip_status_dma_overflow, tvb, offset, 1, ENC_NA);
1267 offset += 1;
1268
1269 proto_tree_add_item(sub_tree, hf_usb_rx_packet_channel, tvb, offset, 1, ENC_NA);
1270 channel = tvb_get_uint8(tvb, offset);
1271 offset += 1;
1272
1273 proto_tree_add_item(sub_tree, hf_clock_ns, tvb, offset, 1, ENC_NA);
1274 offset += 1;
1275
1276 proto_tree_add_item(sub_tree, hf_clock_100ns, tvb, offset, 4, ENC_LITTLE_ENDIAN);
1277 clock_100ns = tvb_get_letohl(tvb, offset);
1278 offset += 4;
1279
1280 proto_tree_add_item(sub_tree, hf_rssi_max, tvb, offset, 1, ENC_NA);
1281 offset += 1;
1282
1283 proto_tree_add_item(sub_tree, hf_rssi_min, tvb, offset, 1, ENC_NA);
1284 offset += 1;
1285
1286 proto_tree_add_item(sub_tree, hf_rssi_avg, tvb, offset, 1, ENC_NA);
1287 offset += 1;
1288
1289 proto_tree_add_item(sub_tree, hf_rssi_count, tvb, offset, 1, ENC_NA);
1290 offset += 1;
1291
1292 proto_tree_add_item(sub_tree, hf_reserved, tvb, offset, 2, ENC_NA);
1293 offset += 2;
1294
1295 data_item = proto_tree_add_item(sub_tree, hf_data, tvb, offset, 50, ENC_NA);
1296 data_tree = proto_item_add_subtree(data_item, ett_usb_rx_packet_data);
1297
1298 switch (command) {
1299 case 27: /* Spectrum Analyzer */
1300 for (i_spec = 0; i_spec < 48; i_spec += 3) {
1301 entry_item = proto_tree_add_item(data_tree, hf_spectrum_entry, tvb, offset, 3, ENC_NA);
1302 entry_tree = proto_item_add_subtree(entry_item, ett_entry);
1303
1304 proto_tree_add_item(entry_tree, hf_frequency, tvb, offset, 2, ENC_BIG_ENDIAN);
1305 offset += 2;
1306
1307 proto_tree_add_item(entry_tree, hf_rssi, tvb, offset, 1, ENC_NA);
1308 offset += 1;
1309
1310 proto_item_append_text(entry_item, " Frequency = %u MHz, RSSI = %i", tvb_get_ntohs(tvb, offset - 3), tvb_get_int8(tvb, offset - 1));
1311 }
1312
1313 proto_tree_add_item(data_tree, hf_reserved, tvb, offset, 2, ENC_NA);
1314 offset += 2;
1315 break;
1316 case 49: /* Poll */
1317 if (packet_type == 0x00) {/* BD/EDR */
1318 /* TODO: btbb dissector */
1319 offset += 50;
1320 } else if (packet_type == 0x01 || packet_type == 0x05) { /* LE || LE Promiscuous */
1321 length = 9; /* From BTLE: AccessAddress (4) + Header (2) + Length from Header (below) + CRC (3) */
1322
1323 if (tvb_get_letohl(tvb, offset) == ACCESS_ADDRESS_ADVERTISING)
1324 length += tvb_get_uint8(tvb, offset + 5) & 0x3f;
1325 else
1326 length += tvb_get_uint8(tvb, offset + 5) & 0x1f;
1327
1328 ubertooth_data = wmem_new(pinfo->pool, ubertooth_data_t);
1329 ubertooth_data->bus_id = urb->bus_id;
1330 ubertooth_data->device_address = urb->device_address;
1331 ubertooth_data->clock_100ns = clock_100ns;
1332 ubertooth_data->channel = channel;
1333
1334 next_tvb = tvb_new_subset_length(tvb, offset, length);
1335 call_dissector_with_data(bluetooth_ubertooth_handle, next_tvb, pinfo, main_tree, ubertooth_data);
1336 offset += length;
1337 } else if (packet_type == 0x06) {/* Ego */
1338 /* NOTE: Yuneec E-GO skateboard - unknown protocol */
1339 offset += 50;
1340 } else if (packet_type == 0x02 || packet_type == 0x03 || packet_type == 0x04) { /* Message || Keep Alive || Spectrum Analyze */
1341 /* NOTE: ? */
1342 offset += 50;
1343 }
1344
1345 if (tvb_reported_length_remaining(tvb, offset) > 0) {
1346 proto_tree_add_item(data_tree, hf_reserved, tvb, offset, -1, ENC_NA);
1347 offset += tvb_captured_length_remaining(tvb, offset);
1348 }
1349
1350 break;
1351 default:
1352 offset += 50;
1353 }
1354
1355 return offset;
1356 }
1357
1358 static int
1359 dissect_ubertooth(tvbuff_t *tvb, packet_info *pinfo, proto_tree *tree, void *data)
1360 {
1361 proto_item *main_tree = NULL;
1362 proto_tree *main_item = NULL;
1363 proto_item *command_item;
1364 proto_item *command_tree;
1365 proto_item *sub_item;
1366 proto_item *sub_tree;
1367 int offset = 0;
1368 urb_info_t *urb = (urb_info_t *)data;
1369 int p2p_dir_save;
1370 uint8_t command;
1371 int16_t command_response = -1;
1372 command_data_t *command_data = NULL;
1373 wmem_tree_t *wmem_tree;
1374 wmem_tree_key_t key[5];
1375 uint32_t bus_id;
1376 uint32_t device_address;
1377 uint32_t k_bus_id;
1378 uint32_t k_device_address;
1379 uint32_t k_frame_number;
1380 uint8_t length;
1381 uint32_t *serial;
1382 uint8_t status;
1383 int32_t register_id = -1;
1384
1385 main_item = proto_tree_add_item(tree, proto_ubertooth, tvb, offset, -1, ENC_NA);
1386 main_tree = proto_item_add_subtree(main_item, ett_ubertooth);
1387
1388 col_set_str(pinfo->cinfo, COL_PROTOCOL, "UBERTOOTH");
1389
1390 if (!urb) return offset;
1391
1392 p2p_dir_save = pinfo->p2p_dir;
1393 pinfo->p2p_dir = (urb->is_request) ? P2P_DIR_SENT : P2P_DIR_RECV;
1394
1395 switch (pinfo->p2p_dir) {
1396
1397 case P2P_DIR_SENT:
1398 col_set_str(pinfo->cinfo, COL_INFO, "Sent ");
1399 break;
1400
1401 case P2P_DIR_RECV:
1402 col_set_str(pinfo->cinfo, COL_INFO, "Rcvd ");
1403 break;
1404
1405 default:
1406 col_add_fstr(pinfo->cinfo, COL_INFO, "Unknown direction %d ",
1407 pinfo->p2p_dir);
1408 break;
1409 }
1410
1411 bus_id = urb->bus_id;
1412 device_address = urb->device_address;
1413
1414 k_bus_id = bus_id;
1415 k_device_address = device_address;
1416 k_frame_number = pinfo->num;
1417
1418 key[0].length = 1;
1419 key[0].key = &k_bus_id;
1420 key[1].length = 1;
1421 key[1].key = &k_device_address;
1422
1423
1424 if (urb->is_setup) {
1425 proto_tree_add_item(main_tree, hf_command, tvb, offset, 1, ENC_NA);
1426 command = tvb_get_uint8(tvb, offset);
1427 offset += 1;
1428
1429 col_append_fstr(pinfo->cinfo, COL_INFO, "Command: %s",
1430 val_to_str_ext_const(command, &command_vals_ext, "Unknown"));
1431
1432 switch (command) {
1433 /* Group of commands with parameters by "setup" */
1434 case 1: /* Rx Symbols */
1435 case 4: /* Set User LED */
1436 case 6: /* Set Rx LED */
1437 case 8: /* Set Tx LED */
1438 case 10: /* Set 1V8 */
1439 case 12: /* Set Channel */
1440 case 17: /* Set PAEN */
1441 case 19: /* Set HGM */
1442 case 23: /* Set Modulation */
1443 case 29: /* Set Power Amplifier Level */
1444 case 34: /* LED Spectrum Analyzer */
1445 case 36: /* Set Squelch */
1446 case 42: /* BTLE Sniffing */
1447 case 48: /* Set CRC Verify */
1448 case 53: /* Read Register */
1449 case 58: /* Write Register */
1450 case 59: /* Jam Mode */
1451 case 60: /* Ego */
1452
1453 switch (command) {
1454 case 1: /* Rx Symbols */
1455 case 42: /* BTLE Sniffing */
1456 proto_tree_add_item(main_tree, hf_rx_packets, tvb, offset, 2, ENC_LITTLE_ENDIAN);
1457 col_append_fstr(pinfo->cinfo, COL_INFO, " - Rx Packets: %u", tvb_get_letohs(tvb, offset));
1458 offset += 2;
1459
1460 break;
1461 case 4: /* Set User LED */
1462 proto_tree_add_item(main_tree, hf_user_led, tvb, offset, 2, ENC_LITTLE_ENDIAN);
1463 col_append_fstr(pinfo->cinfo, COL_INFO, " - %s", val_to_str_ext_const(tvb_get_letohs(tvb, offset), &led_state_vals_ext, "Unknown"));
1464 offset += 2;
1465
1466 break;
1467 case 6: /* Set Rx LED */
1468 proto_tree_add_item(main_tree, hf_rx_led, tvb, offset, 2, ENC_LITTLE_ENDIAN);
1469 col_append_fstr(pinfo->cinfo, COL_INFO, " - %s", val_to_str_ext_const(tvb_get_letohs(tvb, offset), &led_state_vals_ext, "Unknown"));
1470 offset += 2;
1471
1472 break;
1473 case 8: /* Set Tx LED */
1474 proto_tree_add_item(main_tree, hf_tx_led, tvb, offset, 2, ENC_LITTLE_ENDIAN);
1475 col_append_fstr(pinfo->cinfo, COL_INFO, " - %s", val_to_str_ext_const(tvb_get_letohs(tvb, offset), &led_state_vals_ext, "Unknown"));
1476 offset += 2;
1477
1478 break;
1479 case 10: /* Set 1V8 */
1480 proto_tree_add_item(main_tree, hf_1v8_led, tvb, offset, 2, ENC_LITTLE_ENDIAN);
1481 col_append_fstr(pinfo->cinfo, COL_INFO, " - %s", val_to_str_ext_const(tvb_get_letohs(tvb, offset), &led_state_vals_ext, "Unknown"));
1482 offset += 2;
1483
1484 break;
1485 case 12: /* Set Channel */
1486 proto_tree_add_item(main_tree, hf_channel, tvb, offset, 2, ENC_LITTLE_ENDIAN);
1487 col_append_fstr(pinfo->cinfo, COL_INFO, " - %u MHz", tvb_get_letohs(tvb, offset));
1488 offset += 2;
1489
1490 break;
1491 case 17: /* Set PAEN */
1492 proto_tree_add_item(main_tree, hf_paen, tvb, offset, 2, ENC_LITTLE_ENDIAN);
1493 col_append_fstr(pinfo->cinfo, COL_INFO, " - %s", val_to_str_ext_const(tvb_get_letohs(tvb, offset), &state_vals_ext, "Unknown"));
1494 offset += 2;
1495
1496 break;
1497 case 19: /* Set HGM */
1498 proto_tree_add_item(main_tree, hf_hgm, tvb, offset, 2, ENC_LITTLE_ENDIAN);
1499 col_append_fstr(pinfo->cinfo, COL_INFO, " - %s", val_to_str_ext_const(tvb_get_letohs(tvb, offset), &state_vals_ext, "Unknown"));
1500 offset += 2;
1501
1502 break;
1503 case 23: /* Set Modulation */
1504 proto_tree_add_item(main_tree, hf_modulation, tvb, offset, 2, ENC_LITTLE_ENDIAN);
1505 col_append_fstr(pinfo->cinfo, COL_INFO, " - %s", val_to_str_ext_const(tvb_get_letohs(tvb, offset), &modulation_vals_ext, "Unknown"));
1506 offset += 2;
1507
1508 break;
1509 case 29: /* Set Power Amplifier Level */
1510 proto_tree_add_item(main_tree, hf_power_amplifier_reserved, tvb, offset, 1, ENC_NA);
1511 proto_tree_add_item(main_tree, hf_power_amplifier_level, tvb, offset, 1, ENC_NA);
1512 col_append_fstr(pinfo->cinfo, COL_INFO, " = %u", tvb_get_letohs(tvb, offset) & 0x7);
1513 offset += 1;
1514
1515 proto_tree_add_item(main_tree, hf_reserved, tvb, offset, 1, ENC_NA);
1516 offset += 1;
1517
1518 break;
1519 case 34: /* LED Spectrum Analyzer */
1520 proto_tree_add_item(main_tree, hf_rssi_threshold, tvb, offset, 2, ENC_LITTLE_ENDIAN);
1521 col_append_fstr(pinfo->cinfo, COL_INFO, " = %i", tvb_get_letohis(tvb, offset));
1522 offset += 2;
1523
1524 break;
1525 case 36: /* Set Squelch */
1526 proto_tree_add_item(main_tree, hf_squelch, tvb, offset, 2, ENC_LITTLE_ENDIAN);
1527 col_append_fstr(pinfo->cinfo, COL_INFO, " = %i", tvb_get_letohis(tvb, offset));
1528 offset += 2;
1529
1530 break;
1531 case 48: /* Set CRC Verify */
1532 proto_tree_add_item(main_tree, hf_crc_verify, tvb, offset, 2, ENC_LITTLE_ENDIAN);
1533 col_append_fstr(pinfo->cinfo, COL_INFO, " - %s", val_to_str_ext_const(tvb_get_letohs(tvb, offset), &state_vals_ext, "Unknown"));
1534 offset += 2;
1535
1536 break;
1537 case 53: /* Read Register */
1538 sub_item = proto_tree_add_item(main_tree, hf_register, tvb, offset, 2, ENC_LITTLE_ENDIAN);
1539 register_id = tvb_get_letohs(tvb, offset);
1540 col_append_fstr(pinfo->cinfo, COL_INFO, " - %s",
1541 val_to_str_ext_const(register_id, &register_vals_ext, "Unknown"));
1542 if (try_val_to_str_ext(register_id, &register_vals_ext))
1543 proto_item_append_text(sub_item, " [%s]", val_to_str_ext_const(register_id, &register_description_vals_ext, "Unknown"));
1544 offset += 2;
1545
1546 break;
1547 case 58: /* Write Register */
1548 sub_item = proto_tree_add_item(main_tree, hf_register, tvb, offset, 2, ENC_LITTLE_ENDIAN);
1549 register_id = tvb_get_letohs(tvb, offset);
1550 col_append_fstr(pinfo->cinfo, COL_INFO, " - %s",
1551 val_to_str_ext_const(register_id, &register_vals_ext, "Unknown"));
1552 if (try_val_to_str_ext(register_id, &register_vals_ext))
1553 proto_item_append_text(sub_item, " [%s]", val_to_str_ext_const(register_id, &register_description_vals_ext, "Unknown"));
1554 offset += 2;
1555
1556 sub_item = proto_tree_add_item(main_tree, hf_register_value, tvb, offset, 2, ENC_BIG_ENDIAN);
1557 sub_tree = proto_item_add_subtree(sub_item, ett_register_value);
1558 col_append_fstr(pinfo->cinfo, COL_INFO, " = %s: 0x%04x",
1559 val_to_str_ext_const(register_id, &register_vals_ext, "Unknown"),
1560 tvb_get_ntohs(tvb, offset));
1561
1562 dissect_cc2400_register(sub_tree, tvb, offset, register_id);
1563 offset += 2;
1564
1565 break;
1566 case 59: /* Jam Mode */
1567 proto_tree_add_item(main_tree, hf_jam_mode, tvb, offset, 2, ENC_LITTLE_ENDIAN);
1568 col_append_fstr(pinfo->cinfo, COL_INFO, " - %s", val_to_str_const(tvb_get_letohs(tvb, offset), jam_mode_vals, "Unknown"));
1569 offset += 2;
1570
1571 break;
1572 case 60: /* Ego */
1573 proto_tree_add_item(main_tree, hf_ego_mode, tvb, offset, 2, ENC_LITTLE_ENDIAN);
1574 col_append_fstr(pinfo->cinfo, COL_INFO, " - %s", val_to_str_const(tvb_get_letohs(tvb, offset), ego_mode_vals, "Unknown"));
1575 offset += 2;
1576
1577 break;
1578 default:
1579 proto_tree_add_item(main_tree, hf_argument_0, tvb, offset, 2, ENC_LITTLE_ENDIAN);
1580 offset += 2;
1581 }
1582
1583 proto_tree_add_item(main_tree, hf_argument_1, tvb, offset, 2, ENC_LITTLE_ENDIAN);
1584 offset += 2;
1585
1586 break;
1587 case 27: /* Spectrum Analyzer */
1588 proto_tree_add_item(main_tree, hf_low_frequency, tvb, offset, 2, ENC_LITTLE_ENDIAN);
1589 offset += 2;
1590
1591 proto_tree_add_item(main_tree, hf_high_frequency, tvb, offset, 2, ENC_LITTLE_ENDIAN);
1592 offset += 2;
1593
1594 col_append_fstr(pinfo->cinfo, COL_INFO, " - %u-%u MHz", tvb_get_letohs(tvb, offset - 4), tvb_get_letohs(tvb, offset - 2));
1595
1596 break;
1597 /* Group of commands with parameters by "data" but no "setup"*/
1598 case 38: /* Set BDADDR */
1599 case 39: /* Start Hopping */
1600 case 40: /* Set Clock */
1601 case 44: /* Set Access Address */
1602 case 51: /* Set AFH Map */
1603 case 54: /* BTLE Slave */
1604 /* Group of commands without any parameters */
1605 case 0: /* Ping */
1606 case 2: /* Tx Symbols */ /* NOTE: This one seems to be not implemented in firmware at all*/
1607 case 3: /* Get User LED */
1608 case 5: /* Get Rx LED */
1609 case 7: /* Get Tx LED */
1610 case 9: /* Get 1V8 */
1611 case 11: /* Get Channel */
1612 case 13: /* Reset */
1613 case 14: /* Get Microcontroller Serial Number */
1614 case 15: /* Get Microcontroller Part Number */
1615 case 16: /* Get PAEN */
1616 case 18: /* Get HGM */
1617 case 20: /* Tx Test */
1618 case 21: /* Stop */
1619 case 22: /* Get Modulation */
1620 case 24: /* Set ISP */
1621 case 25: /* Flash */
1622 case 26: /* Bootloader Flash */ /* NOTE: This one seems to be not implemented in firmware at all*/
1623 case 28: /* Get Power Amplifier Level */
1624 case 30: /* Repeater */
1625 case 31: /* Range Test */
1626 case 32: /* Range Check */
1627 case 33: /* Get Firmware Revision Number */
1628 case 35: /* Get Hardware Board ID */
1629 case 37: /* Get Squelch */
1630 case 41: /* Get Clock */
1631 case 43: /* Get Access Address */
1632 case 45: /* Do Something */
1633 case 46: /* Do Something Reply */
1634 case 47: /* Get CRC Verify */
1635 case 49: /* Poll */
1636 case 50: /* BTLE Promiscuous Mode */
1637 case 52: /* Clear AFH Map */
1638 case 55: /* Get Compile Info */
1639 default:
1640 proto_tree_add_item(main_tree, hf_argument_0, tvb, offset, 2, ENC_LITTLE_ENDIAN);
1641 offset += 2;
1642
1643 proto_tree_add_item(main_tree, hf_argument_1, tvb, offset, 2, ENC_LITTLE_ENDIAN);
1644 offset += 2;
1645 }
1646
1647 proto_tree_add_item(main_tree, hf_estimated_length, tvb, offset, 2, ENC_LITTLE_ENDIAN);
1648 offset += 2;
1649
1650
1651 switch (command) {
1652 case 38: /* Set BDADDR */
1653 case 54: /* BTLE Slave */
1654 case 56: /* BTLE Set Target */
1655 proto_tree_add_item(main_tree, hf_bdaddr, tvb, offset, 6, ENC_NA);
1656 col_append_fstr(pinfo->cinfo, COL_INFO, " - %s",
1657 tvb_get_ether_name(tvb, offset));
1658
1659 offset += 6;
1660 break;
1661 case 39: /* Start Hopping */
1662 proto_tree_add_item(main_tree, hf_clock_offset, tvb, offset, 4, ENC_LITTLE_ENDIAN);
1663 col_append_fstr(pinfo->cinfo, COL_INFO, " - %u", tvb_get_letohl(tvb, offset));
1664
1665 offset += 4;
1666 break;
1667 case 40: /* Set Clock */
1668 proto_tree_add_item(main_tree, hf_clock_100ns, tvb, offset, 4, ENC_LITTLE_ENDIAN);
1669 col_append_fstr(pinfo->cinfo, COL_INFO, " - %u", tvb_get_letohl(tvb, offset));
1670
1671 offset += 4;
1672 break;
1673 case 44: /* Set Access Address */
1674 proto_tree_add_item(main_tree, hf_access_address, tvb, offset, 4, ENC_LITTLE_ENDIAN);
1675 col_append_fstr(pinfo->cinfo, COL_INFO, " - %08x", tvb_get_letohl(tvb, offset));
1676
1677 offset += 4;
1678 break;
1679 case 51: /* Set AFH Map */
1680 proto_tree_add_item(main_tree, hf_afh_map, tvb, offset, 10, ENC_NA);
1681 col_append_fstr(pinfo->cinfo, COL_INFO, " - %s", tvb_bytes_to_str(pinfo->pool, tvb, offset, 10));
1682
1683 offset += 10;
1684 break;
1685 }
1686
1687 if (tvb_reported_length_remaining(tvb, offset) > 0) {
1688 proto_tree_add_expert(main_tree, pinfo, &ei_unexpected_data, tvb, offset, tvb_captured_length_remaining(tvb, offset));
1689 offset = tvb_captured_length(tvb);
1690 }
1691
1692 /* Save request info (command_data) */
1693 if (!pinfo->fd->visited && command != 21) {
1694 key[2].length = 1;
1695 key[2].key = &k_frame_number;
1696 key[3].length = 0;
1697 key[3].key = NULL;
1698
1699 command_data = wmem_new(wmem_file_scope(), command_data_t);
1700 command_data->bus_id = bus_id;
1701 command_data->device_address = device_address;
1702
1703 command_data->command = command;
1704 command_data->command_frame_number = pinfo->num;
1705 command_data->register_id = register_id;
1706
1707 wmem_tree_insert32_array(command_info, key, command_data);
1708 }
1709
1710 pinfo->p2p_dir = p2p_dir_save;
1711
1712 return offset;
1713 }
1714
1715 /* Get request info (command_data) */
1716 key[2].length = 0;
1717 key[2].key = NULL;
1718
1719 wmem_tree = (wmem_tree_t *) wmem_tree_lookup32_array(command_info, key);
1720 if (wmem_tree) {
1721 command_data = (command_data_t *) wmem_tree_lookup32_le(wmem_tree, pinfo->num);
1722 if (command_data) {
1723 command_response = command_data->command;
1724 register_id = command_data->register_id;
1725 }
1726 }
1727
1728 if (!command_data) {
1729 col_append_str(pinfo->cinfo, COL_INFO, "Response: Unknown");
1730
1731 proto_tree_add_expert(main_tree, pinfo, &ei_unknown_data, tvb, offset, tvb_captured_length_remaining(tvb, offset));
1732
1733 pinfo->p2p_dir = p2p_dir_save;
1734
1735 return tvb_captured_length(tvb);
1736 }
1737
1738 col_append_fstr(pinfo->cinfo, COL_INFO, "Response: %s",
1739 val_to_str_ext_const(command_response, &command_vals_ext, "Unknown"));
1740
1741 command_item = proto_tree_add_uint(main_tree, hf_response, tvb, offset, 0, command_response);
1742 command_tree = proto_item_add_subtree(command_item, ett_command);
1743 proto_item_set_generated(command_item);
1744 switch (command_response) {
1745
1746 case 1: /* Rx Symbols */
1747 case 27: /* Spectrum Analyzer */
1748 if (urb->transfer_type == URB_BULK) {
1749
1750 while (tvb_reported_length_remaining(tvb, offset) > 0) {
1751 offset = dissect_usb_rx_packet(tree, main_tree, pinfo, tvb, offset, command_response, urb);
1752 }
1753 break;
1754 }
1755 /* FALLTHROUGH */
1756 case 0: /* Ping */
1757 case 2: /* Tx Symbols */ /* NOTE: This one seems to be not implemented in firmware at all*/
1758 case 26: /* Bootloader Flash */ /* NOTE: This one seems to be not implemented in firmware at all*/
1759 case 4: /* Set User LED */
1760 case 6: /* Set Rx LED */
1761 case 8: /* Set Tx LED */
1762 case 10: /* Set 1V8 */
1763 case 12: /* Set Channel */
1764 case 13: /* Reset */
1765 case 17: /* Set PAEN */
1766 case 19: /* Set HGM */
1767 case 20: /* Tx Test */
1768 case 21: /* Stop */
1769 case 29: /* Set Power Amplifier Level */
1770 case 30: /* Repeater */
1771 case 31: /* Range Test */
1772 case 23: /* Set Modulation */
1773 case 24: /* Set ISP */
1774 case 25: /* Flash */
1775 case 34: /* LED Spectrum Analyzer */
1776 case 36: /* Set Squelch */
1777 case 38: /* Set BDADDR */
1778 case 39: /* Start Hopping */
1779 case 40: /* Set Clock */
1780 case 42: /* BTLE Sniffing */
1781 case 44: /* Set Access Address */
1782 case 45: /* Do Something */
1783 case 48: /* Set CRC Verify */
1784 case 50: /* BTLE Promiscuous Mode */
1785 case 51: /* Set AFH Map */
1786 case 52: /* Clear AFH Map */
1787 case 54: /* BTLE Slave */
1788 case 56: /* BTLE Set Target */
1789 case 58: /* Write Register */
1790 proto_tree_add_expert(command_tree, pinfo, &ei_unexpected_response, tvb, offset, 0);
1791 if (tvb_reported_length_remaining(tvb, offset) > 0) {
1792 proto_tree_add_expert(main_tree, pinfo, &ei_unknown_data, tvb, offset, -1);
1793 offset = tvb_captured_length(tvb);
1794 }
1795 break;
1796 case 3: /* Get User LED */
1797 proto_tree_add_item(main_tree, hf_user_led, tvb, offset, 1, ENC_NA);
1798 col_append_fstr(pinfo->cinfo, COL_INFO, " = %s", val_to_str_ext_const(tvb_get_uint8(tvb, offset), &led_state_vals_ext, "Unknown"));
1799 offset += 1;
1800
1801 break;
1802 case 5: /* Get Rx LED */
1803 proto_tree_add_item(main_tree, hf_rx_led, tvb, offset, 1, ENC_NA);
1804 col_append_fstr(pinfo->cinfo, COL_INFO, " = %s", val_to_str_ext_const(tvb_get_uint8(tvb, offset), &led_state_vals_ext, "Unknown"));
1805 offset += 1;
1806
1807 break;
1808 case 7: /* Get Tx LED */
1809 proto_tree_add_item(main_tree, hf_tx_led, tvb, offset, 1, ENC_NA);
1810 col_append_fstr(pinfo->cinfo, COL_INFO, " = %s", val_to_str_ext_const(tvb_get_uint8(tvb, offset), &led_state_vals_ext, "Unknown"));
1811 offset += 1;
1812
1813 break;
1814 case 9: /* Get 1V8 */
1815 proto_tree_add_item(main_tree, hf_1v8_led, tvb, offset, 1, ENC_NA);
1816 col_append_fstr(pinfo->cinfo, COL_INFO, " = %s", val_to_str_ext_const(tvb_get_uint8(tvb, offset), &led_state_vals_ext, "Unknown"));
1817 offset += 1;
1818
1819 break;
1820 case 11: /* Get Channel */
1821 proto_tree_add_item(main_tree, hf_channel, tvb, offset, 2, ENC_LITTLE_ENDIAN);
1822 col_append_fstr(pinfo->cinfo, COL_INFO, " = %u MHz", tvb_get_letohs(tvb, offset));
1823 offset += 2;
1824
1825 break;
1826 case 14: /* Get Microcontroller Serial Number */
1827 proto_tree_add_item(main_tree, hf_status, tvb, offset, 1, ENC_NA);
1828 status = tvb_get_uint8(tvb, offset);
1829 offset += 1;
1830
1831 if (status) break;
1832
1833 serial = (uint32_t *) wmem_alloc(pinfo->pool, 16);
1834 serial[0] = tvb_get_ntohl(tvb, offset);
1835 serial[1] = tvb_get_ntohl(tvb, offset + 4);
1836 serial[2] = tvb_get_ntohl(tvb, offset + 8);
1837 serial[3] = tvb_get_ntohl(tvb, offset + 12);
1838
1839 proto_tree_add_bytes(main_tree, hf_serial_number, tvb,
1840 offset, 16, (uint8_t *) serial);
1841 col_append_fstr(pinfo->cinfo, COL_INFO, " = %s",
1842 bytes_to_str(pinfo->pool, (uint8_t *) serial, 16));
1843 offset += 16;
1844
1845 break;
1846 case 15: /* Get Microcontroller Part Number */
1847 proto_tree_add_item(main_tree, hf_status, tvb, offset, 1, ENC_NA);
1848 status = tvb_get_uint8(tvb, offset);
1849 offset += 1;
1850
1851 if (status) break;
1852
1853 proto_tree_add_item(main_tree, hf_part_number, tvb, offset, 4, ENC_LITTLE_ENDIAN);
1854 col_append_fstr(pinfo->cinfo, COL_INFO, " = %08X", tvb_get_letohl(tvb, offset));
1855 offset += 4;
1856
1857 break;
1858 case 16: /* Get PAEN */
1859 proto_tree_add_item(main_tree, hf_paen, tvb, offset, 1, ENC_NA);
1860 col_append_fstr(pinfo->cinfo, COL_INFO, " = %s", val_to_str_ext_const(tvb_get_uint8(tvb, offset), &state_vals_ext, "Unknown"));
1861 offset += 1;
1862
1863 break;
1864 case 18: /* Get HGM */
1865 proto_tree_add_item(main_tree, hf_hgm, tvb, offset, 1, ENC_NA);
1866 col_append_fstr(pinfo->cinfo, COL_INFO, " = %s", val_to_str_ext_const(tvb_get_uint8(tvb, offset), &state_vals_ext, "Unknown"));
1867 offset += 1;
1868
1869 break;
1870 case 22: /* Get Modulation */
1871 proto_tree_add_item(main_tree, hf_modulation, tvb, offset, 1, ENC_NA);
1872 col_append_fstr(pinfo->cinfo, COL_INFO, " = %s", val_to_str_ext_const(tvb_get_uint8(tvb, offset), &modulation_vals_ext, "Unknown"));
1873 offset += 1;
1874
1875 break;
1876 case 28: /* Get Power Amplifier Level */
1877 proto_tree_add_item(main_tree, hf_power_amplifier_reserved, tvb, offset, 1, ENC_NA);
1878 proto_tree_add_item(main_tree, hf_power_amplifier_level, tvb, offset, 1, ENC_NA);
1879 col_append_fstr(pinfo->cinfo, COL_INFO, " = %u", tvb_get_uint8(tvb, offset) & 0x7);
1880 offset += 1;
1881
1882 break;
1883 case 32: /* Range Check */
1884 proto_tree_add_item(main_tree, hf_range_test_valid, tvb, offset, 1, ENC_NA);
1885 offset += 1;
1886
1887 proto_tree_add_item(main_tree, hf_range_test_request_power_amplifier, tvb, offset, 1, ENC_NA);
1888 offset += 1;
1889
1890 proto_tree_add_item(main_tree, hf_range_test_request_number, tvb, offset, 1, ENC_NA);
1891 offset += 1;
1892
1893 proto_tree_add_item(main_tree, hf_range_test_reply_power_amplifier, tvb, offset, 1, ENC_NA);
1894 offset += 1;
1895
1896 proto_tree_add_item(main_tree, hf_range_test_reply_number, tvb, offset, 1, ENC_NA);
1897 offset += 1;
1898
1899 break;
1900 case 33: /* Get Firmware Revision Number */
1901 {
1902 const uint8_t* firmware;
1903 proto_tree_add_item(main_tree, hf_reserved, tvb, offset, 2, ENC_NA);
1904 offset += 2;
1905
1906 proto_tree_add_item(main_tree, hf_length, tvb, offset, 1, ENC_NA);
1907 length = tvb_get_uint8(tvb, offset);
1908 offset += 1;
1909
1910 proto_tree_add_item_ret_string(main_tree, hf_firmware_revision, tvb, offset, length, ENC_NA | ENC_ASCII, pinfo->pool, &firmware);
1911 col_append_fstr(pinfo->cinfo, COL_INFO, " = %s", firmware);
1912 offset += length;
1913 }
1914 break;
1915 case 35: /* Get Hardware Board ID */
1916 proto_tree_add_item(main_tree, hf_board_id, tvb, offset, 1, ENC_NA);
1917 col_append_fstr(pinfo->cinfo, COL_INFO, " = %s", val_to_str_ext_const(tvb_get_uint8(tvb, offset), &board_id_vals_ext, "Unknown"));
1918 offset += 1;
1919
1920 break;
1921 case 37: /* Get Squelch */
1922 proto_tree_add_item(main_tree, hf_squelch, tvb, offset, 1, ENC_NA);
1923 col_append_fstr(pinfo->cinfo, COL_INFO, " = %i", tvb_get_int8(tvb, offset));
1924 offset += 1;
1925
1926 break;
1927 case 41: /* Get Clock */
1928 proto_tree_add_item(main_tree, hf_clock_ns, tvb, offset, 1, ENC_NA);
1929 col_append_fstr(pinfo->cinfo, COL_INFO, " = %u", tvb_get_uint8(tvb, offset));
1930 offset += 1;
1931
1932 break;
1933 case 43: /* Get Access Address */
1934 proto_tree_add_item(main_tree, hf_access_address, tvb, offset, 4, ENC_LITTLE_ENDIAN);
1935 col_append_fstr(pinfo->cinfo, COL_INFO, " = %08x", tvb_get_letohl(tvb, offset));
1936 offset += 4;
1937
1938 break;
1939 case 46: /* Do Something Reply */
1940 proto_tree_add_item(main_tree, hf_reserved, tvb, offset, 2, ENC_NA);
1941 offset += 2;
1942
1943 break;
1944 case 47: /* Get CRC Verify */
1945 proto_tree_add_item(main_tree, hf_crc_verify, tvb, offset, 1, ENC_NA);
1946 col_append_fstr(pinfo->cinfo, COL_INFO, " = %s", val_to_str_ext_const(tvb_get_uint8(tvb, offset), &state_vals_ext, "Unknown"));
1947 offset += 1;
1948
1949 break;
1950 case 49: /* Poll */
1951 case 59: /* Jam Mode */
1952 case 60: /* Ego */
1953 if (tvb_reported_length_remaining(tvb, offset) == 1) {
1954 proto_tree_add_item(main_tree, hf_reserved, tvb, offset, 1, ENC_NA);
1955 offset += 1;
1956 break;
1957 }
1958
1959 offset = dissect_usb_rx_packet(tree, main_tree, pinfo, tvb, offset, command_response, urb);
1960
1961 break;
1962 case 53: /* Read Register */
1963 sub_item = proto_tree_add_uint(main_tree, hf_register, tvb, offset, 0, register_id);
1964 proto_item_set_generated(sub_item);
1965 if (try_val_to_str_ext(register_id, &register_vals_ext))
1966 proto_item_append_text(sub_item, " [%s]", val_to_str_ext_const(register_id, &register_description_vals_ext, "Unknown"));
1967
1968
1969 sub_item = proto_tree_add_item(main_tree, hf_register_value, tvb, offset, 2, ENC_BIG_ENDIAN);
1970 sub_tree = proto_item_add_subtree(sub_item, ett_register_value);
1971 col_append_fstr(pinfo->cinfo, COL_INFO, " = %s: 0x%04x",
1972 val_to_str_ext_const(register_id, &register_vals_ext, "Unknown"),
1973 tvb_get_ntohs(tvb, offset));
1974
1975 dissect_cc2400_register(sub_tree, tvb, offset, register_id);
1976 offset += 2;
1977
1978 break;
1979 case 55: /* Get Compile Info */
1980 {
1981 const uint8_t* compile;
1982 proto_tree_add_item(main_tree, hf_length, tvb, offset, 1, ENC_NA);
1983 length = tvb_get_uint8(tvb, offset);
1984 offset += 1;
1985
1986 proto_tree_add_item_ret_string(main_tree, hf_firmware_compile_info, tvb, offset, length, ENC_NA | ENC_ASCII, pinfo->pool, &compile);
1987 col_append_fstr(pinfo->cinfo, COL_INFO, " = %s", compile);
1988 offset += length;
1989 }
1990 break;
1991 }
1992
1993 if (tvb_reported_length_remaining(tvb, offset) > 0) {
1994 proto_tree_add_expert(main_tree, pinfo, &ei_unknown_data, tvb, offset, -1);
1995 offset = tvb_captured_length(tvb);
1996 }
1997
1998 pinfo->p2p_dir = p2p_dir_save;
1999
2000 return offset;
2001 }
2002
2003 void
2004 proto_register_ubertooth(void)
2005 {
2006 module_t *module;
2007 expert_module_t *expert_module;
2008
2009 static hf_register_info hf[] = {
2010 { &hf_command,
2011 { "Command", "ubertooth.command",
2012 FT_UINT8, BASE_DEC | BASE_EXT_STRING, &command_vals_ext, 0x00,
2013 NULL, HFILL }
2014 },
2015 { &hf_response,
2016 { "Response", "ubertooth.response",
2017 FT_UINT8, BASE_DEC | BASE_EXT_STRING, &command_vals_ext, 0x00,
2018 NULL, HFILL }
2019 },
2020 { &hf_argument_0,
2021 { "Unused Argument 0", "ubertooth.argument.0",
2022 FT_UINT16, BASE_HEX, NULL, 0x00,
2023 NULL, HFILL }
2024 },
2025 { &hf_argument_1,
2026 { "Unused Argument 1", "ubertooth.argument.1",
2027 FT_UINT16, BASE_HEX, NULL, 0x00,
2028 NULL, HFILL }
2029 },
2030 { &hf_estimated_length,
2031 { "Estimated Length", "ubertooth.estimated_length",
2032 FT_UINT16, BASE_DEC, NULL, 0x00,
2033 NULL, HFILL }
2034 },
2035 { &hf_board_id,
2036 { "Board ID", "ubertooth.board_id",
2037 FT_UINT8, BASE_HEX | BASE_EXT_STRING, &board_id_vals_ext, 0x00,
2038 NULL, HFILL }
2039 },
2040 { &hf_reserved,
2041 { "Reserved", "ubertooth.reserved",
2042 FT_BYTES, BASE_NONE, NULL, 0x00,
2043 NULL, HFILL }
2044 },
2045 { &hf_length,
2046 { "Length", "ubertooth.length",
2047 FT_UINT8, BASE_DEC, NULL, 0x00,
2048 NULL, HFILL }
2049 },
2050 { &hf_firmware_revision,
2051 { "Firmware Revision", "ubertooth.firmware.reversion",
2052 FT_STRING, BASE_NONE, NULL, 0x00,
2053 NULL, HFILL }
2054 },
2055 { &hf_firmware_compile_info,
2056 { "Firmware Compile Info", "ubertooth.firmware.compile_info",
2057 FT_STRING, BASE_NONE, NULL, 0x00,
2058 NULL, HFILL }
2059 },
2060 { &hf_user_led,
2061 { "User LED State", "ubertooth.user_led",
2062 FT_UINT16, BASE_HEX | BASE_EXT_STRING, &led_state_vals_ext, 0x00,
2063 NULL, HFILL }
2064 },
2065 { &hf_rx_led,
2066 { "Rx LED State", "ubertooth.rx_led",
2067 FT_UINT16, BASE_HEX | BASE_EXT_STRING, &led_state_vals_ext, 0x00,
2068 NULL, HFILL }
2069 },
2070 { &hf_tx_led,
2071 { "Tx LED State", "ubertooth.tx_led",
2072 FT_UINT16, BASE_HEX | BASE_EXT_STRING, &led_state_vals_ext, 0x00,
2073 NULL, HFILL }
2074 },
2075 { &hf_1v8_led,
2076 { "1V8 LED State", "ubertooth.1v8_led",
2077 FT_UINT16, BASE_HEX | BASE_EXT_STRING, &led_state_vals_ext, 0x00,
2078 NULL, HFILL }
2079 },
2080 { &hf_channel,
2081 { "Channel", "ubertooth.channel",
2082 FT_UINT16, BASE_DEC, NULL, 0x00,
2083 NULL, HFILL }
2084 },
2085 { &hf_usb_rx_packet_channel,
2086 { "Channel", "ubertooth.usb_rx_packet.channel",
2087 FT_UINT8, BASE_DEC, NULL, 0x00,
2088 NULL, HFILL }
2089 },
2090 { &hf_serial_number,
2091 { "Serial Number", "ubertooth.serial_number",
2092 FT_BYTES, BASE_NONE, NULL, 0x00,
2093 NULL, HFILL }
2094 },
2095 { &hf_status,
2096 { "Status", "ubertooth.status",
2097 FT_UINT8, BASE_HEX, NULL, 0x00,
2098 NULL, HFILL }
2099 },
2100 { &hf_part_number,
2101 { "Part Number", "ubertooth.part_number",
2102 FT_UINT32, BASE_HEX, NULL, 0x00,
2103 NULL, HFILL }
2104 },
2105 { &hf_packet_type,
2106 { "Packet Type", "ubertooth.packet_type",
2107 FT_UINT8, BASE_HEX | BASE_EXT_STRING, &packet_type_vals_ext, 0x00,
2108 NULL, HFILL }
2109 },
2110 { &hf_state,
2111 { "State", "ubertooth.state",
2112 FT_UINT8, BASE_HEX, VALS(usb_rx_packet_state_vals), 0x00,
2113 NULL, HFILL }
2114 },
2115 { &hf_crc_init,
2116 { "CRC Init", "ubertooth.crc_init",
2117 FT_UINT24, BASE_HEX, NULL, 0x00,
2118 NULL, HFILL }
2119 },
2120 { &hf_hop_interval,
2121 { "Hop Interval", "ubertooth.hop_interval",
2122 FT_UINT16, BASE_DEC, NULL, 0x00,
2123 "Hop Interval in unit 1.25ms", HFILL }
2124 },
2125 { &hf_hop_increment,
2126 { "Hop Increment", "ubertooth.hop_increment",
2127 FT_UINT8, BASE_DEC, NULL, 0x00,
2128 NULL, HFILL }
2129 },
2130 { &hf_chip_status_reserved,
2131 { "Reserved", "ubertooth.status.reserved",
2132 FT_BOOLEAN, 8, NULL, 0xE0,
2133 NULL, HFILL }
2134 },
2135 { &hf_chip_status_rssi_trigger,
2136 { "RSSI Trigger", "ubertooth.status.rssi_trigger",
2137 FT_BOOLEAN, 8, NULL, 0x10,
2138 NULL, HFILL }
2139 },
2140 { &hf_chip_status_cs_trigger,
2141 { "CS Trigger", "ubertooth.status.cs_trigger",
2142 FT_BOOLEAN, 8, NULL, 0x08,
2143 NULL, HFILL }
2144 },
2145 { &hf_chip_status_fifo_overflow,
2146 { "FIFO Overflow", "ubertooth.status.fifo_overflow",
2147 FT_BOOLEAN, 8, NULL, 0x04,
2148 NULL, HFILL }
2149 },
2150 { &hf_chip_status_dma_error,
2151 { "DMA Error", "ubertooth.status.dma_error",
2152 FT_BOOLEAN, 8, NULL, 0x02,
2153 NULL, HFILL }
2154 },
2155 { &hf_chip_status_dma_overflow,
2156 { "DMA Overflow", "ubertooth.status.dma_overflow",
2157 FT_BOOLEAN, 8, NULL, 0x01,
2158 NULL, HFILL }
2159 },
2160 { &hf_clock_ns,
2161 { "Clock 1ns", "ubertooth.clock_ns",
2162 FT_UINT8, BASE_DEC, NULL, 0x00,
2163 NULL, HFILL }
2164 },
2165 { &hf_clock_100ns,
2166 { "Clock 100ns", "ubertooth.clock_100ns",
2167 FT_UINT32, BASE_DEC, NULL, 0x00,
2168 NULL, HFILL }
2169 },
2170 { &hf_rssi_min,
2171 { "RSSI Min", "ubertooth.rssi_min",
2172 FT_INT8, BASE_DEC, NULL, 0x00,
2173 NULL, HFILL }
2174 },
2175 { &hf_rssi_max,
2176 { "RSSI Max", "ubertooth.rssi_max",
2177 FT_INT8, BASE_DEC, NULL, 0x00,
2178 NULL, HFILL }
2179 },
2180 { &hf_rssi_avg,
2181 { "RSSI Avg", "ubertooth.rssi_avg",
2182 FT_INT8, BASE_DEC, NULL, 0x00,
2183 NULL, HFILL }
2184 },
2185 { &hf_rssi_count,
2186 { "RSSI Count", "ubertooth.rssi_count",
2187 FT_UINT8, BASE_DEC, NULL, 0x00,
2188 NULL, HFILL }
2189 },
2190 { &hf_paen,
2191 { "PAEN", "ubertooth.paen",
2192 FT_UINT16, BASE_HEX | BASE_EXT_STRING, &state_vals_ext, 0x00,
2193 NULL, HFILL }
2194 },
2195 { &hf_hgm,
2196 { "HGM", "ubertooth.hgm",
2197 FT_UINT16, BASE_HEX | BASE_EXT_STRING, &state_vals_ext, 0x00,
2198 NULL, HFILL }
2199 },
2200 { &hf_crc_verify,
2201 { "CRC Verify", "ubertooth.crc_verify",
2202 FT_UINT16, BASE_HEX | BASE_EXT_STRING, &state_vals_ext, 0x00,
2203 NULL, HFILL }
2204 },
2205 { &hf_modulation,
2206 { "Modulation", "ubertooth.modulation",
2207 FT_UINT16, BASE_HEX | BASE_EXT_STRING, &modulation_vals_ext, 0x00,
2208 NULL, HFILL }
2209 },
2210 { &hf_power_amplifier_reserved,
2211 { "Reserved", "ubertooth.power_amplifier.reserved",
2212 FT_UINT8, BASE_HEX, NULL, 0xF8,
2213 NULL, HFILL }
2214 },
2215 { &hf_power_amplifier_level,
2216 { "Level", "ubertooth.power_amplifier.level",
2217 FT_UINT8, BASE_DEC, NULL, 0x07,
2218 NULL, HFILL }
2219 },
2220 { &hf_range_test_valid,
2221 { "Valid", "ubertooth.range_test.valid",
2222 FT_UINT8, BASE_DEC, NULL, 0x00,
2223 NULL, HFILL }
2224 },
2225 { &hf_range_test_request_power_amplifier,
2226 { "Request Power Amplifier", "ubertooth.range_test.request_power_amplifier",
2227 FT_UINT8, BASE_DEC, NULL, 0x00,
2228 NULL, HFILL }
2229 },
2230 { &hf_range_test_request_number,
2231 { "Request Power Amplifier", "ubertooth.range_test.request_number",
2232 FT_UINT8, BASE_DEC, NULL, 0x00,
2233 NULL, HFILL }
2234 },
2235 { &hf_range_test_reply_power_amplifier,
2236 { "Request Power Amplifier", "ubertooth.range_test.reply_power_amplifier",
2237 FT_UINT8, BASE_DEC, NULL, 0x00,
2238 NULL, HFILL }
2239 },
2240 { &hf_range_test_reply_number,
2241 { "Reply Power Amplifier", "ubertooth.range_test.reply_number",
2242 FT_UINT8, BASE_DEC, NULL, 0x00,
2243 NULL, HFILL }
2244 },
2245 { &hf_squelch,
2246 { "Squelch", "ubertooth.squelch",
2247 FT_INT16, BASE_DEC, NULL, 0x00,
2248 NULL, HFILL }
2249 },
2250 { &hf_access_address,
2251 { "Access Address", "ubertooth.access_address",
2252 FT_UINT32, BASE_HEX, NULL, 0x00,
2253 NULL, HFILL }
2254 },
2255 { &hf_jam_mode,
2256 { "Jam Mode", "ubertooth.jam_mode",
2257 FT_UINT16, BASE_HEX, VALS(jam_mode_vals), 0x00,
2258 NULL, HFILL }
2259 },
2260 { &hf_ego_mode,
2261 { "Ego Mode", "ubertooth.ego_mode",
2262 FT_UINT16, BASE_HEX, VALS(ego_mode_vals), 0x00,
2263 NULL, HFILL }
2264 },
2265 { &hf_register,
2266 { "Register", "ubertooth.register",
2267 FT_UINT16, BASE_HEX | BASE_EXT_STRING, &register_vals_ext, 0x00,
2268 NULL, HFILL }
2269 },
2270 { &hf_register_value,
2271 { "Register Value", "ubertooth.register.value",
2272 FT_UINT16, BASE_HEX, NULL, 0x00,
2273 NULL, HFILL }
2274 },
2275 { &hf_low_frequency,
2276 { "Low Frequency", "ubertooth.low_frequency",
2277 FT_UINT16, BASE_DEC, NULL, 0x00,
2278 NULL, HFILL }
2279 },
2280 { &hf_high_frequency,
2281 { "High Frequency", "ubertooth.high_frequency",
2282 FT_UINT16, BASE_DEC, NULL, 0x00,
2283 NULL, HFILL }
2284 },
2285 { &hf_rx_packets,
2286 { "Rx Packets", "ubertooth.rx_packets",
2287 FT_UINT16, BASE_DEC, NULL, 0x00,
2288 NULL, HFILL }
2289 },
2290 { &hf_rssi_threshold,
2291 { "RSSI Threshold", "ubertooth.rssi_threshold",
2292 FT_INT16, BASE_DEC, NULL, 0x00,
2293 NULL, HFILL }
2294 },
2295 { &hf_clock_offset,
2296 { "Clock Offset", "ubertooth.clock_offset",
2297 FT_UINT32, BASE_DEC, NULL, 0x00,
2298 NULL, HFILL }
2299 },
2300 { &hf_afh_map,
2301 { "AFH Map", "ubertooth.afh_map",
2302 FT_BYTES, BASE_NONE, NULL, 0x00,
2303 NULL, HFILL }
2304 },
2305 { &hf_bdaddr,
2306 { "BD_ADDR", "ubertooth.bd_addr",
2307 FT_ETHER, BASE_NONE, NULL, 0x0,
2308 "Bluetooth Device Address", HFILL}
2309 },
2310 { &hf_usb_rx_packet,
2311 { "USB Rx Packet", "ubertooth.usb_rx_packet",
2312 FT_NONE, BASE_NONE, NULL, 0x00,
2313 NULL, HFILL }
2314 },
2315 { &hf_spectrum_entry,
2316 { "Spectrum Entry", "ubertooth.spectrum_entry",
2317 FT_NONE, BASE_NONE, NULL, 0x00,
2318 NULL, HFILL }
2319 },
2320 { &hf_frequency,
2321 { "Frequency", "ubertooth.spectrum_entry.frequency",
2322 FT_UINT16, BASE_DEC, NULL, 0x00,
2323 NULL, HFILL }
2324 },
2325 { &hf_rssi,
2326 { "RSSI", "ubertooth.spectrum_entry.rssi",
2327 FT_INT8, BASE_DEC, NULL, 0x00,
2328 NULL, HFILL }
2329 },
2330 { &hf_data,
2331 { "Data", "ubertooth.data",
2332 FT_NONE, BASE_NONE, NULL, 0x00,
2333 NULL, HFILL }
2334 },
2335 { &hf_cc2400_value,
2336 { "Value", "ubertooth.register.value",
2337 FT_UINT16, BASE_HEX_DEC, NULL, 0xFFFF,
2338 NULL, HFILL }
2339 },
2340 { &hf_cc2400_syncl,
2341 { "Synchronisation Word, lower 16 bit", "ubertooth.register.value.syncl",
2342 FT_UINT16, BASE_HEX, NULL, 0x00,
2343 NULL, HFILL }
2344 },
2345 { &hf_cc2400_synch,
2346 { "Synchronisation Word, upper 16 bit", "ubertooth.register.value.synch",
2347 FT_UINT16, BASE_HEX, NULL, 0x00,
2348 NULL, HFILL }
2349 },
2350 { &hf_cc2400_reserved_0x2B_res_15_14,
2351 { "Reserved [15:14]", "ubertooth.register.value.reserved.0x2B.15_14",
2352 FT_UINT16, BASE_DEC, NULL, 0xC000,
2353 NULL, HFILL }
2354 },
2355 { &hf_cc2400_reserved_0x2B_res_13,
2356 { "Reserved [13]", "ubertooth.register.value.reserved.0x2B.13",
2357 FT_BOOLEAN, 16, NULL, 0x2000,
2358 NULL, HFILL }
2359 },
2360 { &hf_cc2400_reserved_0x2B_res_12,
2361 { "Reserved [12]", "ubertooth.register.value.reserved.0x2B.12",
2362 FT_BOOLEAN, 16, NULL, 0x1000,
2363 NULL, HFILL }
2364 },
2365 { &hf_cc2400_reserved_0x2B_res_11_0,
2366 { "Reserved [11:0]", "ubertooth.register.value.reserved.0x2B.11_0",
2367 FT_UINT16, BASE_DEC, NULL, 0x0FFF,
2368 NULL, HFILL }
2369 },
2370 { &hf_cc2400_reserved_0x2A_res_15_11,
2371 { "Reserved [15:11]", "ubertooth.register.value.reserved.0x2A.15_11",
2372 FT_UINT16, BASE_DEC, NULL, 0xF800,
2373 NULL, HFILL }
2374 },
2375 { &hf_cc2400_reserved_0x2A_res_10,
2376 { "Reserved [10]", "ubertooth.register.value.reserved.0x2A.10",
2377 FT_BOOLEAN, 16, NULL, 0x0400,
2378 NULL, HFILL }
2379 },
2380 { &hf_cc2400_reserved_0x2A_res_9_0,
2381 { "Reserved [9:0]", "ubertooth.register.value.reserved.0x2A.9_0",
2382 FT_UINT16, BASE_DEC, NULL, 0x03FF,
2383 NULL, HFILL }
2384 },
2385 { &hf_cc2400_reserved_0x29_res_15_8,
2386 { "Reserved [15:8]", "ubertooth.register.value.reserved.0x29.15_8",
2387 FT_UINT16, BASE_DEC, NULL, 0xFF00,
2388 NULL, HFILL }
2389 },
2390 { &hf_cc2400_reserved_0x29_res_7_3,
2391 { "Reserved [7:3]", "ubertooth.register.value.reserved.0x29.7_3",
2392 FT_UINT16, BASE_DEC, NULL, 0x00F8,
2393 NULL, HFILL }
2394 },
2395 { &hf_cc2400_reserved_0x29_res_2_0,
2396 { "Reserved [2:0]", "ubertooth.register.value.reserved.0x29.2_0",
2397 FT_UINT16, BASE_DEC, NULL, 0x0007,
2398 NULL, HFILL }
2399 },
2400 { &hf_cc2400_reserved_0x28_res_15,
2401 { "Reserved [15]", "ubertooth.register.value.reserved.0x28.15",
2402 FT_BOOLEAN, 16, NULL, 0x8000,
2403 NULL, HFILL }
2404 },
2405 { &hf_cc2400_reserved_0x28_res_14_13,
2406 { "Reserved [14:13]", "ubertooth.register.value.reserved.0x28.14_13",
2407 FT_UINT16, BASE_DEC, NULL, 0x6000,
2408 NULL, HFILL }
2409 },
2410 { &hf_cc2400_reserved_0x28_res_12_7,
2411 { "Reserved [12:7]", "ubertooth.register.value.reserved.0x28.12_7",
2412 FT_UINT16, BASE_DEC, NULL, 0x1F80,
2413 NULL, HFILL }
2414 },
2415 { &hf_cc2400_reserved_0x28_res_6_0,
2416 { "Reserved [6:0]", "ubertooth.register.value.reserved.0x28.6_0",
2417 FT_UINT16, BASE_DEC, NULL, 0x007F,
2418 NULL, HFILL }
2419 },
2420 { &hf_cc2400_reserved_0x27_res_15_8,
2421 { "Reserved [15:8]", "ubertooth.register.value.reserved.0x27.15_8",
2422 FT_UINT16, BASE_DEC, NULL, 0xFF00,
2423 NULL, HFILL }
2424 },
2425 { &hf_cc2400_reserved_0x27_res_7_3,
2426 { "Reserved [7:3]", "ubertooth.register.value.reserved.0x27.7_3",
2427 FT_UINT16, BASE_DEC, NULL, 0x00F8,
2428 NULL, HFILL }
2429 },
2430 { &hf_cc2400_reserved_0x27_res_2_0,
2431 { "Reserved [2:0]", "ubertooth.register.value.reserved.0x27.2_0",
2432 FT_UINT16, BASE_DEC, NULL, 0x0007,
2433 NULL, HFILL }
2434 },
2435 { &hf_cc2400_reserved_0x26_res_15_10,
2436 { "Reserved [15:10]", "ubertooth.register.value.reserved.0x26.15_10",
2437 FT_UINT16, BASE_DEC, NULL, 0xFC00,
2438 NULL, HFILL }
2439 },
2440 { &hf_cc2400_reserved_0x26_res_9_0,
2441 { "Reserved [9:0]", "ubertooth.register.value.reserved.0x26.9_0",
2442 FT_UINT16, BASE_DEC, NULL, 0x03FF,
2443 NULL, HFILL }
2444 },
2445
2446 { &hf_cc2400_reserved_0x25_res_15_12,
2447 { "Reserved [15:12]", "ubertooth.register.value.reserved.0x25.15_12",
2448 FT_UINT16, BASE_DEC, NULL, 0xF000,
2449 NULL, HFILL }
2450 },
2451 { &hf_cc2400_reserved_0x25_res_11_0,
2452 { "Reserved [11:0]", "ubertooth.register.value.reserved.0x25.11_0",
2453 FT_UINT16, BASE_DEC, NULL, 0x0FFF,
2454 NULL, HFILL }
2455 },
2456 { &hf_cc2400_reserved_0x24_res_15_14,
2457 { "Reserved [15:14]", "ubertooth.register.value.reserved.0x24.15_14",
2458 FT_UINT16, BASE_DEC, NULL, 0xC000,
2459 NULL, HFILL }
2460 },
2461 { &hf_cc2400_reserved_0x24_res_13_10,
2462 { "Reserved [13:10]", "ubertooth.register.value.reserved.0x24.13_10",
2463 FT_UINT16, BASE_DEC, NULL, 0x3C00,
2464 NULL, HFILL }
2465 },
2466 { &hf_cc2400_reserved_0x24_res_9_7,
2467 { "Reserved [9:7]", "ubertooth.register.value.reserved.0x24.9_7",
2468 FT_UINT16, BASE_DEC, NULL, 0x0380,
2469 NULL, HFILL }
2470 },
2471 { &hf_cc2400_reserved_0x24_res_6_0,
2472 { "Reserved [6:0]", "ubertooth.register.value.reserved.0x24.6_0",
2473 FT_UINT16, BASE_DEC, NULL, 0x007F,
2474 NULL, HFILL }
2475 },
2476 { &hf_cc2400_int_reserved_15_8,
2477 { "Reserved [15:8]", "ubertooth.register.value.int.reserved.15_8",
2478 FT_UINT16, BASE_DEC, NULL, 0xFF00,
2479 NULL, HFILL }
2480 },
2481 { &hf_cc2400_int_reserved_7,
2482 { "Reserved [7]", "ubertooth.register.value.int.reserved.7",
2483 FT_BOOLEAN, 16, NULL, 0x0080,
2484 NULL, HFILL }
2485 },
2486 { &hf_cc2400_int_pkt_polarity,
2487 { "PKT Polarity", "ubertooth.register.value.int.pkt_polarity",
2488 FT_BOOLEAN, 16, NULL, 0x0040,
2489 NULL, HFILL }
2490 },
2491 { &hf_cc2400_int_fifo_polarity,
2492 { "FIFO Polarity", "ubertooth.register.value.int.fifo_polarity",
2493 FT_BOOLEAN, 16, NULL, 0x0020,
2494 NULL, HFILL }
2495 },
2496 { &hf_cc2400_int_fifo_threshold,
2497 { "FIFO Threshold", "ubertooth.register.value.int.fifo_threshold",
2498 FT_UINT16, BASE_DEC, NULL, 0x001F,
2499 NULL, HFILL }
2500 },
2501 { &hf_cc2400_main_resetn,
2502 { "Reset N", "ubertooth.register.value.main.resetn",
2503 FT_BOOLEAN, 16, NULL, 0x8000,
2504 NULL, HFILL }
2505 },
2506 { &hf_cc2400_main_reserved_14_10,
2507 { "Reserved [14:10]", "ubertooth.register.value.main.reserved.14_10",
2508 FT_UINT16, BASE_DEC, NULL, 0x7C00,
2509 NULL, HFILL }
2510 },
2511 { &hf_cc2400_main_fs_force_en,
2512 { "Forces Frequency Synthesiser", "ubertooth.register.value.main.fs_force_en",
2513 FT_BOOLEAN, 16, NULL, 0x0200,
2514 NULL, HFILL }
2515 },
2516 { &hf_cc2400_main_rxn_tx,
2517 { "RxN Tx", "ubertooth.register.value.main.rxn_tx",
2518 FT_BOOLEAN, 16, NULL, 0x0100,
2519 NULL, HFILL }
2520 },
2521 { &hf_cc2400_main_reserved_7_4,
2522 { "Reserved [7:4]", "ubertooth.register.value.main.reserved.7_4",
2523 FT_UINT16, BASE_DEC, NULL, 0x00F0,
2524 NULL, HFILL }
2525 },
2526 { &hf_cc2400_main_reserved_3,
2527 { "Reserved [3]", "ubertooth.register.value.main.reserved.3",
2528 FT_BOOLEAN, 16, NULL, 0x0008,
2529 NULL, HFILL }
2530 },
2531 { &hf_cc2400_main_reserved_2,
2532 { "Reserved [2]", "ubertooth.register.value.main.reserved.2",
2533 FT_BOOLEAN, 16, NULL, 0x0004,
2534 NULL, HFILL }
2535 },
2536 { &hf_cc2400_main_xosc16m_bypass,
2537 { "Bypass 16 MHz Crystal Oscillator", "ubertooth.register.value.main.xosc16m_bypass",
2538 FT_BOOLEAN, 16, NULL, 0x0002,
2539 NULL, HFILL }
2540 },
2541 { &hf_cc2400_main_xosc16m_en,
2542 { "Force 16 MHz Crystal Oscillator", "ubertooth.register.value.main.xosc16m_en",
2543 FT_BOOLEAN, 16, NULL, 0x0001,
2544 NULL, HFILL }
2545 },
2546 { &hf_cc2400_fsctrl_reserved,
2547 { "Reserved [15:6]", "ubertooth.register.value.fsctrl.reserved.15_6",
2548 FT_UINT16, BASE_DEC, NULL, 0xFFC0,
2549 NULL, HFILL }
2550 },
2551 { &hf_cc2400_fsctrl_lock_threshold,
2552 { "Lock Threshold", "ubertooth.register.value.fsctrl.lock_threshold",
2553 FT_UINT16, BASE_DEC | BASE_EXT_STRING, &cc2400_fsctlr_lock_threshold_vals_ext, 0x0030,
2554 NULL, HFILL }
2555 },
2556 { &hf_cc2400_fsctrl_cal_done,
2557 { "Calibration Done", "ubertooth.register.value.fsctrl.cal_done",
2558 FT_BOOLEAN, 16, NULL, 0x0008,
2559 NULL, HFILL }
2560 },
2561 { &hf_cc2400_fsctrl_cal_running,
2562 { "Calibration Running", "ubertooth.register.value.fsctrl.cal_running",
2563 FT_BOOLEAN, 16, NULL, 0x0004,
2564 NULL, HFILL }
2565 },
2566 { &hf_cc2400_fsctrl_lock_length,
2567 { "Lock Length", "ubertooth.register.value.fsctrl.lock_length",
2568 FT_UINT16, BASE_DEC | BASE_EXT_STRING, &cc2400_fsctlr_lock_length_vals_ext, 0x0002,
2569 NULL, HFILL }
2570 },
2571 { &hf_cc2400_fsctrl_lock_status,
2572 { "PLL Lock Status", "ubertooth.register.value.fsctrl.lock_status",
2573 FT_BOOLEAN, 16, NULL, 0x0001,
2574 NULL, HFILL }
2575 },
2576 { &hf_cc2400_fsdiv_reserved,
2577 { "Reserved [15:12]", "ubertooth.register.value.fsdiv.reserved.15_12",
2578 FT_UINT16, BASE_DEC, NULL, 0xF000,
2579 NULL, HFILL }
2580 },
2581 { &hf_cc2400_fsdiv_frequency,
2582 { "Frequency", "ubertooth.register.value.fsdiv.frequency",
2583 FT_UINT16, BASE_DEC, NULL, 0x0FFF,
2584 NULL, HFILL }
2585 },
2586 { &hf_cc2400_fsdiv_freq_high,
2587 { "Frequency High Part", "ubertooth.register.value.fsdiv.frequency.high",
2588 FT_UINT16, BASE_DEC, NULL, 0x0C00,
2589 NULL, HFILL }
2590 },
2591 { &hf_cc2400_fsdiv_freq,
2592 { "Frequency Lower Part", "ubertooth.register.value.fsdiv.frequency.low",
2593 FT_UINT16, BASE_DEC, NULL, 0x03FF,
2594 NULL, HFILL }
2595 },
2596 { &hf_cc2400_mdmctrl_reserved,
2597 { "Reserved [15:13]", "ubertooth.register.value.mdmctrl.reserved.15_13",
2598 FT_UINT16, BASE_DEC, NULL, 0xE000,
2599 NULL, HFILL }
2600 },
2601 { &hf_cc2400_mdmctrl_mod_offset,
2602 { "Modulator Offset", "ubertooth.register.value.mdmctrl.mod_offset",
2603 FT_UINT16, BASE_DEC, NULL, 0x1F80,
2604 NULL, HFILL }
2605 },
2606 { &hf_cc2400_mdmctrl_mod_dev,
2607 { "Modulator Deviation", "ubertooth.register.value.mdmctrl.mod_dev",
2608 FT_UINT16, BASE_DEC, NULL, 0x007F,
2609 NULL, HFILL }
2610 },
2611 { &hf_cc2400_agcctrl_vga_gain,
2612 { "VGA Gain", "ubertooth.register.value.agcctrl.vga_gain",
2613 FT_UINT16, BASE_HEX, NULL, 0xFF00,
2614 NULL, HFILL }
2615 },
2616 { &hf_cc2400_agcctrl_reserved,
2617 { "Reserved [7:4]", "ubertooth.register.value.agcctrl.reserved.7_4",
2618 FT_UINT16, BASE_DEC, NULL, 0x00F0,
2619 NULL, HFILL }
2620 },
2621 { &hf_cc2400_agcctrl_agc_locked,
2622 { "AGC Locked", "ubertooth.register.value.agcctrl.agc_locked",
2623 FT_BOOLEAN, 16, NULL, 0x0008,
2624 NULL, HFILL }
2625 },
2626 { &hf_cc2400_agcctrl_agc_lock,
2627 { "AGC Lock", "ubertooth.register.value.agcctrl.agc_lock",
2628 FT_BOOLEAN, 16, NULL, 0x0004,
2629 NULL, HFILL }
2630 },
2631 { &hf_cc2400_agcctrl_agc_sync_lock,
2632 { "AGC Sync Lock", "ubertooth.register.value.agcctrl.agc_sync_lock",
2633 FT_BOOLEAN, 16, NULL, 0x0002,
2634 NULL, HFILL }
2635 },
2636 { &hf_cc2400_agcctrl_vga_gain_oe,
2637 { "VGA Gain Override Enable", "ubertooth.register.value.agcctrl.vga_gain_oe",
2638 FT_BOOLEAN, 16, NULL, 0x0001,
2639 NULL, HFILL }
2640 },
2641 { &hf_cc2400_frend_reserved_15_4,
2642 { "Reserved [15:4]", "ubertooth.register.value.frend.reserved.15_4",
2643 FT_UINT16, BASE_DEC, NULL, 0xFFF0,
2644 NULL, HFILL }
2645 },
2646 { &hf_cc2400_frend_reserved_3,
2647 { "Reserved [3]", "ubertooth.register.value.frend.reserved.3",
2648 FT_BOOLEAN, 16, NULL, 0x0008,
2649 NULL, HFILL }
2650 },
2651 { &hf_cc2400_frend_pa_level,
2652 { "Power Amplifier Level", "ubertooth.register.value.frend.pa_level",
2653 FT_UINT16, BASE_DEC, NULL, 0x0007,
2654 NULL, HFILL }
2655 },
2656 { &hf_cc2400_rssi_rssi_val,
2657 { "Average RSSI Value", "ubertooth.register.value.rssi.rssi_val",
2658 FT_INT16, BASE_DEC, NULL, 0xFF00,
2659 NULL, HFILL }
2660 },
2661 { &hf_cc2400_rssi_rssi_cs_thres,
2662 { "RSSI Carrier Sense Threshold", "ubertooth.register.value.rssi.rssi_cs_thres",
2663 FT_INT16, BASE_DEC, NULL, 0x00FC,
2664 NULL, HFILL }
2665 },
2666 { &hf_cc2400_rssi_rssi_filt,
2667 { "RSSI Averaging Filter Length", "ubertooth.register.value.rssi.rssi_filt",
2668 FT_UINT16, BASE_DEC | BASE_EXT_STRING, &cc2400_rssi_rssi_filt_vals_ext, 0x0003,
2669 NULL, HFILL }
2670 },
2671 { &hf_cc2400_freqest_rx_freq_offset,
2672 { "Rx Frequency Offset", "ubertooth.register.value.freqest.rx_freq_offset",
2673 FT_INT16, BASE_DEC, NULL, 0xFF00,
2674 NULL, HFILL }
2675 },
2676 { &hf_cc2400_freqest_reserved,
2677 { "Reserved [7:0]", "ubertooth.register.value.freqest.reserved.7_0",
2678 FT_UINT16, BASE_DEC, NULL, 0x00FF,
2679 NULL, HFILL }
2680 },
2681 { &hf_cc2400_iocfg_reserved,
2682 { "Reserved [15]", "ubertooth.register.value.iocfg.reserved.15",
2683 FT_BOOLEAN, 16, NULL, 0x8000,
2684 NULL, HFILL }
2685 },
2686 { &hf_cc2400_iocfg_gio6_cfg,
2687 { "GIO6 Configuration", "ubertooth.register.value.iocfg.gio6_cfg",
2688 FT_UINT16, BASE_DEC, NULL, 0x7E00,
2689 NULL, HFILL }
2690 },
2691 { &hf_cc2400_iocfg_gio1_cfg,
2692 { "GIO1 Configuration", "ubertooth.register.value.iocfg.gio1_cfg",
2693 FT_UINT16, BASE_DEC, NULL, 0x01F8,
2694 NULL, HFILL }
2695 },
2696 { &hf_cc2400_iocfg_hssd_src,
2697 { "High Speed Serial Data Source", "ubertooth.register.value.iocfg.hssd_src",
2698 FT_UINT16, BASE_DEC | BASE_EXT_STRING, &cc2400_iocfg_hssd_src_vals_ext, 0x0007,
2699 NULL, HFILL }
2700 },
2701 { &hf_cc2400_fsmtc_tc_rxon2agcen,
2702 { "Rx On to AGC Enabled", "ubertooth.register.value.fsmtc.tc_rxon2agcen",
2703 FT_UINT16, BASE_DEC, NULL, 0xE000,
2704 NULL, HFILL }
2705 },
2706 { &hf_cc2400_fsmtc_tc_paon2switch,
2707 { "Power Amplifier On to Switch", "ubertooth.register.value.fsmtc.tc_paon2switch",
2708 FT_UINT16, BASE_DEC, NULL, 0x1C00,
2709 NULL, HFILL }
2710 },
2711 { &hf_cc2400_fsmtc_res,
2712 { "Reserved [9:6]", "ubertooth.register.value.fsmtc.reserved.9_6",
2713 FT_UINT16, BASE_DEC, NULL, 0x03C0,
2714 NULL, HFILL }
2715 },
2716 { &hf_cc2400_fsmtc_tc_txend2switch,
2717 { "Tx End to Switch", "ubertooth.register.value.fsmtc.tc_txend2switch",
2718 FT_UINT16, BASE_DEC, NULL, 0x0038,
2719 NULL, HFILL }
2720 },
2721 { &hf_cc2400_fsmtc_tc_txend2paoff,
2722 { "Tx End to Power Amplifier Off", "ubertooth.register.value.fsmtc.tc_txend2paoff",
2723 FT_UINT16, BASE_DEC, NULL, 0x0007,
2724 NULL, HFILL }
2725 },
2726 { &hf_cc2400_reserved_0x0C_res_15_5,
2727 { "Reserved [15:5]", "ubertooth.register.value.reserved.0x0C.15_5",
2728 FT_UINT16, BASE_DEC, NULL, 0xFFE0,
2729 NULL, HFILL }
2730 },
2731 { &hf_cc2400_reserved_0x0C_res_4_0,
2732 { "Reserved [4:0]", "ubertooth.register.value.reserved.0x0C.4_0",
2733 FT_UINT16, BASE_DEC, NULL, 0x001F,
2734 NULL, HFILL }
2735 },
2736 { &hf_cc2400_manand_vga_reset_n,
2737 { "No VGA Reset", "ubertooth.register.value.manand.vga_reset_n",
2738 FT_BOOLEAN, 16, NULL, 0x8000,
2739 NULL, HFILL }
2740 },
2741 { &hf_cc2400_manand_lock_status,
2742 { "Lock Status", "ubertooth.register.value.manand.lock_status",
2743 FT_BOOLEAN, 16, NULL, 0x4000,
2744 NULL, HFILL }
2745 },
2746 { &hf_cc2400_manand_balun_ctrl,
2747 { "Balun Control", "ubertooth.register.value.manand.balun_ctrl",
2748 FT_BOOLEAN, 16, NULL, 0x2000,
2749 NULL, HFILL }
2750 },
2751 { &hf_cc2400_manand_rxtx,
2752 { "RxTx", "ubertooth.register.value.manand.rxtx",
2753 FT_BOOLEAN, 16, NULL, 0x1000,
2754 NULL, HFILL }
2755 },
2756 { &hf_cc2400_manand_pre_pd,
2757 { "Power Down of Prescaler", "ubertooth.register.value.manand.pre_pd",
2758 FT_BOOLEAN, 16, NULL, 0x0800,
2759 NULL, HFILL }
2760 },
2761 { &hf_cc2400_manand_pa_n_pd,
2762 { "Power Down of Power Amplifier (negative path)", "ubertooth.register.value.manand.pa_n_pd",
2763 FT_BOOLEAN, 16, NULL, 0x0400,
2764 NULL, HFILL }
2765 },
2766 { &hf_cc2400_manand_pa_p_pd,
2767 { "Power Down of Power Amplifier (positive path)", "ubertooth.register.value.manand.pa_p_pd",
2768 FT_BOOLEAN, 16, NULL, 0x0200,
2769 NULL, HFILL }
2770 },
2771 { &hf_cc2400_manand_dac_lpf_pd,
2772 { "Power Down of Tx DAC", "ubertooth.register.value.manand.dac_lpf_pd",
2773 FT_BOOLEAN, 16, NULL, 0x0100,
2774 NULL, HFILL }
2775 },
2776 { &hf_cc2400_manand_bias_pd,
2777 { "Power Down control of global bias generator + XOSC clock buffer", "ubertooth.register.value.manand.bias_pd",
2778 FT_BOOLEAN, 16, NULL, 0x0080,
2779 NULL, HFILL }
2780 },
2781 { &hf_cc2400_manand_xosc16m_pd,
2782 { "Power Down control of 16 MHz XOSC core", "ubertooth.register.value.manand.xosc16m_pd",
2783 FT_BOOLEAN, 16, NULL, 0x0040,
2784 NULL, HFILL }
2785 },
2786 { &hf_cc2400_manand_chp_pd,
2787 { "Power Down control of Charge Pump", "ubertooth.register.value.manand.chp_pd",
2788 FT_BOOLEAN, 16, NULL, 0x0020,
2789 NULL, HFILL }
2790 },
2791 { &hf_cc2400_manand_fs_pd,
2792 { "Power Down control of VCO, I/Q generator, LO buffers", "ubertooth.register.value.manand.fs_pd",
2793 FT_BOOLEAN, 16, NULL, 0x0010,
2794 NULL, HFILL }
2795 },
2796 { &hf_cc2400_manand_adc_pd,
2797 { "Power Down control of the ADC", "ubertooth.register.value.manand.adc_pd",
2798 FT_BOOLEAN, 16, NULL, 0x0008,
2799 NULL, HFILL }
2800 },
2801 { &hf_cc2400_manand_vga_pd,
2802 { "Power Down control of the VGA", "ubertooth.register.value.manand.vga_pd",
2803 FT_BOOLEAN, 16, NULL, 0x0004,
2804 NULL, HFILL }
2805 },
2806 { &hf_cc2400_manand_rxbpf_pd,
2807 { "Power Down control of complex band-pass receive filter", "ubertooth.register.value.manand.rxbpf_pd",
2808 FT_BOOLEAN, 16, NULL, 0x0002,
2809 NULL, HFILL }
2810 },
2811 { &hf_cc2400_manand_lnamix_pd,
2812 { "Power Down control of LNA, down-conversion mixers and front-end bias", "ubertooth.register.value.manand.lnamix_pd",
2813 FT_BOOLEAN, 16, NULL, 0x0001,
2814 NULL, HFILL }
2815 },
2816 { &hf_cc2400_fsmstate_reserved_15_13,
2817 { "Reserved [15:13]", "ubertooth.register.value.fsmstate.reserved.15_13",
2818 FT_UINT16, BASE_DEC, NULL, 0xE000,
2819 NULL, HFILL }
2820 },
2821 { &hf_cc2400_fsmstate_fsm_state_bkpt,
2822 { "FSM breakpoint state", "ubertooth.register.value.fsmstate.fsm_state_bkpt",
2823 FT_UINT16, BASE_DEC, NULL, 0x1F00,
2824 NULL, HFILL }
2825 },
2826 { &hf_cc2400_fsmstate_reserved_7_5,
2827 { "Reserved [7:5]", "ubertooth.register.value.fsmstate.reserved.7_5",
2828 FT_UINT16, BASE_DEC, NULL, 0x00E0,
2829 NULL, HFILL }
2830 },
2831 { &hf_cc2400_fsmstate_fsm_cur_state,
2832 { "Current state of the finite state machine", "ubertooth.register.value.fsmstate.fsm_cur_state",
2833 FT_UINT16, BASE_DEC, NULL, 0x001F,
2834 NULL, HFILL }
2835 },
2836 { &hf_cc2400_adctst_reserved_15,
2837 { "Reserved [15]", "ubertooth.register.value.adctst.reserved.15",
2838 FT_BOOLEAN, 16, NULL, 0x8000,
2839 NULL, HFILL }
2840 },
2841 { &hf_cc2400_adctst_adc_i,
2842 { "Current ADC I-branch value", "ubertooth.register.value.adctst.adc_i",
2843 FT_UINT16, BASE_DEC, NULL, 0x7F00,
2844 NULL, HFILL }
2845 },
2846 { &hf_cc2400_adctst_reserved_7,
2847 { "Reserved [7]", "ubertooth.register.value.adctst.reserved.7",
2848 FT_BOOLEAN, 16, NULL, 0x0080,
2849 NULL, HFILL }
2850 },
2851 { &hf_cc2400_adctst_adc_q,
2852 { "Current ADC Q-branch value", "ubertooth.register.value.adctst.adc_q",
2853 FT_UINT16, BASE_DEC, NULL, 0x007F,
2854 NULL, HFILL }
2855 },
2856 { &hf_cc2400_rxbpftst_reserved,
2857 { "Reserved [15]", "ubertooth.register.value.rxbpftst.reserved.15",
2858 FT_BOOLEAN, 16, NULL, 0x8000,
2859 NULL, HFILL }
2860 },
2861 { &hf_cc2400_rxbpftst_rxbpf_cap_oe,
2862 { "RX band-pass filter capacitance calibration override enable", "ubertooth.register.value.rxbpftst.rxbpf_cap_oe",
2863 FT_BOOLEAN, 16, NULL, 0x4000,
2864 NULL, HFILL }
2865 },
2866 { &hf_cc2400_rxbpftst_rxbpf_cap_o,
2867 { "RX band-pass filter capacitance calibration override value", "ubertooth.register.value.rxbpftst.rxbpf_cap_o",
2868 FT_UINT16, BASE_DEC, NULL, 0x3F80,
2869 NULL, HFILL }
2870 },
2871 { &hf_cc2400_rxbpftst_rxbpf_cap_res,
2872 { "RX band-pass filter capacitance calibration result", "ubertooth.register.value.rxbpftst.rxbpf_cap_res",
2873 FT_UINT16, BASE_DEC, NULL, 0x007F,
2874 NULL, HFILL }
2875 },
2876 { &hf_cc2400_pamtst_reserved_15_13,
2877 { "Reserved [15:13]", "ubertooth.register.value.pamtst.reserved.15_13",
2878 FT_UINT16, BASE_DEC, NULL, 0xE000,
2879 NULL, HFILL }
2880 },
2881 { &hf_cc2400_pamtst_vc_in_test_en,
2882 { "VC in Test En", "ubertooth.register.value.pamtst.vc_in_test_en",
2883 FT_BOOLEAN, 16, NULL, 0x1000,
2884 NULL, HFILL }
2885 },
2886 { &hf_cc2400_pamtst_atestmod_pd,
2887 { "Power down of the analog test module", "ubertooth.register.value.pamtst.atestmod_pd",
2888 FT_BOOLEAN, 16, NULL, 0x0800,
2889 NULL, HFILL }
2890 },
2891 { &hf_cc2400_pamtst_atestmod_mode,
2892 { "Function of the Analog Test Module", "ubertooth.register.value.pamtst.atestmod_mode",
2893 FT_UINT16, BASE_DEC | BASE_EXT_STRING, &cc2400_pamtst_atestmod_mode_vals_ext, 0x0700,
2894 NULL, HFILL }
2895 },
2896 { &hf_cc2400_pamtst_reserved_7,
2897 { "Reserved [7]", "ubertooth.register.value.pamtst.reserved.7",
2898 FT_BOOLEAN, 16, NULL, 0x0080,
2899 NULL, HFILL }
2900 },
2901 { &hf_cc2400_pamtst_txmix_cap_array,
2902 { "Varactor array settings in the transmit mixers", "ubertooth.register.value.pamtst.txmix_cap_array",
2903 FT_UINT16, BASE_DEC, NULL, 0x0060,
2904 NULL, HFILL }
2905 },
2906 { &hf_cc2400_pamtst_txmix_current,
2907 { "Transmit Mixers Current", "ubertooth.register.value.pamtst.txmix_current",
2908 FT_UINT16, BASE_DEC | BASE_EXT_STRING, &cc2400_pamtst_txmix_current_vals_ext, 0x0018,
2909 NULL, HFILL }
2910 },
2911 { &hf_cc2400_pamtst_pa_current,
2912 { "Power Amplifier Current", "ubertooth.register.value.pamtst.pa_current",
2913 FT_UINT16, BASE_DEC | BASE_EXT_STRING, &cc2400_pamtst_pa_current_vals_ext, 0x0007,
2914 NULL, HFILL }
2915 },
2916 { &hf_cc2400_lmtst_reserved,
2917 { "Reserved [15:14]", "ubertooth.register.value.lmtst.reserved.15_14",
2918 FT_UINT16, BASE_DEC, NULL, 0xC000,
2919 NULL, HFILL }
2920 },
2921 { &hf_cc2400_lmtst_rxmix_hgm,
2922 { "Receiver Mixers High Gain Mode Enable", "ubertooth.register.value.lmtst.rxmix_hgm",
2923 FT_BOOLEAN, 16, NULL, 0x2000,
2924 NULL, HFILL }
2925 },
2926 { &hf_cc2400_lmtst_rxmix_tail,
2927 { "Receiver Mixers Output Current", "ubertooth.register.value.lmtst.rxmix_tail",
2928 FT_UINT16, BASE_DEC | BASE_EXT_STRING, &cc2400_lmtst_rxmix_tail_vals_ext, 0x1800,
2929 NULL, HFILL }
2930 },
2931 { &hf_cc2400_lmtst_rxmix_vcm,
2932 { "Controls VCM level in the mixer feedback loop", "ubertooth.register.value.lmtst.rxmix_vcm",
2933 FT_UINT16, BASE_DEC | BASE_EXT_STRING, &cc2400_lmtst_rxmix_vcm_vals_ext, 0x0600,
2934 NULL, HFILL }
2935 },
2936 { &hf_cc2400_lmtst_rxmix_current,
2937 { "Controls current in the mixer", "ubertooth.register.value.lmtst.rxmix_current",
2938 FT_UINT16, BASE_DEC | BASE_EXT_STRING, &cc2400_lmtst_rxmix_current_vals_ext, 0x0180,
2939 NULL, HFILL }
2940 },
2941 { &hf_cc2400_lmtst_lna_cap_array,
2942 { "Varactor array setting in the LNA", "ubertooth.register.value.lmtst.lna_cap_array",
2943 FT_UINT16, BASE_DEC | BASE_EXT_STRING, &cc2400_lmtst_lna_cap_array_vals_ext, 0x0060,
2944 NULL, HFILL }
2945 },
2946 { &hf_cc2400_lmtst_lna_lowgain,
2947 { "Low gain mode of the LNA", "ubertooth.register.value.lmtst.lna_lowgain",
2948 FT_UINT16, BASE_DEC | BASE_EXT_STRING, &cc2400_lmtst_lna_lowgain_vals_ext, 0x0010,
2949 NULL, HFILL }
2950 },
2951 { &hf_cc2400_lmtst_lna_gain,
2952 { "Controls current in the LNA gain compensation branch", "ubertooth.register.value.lmtst.lna_gain",
2953 FT_UINT16, BASE_DEC | BASE_EXT_STRING, &cc2400_lmtst_lna_gain_vals_ext, 0x000C,
2954 NULL, HFILL }
2955 },
2956 { &hf_cc2400_lmtst_lna_current,
2957 { "Main current in the LNA", "ubertooth.register.value.lmtst.lna_current",
2958 FT_UINT16, BASE_DEC | BASE_EXT_STRING, &cc2400_lmtst_lna_current_vals_ext, 0x0003,
2959 NULL, HFILL }
2960 },
2961 { &hf_cc2400_manor_vga_reset_n,
2962 { "No VGA Reset", "ubertooth.register.value.manor.vga_reset_n",
2963 FT_BOOLEAN, 16, NULL, 0x8000,
2964 NULL, HFILL }
2965 },
2966 { &hf_cc2400_manor_lock_status,
2967 { "Lock Status", "ubertooth.register.value.manor.lock_status",
2968 FT_BOOLEAN, 16, NULL, 0x4000,
2969 NULL, HFILL }
2970 },
2971 { &hf_cc2400_manor_balun_ctrl,
2972 { "Balun Control", "ubertooth.register.value.manor.balun_ctrl",
2973 FT_BOOLEAN, 16, NULL, 0x2000,
2974 NULL, HFILL }
2975 },
2976 { &hf_cc2400_manor_rxtx,
2977 { "RxTx", "ubertooth.register.value.manor.rxtx",
2978 FT_BOOLEAN, 16, NULL, 0x1000,
2979 NULL, HFILL }
2980 },
2981 { &hf_cc2400_manor_pre_pd,
2982 { "Power Down of Prescaler", "ubertooth.register.value.manor.pre_pd",
2983 FT_BOOLEAN, 16, NULL, 0x0800,
2984 NULL, HFILL }
2985 },
2986 { &hf_cc2400_manor_pa_n_pd,
2987 { "Power Down of Power Amplifier (negative path)", "ubertooth.register.value.manor.pa_n_pd",
2988 FT_BOOLEAN, 16, NULL, 0x0400,
2989 NULL, HFILL }
2990 },
2991 { &hf_cc2400_manor_pa_p_pd,
2992 { "Power Down of Power Amplifier (positive path)", "ubertooth.register.value.manor.pa_p_pd",
2993 FT_BOOLEAN, 16, NULL, 0x0200,
2994 NULL, HFILL }
2995 },
2996 { &hf_cc2400_manor_dac_lpf_pd,
2997 { "Power Down of Tx DAC", "ubertooth.register.value.manor.dac_lpf_pd",
2998 FT_BOOLEAN, 16, NULL, 0x0100,
2999 NULL, HFILL }
3000 },
3001 { &hf_cc2400_manor_bias_pd,
3002 { "Power Down control of global bias generator + XOSC clock buffer", "ubertooth.register.value.manor.bias_pd",
3003 FT_BOOLEAN, 16, NULL, 0x0080,
3004 NULL, HFILL }
3005 },
3006 { &hf_cc2400_manor_xosc16m_pd,
3007 { "Power Down control of 16 MHz XOSC core", "ubertooth.register.value.manor.xosc16m_pd",
3008 FT_BOOLEAN, 16, NULL, 0x0040,
3009 NULL, HFILL }
3010 },
3011 { &hf_cc2400_manor_chp_pd,
3012 { "Power Down control of Charge Pump", "ubertooth.register.value.manor.chp_pd",
3013 FT_BOOLEAN, 16, NULL, 0x0020,
3014 NULL, HFILL }
3015 },
3016 { &hf_cc2400_manor_fs_pd,
3017 { "Power Down control of VCO, I/Q generator, LO buffers", "ubertooth.register.value.manor.fs_pd",
3018 FT_BOOLEAN, 16, NULL, 0x0010,
3019 NULL, HFILL }
3020 },
3021 { &hf_cc2400_manor_adc_pd,
3022 { "Power Down control of the ADC", "ubertooth.register.value.manor.adc_pd",
3023 FT_BOOLEAN, 16, NULL, 0x0008,
3024 NULL, HFILL }
3025 },
3026 { &hf_cc2400_manor_vga_pd,
3027 { "Power Down control of the VGA", "ubertooth.register.value.manor.vga_pd",
3028 FT_BOOLEAN, 16, NULL, 0x0004,
3029 NULL, HFILL }
3030 },
3031 { &hf_cc2400_manor_rxbpf_pd,
3032 { "Power Down control of complex band-pass receive filter", "ubertooth.register.value.manor.rxbpf_pd",
3033 FT_BOOLEAN, 16, NULL, 0x0002,
3034 NULL, HFILL }
3035 },
3036 { &hf_cc2400_manor_lnamix_pd,
3037 { "Power Down control of LNA, down-conversion mixers and front-end bias", "ubertooth.register.value.manor.lnamix_pd",
3038 FT_BOOLEAN, 16, NULL, 0x0001,
3039 NULL, HFILL }
3040 },
3041 { &hf_cc2400_mdmtst0_reserved,
3042 { "Reserved [15:14]", "ubertooth.register.value.mdmtst0.reserved.15_14",
3043 FT_UINT16, BASE_DEC, NULL, 0xC000,
3044 NULL, HFILL }
3045 },
3046 { &hf_cc2400_mdmtst0_tx_prng,
3047 { "Tx PRNG", "ubertooth.register.value.mdmtst0.tx_prng",
3048 FT_BOOLEAN, 16, NULL, 0x2000,
3049 NULL, HFILL }
3050 },
3051 { &hf_cc2400_mdmtst0_tx_1mhz_offset_n,
3052 { "Tx No 1MHz Offset", "ubertooth.register.value.mdmtst0.tx_1mhz_offset_n",
3053 FT_BOOLEAN, 16, NULL, 0x1000,
3054 NULL, HFILL }
3055 },
3056 { &hf_cc2400_mdmtst0_invert_data,
3057 { "Invert Data", "ubertooth.register.value.mdmtst0.invert_data",
3058 FT_BOOLEAN, 16, NULL, 0x0800,
3059 NULL, HFILL }
3060 },
3061 { &hf_cc2400_mdmtst0_afc_adjust_on_packet,
3062 { "AFC Adjust on Packet", "ubertooth.register.value.mdmtst0.afc_adjust_on_packet",
3063 FT_BOOLEAN, 16, NULL, 0x0400,
3064 NULL, HFILL }
3065 },
3066 { &hf_cc2400_mdmtst0_afc_settling,
3067 { "AFC Settling", "ubertooth.register.value.mdmtst0.afc_settling",
3068 FT_UINT16, BASE_DEC | BASE_EXT_STRING, &cc2400_mdmtst0_afc_settling_vals_ext, 0x0300,
3069 NULL, HFILL }
3070 },
3071 { &hf_cc2400_mdmtst0_afc_delta,
3072 { "AFC Delta", "ubertooth.register.value.mdmtst0.afc_delta",
3073 FT_UINT16, BASE_DEC, NULL, 0x00FF,
3074 NULL, HFILL }
3075 },
3076 { &hf_cc2400_mdmtst1_reserved,
3077 { "Reserved [15:7]", "ubertooth.register.value.mdmtst1.reserved.15_7",
3078 FT_UINT16, BASE_DEC, NULL, 0xFF80,
3079 NULL, HFILL }
3080 },
3081 { &hf_cc2400_mdmtst1_bsync_threshold,
3082 { "B-Sync Threshold", "ubertooth.register.value.mdmtst1.bsync_threshold",
3083 FT_UINT16, BASE_DEC, NULL, 0x007F,
3084 NULL, HFILL }
3085 },
3086 { &hf_cc2400_dactst_reserved,
3087 { "Reserved [15]", "ubertooth.register.value.dactst.reserved.15",
3088 FT_BOOLEAN, 16, NULL, 0x8000,
3089 NULL, HFILL }
3090 },
3091 { &hf_cc2400_dactst_dac_src,
3092 { "DAC Source", "ubertooth.register.value.dactst.dac_src",
3093 FT_UINT16, BASE_DEC | BASE_EXT_STRING, &cc2400_dactst_dac_src_vals_ext, 0x7000,
3094 NULL, HFILL }
3095 },
3096 { &hf_cc2400_dactst_dac_i_o,
3097 { "I-branch DAC Override Value", "ubertooth.register.value.dactst.dac_i_o",
3098 FT_UINT16, BASE_DEC, NULL, 0x0FC0,
3099 NULL, HFILL }
3100 },
3101 { &hf_cc2400_dactst_dac_q_o,
3102 { "Q-branch DAC Override Value", "ubertooth.register.value.dactst.dac_q_o",
3103 FT_UINT16, BASE_DEC, NULL, 0x003F,
3104 NULL, HFILL }
3105 },
3106 { &hf_cc2400_agctst0_agc_settle_blank_dn,
3107 { "AGC Settle Blank Down", "ubertooth.register.value.agctst0.agc_settle_blank_down",
3108 FT_UINT16, BASE_DEC, NULL, 0xE000,
3109 "Duration of blanking signal in 8 MHz clock cycles", HFILL }
3110 },
3111 { &hf_cc2400_agctst0_agc_win_size,
3112 { "AGC Window Size", "ubertooth.register.value.agctst0.agc_win_size",
3113 FT_UINT16, BASE_DEC, NULL, 0x1800,
3114 NULL, HFILL }
3115 },
3116 { &hf_cc2400_agctst0_agc_settle_peak,
3117 { "AGC Settle Peak Period", "ubertooth.register.value.agctst0.agc_settle_peak",
3118 FT_UINT16, BASE_DEC, NULL, 0x0780,
3119 NULL, HFILL }
3120 },
3121 { &hf_cc2400_agctst0_agc_settle_adc,
3122 { "AGC Settle ADC Period", "ubertooth.register.value.agctst0.agc_settle_adc",
3123 FT_UINT16, BASE_DEC, NULL, 0x0078,
3124 NULL, HFILL }
3125 },
3126 { &hf_cc2400_agctst0_agc_attempts,
3127 { "AGC Attempts", "ubertooth.register.value.agctst0.agc_attempts",
3128 FT_UINT16, BASE_DEC, NULL, 0x0007,
3129 NULL, HFILL }
3130 },
3131 { &hf_cc2400_agctst1_reserved,
3132 { "Reserved [15]", "ubertooth.register.value.agctst1.reserved.15",
3133 FT_BOOLEAN, 16, NULL, 0x8000,
3134 NULL, HFILL }
3135 },
3136 { &hf_cc2400_agctst1_agc_var_gain_sat,
3137 { "AGC Variable Gain Stage", "ubertooth.register.value.agctst1.agc_var_gain_sat",
3138 FT_UINT16, BASE_DEC | BASE_EXT_STRING, &cc2400_agctst1_agc_var_gain_sat_vals_ext, 0x4000,
3139 NULL, HFILL }
3140 },
3141 { &hf_cc2400_agctst1_agc_settle_blank_up,
3142 { "AGC Settle Bank Up", "ubertooth.register.value.agctst1.agc_settle_blank_up",
3143 FT_UINT16, BASE_DEC, NULL, 0x3800,
3144 "Duration of blanking signal in 8 MHz clock cycles", HFILL }
3145 },
3146 { &hf_cc2400_agctst1_peakdet_cur_boost,
3147 { "Current Peak Detectors Boost", "ubertooth.register.value.agctst1.peakdet_cur_boost",
3148 FT_BOOLEAN, 16, NULL, 0x0400,
3149 NULL, HFILL }
3150 },
3151 { &hf_cc2400_agctst1_agc_mult_slow,
3152 { "AGC Timing Multiplier Slow Mode", "ubertooth.register.value.agctst1.agc_mult_slow",
3153 FT_UINT16, BASE_DEC, NULL, 0x03C0,
3154 NULL, HFILL }
3155 },
3156 { &hf_cc2400_agctst1_agc_settle_fixed,
3157 { "AGC Settling Period Fixed Gain Step", "ubertooth.register.value.agctst1.agc_settle_fixed",
3158 FT_UINT16, BASE_DEC, NULL, 0x003C,
3159 NULL, HFILL }
3160 },
3161 { &hf_cc2400_agctst1_agc_settle_var,
3162 { "AGC Settling Period Variable Gain Step", "ubertooth.register.value.agctst1.agc_settle_var",
3163 FT_UINT16, BASE_DEC, NULL, 0x0003,
3164 NULL, HFILL }
3165 },
3166 { &hf_cc2400_agctst2_reserved,
3167 { "Reserved [15:14]", "ubertooth.register.value.agctst2.reserved.15_14",
3168 FT_UINT16, BASE_DEC, NULL, 0xC000,
3169 NULL, HFILL }
3170 },
3171 { &hf_cc2400_agctst2_agc_backend_blanking,
3172 { "AGC Backend Blanking", "ubertooth.register.value.agctst2.agc_backend_blanking",
3173 FT_UINT16, BASE_DEC, NULL, 0x3000,
3174 NULL, HFILL }
3175 },
3176 { &hf_cc2400_agctst2_agc_adjust_m3db,
3177 { "AGC Adjust -3db", "ubertooth.register.value.agctst2.agc_adjust_m3db",
3178 FT_UINT16, BASE_DEC, NULL, 0x0E00,
3179 NULL, HFILL }
3180 },
3181 { &hf_cc2400_agctst2_agc_adjust_m1db,
3182 { "AGC Adjust -1db", "ubertooth.register.value.agctst2.agc_adjust_m1db",
3183 FT_UINT16, BASE_DEC, NULL, 0x01C0,
3184 NULL, HFILL }
3185 },
3186 { &hf_cc2400_agctst2_agc_adjust_p3db,
3187 { "AGC Adjust +3db", "ubertooth.register.value.agctst2.agc_adjust_p3db",
3188 FT_UINT16, BASE_DEC, NULL, 0x0038,
3189 NULL, HFILL }
3190 },
3191 { &hf_cc2400_agctst2_agc_adjust_p1db,
3192 { "AGC Adjust +1db", "ubertooth.register.value.agctst2.agc_adjust_p1db",
3193 FT_UINT16, BASE_DEC, NULL, 0x0007,
3194 NULL, HFILL }
3195 },
3196 { &hf_cc2400_fstst0_rxmixbuf_cur,
3197 { "Rx Mixer Buffer Bias Current", "ubertooth.register.value.fstst0.rxmixbuf_cur",
3198 FT_UINT16, BASE_DEC | BASE_EXT_STRING, &cc2400_fstst0_rxtxmixbuf_cur_vals_ext, 0xC000,
3199 NULL, HFILL }
3200 },
3201 { &hf_cc2400_fstst0_txmixbuf_cur,
3202 { "TX Mixer Buffer Bias Current", "ubertooth.register.value.fstst0.txmixbuf_cur",
3203 FT_UINT16, BASE_DEC | BASE_EXT_STRING, &cc2400_fstst0_rxtxmixbuf_cur_vals_ext, 0x3000,
3204 NULL, HFILL }
3205 },
3206 { &hf_cc2400_fstst0_vco_array_settle_long,
3207 { "Voltage Controlled Oscillator Array Settle Long", "ubertooth.register.value.fstst0.vco_array_settle_lon",
3208 FT_BOOLEAN, 16, NULL, 0x0800,
3209 NULL, HFILL }
3210 },
3211 { &hf_cc2400_fstst0_vco_array_oe,
3212 { "Voltage Controlled Oscillator Array Manual Override Enable", "ubertooth.register.value.fstst0.vco_array_oe",
3213 FT_BOOLEAN, 16, NULL, 0x0400,
3214 NULL, HFILL }
3215 },
3216 { &hf_cc2400_fstst0_vco_array_o,
3217 { "Voltage Controlled Oscillator Array Override Value", "ubertooth.register.value.fstst0.vco_array_o",
3218 FT_UINT16, BASE_DEC, NULL, 0x03E0,
3219 NULL, HFILL }
3220 },
3221 { &hf_cc2400_fstst0_vco_array_res,
3222 { "Resulting VCO Array Setting from Last Calibration", "ubertooth.register.value.fstst0.vco_array_res",
3223 FT_UINT16, BASE_DEC, NULL, 0x001F,
3224 NULL, HFILL }
3225 },
3226 { &hf_cc2400_fstst1_rxbpf_locur,
3227 { "Rx Band-pass Filters LO Bias Current", "ubertooth.register.value.fstst1.rxbpf_locur",
3228 FT_UINT16, BASE_DEC | BASE_EXT_STRING, &cc2400_fstst1_rxbpf_locur_vals_ext, 0x8000,
3229 NULL, HFILL }
3230 },
3231 { &hf_cc2400_fstst1_rxbpf_midcur,
3232 { "Rx Band-pass Filters MID Bias Current", "ubertooth.register.value.fstst1.rxbpf_midcur",
3233 FT_UINT16, BASE_DEC | BASE_EXT_STRING, &cc2400_fstst1_rxbpf_midcur_vals_ext, 0x4000,
3234 NULL, HFILL }
3235 },
3236 { &hf_cc2400_fstst1_vco_current_ref,
3237 { "VCO Current Reference", "ubertooth.register.value.fstst1.vco_current_ref",
3238 FT_UINT16, BASE_DEC, NULL, 0x3C00,
3239 NULL, HFILL }
3240 },
3241 { &hf_cc2400_fstst1_vco_current_k,
3242 { "VCO Current Calibration Constant", "ubertooth.register.value.fstst1.vco_current_k",
3243 FT_UINT16, BASE_DEC, NULL, 0x03F0,
3244 NULL, HFILL }
3245 },
3246 { &hf_cc2400_fstst1_vc_dac_en,
3247 { "VCO Source", "ubertooth.register.value.fstst1.vc_dac_en",
3248 FT_UINT16, BASE_DEC | BASE_EXT_STRING, &cc2400_fstst1_vc_dac_en_vals_ext, 0x0008,
3249 NULL, HFILL }
3250 },
3251 { &hf_cc2400_fstst1_vc_dac_val,
3252 { "VCO DAC Output Value", "ubertooth.register.value.fstst1.vc_dac_val",
3253 FT_UINT16, BASE_DEC, NULL, 0x0007,
3254 NULL, HFILL }
3255 },
3256 { &hf_cc2400_fstst2_reserved,
3257 { "Reserved [15]", "ubertooth.register.value.fstst2.reserved.15",
3258 FT_BOOLEAN, 16, NULL, 0x8000,
3259 NULL, HFILL }
3260 },
3261 { &hf_cc2400_fstst2_vco_curcal_speed,
3262 { "Voltage Controlled Oscillator Current Calibration", "ubertooth.register.value.fstst2.vco_curcal_speed",
3263 FT_UINT16, BASE_DEC | BASE_EXT_STRING, &cc2400_fstst2_vco_curcal_speed_vals_ext, 0x6000,
3264 NULL, HFILL }
3265 },
3266 { &hf_cc2400_fstst2_vco_current_oe,
3267 { "Voltage Controlled Oscillator Current Manual Override Enable", "ubertooth.register.value.fstst2.vco_current_oe",
3268 FT_BOOLEAN, 16, NULL, 0x1000,
3269 NULL, HFILL }
3270 },
3271 { &hf_cc2400_fstst2_vco_current_o,
3272 { "Voltage Controlled Oscillator Current Override Value", "ubertooth.register.value.fstst2.vco_current_o",
3273 FT_UINT16, BASE_DEC, NULL, 0x0FC0,
3274 NULL, HFILL }
3275 },
3276 { &hf_cc2400_fstst2_vco_current_res,
3277 { "Resulting VCO Current Setting from Last Calibration", "ubertooth.register.value.fstst2.vco_current_res",
3278 FT_UINT16, BASE_DEC, NULL, 0x003F,
3279 NULL, HFILL }
3280 },
3281 { &hf_cc2400_fstst3_reserved,
3282 { "Reserved [15:14]", "ubertooth.register.value.fstst3.reserved.15_14",
3283 FT_UINT16, BASE_DEC, NULL, 0xC000,
3284 NULL, HFILL }
3285 },
3286 { &hf_cc2400_fstst3_chp_test_up,
3287 { "Charge Pump Test Up", "ubertooth.register.value.fstst3.chp_test_up",
3288 FT_BOOLEAN, 16, NULL, 0x2000,
3289 NULL, HFILL }
3290 },
3291 { &hf_cc2400_fstst3_chp_test_dn,
3292 { "Charge Pump Test Down", "ubertooth.register.value.fstst3.chp_test_down",
3293 FT_BOOLEAN, 16, NULL, 0x1000,
3294 NULL, HFILL }
3295 },
3296 { &hf_cc2400_fstst3_chp_disable,
3297 { "Charge Pump Disable", "ubertooth.register.value.fstst3.chp_disable",
3298 FT_BOOLEAN, 16, NULL, 0x0800,
3299 NULL, HFILL }
3300 },
3301 { &hf_cc2400_fstst3_pd_delay,
3302 { "Phase Detector Delay", "ubertooth.register.value.fstst3.pd_delay",
3303 FT_UINT16, BASE_DEC | BASE_EXT_STRING, &cc2400_fstst3_pd_delay_vals_ext, 0x0400,
3304 NULL, HFILL }
3305 },
3306 { &hf_cc2400_fstst3_chp_step_period,
3307 { "Charge Pump Step Period", "ubertooth.register.value.fstst3.chp_step_period",
3308 FT_UINT16, BASE_DEC | BASE_EXT_STRING, &cc2400_fstst3_chp_step_period_vals_ext, 0x0300,
3309 NULL, HFILL }
3310 },
3311 { &hf_cc2400_fstst3_stop_chp_current,
3312 { "Stop Charge Pump Current", "ubertooth.register.value.fstst3.stop_chp_current",
3313 FT_UINT16, BASE_DEC, NULL, 0x00F0,
3314 NULL, HFILL }
3315 },
3316 { &hf_cc2400_fstst3_start_chp_current,
3317 { "Start Charge Pump Current", "ubertooth.register.value.fstst3.start_chp_current",
3318 FT_UINT16, BASE_DEC, NULL, 0x000F,
3319 NULL, HFILL }
3320 },
3321
3322 { &hf_cc2400_manfidl_partnum,
3323 { "Part Number [3:0]", "ubertooth.register.value.manfidl.partnum",
3324 FT_UINT16, BASE_DEC, NULL, 0xF000,
3325 NULL, HFILL }
3326 },
3327 { &hf_cc2400_manfidl_manfid,
3328 { "Manufacturer ID", "ubertooth.register.value.manfidl.manfid",
3329 FT_UINT16, BASE_HEX, NULL, 0x0FFF,
3330 NULL, HFILL }
3331 },
3332 { &hf_cc2400_manfidh_version,
3333 { "Version", "ubertooth.register.value.manfidh.version",
3334 FT_UINT16, BASE_DEC, NULL, 0xF000,
3335 NULL, HFILL }
3336 },
3337 { &hf_cc2400_manfidh_partnum,
3338 { "Part Number [15:4]", "ubertooth.register.value.manfidh.partnum",
3339 FT_UINT16, BASE_DEC, NULL, 0x0FFF,
3340 NULL, HFILL }
3341 },
3342 { &hf_cc2400_grmdm_reserved,
3343 { "Reserved [15]", "ubertooth.register.value.grmdm.reserved.15",
3344 FT_BOOLEAN, 16, NULL, 0x8000,
3345 NULL, HFILL }
3346 },
3347 { &hf_cc2400_grmdm_sync_errbits_allowed,
3348 { "Sync Error Bits Allowed", "ubertooth.register.value.grmdm.sync_errbits_allowed",
3349 FT_UINT16, BASE_DEC, NULL, 0x6000,
3350 NULL, HFILL }
3351 },
3352 { &hf_cc2400_grmdm_pin_mode,
3353 { "PIN Mode", "ubertooth.register.value.grmdm.pin_mode",
3354 FT_UINT16, BASE_DEC | BASE_EXT_STRING, &cc2400_grmdm_pin_mode_vals_ext, 0x1800,
3355 NULL, HFILL }
3356 },
3357 { &hf_cc2400_grmdm_packet_mode,
3358 { "Packet Mode", "ubertooth.register.value.grmdm.packet_mode",
3359 FT_BOOLEAN, 16, NULL, 0x0400,
3360 NULL, HFILL }
3361 },
3362 { &hf_cc2400_grmdm_pre_bytes,
3363 { "Preamble Bytes", "ubertooth.register.value.grmdm.pre_bytes",
3364 FT_UINT16, BASE_DEC | BASE_EXT_STRING, &cc2400_grmdm_pre_bytes_vals_ext, 0x0380,
3365 NULL, HFILL }
3366 },
3367 { &hf_cc2400_grmdm_sync_word_size,
3368 { "Sync Word Size", "ubertooth.register.value.grmdm.sync_word_size",
3369 FT_UINT16, BASE_DEC | BASE_EXT_STRING, &cc2400_grmdm_sync_word_size_vals_ext, 0x0060,
3370 NULL, HFILL }
3371 },
3372 { &hf_cc2400_grmdm_crc_on,
3373 { "CRC On", "ubertooth.register.value.grmdm.crc_on",
3374 FT_BOOLEAN, 16, NULL, 0x0010,
3375 NULL, HFILL }
3376 },
3377 { &hf_cc2400_grmdm_data_format,
3378 { "Data Format", "ubertooth.register.value.grmdm.data_format",
3379 FT_UINT16, BASE_DEC | BASE_EXT_STRING, &cc2400_grmdm_data_format_vals_ext, 0x000C,
3380 NULL, HFILL }
3381 },
3382 { &hf_cc2400_grmdm_modulation_format,
3383 { "Modulation Format", "ubertooth.register.value.grmdm.modulation_format",
3384 FT_UINT16, BASE_DEC | BASE_EXT_STRING, &cc2400_grmdm_modulation_format_vals_ext, 0x0002,
3385 NULL, HFILL }
3386 },
3387 { &hf_cc2400_grmdm_tx_gaussian_filter,
3388 { "Tx Gaussian Filter", "ubertooth.register.value.grmdm.tx_gaussian_filter",
3389 FT_BOOLEAN, 16, NULL, 0x0001,
3390 NULL, HFILL }
3391 },
3392 { &hf_cc2400_grdec_reserved,
3393 { "Reserved [15:13]", "ubertooth.register.value.grdec.reserved.15_13",
3394 FT_UINT16, BASE_DEC, NULL, 0xE000,
3395 NULL, HFILL }
3396 },
3397 { &hf_cc2400_grdec_ind_saturation,
3398 { "Ind Saturation", "ubertooth.register.value.grdec.ind_saturation",
3399 FT_BOOLEAN, 16, NULL, 0x1000,
3400 NULL, HFILL }
3401 },
3402 { &hf_cc2400_grdec_dec_shift,
3403 { "Decimation Shift", "ubertooth.register.value.grdec.dec_shift",
3404 FT_UINT16, BASE_DEC | BASE_EXT_STRING, &cc2400_grdec_dec_shift_vals_ext, 0x0C00,
3405 NULL, HFILL }
3406 },
3407 { &hf_cc2400_grdec_channel_dec,
3408 { "Channel Decimation", "ubertooth.register.value.grdec.channel_dec",
3409 FT_UINT16, BASE_DEC | BASE_EXT_STRING, &cc2400_grdec_channel_dec_vals_ext, 0x0300,
3410 NULL, HFILL }
3411 },
3412 { &hf_cc2400_grdec_dec_val,
3413 { "Decimation Value", "ubertooth.register.value.grdec.dec_val",
3414 FT_UINT16, BASE_DEC, NULL, 0x00FF,
3415 NULL, HFILL }
3416 },
3417 { &hf_cc2400_pktstatus_reserved_15_11,
3418 { "Reserved [15:11]", "ubertooth.register.value.pktstatus.reserved.15_11",
3419 FT_UINT16, BASE_DEC, NULL, 0xF800,
3420 NULL, HFILL }
3421 },
3422 { &hf_cc2400_pktstatus_sync_word_received,
3423 { "Sync Word Received", "ubertooth.register.value.pktstatus.sync_word_received",
3424 FT_BOOLEAN, 16, NULL, 0x0400,
3425 NULL, HFILL }
3426 },
3427 { &hf_cc2400_pktstatus_crc_ok,
3428 { "CRC OK", "ubertooth.register.value.pktstatus.crc_ok",
3429 FT_BOOLEAN, 16, NULL, 0x0200,
3430 NULL, HFILL }
3431 },
3432 { &hf_cc2400_pktstatus_reserved_8,
3433 { "Reserved [8]", "ubertooth.register.value.pktstatus.reserved.8",
3434 FT_BOOLEAN, 16, NULL, 0x0100,
3435 NULL, HFILL }
3436 },
3437 { &hf_cc2400_pktstatus_reserved_7_0,
3438 { "Reserved [7:0]", "ubertooth.register.value.pktstatus.reserved.7_0",
3439 FT_UINT16, BASE_DEC, NULL, 0x00FF,
3440 NULL, HFILL }
3441 },
3442 };
3443
3444 static ei_register_info ei[] = {
3445 { &ei_unexpected_response, { "ubertooth.unexpected_response", PI_PROTOCOL, PI_ERROR, "Unexpected response for this command", EXPFILL }},
3446 { &ei_unknown_data, { "ubertooth.unknown_data", PI_PROTOCOL, PI_NOTE, "Unknown data", EXPFILL }},
3447 { &ei_unexpected_data, { "ubertooth.unexpected_data", PI_PROTOCOL, PI_WARN, "Unexpected data", EXPFILL }},
3448 };
3449
3450 static int *ett[] = {
3451 &ett_ubertooth,
3452 &ett_command,
3453 &ett_usb_rx_packet,
3454 &ett_usb_rx_packet_data,
3455 &ett_entry,
3456 &ett_register_value,
3457 &ett_fsdiv_frequency
3458 };
3459
3460 command_info = wmem_tree_new_autoreset(wmem_epan_scope(), wmem_file_scope());
3461
3462 proto_ubertooth = proto_register_protocol("Ubertooth", "UBERTOOTH", "ubertooth");
3463 proto_register_field_array(proto_ubertooth, hf, array_length(hf));
3464 proto_register_subtree_array(ett, array_length(ett));
3465 ubertooth_handle = register_dissector("ubertooth", dissect_ubertooth, proto_ubertooth);
3466
3467 expert_module = expert_register_protocol(proto_ubertooth);
3468 expert_register_field_array(expert_module, ei, array_length(ei));
3469
3470 module = prefs_register_protocol(proto_ubertooth, NULL);
3471 prefs_register_static_text_preference(module, "version",
3472 "Ubertooth Firmware: 2012-10-R1 (also latest version prior to: git-4470774)",
3473 "Version of protocol supported by this dissector.");
3474 }
3475
3476 void
3477 proto_reg_handoff_ubertooth(void)
3478 {
3479 bluetooth_ubertooth_handle = find_dissector_add_dependency("bluetooth_ubertooth", proto_ubertooth);
3480
3481 dissector_add_uint("usb.product", (0x1d50 << 16) | 0x6000, ubertooth_handle); /* Ubertooth Zero */
3482 dissector_add_uint("usb.product", (0x1d50 << 16) | 0x6002, ubertooth_handle); /* Ubertooth One */
3483
3484 dissector_add_for_decode_as("usb.device", ubertooth_handle);
3485 dissector_add_for_decode_as("usb.protocol", ubertooth_handle);
3486 }
3487
3488 /*
3489 * Editor modelines - https://www.wireshark.org/tools/modelines.html
3490 *
3491 * Local variables:
3492 * c-basic-offset: 4
3493 * tab-width: 8
3494 * indent-tabs-mode: nil
3495 * End:
3496 *
3497 * vi: set shiftwidth=4 tabstop=8 expandtab:
3498 * :indentSize=4:tabSize=8:noTabs=true:
3499 */
Metzes wireshark repo