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Revert "TODO epan/dissectors/asn1/kerberos/packet-kerberos-template.c new GSS flags"
[wireshark-sm.git] / epan / dissectors / packet-bthci_vendor_intel.c
blobe0e8fc29ad74faca1d26d6084bd0998ac3777bca
1 /* packet-bthci_vendor.c
2 * Routines for the Bluetooth HCI Vendors Commands/Events
3 *
4 * Copyright 2014, Michal Labedzki for Tieto Corporation
5 *
6 * Wireshark - Network traffic analyzer
7 * By Gerald Combs <gerald@wireshark.org>
8 * Copyright 1998 Gerald Combs
9 *
10 * SPDX-License-Identifier: GPL-2.0-or-later
11 */
12
13 #include "config.h"
14
15 #include <epan/packet.h>
16 #include <epan/expert.h>
17 #include <epan/tap.h>
18
19 #include "packet-bluetooth.h"
20 #include "packet-bthci_cmd.h"
21 #include "packet-bthci_evt.h"
22
23
24 static int proto_bthci_vendor_intel;
25
26 static int hf_intel_opcode;
27 static int hf_intel_opcode_ogf;
28 static int hf_intel_opcode_ocf;
29 static int hf_intel_parameter_length;
30 static int hf_intel_number_of_allowed_command_packets;
31 static int hf_intel_event_code;
32 static int hf_intel_status;
33 static int hf_intel_line;
34 static int hf_intel_module;
35 static int hf_intel_reason;
36 static int hf_intel_zero;
37 static int hf_intel_number_of_packets;
38 static int hf_intel_source;
39 static int hf_intel_reset_type;
40 static int hf_intel_reset_reason;
41 static int hf_intel_ddc_status;
42 static int hf_intel_bd_data_status;
43 static int hf_intel_secure_send_commands_result;
44 static int hf_intel_handle;
45 static int hf_intel_access_address;
46 static int hf_intel_scan_status;
47 static int hf_intel_scan_status_reserved;
48 static int hf_intel_scan_status_page_scan;
49 static int hf_intel_scan_status_inquiry_scan;
50 static int hf_intel_link_pdu_trace_type;
51 static int hf_intel_link_clock;
52 static int hf_intel_link_id;
53 static int hf_intel_link_count;
54 static int hf_intel_bd_addr;
55 static int hf_intel_packet_table;
56 static int hf_intel_exception_type;
57 static int hf_intel_reset_reset_type;
58 static int hf_intel_reset_patch_enable;
59 static int hf_intel_reset_ddc_reload;
60 static int hf_intel_reset_boot_option;
61 static int hf_intel_reset_boot_address;
62 static int hf_intel_hardware_platform;
63 static int hf_intel_hardware_variant;
64 static int hf_intel_hardware_revision;
65 static int hf_intel_firmware_variant;
66 static int hf_intel_firmware_revision;
67 static int hf_intel_firmware_build_version_nn;
68 static int hf_intel_firmware_build_version_cw;
69 static int hf_intel_firmware_build_version_yy;
70 static int hf_intel_firmware_patch;
71 static int hf_intel_identifier;
72 static int hf_intel_secure_send_type;
73 static int hf_intel_manufacturer_mode;
74 static int hf_intel_manufacturer_reset;
75 static int hf_intel_transmit_traces;
76 static int hf_intel_transmit_arq;
77 static int hf_intel_receive_traces;
78 static int hf_intel_stimulated_exception_type;
79 static int hf_intel_mem_address;
80 static int hf_intel_mem_mode;
81 static int hf_intel_mem_length;
82 static int hf_intel_ddc_config_length;
83 static int hf_intel_set_event_mask;
84 static int hf_intel_set_event_mask_reserved_15_63;
85 static int hf_intel_set_event_mask_firmware_trace_string;
86 static int hf_intel_set_event_mask_le_link_established;
87 static int hf_intel_set_event_mask_reserved_12;
88 static int hf_intel_set_event_mask_system_exception;
89 static int hf_intel_set_event_mask_fatal_exception;
90 static int hf_intel_set_event_mask_debug_exception;
91 static int hf_intel_set_event_mask_reserved_8;
92 static int hf_intel_set_event_mask_scan_status;
93 static int hf_intel_set_event_mask_reserved_3_6;
94 static int hf_intel_set_event_mask_ptt_switch_notification;
95 static int hf_intel_set_event_mask_sco_rejected_via_lmp;
96 static int hf_intel_set_event_mask_bootup;
97 static int hf_intel_data;
98
99 static int * const hfx_intel_scan_status[] = {
100 &hf_intel_scan_status_reserved,
101 &hf_intel_scan_status_page_scan,
102 &hf_intel_scan_status_inquiry_scan,
103 NULL
104 };
105
106 static int * const hfx_intel_set_event_mask[] = {
107 &hf_intel_set_event_mask_reserved_15_63,
108 &hf_intel_set_event_mask_firmware_trace_string,
109 &hf_intel_set_event_mask_le_link_established,
110 &hf_intel_set_event_mask_reserved_12,
111 &hf_intel_set_event_mask_system_exception,
112 &hf_intel_set_event_mask_fatal_exception,
113 &hf_intel_set_event_mask_debug_exception,
114 &hf_intel_set_event_mask_reserved_8,
115 &hf_intel_set_event_mask_scan_status,
116 &hf_intel_set_event_mask_reserved_3_6,
117 &hf_intel_set_event_mask_ptt_switch_notification,
118 &hf_intel_set_event_mask_sco_rejected_via_lmp,
119 &hf_intel_set_event_mask_bootup,
120 NULL
121 };
122
123 static dissector_handle_t bthci_vendor_intel_handle;
124 static dissector_handle_t btlmp_handle;
125 static dissector_handle_t btle_handle;
126
127 static int ett_intel;
128 static int ett_intel_opcode;
129 static int ett_intel_scan_status;
130 static int ett_intel_set_event_mask;
131
132 static expert_field ei_intel_undecoded;
133 static expert_field ei_intel_unexpected_parameter;
134 static expert_field ei_intel_unexpected_data;
135
136 #define INTEL_OPCODE_VALS(base) \
137 { (base) | 0x0001, "Reset" }, \
138 { (base) | 0x0002, "No Operation" }, \
139 { (base) | 0x0005, "Read Version" }, \
140 { (base) | 0x0006, "Set UART Baudrate" }, \
141 { (base) | 0x0007, "Enable LPM" }, \
142 { (base) | 0x0008, "PCM Write Configuration" }, \
143 { (base) | 0x0009, "Secure Send" }, \
144 { (base) | 0x000D, "Read Secure Boot Params" }, \
145 { (base) | 0x000E, "Write Secure Boot Params" }, \
146 { (base) | 0x000F, "Unlock" }, \
147 { (base) | 0x0010, "Change UART Baudrate" }, \
148 { (base) | 0x0011, "Manufacturer Mode" }, \
149 { (base) | 0x0012, "Read Link RSSI" }, \
150 { (base) | 0x0022, "Get Exception Info" }, \
151 { (base) | 0x0024, "Clear Exception Info" }, \
152 { (base) | 0x002F, "Write BD Data" }, \
153 { (base) | 0x0030, "Read BD Data" }, \
154 { (base) | 0x0031, "Write BD Address" }, \
155 { (base) | 0x0032, "Flow Specification" }, \
156 { (base) | 0x0034, "Read Secure ID" }, \
157 { (base) | 0x0038, "Set Synchronous USB Interface Type" }, \
158 { (base) | 0x0039, "Config Synchronous Interface" }, \
159 { (base) | 0x003F, "SW RF Kill" }, \
160 { (base) | 0x0043, "Activate/Deactivate Traces" }, \
161 { (base) | 0x004D, "Stimulate Exception" }, \
162 { (base) | 0x0050, "Read HW Version" }, \
163 { (base) | 0x0052, "Set Event Mask" }, \
164 { (base) | 0x0053, "Config_Link_Controller" }, \
165 { (base) | 0x0089, "DDC Write" }, \
166 { (base) | 0x008A, "DDC Read" }, \
167 { (base) | 0x008B, "DDC Config Write" }, \
168 { (base) | 0x008C, "DDC Config Read" }, \
169 { (base) | 0x008D, "Memory Read" }, \
170 { (base) | 0x008E, "Memory Write" }
171
172 static const value_string intel_opcode_ocf_vals[] = {
173 INTEL_OPCODE_VALS(0x0),
174 { 0, NULL }
175 };
176
177 static const value_string intel_opcode_vals[] = {
178 INTEL_OPCODE_VALS(0x3F << 10),
179 { 0, NULL }
180 };
181
182 static const value_string intel_event_code_vals[] = {
183 { 0x01, "Fatal Exception" },
184 { 0x02, "Bootup" },
185 { 0x05, "Default BD Data" },
186 { 0x06, "Secure Send Commands Result" },
187 { 0x08, "Debug Exception" },
188 { 0x0F, "LE Link Established" },
189 { 0x11, "Scan Status" },
190 { 0x16, "Activate/Deactivate Traces Complete" },
191 { 0x17, "Link PDU Trace" },
192 { 0x19, "Write BD Data Complete" },
193 { 0x25, "SCO Rejected via LMP" },
194 { 0x26, "PTT Switch Notification" },
195 { 0x29, "System Exception" },
196 { 0x2C, "FW Trace String" },
197 { 0x2E, "FW Trace Binary" },
198 { 0, NULL }
199 };
200
201 static const value_string intel_module_vals[] = {
202 { 0x01, "BC" },
203 { 0x02, "HCI" },
204 { 0x03, "LLC" },
205 { 0x04, "OS" },
206 { 0x05, "LM" },
207 { 0x06, "SC" },
208 { 0x07, "SP" },
209 { 0x08, "OSAL" },
210 { 0x09, "LC" },
211 { 0x0A, "APP" },
212 { 0x0B, "TLD" },
213 { 0xF0, "Debug" },
214 { 0, NULL }
215 };
216
217 static const value_string intel_source_vals[] = {
218 { 0x00, "Bootloader" },
219 { 0x01, "Operational Firmware" },
220 { 0x02, "Self Test Firmware" },
221 { 0, NULL }
222 };
223
224 static const value_string intel_reset_type_vals[] = {
225 { 0x00, "Hardware Reset" },
226 { 0x01, "Soft Watchdog Reset" },
227 { 0x02, "Soft Software Reset" },
228 { 0x03, "Hard Watchdog Reset" },
229 { 0x04, "Hard Software Reset" },
230 { 0, NULL }
231 };
232
233 static const value_string intel_reset_reason_vals[] = {
234 { 0x00, "Power On" },
235 { 0x01, "Reset Command" },
236 { 0x02, "Intel Reset Command" },
237 { 0x03, "Watchdog" },
238 { 0x04, "Fatal Exception" },
239 { 0x05, "System Exception" },
240 { 0xFF, "Unknown" },
241 { 0, NULL }
242 };
243
244 static const value_string intel_ddc_status_vals[] = {
245 { 0x00, "Firmware Default" },
246 { 0x01, "Firmware Default Plus OTP" },
247 { 0x02, "Persistent RAM" },
248 { 0x03, "Not Used" },
249 { 0, NULL }
250 };
251
252 static const value_string intel_bd_data_status_vals[] = {
253 { 0x02, "Invalid Manufacturing Data" },
254 { 0, NULL }
255 };
256
257 static const value_string intel_secure_send_commands_result_vals[] = {
258 { 0x00, "Success" },
259 { 0x01, "General Failure" },
260 { 0x02, "Hardware Failure" },
261 { 0x03, "Signature Verification Failed" },
262 { 0x04, "Parsing Error of Command Buffer" },
263 { 0x05, "Command Execution Failure" },
264 { 0x06, "Command Parameters Error" },
265 { 0x07, "Command Missing" },
266 { 0, NULL }
267 };
268
269 static const value_string intel_link_pdu_trace_type_vals[] = {
270 { 0x00, "LMP Rx" },
271 { 0x01, "LMP Tx" },
272 { 0x02, "LMP Ack" },
273 { 0x03, "LL Rx" },
274 { 0x04, "LL Tx" },
275 { 0x05, "LL Ack" },
276 { 0, NULL }
277 };
278
279 static const value_string intel_packet_table_vals[] = {
280 { 0x00, "Basic Rate" },
281 { 0x01, "Enhanced Data Rate" },
282 { 0, NULL }
283 };
284
285 static const value_string intel_exception_type_vals[] = {
286 { 0x00, "No Exception" },
287 { 0x01, "Undefined Instruction" },
288 { 0x02, "Prefetch Abort" },
289 { 0x03, "Data Abort" },
290 { 0, NULL }
291 };
292
293 static const value_string intel_reset_reset_type_vals[] = {
294 { 0x00, "Soft Software Reset" },
295 { 0x01, "Hard Software Reset" },
296 { 0, NULL }
297 };
298
299 static const value_string intel_reset_patch_enable_vals[] = {
300 { 0x00, "Disabled" },
301 { 0x01, "Enabled" },
302 { 0, NULL }
303 };
304
305 static const value_string intel_reset_ddc_reload_vals[] = {
306 { 0x00, "Disabled" },
307 { 0x01, "Reload from OTP" },
308 { 0, NULL }
309 };
310
311 static const value_string intel_secure_send_type_vals[] = {
312 { 0x00, "Init" },
313 { 0x01, "Data" },
314 { 0x02, "Sign" },
315 { 0x03, "PKey" },
316 { 0, NULL }
317 };
318
319 static const value_string intel_manufacturer_mode_vals[] = {
320 { 0x00, "Disabled" },
321 { 0x01, "Enabled" },
322 { 0, NULL }
323 };
324
325 static const value_string intel_manufacturer_reset_vals[] = {
326 { 0x00, "No Reset" },
327 { 0x01, "Reset and Deactivate Patches" },
328 { 0x02, "Reset and Activate Patches" },
329 { 0, NULL }
330 };
331
332 static const value_string intel_stimulated_exception_type_vals[] = {
333 { 0x00, "Fatal Exception" },
334 { 0x01, "Debug Exception" },
335 { 0, NULL }
336 };
337
338 static const value_string intel_mem_mode_vals[] = {
339 { 0x00, "Byte Access" },
340 { 0x01, "Half Word Access" },
341 { 0x02, "Word Access" },
342 { 0, NULL }
343 };
344
345
346 void proto_register_bthci_vendor_intel(void);
347 void proto_reg_handoff_bthci_vendor_intel(void);
348
349 static int
350 dissect_bthci_vendor_intel(tvbuff_t *tvb, packet_info *pinfo, proto_tree *tree, void *data)
351 {
352 proto_item *main_item;
353 proto_tree *main_tree;
354 proto_item *opcode_item;
355 proto_tree *opcode_tree;
356 proto_item *sub_item;
357 bluetooth_data_t *bluetooth_data;
358 int offset = 0;
359 int offset_parameters;
360 uint16_t opcode;
361 uint16_t ocf;
362 const char *description;
363 uint8_t length;
364 uint8_t event_code;
365 uint8_t status;
366 uint8_t type;
367 uint32_t interface_id;
368 uint32_t adapter_id;
369
370 bluetooth_data = (bluetooth_data_t *) data;
371 if (bluetooth_data) {
372 interface_id = bluetooth_data->interface_id;
373 adapter_id = bluetooth_data->adapter_id;
374 } else {
375 interface_id = HCI_INTERFACE_DEFAULT;
376 adapter_id = HCI_ADAPTER_DEFAULT;
377 }
378
379 main_item = proto_tree_add_item(tree, proto_bthci_vendor_intel, tvb, 0, -1, ENC_NA);
380 main_tree = proto_item_add_subtree(main_item, ett_intel);
381
382 switch (pinfo->p2p_dir) {
383
384 case P2P_DIR_SENT:
385 col_set_str(pinfo->cinfo, COL_PROTOCOL, "HCI_CMD_INTEL");
386 col_set_str(pinfo->cinfo, COL_INFO, "Sent Intel ");
387
388 opcode_item = proto_tree_add_item(main_tree, hf_intel_opcode, tvb, offset, 2, ENC_LITTLE_ENDIAN);
389 opcode_tree = proto_item_add_subtree(opcode_item, ett_intel_opcode);
390 opcode = tvb_get_letohs(tvb, offset);
391 proto_tree_add_item(opcode_tree, hf_intel_opcode_ogf, tvb, offset, 2, ENC_LITTLE_ENDIAN);
392
393 proto_tree_add_item(opcode_tree, hf_intel_opcode_ocf, tvb, offset, 2, ENC_LITTLE_ENDIAN);
394 ocf = opcode & 0x03ff;
395 offset+=2;
396
397 description = val_to_str_const(ocf, intel_opcode_ocf_vals, "unknown");
398 if (g_strcmp0(description, "unknown") != 0)
399 col_append_str(pinfo->cinfo, COL_INFO, description);
400 else
401 col_append_fstr(pinfo->cinfo, COL_INFO, "Unknown Command 0x%04X (opcode 0x%04X)", ocf, opcode);
402
403 if (have_tap_listener(bluetooth_hci_summary_tap)) {
404 bluetooth_hci_summary_tap_t *tap_hci_summary;
405
406 tap_hci_summary = wmem_new(pinfo->pool, bluetooth_hci_summary_tap_t);
407 tap_hci_summary->interface_id = interface_id;
408 tap_hci_summary->adapter_id = adapter_id;
409
410 tap_hci_summary->type = BLUETOOTH_HCI_SUMMARY_VENDOR_OPCODE;
411 tap_hci_summary->ogf = opcode >> 10;
412 tap_hci_summary->ocf = ocf;
413 if (try_val_to_str(ocf, intel_opcode_ocf_vals))
414 tap_hci_summary->name = description;
415 else
416 tap_hci_summary->name = NULL;
417 tap_queue_packet(bluetooth_hci_summary_tap, pinfo, tap_hci_summary);
418 }
419
420 proto_tree_add_item(main_tree, hf_intel_parameter_length, tvb, offset, 1, ENC_NA);
421 length = tvb_get_uint8(tvb, offset);
422 offset += 1;
423
424 offset_parameters = offset;
425
426 switch(ocf) {
427 case 0x0001: /* Reset */
428 proto_tree_add_item(main_tree, hf_intel_reset_reset_type, tvb, offset, 1, ENC_NA);
429 offset += 1;
430
431 proto_tree_add_item(main_tree, hf_intel_reset_patch_enable, tvb, offset, 1, ENC_NA);
432 offset += 1;
433
434 proto_tree_add_item(main_tree, hf_intel_reset_ddc_reload, tvb, offset, 1, ENC_NA);
435 offset += 1;
436
437 proto_tree_add_item(main_tree, hf_intel_reset_ddc_reload, tvb, offset, 1, ENC_NA);
438 offset += 1;
439
440 proto_tree_add_item(main_tree, hf_intel_reset_boot_option, tvb, offset, 1, ENC_NA);
441 offset += 1;
442
443 proto_tree_add_item(main_tree, hf_intel_reset_boot_address, tvb, offset, 4, ENC_LITTLE_ENDIAN);
444 offset += 4;
445
446 break;
447 case 0x0002: /* No Operation */
448 case 0x0006: /* Set UART Baudrate */
449 case 0x0007: /* Enable LPM */
450 case 0x0008: /* PCM Write Configuration */
451 case 0x000E: /* Write Secure Boot Params */
452 case 0x000F: /* Unlock */
453 case 0x0010: /* Change UART Baudrate */
454 case 0x0012: /* Read Link RSSI */
455 case 0x0022: /* Get Exception Info */
456 case 0x0024: /* Clear Exception Info */
457 case 0x0032: /* Flow Specification */
458 case 0x0034: /* Read Secure ID */
459 case 0x0038: /* Set Synchronous USB Interface Type */
460 case 0x0039: /* Config Synchronous Interface */
461 case 0x0050: /* Read HW Version */
462 case 0x0053: /* Config_Link_Controller */
463 case 0x0089: /* DDC Write */
464 case 0x008A: /* DDC Read */
465 case 0x008C: /* DDC Config Read */
466 case 0x008D: /* Memory Read */
467 /* unknown */
468
469 break;
470 case 0x0005: /* Read Version */
471 case 0x000D: /* Read Secure Boot Params */
472 case 0x0030: /* Read BD Data */
473 case 0x003F: /* SW RF Kill */
474 /* nop */
475
476 break;
477 case 0x0009: /* Secure Send */
478 proto_tree_add_item(main_tree, hf_intel_secure_send_type, tvb, offset, 1, ENC_NA);
479 offset += 1;
480
481 if (length - 1 > 0) {
482 sub_item = proto_tree_add_item(main_tree, hf_intel_data, tvb, offset, length, ENC_NA);
483 expert_add_info(pinfo, sub_item, &ei_intel_undecoded);
484 offset += length - 1;
485 }
486
487 break;
488 case 0x0011: /* Manufacturer Mode */
489 proto_tree_add_item(main_tree, hf_intel_manufacturer_mode, tvb, offset, 1, ENC_NA);
490 offset += 1;
491
492 proto_tree_add_item(main_tree, hf_intel_manufacturer_reset, tvb, offset, 1, ENC_NA);
493 offset += 1;
494
495 break;
496 case 0x002F: /* Write BD Data */
497 offset = dissect_bd_addr(hf_intel_bd_addr, pinfo, main_tree, tvb, offset, false, interface_id, adapter_id, NULL);
498
499 sub_item = proto_tree_add_item(main_tree, hf_intel_data, tvb, offset, 6, ENC_NA);
500 expert_add_info(pinfo, sub_item, &ei_intel_undecoded);
501 offset += 6;
502
503 sub_item = proto_tree_add_item(main_tree, hf_intel_data, tvb, offset, 8, ENC_NA);
504 expert_add_info(pinfo, sub_item, &ei_intel_undecoded);
505 offset += 8;
506
507 sub_item = proto_tree_add_item(main_tree, hf_intel_data, tvb, offset, 1, ENC_NA);
508 expert_add_info(pinfo, sub_item, &ei_intel_undecoded);
509 offset += 1;
510
511 if (length - 6 - 8 - 1 > 0) {
512 sub_item = proto_tree_add_item(main_tree, hf_intel_data, tvb, offset, length - 6 - 8 - 1, ENC_NA);
513 expert_add_info(pinfo, sub_item, &ei_intel_undecoded);
514 offset += length - 6 - 8 - 1;
515 }
516
517 break;
518 case 0x0031: /* Write BD Address */
519 offset = dissect_bd_addr(hf_intel_bd_addr, pinfo, main_tree, tvb, offset, false, interface_id, adapter_id, NULL);
520
521 break;
522 case 0x0043: /* Activate/Deactivate Traces */
523 proto_tree_add_item(main_tree, hf_intel_transmit_traces, tvb, offset, 1, ENC_NA);
524 offset += 1;
525
526 proto_tree_add_item(main_tree, hf_intel_transmit_arq, tvb, offset, 1, ENC_NA);
527 offset += 1;
528
529 proto_tree_add_item(main_tree, hf_intel_receive_traces, tvb, offset, 1, ENC_NA);
530 offset += 1;
531
532 break;
533 case 0x004D: /* Stimulate Exception */
534 proto_tree_add_item(main_tree, hf_intel_stimulated_exception_type, tvb, offset, 1, ENC_NA);
535 offset += 1;
536
537 break;
538 case 0x0052: /* Set Event Mask */
539 proto_tree_add_bitmask(main_tree, tvb, offset, hf_intel_set_event_mask, ett_intel_set_event_mask, hfx_intel_set_event_mask, ENC_LITTLE_ENDIAN);
540 offset += 8;
541
542 break;
543 case 0x008B: /* DDC Config Write */
544 while (length > 0) {
545 uint8_t ddc_config_length;
546
547 proto_tree_add_item(main_tree, hf_intel_ddc_config_length, tvb, offset, 1, ENC_NA);
548 ddc_config_length = tvb_get_uint8(tvb, offset);
549 offset += 1;
550
551 proto_tree_add_item(main_tree, hf_intel_identifier, tvb, offset, 2, ENC_LITTLE_ENDIAN);
552 offset += 2;
553
554 proto_tree_add_item(main_tree, hf_intel_data, tvb, offset, ddc_config_length, ENC_NA);
555 offset += ddc_config_length;
556
557 length -= 1 + 3 + ddc_config_length;
558 }
559
560 break;
561 case 0x008E: /* Memory Write */
562 proto_tree_add_item(main_tree, hf_intel_mem_address, tvb, offset, 4, ENC_LITTLE_ENDIAN);
563 offset += 4;
564
565 proto_tree_add_item(main_tree, hf_intel_mem_mode, tvb, offset, 1, ENC_NA);
566 offset += 1;
567
568 proto_tree_add_item(main_tree, hf_intel_mem_length, tvb, offset, 1, ENC_NA);
569 offset += 1;
570
571 proto_tree_add_item(main_tree, hf_intel_data, tvb, offset, tvb_get_uint8(tvb, offset - 1), ENC_NA);
572 offset += tvb_get_uint8(tvb, offset - 1);
573
574 break;
575 default:
576 if (length > 0) {
577 sub_item = proto_tree_add_item(main_tree, hf_intel_data, tvb, offset, length, ENC_NA);
578 expert_add_info(pinfo, sub_item, &ei_intel_undecoded);
579 offset += length;
580 }
581 }
582
583 if (offset - offset_parameters < length) {
584 sub_item = proto_tree_add_item(main_tree, hf_intel_data, tvb, offset, length - (offset - offset_parameters), ENC_NA);
585 expert_add_info(pinfo, sub_item, &ei_intel_unexpected_parameter);
586 offset += length - (offset - offset_parameters);
587 }
588
589 break;
590 case P2P_DIR_RECV:
591 col_set_str(pinfo->cinfo, COL_PROTOCOL, "HCI_EVT_INTEL");
592 col_set_str(pinfo->cinfo, COL_INFO, "Rcvd Intel ");
593
594 event_code = tvb_get_uint8(tvb, offset);
595
596 if (try_val_to_str(event_code, intel_event_code_vals))
597 description = val_to_str(event_code, intel_event_code_vals, "Unknown 0x%08x");
598 else
599 description = val_to_str_ext(event_code, &bthci_evt_evt_code_vals_ext, "Unknown 0x%08x");
600 col_append_str(pinfo->cinfo, COL_INFO, description);
601 proto_tree_add_item(main_tree, hf_intel_event_code, tvb, offset, 1, ENC_NA);
602 offset += 1;
603
604 if (have_tap_listener(bluetooth_hci_summary_tap)) {
605 bluetooth_hci_summary_tap_t *tap_hci_summary;
606
607 tap_hci_summary = wmem_new(pinfo->pool, bluetooth_hci_summary_tap_t);
608 tap_hci_summary->interface_id = interface_id;
609 tap_hci_summary->adapter_id = adapter_id;
610
611 tap_hci_summary->type = BLUETOOTH_HCI_SUMMARY_VENDOR_EVENT;
612 tap_hci_summary->event = event_code;
613 if (try_val_to_str_ext(event_code, &bthci_evt_evt_code_vals_ext))
614 tap_hci_summary->name = description;
615 else
616 tap_hci_summary->name = NULL;
617 tap_queue_packet(bluetooth_hci_summary_tap, pinfo, tap_hci_summary);
618 }
619
620 proto_tree_add_item(main_tree, hf_intel_parameter_length, tvb, offset, 1, ENC_NA);
621 length = tvb_get_uint8(tvb, offset);
622 offset += 1;
623
624 offset_parameters = offset;
625
626 switch (event_code) {
627 case 0x0e: /* Command Complete */
628 proto_tree_add_item(main_tree, hf_intel_number_of_allowed_command_packets, tvb, offset, 1, ENC_NA);
629 offset += 1;
630
631 opcode_item = proto_tree_add_item(main_tree, hf_intel_opcode, tvb, offset, 2, ENC_LITTLE_ENDIAN);
632 opcode_tree = proto_item_add_subtree(opcode_item, ett_intel_opcode);
633 opcode = tvb_get_letohs(tvb, offset);
634 proto_tree_add_item(opcode_tree, hf_intel_opcode_ogf, tvb, offset, 2, ENC_LITTLE_ENDIAN);
635
636 proto_tree_add_item(opcode_tree, hf_intel_opcode_ocf, tvb, offset, 2, ENC_LITTLE_ENDIAN);
637 ocf = opcode & 0x03ff;
638 offset += 2;
639
640 description = val_to_str_const(ocf, intel_opcode_ocf_vals, "unknown");
641 if (g_strcmp0(description, "unknown") != 0)
642 col_append_fstr(pinfo->cinfo, COL_INFO, " (%s)", description);
643 else
644 col_append_fstr(pinfo->cinfo, COL_INFO, " (Unknown Command 0x%04X [opcode 0x%04X])", ocf, opcode);
645
646 if (have_tap_listener(bluetooth_hci_summary_tap)) {
647 bluetooth_hci_summary_tap_t *tap_hci_summary;
648
649 tap_hci_summary = wmem_new(pinfo->pool, bluetooth_hci_summary_tap_t);
650 tap_hci_summary->interface_id = interface_id;
651 tap_hci_summary->adapter_id = adapter_id;
652
653 tap_hci_summary->type = BLUETOOTH_HCI_SUMMARY_VENDOR_EVENT_OPCODE;
654 tap_hci_summary->ogf = opcode >> 10;
655 tap_hci_summary->ocf = ocf;
656 if (try_val_to_str(ocf, intel_opcode_ocf_vals))
657 tap_hci_summary->name = description;
658 else
659 tap_hci_summary->name = NULL;
660 tap_queue_packet(bluetooth_hci_summary_tap, pinfo, tap_hci_summary);
661 }
662
663 proto_tree_add_item(main_tree, hf_intel_status, tvb, offset, 1, ENC_NA);
664 status = tvb_get_uint8(tvb, offset);
665 offset += 1;
666
667 switch (ocf) {
668 case 0x0001: /* Reset */
669 case 0x0009: /* Secure Send */
670 case 0x0011: /* Manufacturer Mode */
671 case 0x0031: /* Write BD Address */
672 case 0x003F: /* SW RF Kill */
673 case 0x004D: /* Stimulate Exception */
674 case 0x0052: /* Set Event Mask */
675 case 0x008E: /* Memory Write */
676 /* nop */
677
678 break;
679 case 0x0002: /* No Operation */
680 case 0x0006: /* Set UART Baudrate */
681 case 0x0007: /* Enable LPM */
682 case 0x0008: /* PCM Write Configuration */
683 case 0x000D: /* Read Secure Boot Params */
684 case 0x000E: /* Write Secure Boot Params */
685 case 0x000F: /* Unlock */
686 case 0x0010: /* Change UART Baudrate */
687 case 0x0012: /* Read Link RSSI */
688 case 0x0022: /* Get Exception Info */
689 case 0x0024: /* Clear Exception Info */
690 case 0x002F: /* Write BD Data */
691 case 0x0032: /* Flow Specification */
692 case 0x0034: /* Read Secure ID */
693 case 0x0038: /* Set Synchronous USB Interface Type */
694 case 0x0039: /* Config Synchronous Interface */
695 case 0x0043: /* Activate/Deactivate Traces */
696 case 0x0050: /* Read HW Version */
697 case 0x0053: /* Config_Link_Controller */
698 case 0x0089: /* DDC Write */
699 case 0x008A: /* DDC Read */
700 case 0x008C: /* DDC Config Read */
701 case 0x008D: /* Memory Read */
702 /* unknown */
703
704 if (length > 0) {
705 sub_item = proto_tree_add_item(main_tree, hf_intel_data, tvb, offset, length, ENC_NA);
706 if (status == STATUS_SUCCESS)
707 expert_add_info(pinfo, sub_item, &ei_intel_undecoded);
708 else
709 expert_add_info(pinfo, sub_item, &ei_intel_unexpected_parameter);
710 offset += length;
711 }
712 break;
713 case 0x0005: /* Read Version */
714 proto_tree_add_item(main_tree, hf_intel_hardware_platform, tvb, offset, length, ENC_NA);
715 offset += 1;
716
717 proto_tree_add_item(main_tree, hf_intel_hardware_variant, tvb, offset, length, ENC_NA);
718 offset += 1;
719
720 proto_tree_add_item(main_tree, hf_intel_hardware_revision, tvb, offset, length, ENC_NA);
721 offset += 1;
722
723 proto_tree_add_item(main_tree, hf_intel_firmware_variant, tvb, offset, length, ENC_NA);
724 offset += 1;
725
726 proto_tree_add_item(main_tree, hf_intel_firmware_revision, tvb, offset, length, ENC_NA);
727 offset += 1;
728
729 proto_tree_add_item(main_tree, hf_intel_firmware_build_version_nn, tvb, offset, length, ENC_NA);
730 offset += 1;
731
732 proto_tree_add_item(main_tree, hf_intel_firmware_build_version_cw, tvb, offset, length, ENC_NA);
733 offset += 1;
734
735 proto_tree_add_item(main_tree, hf_intel_firmware_build_version_yy, tvb, offset, length, ENC_NA);
736 offset += 1;
737
738 proto_tree_add_item(main_tree, hf_intel_firmware_patch, tvb, offset, length, ENC_NA);
739 offset += 1;
740
741 break;
742 case 0x0030: /* Read BD Data */
743 offset = dissect_bd_addr(hf_intel_bd_addr, pinfo, main_tree, tvb, offset, false, interface_id, adapter_id, NULL);
744
745 break;
746 case 0x008B: /* DDC Config Write */
747 proto_tree_add_item(main_tree, hf_intel_identifier, tvb, offset, 2, ENC_LITTLE_ENDIAN);
748 offset += 2;
749
750 break;
751 default:
752 if (length > 0) {
753 sub_item = proto_tree_add_item(main_tree, hf_intel_data, tvb, offset, length, ENC_NA);
754 if (status == STATUS_SUCCESS)
755 expert_add_info(pinfo, sub_item, &ei_intel_undecoded);
756 else
757 expert_add_info(pinfo, sub_item, &ei_intel_unexpected_parameter);
758 offset += length;
759 }
760
761 break;
762 }
763
764 break;
765
766 case 0x01: /* Fatal Exception */
767 case 0x08: /* Debug Exception */
768 proto_tree_add_item(main_tree, hf_intel_line, tvb, offset, 2, ENC_LITTLE_ENDIAN);
769 offset += 2;
770
771 proto_tree_add_item(main_tree, hf_intel_module, tvb, offset, 1, ENC_NA);
772 offset += 1;
773
774 proto_tree_add_item(main_tree, hf_intel_reason, tvb, offset, 1, ENC_NA);
775 offset += 1;
776
777 break;
778 case 0x02: /* Bootup */
779 proto_tree_add_item(main_tree, hf_intel_zero, tvb, offset, 1, ENC_NA);
780 offset += 1;
781
782 proto_tree_add_item(main_tree, hf_intel_number_of_packets, tvb, offset, 1, ENC_NA);
783 offset += 1;
784
785 proto_tree_add_item(main_tree, hf_intel_source, tvb, offset, 1, ENC_NA);
786 offset += 1;
787
788 proto_tree_add_item(main_tree, hf_intel_reset_type, tvb, offset, 1, ENC_NA);
789 offset += 1;
790
791 proto_tree_add_item(main_tree, hf_intel_reset_reason, tvb, offset, 1, ENC_NA);
792 offset += 1;
793
794 proto_tree_add_item(main_tree, hf_intel_ddc_status, tvb, offset, 1, ENC_NA);
795 offset += 1;
796
797 break;
798 case 0x05: /* Default BD Data */
799 proto_tree_add_item(main_tree, hf_intel_bd_data_status, tvb, offset, 1, ENC_NA);
800 offset += 1;
801
802 break;
803 case 0x06: /* Secure Send Commands Result */
804 proto_tree_add_item(main_tree, hf_intel_secure_send_commands_result, tvb, offset, 1, ENC_NA);
805 offset += 1;
806
807 opcode_item = proto_tree_add_item(main_tree, hf_intel_opcode, tvb, offset, 2, ENC_LITTLE_ENDIAN);
808 opcode_tree = proto_item_add_subtree(opcode_item, ett_intel_opcode);
809 proto_tree_add_item(opcode_tree, hf_intel_opcode_ogf, tvb, offset, 2, ENC_LITTLE_ENDIAN);
810
811 proto_tree_add_item(opcode_tree, hf_intel_opcode_ocf, tvb, offset, 2, ENC_LITTLE_ENDIAN);
812 offset += 2;
813
814 proto_tree_add_item(main_tree, hf_intel_status, tvb, offset, 1, ENC_NA);
815 offset += 1;
816
817 break;
818 case 0x0F: /* LE Link Established */
819 proto_tree_add_item(main_tree, hf_intel_handle, tvb, offset, 2, ENC_LITTLE_ENDIAN);
820 offset += 2;
821
822 sub_item = proto_tree_add_item(main_tree, hf_intel_data, tvb, offset, 8, ENC_NA);
823 expert_add_info(pinfo, sub_item, &ei_intel_undecoded);
824 offset += 8;
825
826 proto_tree_add_item(main_tree, hf_intel_access_address, tvb, offset, 4, ENC_LITTLE_ENDIAN);
827 offset += 4;
828
829 sub_item = proto_tree_add_item(main_tree, hf_intel_data, tvb, offset, length - 2 - 8 - 4, ENC_NA);
830 expert_add_info(pinfo, sub_item, &ei_intel_undecoded);
831 offset += length - 2 - 8 - 4;
832
833 break;
834 case 0x11: /* Scan Status */
835 proto_tree_add_bitmask(main_tree, tvb, offset, hf_intel_scan_status, ett_intel_scan_status, hfx_intel_scan_status, ENC_NA);
836 offset += 1;
837
838 break;
839 case 0x16: /* Activate/Deactivate Traces Complete */
840 proto_tree_add_item(main_tree, hf_intel_status, tvb, offset, 1, ENC_NA);
841 offset += 1;
842
843 break;
844 case 0x17: /* Link PDU Trace */
845 proto_tree_add_item(main_tree, hf_intel_link_pdu_trace_type, tvb, offset, 1, ENC_NA);
846 type = tvb_get_uint8(tvb, offset);
847 offset += 1;
848
849 proto_tree_add_item(main_tree, hf_intel_handle, tvb, offset, 2, ENC_LITTLE_ENDIAN);
850 offset += 2;
851
852 switch (type) {
853 case 0x00: /* LMP Rx*/
854 sub_item = proto_tree_add_item(main_tree, hf_intel_data, tvb, offset, 1, ENC_NA);
855 expert_add_info(pinfo, sub_item, &ei_intel_undecoded);
856 offset += 1;
857
858 call_dissector(btlmp_handle, tvb_new_subset_length(tvb, offset, length - 3 - 4), pinfo, tree);
859 offset += length - 3 - 4;
860
861 proto_tree_add_item(main_tree, hf_intel_link_clock, tvb, offset, 4, ENC_LITTLE_ENDIAN);
862 offset += 4;
863
864 break;
865 case 0x01: /* LMP Tx*/
866 sub_item = proto_tree_add_item(main_tree, hf_intel_data, tvb, offset, 1, ENC_NA);
867 expert_add_info(pinfo, sub_item, &ei_intel_undecoded);
868 offset += 1;
869
870 call_dissector(btlmp_handle, tvb_new_subset_length(tvb, offset, length - 3 - 5), pinfo, tree);
871 offset += length - 3 - 5;
872
873 proto_tree_add_item(main_tree, hf_intel_link_clock, tvb, offset, 4, ENC_LITTLE_ENDIAN);
874 offset += 4;
875
876 proto_tree_add_item(main_tree, hf_intel_link_id, tvb, offset, 1, ENC_NA);
877 offset += 1;
878
879 break;
880 case 0x02: /* LMP Ack */
881 proto_tree_add_item(main_tree, hf_intel_link_clock, tvb, offset, 4, ENC_LITTLE_ENDIAN);
882 offset += 4;
883
884 proto_tree_add_item(main_tree, hf_intel_link_id, tvb, offset, 1, ENC_NA);
885 offset += 1;
886
887 break;
888 case 0x03: /* LL Rx */
889 case 0x04: /* LL Tx */
890 proto_tree_add_item(main_tree, hf_intel_link_count, tvb, offset, 2, ENC_LITTLE_ENDIAN);
891 offset += 2;
892
893 proto_tree_add_item(main_tree, hf_intel_link_id, tvb, offset, 1, ENC_NA);
894 offset += 1;
895
896 sub_item = proto_tree_add_item(main_tree, hf_intel_data, tvb, offset, 2, ENC_NA);
897 expert_add_info(pinfo, sub_item, &ei_intel_undecoded);
898 offset += 2;
899
900 call_dissector(btle_handle, tvb_new_subset_length(tvb, offset, length - 3 - 2 - 1 - 2), pinfo, tree);
901 offset += length - 3 - 2 - 1 - 2;
902
903 break;
904 case 0x05: /* LL Ack */
905 proto_tree_add_item(main_tree, hf_intel_link_count, tvb, offset, 2, ENC_LITTLE_ENDIAN);
906 offset += 2;
907
908 proto_tree_add_item(main_tree, hf_intel_link_id, tvb, offset, 1, ENC_NA);
909 offset += 1;
910
911 break;
912 };
913
914 break;
915 case 0x19: /* Write BD Data Complete */
916 proto_tree_add_item(main_tree, hf_intel_status, tvb, offset, 1, ENC_NA);
917 offset += 1;
918
919 break;
920 case 0x25: /* SCO Rejected via LMP */
921 offset = dissect_bd_addr(hf_intel_bd_addr, pinfo, main_tree, tvb, offset, false, interface_id, adapter_id, NULL);
922
923 proto_tree_add_item(main_tree, hf_intel_reason, tvb, offset, 1, ENC_NA);
924 offset += 1;
925
926 break;
927 case 0x26: /* PTT Switch Notification */
928 proto_tree_add_item(main_tree, hf_intel_handle, tvb, offset, 2, ENC_LITTLE_ENDIAN);
929 offset += 2;
930
931 proto_tree_add_item(main_tree, hf_intel_packet_table, tvb, offset, 1, ENC_NA);
932 offset += 1;
933
934 break;
935 case 0x29: /* System Exception */
936 proto_tree_add_item(main_tree, hf_intel_exception_type, tvb, offset, 1, ENC_NA);
937 offset += 1;
938
939 sub_item = proto_tree_add_item(main_tree, hf_intel_data, tvb, offset, length - 1, ENC_NA);
940 expert_add_info(pinfo, sub_item, &ei_intel_undecoded);
941 offset += length - 1;
942
943 break;
944 case 0x2C: /* FW Trace String */
945 case 0x2E: /* FW Trace Binary */
946 sub_item = proto_tree_add_item(main_tree, hf_intel_data, tvb, offset, length, ENC_NA);
947 expert_add_info(pinfo, sub_item, &ei_intel_undecoded);
948 offset += length;
949
950 break;
951 default:
952 if (length > 0) {
953 sub_item = proto_tree_add_item(main_tree, hf_intel_data, tvb, offset, length, ENC_NA);
954 expert_add_info(pinfo, sub_item, &ei_intel_undecoded);
955 offset += length;
956 }
957 }
958
959 if (offset - offset_parameters < length) {
960 sub_item = proto_tree_add_item(main_tree, hf_intel_data, tvb, offset, length - (offset - offset_parameters), ENC_NA);
961 expert_add_info(pinfo, sub_item, &ei_intel_unexpected_parameter);
962 offset += length - (offset - offset_parameters);
963 }
964
965 break;
966
967 case P2P_DIR_UNKNOWN:
968 default:
969 col_set_str(pinfo->cinfo, COL_PROTOCOL, "HCI_INTEL");
970 col_set_str(pinfo->cinfo, COL_INFO, "UnknownDirection Intel ");
971
972 if (tvb_captured_length_remaining(tvb, offset) > 0) {
973 proto_tree_add_item(main_tree, hf_intel_data, tvb, offset, tvb_captured_length_remaining(tvb, offset), ENC_NA);
974 offset += tvb_captured_length_remaining(tvb, offset);
975 }
976 break;
977 }
978
979 if (tvb_captured_length_remaining(tvb, offset) > 0) {
980 sub_item = proto_tree_add_item(main_tree, hf_intel_data, tvb, offset, tvb_captured_length_remaining(tvb, offset), ENC_NA);
981 expert_add_info(pinfo, sub_item, &ei_intel_unexpected_data);
982 offset += tvb_captured_length_remaining(tvb, offset);
983 }
984
985 return offset;
986 }
987
988 void
989 proto_register_bthci_vendor_intel(void)
990 {
991 expert_module_t *expert_module;
992
993 static hf_register_info hf[] = {
994 { &hf_intel_opcode,
995 { "Command Opcode", "bthci_vendor.intel.opcode",
996 FT_UINT16, BASE_HEX, VALS(intel_opcode_vals), 0x0,
997 "HCI Command Opcode", HFILL }
998 },
999 { &hf_intel_opcode_ogf,
1000 { "Opcode Group Field", "bthci_vendor.intel.opcode.ogf",
1001 FT_UINT16, BASE_HEX|BASE_EXT_STRING, &bthci_cmd_ogf_vals_ext, 0xfc00,
1002 NULL, HFILL }
1003 },
1004 { &hf_intel_opcode_ocf,
1005 { "Opcode Command Field", "bthci_vendor.intel.opcode.ocf",
1006 FT_UINT16, BASE_HEX, VALS(intel_opcode_ocf_vals), 0x03ff,
1007 NULL, HFILL }
1008 },
1009 { &hf_intel_parameter_length,
1010 { "Parameter Total Length", "bthci_vendor.intel.parameter_length",
1011 FT_UINT8, BASE_DEC, NULL, 0x0,
1012 NULL, HFILL }
1013 },
1014 { &hf_intel_number_of_allowed_command_packets,
1015 { "Number of Allowed Command Packets", "bthci_vendor.intel.number_of_allowed_command_packets",
1016 FT_UINT8, BASE_DEC, NULL, 0x0,
1017 NULL, HFILL }
1018 },
1019 { &hf_intel_event_code,
1020 { "Event Code", "bthci_vendor.intel.event_code",
1021 FT_UINT8, BASE_HEX, VALS(intel_event_code_vals), 0x0,
1022 NULL, HFILL }
1023 },
1024 { &hf_intel_status,
1025 { "Status", "bthci_vendor.intel.status",
1026 FT_UINT8, BASE_HEX|BASE_EXT_STRING, &bthci_cmd_status_vals_ext, 0x0,
1027 NULL, HFILL }
1028 },
1029 { &hf_intel_line,
1030 { "Line", "bthci_vendor.intel.line",
1031 FT_UINT16, BASE_DEC, NULL, 0x0,
1032 NULL, HFILL }
1033 },
1034 { &hf_intel_module,
1035 { "Module", "bthci_vendor.intel.module",
1036 FT_UINT8, BASE_HEX, VALS(intel_module_vals), 0x0,
1037 NULL, HFILL }
1038 },
1039 { &hf_intel_reason,
1040 { "Reason", "bthci_vendor.intel.reason",
1041 FT_UINT8, BASE_DEC, NULL, 0x0,
1042 NULL, HFILL }
1043 },
1044 { &hf_intel_zero,
1045 { "Zero", "bthci_vendor.intel.zero",
1046 FT_UINT8, BASE_HEX, NULL, 0x0,
1047 NULL, HFILL }
1048 },
1049 { &hf_intel_number_of_packets,
1050 { "Number of Packets", "bthci_vendor.intel.number_of_packets",
1051 FT_UINT8, BASE_DEC, NULL, 0x0,
1052 NULL, HFILL }
1053 },
1054 { &hf_intel_source,
1055 { "Source", "bthci_vendor.intel.source",
1056 FT_UINT8, BASE_HEX, VALS(intel_source_vals), 0x0,
1057 NULL, HFILL }
1058 },
1059 { &hf_intel_reset_type,
1060 { "Reset Type", "bthci_vendor.intel.reset_type",
1061 FT_UINT8, BASE_HEX, VALS(intel_reset_type_vals), 0x0,
1062 NULL, HFILL }
1063 },
1064 { &hf_intel_reset_reason,
1065 { "Reset Reason", "bthci_vendor.intel.reset_reason",
1066 FT_UINT8, BASE_HEX, VALS(intel_reset_reason_vals), 0x0,
1067 NULL, HFILL }
1068 },
1069 { &hf_intel_ddc_status,
1070 { "DDC Status", "bthci_vendor.intel.ddc_status",
1071 FT_UINT8, BASE_HEX, VALS(intel_ddc_status_vals), 0x0,
1072 NULL, HFILL }
1073 },
1074 { &hf_intel_bd_data_status,
1075 { "BD Data Status", "bthci_vendor.intel.bd_data_status",
1076 FT_UINT8, BASE_HEX, VALS(intel_bd_data_status_vals), 0x0,
1077 NULL, HFILL }
1078 },
1079 { &hf_intel_secure_send_commands_result,
1080 { "Secure Send Commands Result", "bthci_vendor.intel.secure_send_commands_result",
1081 FT_UINT8, BASE_HEX, VALS(intel_secure_send_commands_result_vals), 0x0,
1082 NULL, HFILL }
1083 },
1084 { &hf_intel_handle,
1085 { "Handle", "bthci_vendor.intel.handle",
1086 FT_UINT16, BASE_HEX, NULL, 0x0,
1087 NULL, HFILL }
1088 },
1089 { &hf_intel_access_address,
1090 { "Access Address", "bthci_vendor.intel.access_address",
1091 FT_UINT32, BASE_HEX, NULL, 0x0,
1092 NULL, HFILL }
1093 },
1094 { &hf_intel_scan_status,
1095 { "Scan Status", "bthci_vendor.intel.scan_status",
1096 FT_UINT8, BASE_HEX, NULL, 0x0,
1097 NULL, HFILL }
1098 },
1099 { &hf_intel_scan_status_reserved,
1100 { "Reserved", "bthci_vendor.intel.scan_status.reserved",
1101 FT_UINT8, BASE_HEX, NULL, 0xFC,
1102 NULL, HFILL }
1103 },
1104 { &hf_intel_scan_status_page_scan,
1105 { "Page Scan", "bthci_vendor.intel.scan_status.page_scan",
1106 FT_UINT8, BASE_HEX, NULL, 0x2,
1107 NULL, HFILL }
1108 },
1109 { &hf_intel_scan_status_inquiry_scan,
1110 { "Inquiry Scan", "bthci_vendor.intel.scan_status.inquiry_scan",
1111 FT_UINT8, BASE_HEX, NULL, 0x1,
1112 NULL, HFILL }
1113 },
1114 { &hf_intel_link_pdu_trace_type,
1115 { "Link PDU Trace Type", "bthci_vendor.intel.link_pdu_trace_type",
1116 FT_UINT8, BASE_HEX, VALS(intel_link_pdu_trace_type_vals), 0x0,
1117 NULL, HFILL }
1118 },
1119 { &hf_intel_link_clock,
1120 { "Clock", "bthci_vendor.intel.clock",
1121 FT_UINT32, BASE_HEX, NULL, 0x0,
1122 NULL, HFILL }
1123 },
1124 { &hf_intel_link_id,
1125 { "ID", "bthci_vendor.intel.id",
1126 FT_UINT8, BASE_HEX, NULL, 0x0,
1127 NULL, HFILL }
1128 },
1129 { &hf_intel_link_count,
1130 { "Count", "bthci_vendor.intel.count",
1131 FT_UINT16, BASE_DEC, NULL, 0x0,
1132 NULL, HFILL }
1133 },
1134 { &hf_intel_bd_addr,
1135 { "BD_ADDR", "bthci_vendor.intel.bd_addr",
1136 FT_ETHER, BASE_NONE, NULL, 0x0,
1137 "Bluetooth Device Address", HFILL}
1138 },
1139 { &hf_intel_packet_table,
1140 { "Packet Table", "bthci_vendor.intel.packet_table",
1141 FT_UINT8, BASE_HEX, VALS(intel_packet_table_vals), 0x0,
1142 NULL, HFILL }
1143 },
1144 { &hf_intel_exception_type,
1145 { "Exception Type", "bthci_vendor.intel.exception_type",
1146 FT_UINT8, BASE_HEX, VALS(intel_exception_type_vals), 0x0,
1147 NULL, HFILL }
1148 },
1149 { &hf_intel_reset_reset_type,
1150 { "Type", "bthci_vendor.intel.reset.type",
1151 FT_UINT8, BASE_HEX, VALS(intel_reset_reset_type_vals), 0x0,
1152 NULL, HFILL }
1153 },
1154 { &hf_intel_reset_patch_enable,
1155 { "Patch Enable", "bthci_vendor.intel.reset.patch_enable",
1156 FT_UINT8, BASE_HEX, VALS(intel_reset_patch_enable_vals), 0x0,
1157 NULL, HFILL }
1158 },
1159 { &hf_intel_reset_ddc_reload,
1160 { "DDC Reload", "bthci_vendor.intel.reset.ddc_reload",
1161 FT_UINT8, BASE_HEX, VALS(intel_reset_ddc_reload_vals), 0x0,
1162 NULL, HFILL }
1163 },
1164 { &hf_intel_reset_boot_option,
1165 { "Boot Option", "bthci_vendor.intel.reset.boot.option",
1166 FT_UINT8, BASE_HEX, NULL, 0x0,
1167 NULL, HFILL }
1168 },
1169 { &hf_intel_reset_boot_address,
1170 { "Boot Address", "bthci_vendor.intel.reset.boot.address",
1171 FT_UINT32, BASE_HEX, NULL, 0x0,
1172 NULL, HFILL }
1173 },
1174 { &hf_intel_hardware_platform,
1175 { "Hardware Platform", "bthci_vendor.intel.hardware.platform",
1176 FT_UINT8, BASE_HEX, NULL, 0x0,
1177 NULL, HFILL }
1178 },
1179 { &hf_intel_hardware_variant,
1180 { "Hardware Variant", "bthci_vendor.intel.hardware.variant",
1181 FT_UINT8, BASE_HEX, NULL, 0x0,
1182 NULL, HFILL }
1183 },
1184 { &hf_intel_hardware_revision,
1185 { "Hardware Revision", "bthci_vendor.intel.hardware.revision",
1186 FT_UINT8, BASE_HEX, NULL, 0x0,
1187 NULL, HFILL }
1188 },
1189 { &hf_intel_firmware_variant,
1190 { "Firmware Variant", "bthci_vendor.intel.firmware.variant",
1191 FT_UINT8, BASE_HEX, NULL, 0x0,
1192 NULL, HFILL }
1193 },
1194 { &hf_intel_firmware_revision,
1195 { "Firmware Revision", "bthci_vendor.intel.firmware.revision",
1196 FT_UINT8, BASE_HEX, NULL, 0x0,
1197 NULL, HFILL }
1198 },
1199 { &hf_intel_firmware_build_version_nn,
1200 { "Firmware Build Version nn", "bthci_vendor.intel.firmware.build_version.nn",
1201 FT_UINT8, BASE_DEC, NULL, 0x0,
1202 NULL, HFILL }
1203 },
1204 { &hf_intel_firmware_build_version_cw,
1205 { "Firmware Build Version cw", "bthci_vendor.intel.firmware.build_version.cw",
1206 FT_UINT8, BASE_DEC, NULL, 0x0,
1207 NULL, HFILL }
1208 },
1209 { &hf_intel_firmware_build_version_yy,
1210 { "Firmware Build Version yy", "bthci_vendor.intel.firmware.build_version.yy",
1211 FT_UINT8, BASE_DEC, NULL, 0x0,
1212 NULL, HFILL }
1213 },
1214 { &hf_intel_firmware_patch,
1215 { "Firmware Patch", "bthci_vendor.intel.firmware.patch",
1216 FT_UINT8, BASE_DEC, NULL, 0x0,
1217 NULL, HFILL }
1218 },
1219 { &hf_intel_identifier,
1220 { "Identifier", "bthci_vendor.intel.identifier",
1221 FT_UINT16, BASE_HEX, NULL, 0x0,
1222 NULL, HFILL }
1223 },
1224 { &hf_intel_secure_send_type,
1225 { "Type", "bthci_vendor.intel.secure_send.type",
1226 FT_UINT8, BASE_HEX, VALS(intel_secure_send_type_vals), 0x0,
1227 NULL, HFILL }
1228 },
1229 { &hf_intel_manufacturer_mode,
1230 { "Manufacturer Mode", "bthci_vendor.intel.manufacturer.mode",
1231 FT_UINT8, BASE_HEX, VALS(intel_manufacturer_mode_vals), 0x0,
1232 NULL, HFILL }
1233 },
1234 { &hf_intel_manufacturer_reset,
1235 { "Manufacturer Reset", "bthci_vendor.intel.manufacturer.reset",
1236 FT_UINT8, BASE_HEX, VALS(intel_manufacturer_reset_vals), 0x0,
1237 NULL, HFILL }
1238 },
1239 { &hf_intel_transmit_traces,
1240 { "Transmit Traces", "bthci_vendor.intel.transmit_traces",
1241 FT_UINT8, BASE_DEC, NULL, 0x0,
1242 NULL, HFILL }
1243 },
1244 { &hf_intel_transmit_arq,
1245 { "Transmit ARQ", "bthci_vendor.intel.transmit_arq",
1246 FT_UINT8, BASE_HEX, NULL, 0x0,
1247 NULL, HFILL }
1248 },
1249 { &hf_intel_receive_traces,
1250 { "Receive Traces", "bthci_vendor.intel.receive_traces",
1251 FT_UINT8, BASE_DEC, NULL, 0x0,
1252 NULL, HFILL }
1253 },
1254 { &hf_intel_stimulated_exception_type,
1255 { "Stimulated Exception Type", "bthci_vendor.intel.stimulated_exception_type",
1256 FT_UINT8, BASE_HEX, VALS(intel_stimulated_exception_type_vals), 0x0,
1257 NULL, HFILL }
1258 },
1259 { &hf_intel_mem_address,
1260 { "Address", "bthci_vendor.intel.mem.address",
1261 FT_UINT32, BASE_HEX, NULL, 0x0,
1262 NULL, HFILL }
1263 },
1264 { &hf_intel_mem_mode,
1265 { "Mode", "bthci_vendor.intel.mem.mode",
1266 FT_UINT8, BASE_HEX, VALS(intel_mem_mode_vals), 0x0,
1267 NULL, HFILL }
1268 },
1269 { &hf_intel_mem_length,
1270 { "Length", "bthci_vendor.intel.mem.length",
1271 FT_UINT8, BASE_DEC, NULL, 0x0,
1272 NULL, HFILL }
1273 },
1274 { &hf_intel_ddc_config_length,
1275 { "Length", "bthci_vendor.intel.ddc_config.length",
1276 FT_UINT8, BASE_DEC, NULL, 0x0,
1277 NULL, HFILL }
1278 },
1279 { &hf_intel_set_event_mask,
1280 { "Event Mask", "bthci_vendor.intel.event_mask",
1281 FT_UINT64, BASE_HEX, NULL, 0x0,
1282 NULL, HFILL }
1283 },
1284 { &hf_intel_set_event_mask_reserved_15_63,
1285 { "Reserved", "bthci_vendor.intel.event_mask.reserved.15_63",
1286 FT_UINT64, BASE_HEX, NULL, UINT64_C(0xFFFFFFFFFFFF8000),
1287 NULL, HFILL }
1288 },
1289 { &hf_intel_set_event_mask_firmware_trace_string,
1290 { "Firmware Trace String", "bthci_vendor.intel.event_mask.firmware_trace_string",
1291 FT_BOOLEAN, 64, NULL, 0x0000000000004000,
1292 NULL, HFILL }
1293 },
1294 { &hf_intel_set_event_mask_le_link_established,
1295 { "LE Link_Established", "bthci_vendor.intel.event_mask.le_link_established",
1296 FT_BOOLEAN, 64, NULL, 0x0000000000002000,
1297 NULL, HFILL }
1298 },
1299 { &hf_intel_set_event_mask_reserved_12,
1300 { "Reserved", "bthci_vendor.intel.event_mask.reserved.12",
1301 FT_UINT64, BASE_HEX, NULL, 0x0000000000001000,
1302 NULL, HFILL }
1303 },
1304 { &hf_intel_set_event_mask_system_exception,
1305 { "System Exception", "bthci_vendor.intel.event_mask.system_exception",
1306 FT_BOOLEAN, 64, NULL, 0x0000000000000800,
1307 NULL, HFILL }
1308 },
1309 { &hf_intel_set_event_mask_fatal_exception,
1310 { "Fatal Exception", "bthci_vendor.intel.event_mask.fatal_exception",
1311 FT_BOOLEAN, 64, NULL, 0x0000000000000400,
1312 NULL, HFILL }
1313 },
1314 { &hf_intel_set_event_mask_debug_exception,
1315 { "Debug Exception", "bthci_vendor.intel.event_mask.debug_exception",
1316 FT_BOOLEAN, 64, NULL, 0x0000000000000200,
1317 NULL, HFILL }
1318 },
1319 { &hf_intel_set_event_mask_reserved_8,
1320 { "Reserved", "bthci_vendor.intel.event_mask.reserved",
1321 FT_UINT64, BASE_HEX, NULL, 0x0000000000000100,
1322 NULL, HFILL }
1323 },
1324 { &hf_intel_set_event_mask_scan_status,
1325 { "Scan Status", "bthci_vendor.intel.event_mask.scan_status",
1326 FT_BOOLEAN, 64, NULL, 0x0000000000000080,
1327 NULL, HFILL }
1328 },
1329 { &hf_intel_set_event_mask_reserved_3_6,
1330 { "Reserved", "bthci_vendor.intel.event_mask.reserved.3_6",
1331 FT_UINT64, BASE_HEX, NULL, 0x0000000000000078,
1332 NULL, HFILL }
1333 },
1334 { &hf_intel_set_event_mask_ptt_switch_notification,
1335 { "PTT Switch Notification", "bthci_vendor.intel.event_mask.ptt_switch_notification",
1336 FT_BOOLEAN, 64, NULL, 0x0000000000000004,
1337 NULL, HFILL }
1338 },
1339 { &hf_intel_set_event_mask_sco_rejected_via_lmp,
1340 { "SCO Rejected via LMP", "bthci_vendor.intel.event_mask.sco_rejected_via_lmp",
1341 FT_BOOLEAN, 64, NULL, 0x0000000000000002,
1342 NULL, HFILL }
1343 },
1344 { &hf_intel_set_event_mask_bootup,
1345 { "Bootup", "bthci_vendor.intel.event_mask.bootup",
1346 FT_BOOLEAN, 64, NULL, 0x0000000000000001,
1347 NULL, HFILL }
1348 },
1349 { &hf_intel_data,
1350 { "Data", "bthci_vendor.intel.data",
1351 FT_NONE, BASE_NONE, NULL, 0x0,
1352 NULL, HFILL }
1353 },
1354 };
1355
1356 static int *ett[] = {
1357 &ett_intel,
1358 &ett_intel_opcode,
1359 &ett_intel_scan_status,
1360 &ett_intel_set_event_mask
1361 };
1362
1363 static ei_register_info ei[] = {
1364 { &ei_intel_undecoded, { "bthci_vendor.intel.undecoded", PI_UNDECODED, PI_NOTE, "Undecoded", EXPFILL }},
1365 { &ei_intel_unexpected_parameter, { "bthci_vendor.intel.unexpected_parameter", PI_PROTOCOL, PI_WARN, "Unexpected parameter", EXPFILL }},
1366 { &ei_intel_unexpected_data, { "bthci_vendor.intel.unexpected_data", PI_PROTOCOL, PI_WARN, "Unexpected data", EXPFILL }},
1367 };
1368
1369 proto_bthci_vendor_intel = proto_register_protocol("Bluetooth Intel HCI",
1370 "HCI Intel", "bthci_vendor.intel");
1371
1372 bthci_vendor_intel_handle = register_dissector("bthci_vendor.intel", dissect_bthci_vendor_intel, proto_bthci_vendor_intel);
1373
1374 proto_register_field_array(proto_bthci_vendor_intel, hf, array_length(hf));
1375 proto_register_subtree_array(ett, array_length(ett));
1376
1377 expert_module = expert_register_protocol(proto_bthci_vendor_intel);
1378 expert_register_field_array(expert_module, ei, array_length(ei));
1379 }
1380
1381 void
1382 proto_reg_handoff_bthci_vendor_intel(void)
1383 {
1384 btlmp_handle = find_dissector_add_dependency("btlmp", proto_bthci_vendor_intel);
1385 btle_handle = find_dissector_add_dependency("btle", proto_bthci_vendor_intel);
1386
1387 dissector_add_for_decode_as("bthci_cmd.vendor", bthci_vendor_intel_handle);
1388
1389 dissector_add_uint("bluetooth.vendor", 0x0002, bthci_vendor_intel_handle);
1390 }
1391
1392 /*
1393 * Editor modelines - https://www.wireshark.org/tools/modelines.html
1394 *
1395 * Local variables:
1396 * c-basic-offset: 4
1397 * tab-width: 8
1398 * indent-tabs-mode: nil
1399 * End:
1400 *
1401 * vi: set shiftwidth=4 tabstop=8 expandtab:
1402 * :indentSize=4:tabSize=8:noTabs=true:
1403 */
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