plugins/epan/wimax/msg_reg_req.c

   1 /* msg_reg_req.c
   2  * WiMax MAC Management REG-REQ Message decoder
   3  *
   4  * Copyright (c) 2007 by Intel Corporation.
   5  *
   6  * Author: John R. Underwood <junderx@yahoo.com>
   7  *
   8  * Wireshark - Network traffic analyzer
   9  * By Gerald Combs <gerald@wireshark.org>
  10  * Copyright 1999 Gerald Combs
  11  *
  12  * SPDX-License-Identifier: GPL-2.0-or-later
  13  */
  14
  15 /* Include files */
  16
  17 #include "config.h"
  18
  19 #define WIMAX_16E_2005
  20
  21 #include <epan/packet.h>
  22 #include <epan/tfs.h>
  23 #include <wsutil/array.h>
  24 #include "wimax_tlv.h"
  25 #include "wimax_mac.h"
  26 #include "wimax_utils.h"
  27 #include "wimax_prefs.h"
  28
  29 void proto_register_mac_mgmt_msg_reg_req(void);
  30 void proto_reg_handoff_mac_mgmt_msg_reg_req(void);
  31
  32 static dissector_handle_t reg_req_handle;
  33
  34 static int proto_mac_mgmt_msg_reg_req_decoder;
  35 static int ett_mac_mgmt_msg_reg_req_decoder;
  36
  37 /* REG-REQ fields */
  38 static int hf_reg_ss_mgmt_support;
  39 static int hf_reg_ip_mgmt_mode;
  40 static int hf_reg_ip_version;
  41 static int hf_reg_req_secondary_mgmt_cid;
  42 static int hf_reg_ul_cids;
  43 static int hf_reg_max_classifiers;
  44 static int hf_reg_phs;
  45 static int hf_reg_arq;
  46 static int hf_reg_dsx_flow_control;
  47 static int hf_reg_mac_crc_support;
  48 static int hf_reg_mca_flow_control;
  49 static int hf_reg_mcast_polling_cids;
  50 static int hf_reg_num_dl_trans_cid;
  51 static int hf_reg_mac_address;
  52 static int hf_reg_tlv_t_20_1_max_mac_level_data_per_dl_frame;
  53 static int hf_reg_tlv_t_20_2_max_mac_level_data_per_ul_frame;
  54 static int hf_reg_tlv_t_21_packing_support;
  55 static int hf_reg_tlv_t_22_mac_extended_rtps_support;
  56 static int hf_reg_tlv_t_23_max_num_bursts_concurrently_to_the_ms;
  57 static int hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_dhcp;
  58 static int hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_mobile_ipv4;
  59 static int hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_dhcpv6;
  60 static int hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_ipv6;
  61 static int hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_rsvd;
  62 static int hf_reg_tlv_t_27_handover_fbss_mdho_ho_disable;
  63 static int hf_reg_tlv_t_27_handover_fbss_mdho_dl_rf_monitoring_maps;
  64 static int hf_reg_tlv_t_27_handover_mdho_dl_monitoring_single_map;
  65 static int hf_reg_tlv_t_27_handover_mdho_dl_monitoring_maps;
  66 static int hf_reg_tlv_t_27_handover_mdho_ul_multiple;
  67 static int hf_reg_tlv_t_27_handover_reserved;
  68 static int hf_reg_tlv_t_29_ho_process_opt_ms_timer;
  69 static int hf_reg_tlv_t_31_mobility_handover;
  70 static int hf_reg_tlv_t_31_mobility_sleep_mode;
  71 static int hf_reg_tlv_t_31_mobility_idle_mode;
  72 static int hf_reg_req_tlv_t_32_sleep_mode_recovery_time;
  73 static int hf_ms_previous_ip_address_v4;
  74 static int hf_ms_previous_ip_address_v6;
  75 static int hf_idle_mode_timeout;
  76 static int hf_reg_req_tlv_t_45_ms_periodic_ranging_timer;
  77 static int hf_reg_tlv_t_40_arq_ack_type_selective_ack_entry;
  78 static int hf_reg_tlv_t_40_arq_ack_type_cumulative_ack_entry;
  79 static int hf_reg_tlv_t_40_arq_ack_type_cumulative_with_selective_ack_entry;
  80 static int hf_reg_tlv_t_40_arq_ack_type_cumulative_ack_with_block_sequence_ack;
  81 static int hf_reg_tlv_t_40_arq_ack_type_reserved;
  82 static int hf_reg_tlv_t_41_ho_connections_param_processing_time;
  83 static int hf_reg_tlv_t_42_ho_tek_processing_time;
  84 static int hf_reg_tlv_t_43_bandwidth_request_ul_tx_power_report_header_support;
  85 static int hf_reg_tlv_t_43_bandwidth_request_cinr_report_header_support;
  86 static int hf_reg_tlv_t_43_cqich_allocation_request_header_support;
  87 static int hf_reg_tlv_t_43_phy_channel_report_header_support;
  88 static int hf_reg_tlv_t_43_bandwidth_request_ul_sleep_control_header_support;
  89 static int hf_reg_tlv_t_43_sn_report_header_support;
  90 static int hf_reg_tlv_t_43_feedback_header_support;
  91 static int hf_reg_tlv_t_43_sdu_sn_extended_subheader_support_and_parameter;
  92 static int hf_reg_tlv_t_43_sdu_sn_parameter;
  93 static int hf_reg_tlv_t_43_dl_sleep_control_extended_subheader;
  94 static int hf_reg_tlv_t_43_feedback_request_extended_subheader;
  95 static int hf_reg_tlv_t_43_mimo_mode_feedback_extended_subheader;
  96 static int hf_reg_tlv_t_43_ul_tx_power_report_extended_subheader;
  97 static int hf_reg_tlv_t_43_mini_feedback_extended_subheader;
  98 static int hf_reg_tlv_t_43_sn_request_extended_subheader;
  99 static int hf_reg_tlv_t_43_pdu_sn_short_extended_subheader;
 100 static int hf_reg_tlv_t_43_pdu_sn_long_extended_subheader;
 101 static int hf_reg_tlv_t_43_reserved;
 102 static int hf_reg_tlv_t_46_handover_indication_readiness_timer;
 103 static int hf_reg_req_min_time_for_intra_fa;
 104 static int hf_reg_req_min_time_for_inter_fa;
 105 static int hf_reg_encap_atm_4;
 106 static int hf_reg_encap_ipv4_4;
 107 static int hf_reg_encap_ipv6_4;
 108 static int hf_reg_encap_802_3_4;
 109 static int hf_reg_encap_802_1q_4;
 110 static int hf_reg_encap_ipv4_802_3_4;
 111 static int hf_reg_encap_ipv6_802_3_4;
 112 static int hf_reg_encap_ipv4_802_1q_4;
 113 static int hf_reg_encap_ipv6_802_1q_4;
 114 static int hf_reg_encap_packet_8023_ethernet_and_rohc_header_compression_4;
 115 static int hf_reg_encap_packet_8023_ethernet_and_ecrtp_header_compression_4;
 116 static int hf_reg_encap_packet_ip_rohc_header_compression_4;
 117 static int hf_reg_encap_packet_ip_ecrtp_header_compression_4;
 118 static int hf_reg_encap_rsvd_4;
 119 static int hf_reg_encap_atm_2;
 120 static int hf_reg_encap_ipv4_2;
 121 static int hf_reg_encap_ipv6_2;
 122 static int hf_reg_encap_802_3_2;
 123 static int hf_reg_encap_802_1q_2;
 124 static int hf_reg_encap_ipv4_802_3_2;
 125 static int hf_reg_encap_ipv6_802_3_2;
 126 static int hf_reg_encap_ipv4_802_1q_2;
 127 static int hf_reg_encap_ipv6_802_1q_2;
 128 static int hf_reg_encap_packet_8023_ethernet_and_rohc_header_compression_2;
 129 static int hf_reg_encap_packet_8023_ethernet_and_ecrtp_header_compression_2;
 130 static int hf_reg_encap_packet_ip_rohc_header_compression_2;
 131 static int hf_reg_encap_packet_ip_ecrtp_header_compression_2;
 132 static int hf_reg_encap_rsvd_2;
 133 static int hf_tlv_type;
 134 static int hf_reg_invalid_tlv;
 135 static int hf_reg_power_saving_class_type_i;
 136 static int hf_reg_power_saving_class_type_ii;
 137 static int hf_reg_power_saving_class_type_iii;
 138 static int hf_reg_multi_active_power_saving_classes;
 139 static int hf_reg_total_power_saving_class_instances;
 140 static int hf_reg_power_saving_class_reserved;
 141 static int hf_reg_power_saving_class_capability;
 142 static int hf_reg_ip_phs_sdu_encap;
 143 static int hf_reg_tlv_t_26_method_alloc_ip_addr_secondary_mgmnt_conn;
 144 static int hf_reg_tlv_t_27_handover_supported;
 145 static int hf_reg_tlv_t_31_mobility_features_supported;
 146 static int hf_reg_tlv_t_40_arq_ack_type;
 147 static int hf_reg_tlv_t_43_mac_header_ext_header_support;
 148 static int hf_reg_req_bs_switching_timer;
 149
 150 /* STRING RESOURCES */
 151
 152 static const true_false_string tfs_reg_ip_mgmt_mode = {
 153         "IP-managed mode",
 154         "Unmanaged mode"
 155 };
 156
 157 static const true_false_string tfs_reg_ss_mgmt_support = {
 158         "secondary management connection",
 159         "no secondary management connection"
 160 };
 161
 162 #if 0
 163 static const true_false_string tfs_arq_enable = {
 164         "ARQ Requested/Accepted",
 165         "ARQ Not Requested/Accepted"
 166 };
 167 #endif
 168
 169 #if 0
 170 static const true_false_string tfs_arq_deliver_in_order = {
 171         "Order of delivery is preserved",
 172         "Order of delivery is not preserved"
 173 };
 174 #endif
 175
 176 static const true_false_string tfs_reg_fbss_mdho_ho_disable = {
 177         "Disable",
 178         "Enable"
 179 };
 180
 181 static const value_string vals_reg_ip_version[] = {
 182         {0x1, "IPv4"},
 183         {0x2, "IPV6"},
 184         {0, NULL}
 185 };
 186
 187 static const value_string vals_reg_phs_support[] = {
 188         {0, "no PHS support"},
 189         {1, "ATM PHS"},
 190         {2, "Packet PHS"},
 191         {3, "ATM and Packet PHS"},
 192         {0, NULL}
 193 };
 194
 195 static const true_false_string tfs_supported = {
 196         "supported",
 197         "unsupported"
 198 };
 199
 200 static const true_false_string tfs_mac_crc_support = {
 201         "MAC CRC Support (Default)",
 202         "No MAC CRC Support"
 203 };
 204
 205 static const value_string tfs_support[] = {
 206         {0, "not supported"},
 207         {1, "supported"},
 208         {0, NULL}
 209 };
 210
 211 static const value_string unique_no_limit[] = {
 212         {0, "no limit"},
 213         {0, NULL}
 214 };
 215
 216 /* Decode REG-REQ sub-TLV's. */
 217 void dissect_extended_tlv(proto_tree *reg_req_tree, int tlv_type, tvbuff_t *tvb, unsigned tlv_offset, unsigned tlv_len, packet_info *pinfo, unsigned offset, int proto_registry)
 218 {
 219         proto_item *tlv_item;
 220         proto_tree *tlv_tree;
 221         unsigned tvb_len;
 222         tlv_info_t tlv_info;
 223         unsigned tlv_end;
 224         unsigned length;
 225         unsigned nblocks;
 226
 227         /* Get the tvb reported length */
 228         tvb_len =  tvb_reported_length(tvb);
 229
 230         /* get the TLV information */
 231         init_tlv_info(&tlv_info, tvb, offset);
 232
 233 #ifdef WIMAX_16E_2005
 234         switch (tlv_type) {
 235                 case REG_ARQ_PARAMETERS:
 236                         /* display ARQ Service Flow Encodings info */
 237                         /* add subtree */
 238                         tlv_tree = add_protocol_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_registry, tvb, offset, tlv_len, "ARQ Service Flow Encodings");
 239                         /* decode and display the DL Service Flow Encodings */
 240                         wimax_service_flow_encodings_decoder(tvb_new_subset_length(tvb, tlv_offset, tlv_len), pinfo, tlv_tree);
 241                         break;
 242                 case REG_SS_MGMT_SUPPORT:
 243                         add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_ss_mgmt_support, tvb, offset, ENC_BIG_ENDIAN);
 244                         break;
 245                 case REG_IP_MGMT_MODE:
 246                         add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_ip_mgmt_mode, tvb, offset, ENC_BIG_ENDIAN);
 247                         break;
 248                 case REG_IP_VERSION:
 249                         add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_ip_version, tvb, offset, ENC_BIG_ENDIAN);
 250                         break;
 251                 case REG_UL_TRANSPORT_CIDS_SUPPORTED:
 252                         add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_ul_cids, tvb, offset, ENC_BIG_ENDIAN);
 253                         break;
 254
 255                 case REG_POWER_SAVING_CLASS_CAPABILITY:
 256                         tlv_item = add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_power_saving_class_capability, tvb, offset, ENC_BIG_ENDIAN);
 257                         tlv_tree = proto_item_add_subtree(tlv_item, ett_mac_mgmt_msg_reg_req_decoder);
 258                         proto_tree_add_item(tlv_tree, hf_reg_power_saving_class_type_i, tvb, tlv_offset, 2, ENC_BIG_ENDIAN);
 259                         proto_tree_add_item(tlv_tree, hf_reg_power_saving_class_type_ii, tvb, tlv_offset, 2, ENC_BIG_ENDIAN);
 260                         proto_tree_add_item(tlv_tree, hf_reg_power_saving_class_type_iii, tvb, tlv_offset, 2, ENC_BIG_ENDIAN);
 261                         proto_tree_add_item(tlv_tree, hf_reg_multi_active_power_saving_classes, tvb, tlv_offset, 2, ENC_BIG_ENDIAN);
 262                         proto_tree_add_item(tlv_tree, hf_reg_total_power_saving_class_instances, tvb, tlv_offset, 2, ENC_BIG_ENDIAN);
 263                         proto_tree_add_item(tlv_tree, hf_reg_power_saving_class_reserved, tvb, tlv_offset, 2, ENC_BIG_ENDIAN);
 264                         break;
 265                 case REG_IP_PHS_SDU_ENCAP:
 266                         tlv_item = add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_ip_phs_sdu_encap, tvb, offset, ENC_BIG_ENDIAN);
 267                         tlv_tree = proto_item_add_subtree(tlv_item, ett_mac_mgmt_msg_reg_req_decoder);
 268
 269 #ifdef WIMAX_16E_2005
 270                         if (tlv_len == 2){
 271                                 proto_tree_add_item(tlv_tree, hf_reg_encap_atm_2, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
 272                                 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv4_2, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
 273                                 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv6_2, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
 274                                 proto_tree_add_item(tlv_tree, hf_reg_encap_802_3_2, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
 275                                 proto_tree_add_item(tlv_tree, hf_reg_encap_802_1q_2, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
 276                                 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv4_802_3_2, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
 277                                 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv6_802_3_2, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
 278                                 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv4_802_1q_2, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
 279                                 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv6_802_1q_2, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
 280                                 proto_tree_add_item(tlv_tree, hf_reg_encap_packet_8023_ethernet_and_rohc_header_compression_2, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
 281                                 proto_tree_add_item(tlv_tree, hf_reg_encap_packet_8023_ethernet_and_ecrtp_header_compression_2, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
 282                                 proto_tree_add_item(tlv_tree, hf_reg_encap_packet_ip_rohc_header_compression_2, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
 283                                 proto_tree_add_item(tlv_tree, hf_reg_encap_packet_ip_ecrtp_header_compression_2, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
 284                                 proto_tree_add_item(tlv_tree, hf_reg_encap_rsvd_2, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
 285                         } else if(tlv_len == 4){
 286                                 proto_tree_add_item(tlv_tree, hf_reg_encap_atm_4, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
 287                                 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv4_4, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
 288                                 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv6_4, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
 289                                 proto_tree_add_item(tlv_tree, hf_reg_encap_802_3_4, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
 290                                 proto_tree_add_item(tlv_tree, hf_reg_encap_802_1q_4, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
 291                                 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv4_802_3_4, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
 292                                 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv6_802_3_4, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
 293                                 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv4_802_1q_4, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
 294                                 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv6_802_1q_4, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
 295                                 proto_tree_add_item(tlv_tree, hf_reg_encap_packet_8023_ethernet_and_rohc_header_compression_4, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
 296                                 proto_tree_add_item(tlv_tree, hf_reg_encap_packet_8023_ethernet_and_ecrtp_header_compression_4, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
 297                                 proto_tree_add_item(tlv_tree, hf_reg_encap_packet_ip_rohc_header_compression_4, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
 298                                 proto_tree_add_item(tlv_tree, hf_reg_encap_packet_ip_ecrtp_header_compression_4, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
 299                                 proto_tree_add_item(tlv_tree, hf_reg_encap_rsvd_4, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
 300                         }
 301 #endif
 302                         break;
 303                 case REG_MAX_CLASSIFIERS_SUPPORTED:
 304                         add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_max_classifiers, tvb, offset, ENC_BIG_ENDIAN);
 305                         break;
 306                 case REG_PHS_SUPPORT:
 307                         add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_phs, tvb, offset, ENC_BIG_ENDIAN);
 308                         break;
 309                 case REG_ARQ_SUPPORT:
 310                         add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_arq, tvb, offset, ENC_BIG_ENDIAN);
 311                         break;
 312                 case REG_DSX_FLOW_CONTROL:
 313                         add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_dsx_flow_control, tvb, offset, ENC_BIG_ENDIAN);
 314                         break;
 315                 case REG_MAC_CRC_SUPPORT:
 316                         if (!include_cor2_changes) {
 317                                 add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_mac_crc_support, tvb, offset, ENC_NA);
 318                         } else {
 319                                 /* Unknown TLV Type */
 320                                 add_tlv_subtree(&tlv_info, reg_req_tree, hf_tlv_type, tvb, offset, ENC_NA);
 321                         }
 322                         break;
 323                 case REG_MCA_FLOW_CONTROL:
 324                         add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_mca_flow_control, tvb, offset, ENC_BIG_ENDIAN);
 325                         break;
 326                 case REG_MCAST_POLLING_CIDS:
 327                         add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_mcast_polling_cids, tvb, offset, ENC_BIG_ENDIAN);
 328                         break;
 329                 case REG_NUM_DL_TRANS_CID:
 330                         add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_num_dl_trans_cid, tvb, offset, ENC_BIG_ENDIAN);
 331                         break;
 332                 case REG_MAC_ADDRESS:
 333                         add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_mac_address, tvb, offset, ENC_NA);
 334                         break;
 335                 case REG_TLV_T_20_MAX_MAC_DATA_PER_FRAME_SUPPORT:
 336                         /* display Maximum MAC level data per frame info */
 337                         /* add subtree */
 338                         tlv_tree = add_protocol_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_registry, tvb, offset, tlv_len, "Maximum MAC level data per frame");
 339                         /* decode and display Maximum MAC level data per frame for UL & DL */
 340                         /* Set endpoint of the subTLVs (tlv_offset + length) */
 341                         tlv_end = tlv_offset + tlv_len;
 342                         /* process subTLVs */
 343                         while ( tlv_offset < tlv_end )
 344                         {       /* get the TLV information */
 345                                 init_tlv_info(&tlv_info, tvb, tlv_offset);
 346                                 /* get the TLV type */
 347                                 tlv_type = get_tlv_type(&tlv_info);
 348                                 /* get the TLV length */
 349                                 length = get_tlv_length(&tlv_info);
 350                                 if(tlv_type == -1 || length > MAX_TLV_LEN || length < 1)
 351                                 {       /* invalid tlv info */
 352                                         col_append_sep_str(pinfo->cinfo, COL_INFO, NULL, "REG-REQ TLV error");
 353                                         proto_tree_add_item(reg_req_tree, hf_reg_invalid_tlv, tvb, offset, (tvb_len - offset), ENC_NA);
 354                                         break;
 355                                 }
 356                                 /* update the offset */
 357                                 tlv_offset += get_tlv_value_offset(&tlv_info);
 358                                 nblocks = tvb_get_ntohs(tvb, tlv_offset);
 359                                 switch (tlv_type)
 360                                 {
 361                                         case REG_TLV_T_20_1_MAX_MAC_LEVEL_DATA_PER_DL_FRAME:
 362                                                 tlv_item = add_tlv_subtree(&tlv_info, tlv_tree, hf_reg_tlv_t_20_1_max_mac_level_data_per_dl_frame, tvb, tlv_offset-get_tlv_value_offset(&tlv_info), ENC_BIG_ENDIAN);
 363                                                 if ( nblocks == 0 )
 364                                                 {
 365                                                         proto_item_append_text(tlv_item, " (Unlimited bytes)");
 366                                                 } else {
 367                                                         proto_item_append_text(tlv_item, " (%d bytes)", 256 * nblocks);
 368                                                 }
 369                                                 break;
 370                                         case REG_TLV_T_20_2_MAX_MAC_LEVEL_DATA_PER_UL_FRAME:
 371                                                 tlv_item = add_tlv_subtree(&tlv_info, tlv_tree, hf_reg_tlv_t_20_2_max_mac_level_data_per_ul_frame, tvb, tlv_offset-get_tlv_value_offset(&tlv_info), ENC_BIG_ENDIAN);
 372                                                 if ( nblocks == 0 )
 373                                                 {
 374                                                         proto_item_append_text(tlv_item, " (Unlimited bytes)");
 375                                                 } else {
 376                                                         proto_item_append_text(tlv_item, " (%d bytes)", 256 * nblocks);
 377                                                 }
 378                                                 break;
 379                                         default:
 380                                                 add_tlv_subtree(&tlv_info, tlv_tree, hf_reg_invalid_tlv, tvb, tlv_offset-get_tlv_value_offset(&tlv_info), ENC_NA);
 381                                                 break;
 382                                 }
 383                                 tlv_offset += length;
 384                         }
 385                         break;
 386
 387                 case REG_TLV_T_21_PACKING_SUPPORT:
 388                         add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_tlv_t_21_packing_support, tvb, offset, ENC_BIG_ENDIAN);
 389                         break;
 390                 case REG_TLV_T_22_MAC_EXTENDED_RTPS_SUPPORT:
 391                         add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_tlv_t_22_mac_extended_rtps_support, tvb, offset, ENC_BIG_ENDIAN);
 392                         break;
 393                 case REG_TLV_T_23_MAX_NUM_BURSTS_TRANSMITTED_CONCURRENTLY_TO_THE_MS:
 394                         add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_tlv_t_23_max_num_bursts_concurrently_to_the_ms, tvb, offset, ENC_BIG_ENDIAN);
 395                         break;
 396                 case REG_TLV_T_26_METHOD_FOR_ALLOCATING_IP_ADDR_SECONDARY_MGMNT_CONNECTION:
 397                         tlv_item = add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_tlv_t_26_method_alloc_ip_addr_secondary_mgmnt_conn, tvb, offset, ENC_BIG_ENDIAN);
 398                         tlv_tree = proto_item_add_subtree(tlv_item, ett_mac_mgmt_msg_reg_req_decoder);
 399                         proto_tree_add_item(tlv_tree, hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_dhcp, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
 400                         proto_tree_add_item(tlv_tree, hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_mobile_ipv4, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
 401                         proto_tree_add_item(tlv_tree, hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_dhcpv6, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
 402                         proto_tree_add_item(tlv_tree, hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_ipv6, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
 403                         proto_tree_add_item(tlv_tree, hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_rsvd, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
 404                         break;
 405                 case REG_TLV_T_27_HANDOVER_SUPPORTED:
 406                         tlv_item = add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_tlv_t_27_handover_supported, tvb, offset, ENC_BIG_ENDIAN);
 407                         tlv_tree = proto_item_add_subtree(tlv_item, ett_mac_mgmt_msg_reg_req_decoder);
 408                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_27_handover_fbss_mdho_ho_disable, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
 409                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_27_handover_fbss_mdho_dl_rf_monitoring_maps, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
 410                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_27_handover_mdho_dl_monitoring_single_map, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
 411                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_27_handover_mdho_dl_monitoring_maps, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
 412                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_27_handover_mdho_ul_multiple, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
 413                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_27_handover_reserved, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
 414                         break;
 415                 case REG_TLV_T_29_HO_PROCESS_OPTIMIZATION_MS_TIMER:
 416                         add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_tlv_t_29_ho_process_opt_ms_timer, tvb, offset, ENC_BIG_ENDIAN);
 417                         break;
 418                 case REG_TLV_T_31_MOBILITY_FEATURES_SUPPORTED:
 419                         tlv_item = add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_tlv_t_31_mobility_features_supported, tvb, offset, ENC_BIG_ENDIAN);
 420                         tlv_tree = proto_item_add_subtree(tlv_item, ett_mac_mgmt_msg_reg_req_decoder);
 421                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_31_mobility_handover, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
 422                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_31_mobility_sleep_mode, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
 423                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_31_mobility_idle_mode, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
 424                         break;
 425                 case REG_TLV_T_40_ARQ_ACK_TYPE:
 426                         tlv_item = add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_tlv_t_40_arq_ack_type, tvb, offset, ENC_BIG_ENDIAN);
 427                         tlv_tree = proto_item_add_subtree(tlv_item, ett_mac_mgmt_msg_reg_req_decoder);
 428                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_40_arq_ack_type_selective_ack_entry, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
 429                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_40_arq_ack_type_cumulative_ack_entry, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
 430                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_40_arq_ack_type_cumulative_with_selective_ack_entry, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
 431                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_40_arq_ack_type_cumulative_ack_with_block_sequence_ack, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
 432                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_40_arq_ack_type_reserved, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
 433                         break;
 434                 case REG_TLV_T_41_MS_HO_CONNECTIONS_PARAM_PROCESSING_TIME:
 435                         add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_tlv_t_41_ho_connections_param_processing_time, tvb, offset, ENC_BIG_ENDIAN);
 436                         break;
 437                 case REG_TLV_T_42_MS_HO_TEK_PROCESSING_TIME:
 438                         add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_tlv_t_42_ho_tek_processing_time, tvb, offset, ENC_BIG_ENDIAN);
 439                         break;
 440                 case REG_TLV_T_43_MAC_HEADER_AND_EXTENDED_SUBHEADER_SUPPORT:
 441                         tlv_item = add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_tlv_t_43_mac_header_ext_header_support, tvb, offset, ENC_BIG_ENDIAN);
 442                         tlv_tree = proto_item_add_subtree(tlv_item, ett_mac_mgmt_msg_reg_req_decoder);
 443                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_bandwidth_request_ul_tx_power_report_header_support, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
 444                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_bandwidth_request_cinr_report_header_support, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
 445                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_cqich_allocation_request_header_support, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
 446                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_phy_channel_report_header_support, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
 447                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_bandwidth_request_ul_sleep_control_header_support, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
 448                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_sn_report_header_support, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
 449                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_feedback_header_support, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
 450                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_sdu_sn_extended_subheader_support_and_parameter, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
 451                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_sdu_sn_parameter, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
 452                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_dl_sleep_control_extended_subheader, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
 453                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_feedback_request_extended_subheader, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
 454                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_mimo_mode_feedback_extended_subheader, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
 455                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_ul_tx_power_report_extended_subheader, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
 456                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_mini_feedback_extended_subheader, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
 457                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_sn_request_extended_subheader, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
 458                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_pdu_sn_short_extended_subheader, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
 459                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_pdu_sn_long_extended_subheader, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
 460                         proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_reserved, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
 461                         break;
 462                 case REG_REQ_BS_SWITCHING_TIMER:
 463                         tlv_item = add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_req_bs_switching_timer, tvb, offset, ENC_BIG_ENDIAN);
 464                         tlv_tree = proto_item_add_subtree(tlv_item, ett_mac_mgmt_msg_reg_req_decoder);
 465                         proto_tree_add_item(tlv_tree, hf_reg_req_min_time_for_intra_fa, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
 466                         proto_tree_add_item(tlv_tree, hf_reg_req_min_time_for_inter_fa, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
 467                         break;
 468                 case VENDOR_SPECIFIC_INFO:
 469                 case VENDOR_ID_ENCODING:
 470                 case CURRENT_TX_POWER:
 471                 case MAC_VERSION_ENCODING:
 472                 case CMAC_TUPLE:        /* Table 348b */
 473                         wimax_common_tlv_encoding_decoder(tvb_new_subset_remaining(tvb, offset), pinfo, reg_req_tree);
 474                         break;
 475                 default:
 476                         add_tlv_subtree(&tlv_info, reg_req_tree, proto_registry, tvb, offset, ENC_NA);
 477                         break;
 478         }
 479 #endif
 480 }
 481
 482
 483 /* Decode REG-REQ messages. */
 484 static int dissect_mac_mgmt_msg_reg_req_decoder(tvbuff_t *tvb, packet_info *pinfo, proto_tree *tree, void* data _U_)
 485 {
 486         unsigned offset = 0;
 487         unsigned tlv_offset;
 488         unsigned tvb_len;
 489         proto_item *reg_req_item = NULL;
 490         proto_tree *reg_req_tree = NULL;
 491         proto_tree *tlv_tree = NULL;
 492         bool hmac_found = false;
 493         tlv_info_t tlv_info;
 494         int tlv_type;
 495         int tlv_len;
 496
 497         {       /* we are being asked for details */
 498
 499                 /* Get the tvb reported length */
 500                 tvb_len =  tvb_reported_length(tvb);
 501                 /* display MAC payload type REG-REQ */
 502                 reg_req_item = proto_tree_add_protocol_format(tree, proto_mac_mgmt_msg_reg_req_decoder, tvb, offset, tvb_len, "MAC Management Message, REG-REQ");
 503                 /* add MAC REG-REQ subtree */
 504                 reg_req_tree = proto_item_add_subtree(reg_req_item, ett_mac_mgmt_msg_reg_req_decoder);
 505
 506                 while(offset < tvb_len)
 507                 {
 508                         /* Get the TLV data. */
 509                         init_tlv_info(&tlv_info, tvb, offset);
 510                         /* get the TLV type */
 511                         tlv_type = get_tlv_type(&tlv_info);
 512                         /* get the TLV length */
 513                         tlv_len = get_tlv_length(&tlv_info);
 514                         if(tlv_type == -1 || tlv_len > MAX_TLV_LEN || tlv_len < 1)
 515                         {       /* invalid tlv info */
 516                                 col_append_sep_str(pinfo->cinfo, COL_INFO, NULL, "REG-REQ TLV error");
 517                                 proto_tree_add_item(reg_req_tree, hf_reg_invalid_tlv, tvb, offset, (tvb_len - offset), ENC_NA);
 518                                 break;
 519                         }
 520                         /* get the offset to the TLV data */
 521                         tlv_offset = offset + get_tlv_value_offset(&tlv_info);
 522
 523                         switch (tlv_type) {
 524                                 case REG_ARQ_PARAMETERS:
 525                                 case REG_SS_MGMT_SUPPORT:
 526                                 case REG_IP_MGMT_MODE:
 527                                 case REG_IP_VERSION:
 528                                 case REG_UL_TRANSPORT_CIDS_SUPPORTED:
 529                                 case REG_IP_PHS_SDU_ENCAP:
 530                                 case REG_MAX_CLASSIFIERS_SUPPORTED:
 531                                 case REG_PHS_SUPPORT:
 532                                 case REG_ARQ_SUPPORT:
 533                                 case REG_DSX_FLOW_CONTROL:
 534                                 case REG_MAC_CRC_SUPPORT:
 535                                 case REG_MCA_FLOW_CONTROL:
 536                                 case REG_MCAST_POLLING_CIDS:
 537                                 case REG_NUM_DL_TRANS_CID:
 538                                 case REG_MAC_ADDRESS:
 539 #ifdef WIMAX_16E_2005
 540                                 case REG_TLV_T_20_MAX_MAC_DATA_PER_FRAME_SUPPORT:
 541                                 case REG_TLV_T_21_PACKING_SUPPORT:
 542                                 case REG_TLV_T_22_MAC_EXTENDED_RTPS_SUPPORT:
 543                                 case REG_TLV_T_23_MAX_NUM_BURSTS_TRANSMITTED_CONCURRENTLY_TO_THE_MS:
 544                                 case REG_TLV_T_26_METHOD_FOR_ALLOCATING_IP_ADDR_SECONDARY_MGMNT_CONNECTION:
 545                                 case REG_TLV_T_27_HANDOVER_SUPPORTED:
 546                                 case REG_TLV_T_29_HO_PROCESS_OPTIMIZATION_MS_TIMER:
 547                                 case REG_TLV_T_31_MOBILITY_FEATURES_SUPPORTED:
 548                                 case REG_TLV_T_40_ARQ_ACK_TYPE:
 549                                 case REG_TLV_T_41_MS_HO_CONNECTIONS_PARAM_PROCESSING_TIME:
 550                                 case REG_TLV_T_42_MS_HO_TEK_PROCESSING_TIME:
 551                                 case REG_TLV_T_43_MAC_HEADER_AND_EXTENDED_SUBHEADER_SUPPORT:
 552                                 case REG_REQ_BS_SWITCHING_TIMER:
 553                                 case REG_POWER_SAVING_CLASS_CAPABILITY:
 554 #endif
 555                                         /* Decode REG-REQ sub-TLV's. */
 556                                         dissect_extended_tlv(reg_req_tree, tlv_type, tvb, tlv_offset, tlv_len, pinfo, offset, proto_mac_mgmt_msg_reg_req_decoder);
 557                                         break;
 558                                 case REG_REQ_SECONDARY_MGMT_CID:
 559                                         add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_req_secondary_mgmt_cid, tvb, offset, ENC_BIG_ENDIAN);
 560                                         break;
 561                                 case REG_REQ_TLV_T_32_SLEEP_MODE_RECOVERY_TIME:
 562                                         add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_req_tlv_t_32_sleep_mode_recovery_time, tvb, offset, ENC_BIG_ENDIAN);
 563                                         break;
 564                                 case REG_REQ_TLV_T_33_MS_PREV_IP_ADDR:
 565                                         if ( tlv_len == 4 ) {
 566                                                 add_tlv_subtree(&tlv_info, reg_req_tree, hf_ms_previous_ip_address_v4, tvb, offset, ENC_BIG_ENDIAN);
 567                                         } else if ( tlv_len == 16 ) {
 568                                                 add_tlv_subtree(&tlv_info, reg_req_tree, hf_ms_previous_ip_address_v6, tvb, offset, ENC_NA);
 569                                         }
 570                                         break;
 571                                 case REG_TLV_T_37_IDLE_MODE_TIMEOUT:
 572                                         add_tlv_subtree(&tlv_info, reg_req_tree, hf_idle_mode_timeout, tvb, offset, ENC_BIG_ENDIAN);
 573                                         break;
 574                                 case REG_REQ_TLV_T_45_MS_PERIODIC_RANGING_TIMER_INFO:
 575                                         add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_req_tlv_t_45_ms_periodic_ranging_timer, tvb, offset, ENC_BIG_ENDIAN);
 576                                         break;
 577                                 case REG_HANDOVER_INDICATION_READINESS_TIMER:
 578                                         add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_tlv_t_46_handover_indication_readiness_timer, tvb, offset, ENC_BIG_ENDIAN);
 579                                         break;
 580
 581                                 case DSx_UPLINK_FLOW:
 582                                         /* display Uplink Service Flow Encodings info */
 583                                         /* add subtree */
 584                                         tlv_tree = add_protocol_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_mac_mgmt_msg_reg_req_decoder, tvb, offset, tlv_len, "Uplink Service Flow Encodings");
 585                                         /* decode and display the DL Service Flow Encodings */
 586                                         wimax_service_flow_encodings_decoder(tvb_new_subset_length(tvb, tlv_offset, tlv_len), pinfo, tlv_tree);
 587                                         break;
 588                                 case DSx_DOWNLINK_FLOW:
 589                                         /* display Downlink Service Flow Encodings info */
 590                                         /* add subtree */
 591                                         tlv_tree = add_protocol_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_mac_mgmt_msg_reg_req_decoder, tvb, offset, tlv_len, "Downlink Service Flow Encodings");
 592                                         /* decode and display the DL Service Flow Encodings */
 593                                         wimax_service_flow_encodings_decoder(tvb_new_subset_length(tvb, tlv_offset, tlv_len), pinfo, tlv_tree);
 594                                         break;
 595                                 case HMAC_TUPLE:        /* Table 348d */
 596                                         /* decode and display the HMAC Tuple */
 597                                         tlv_tree = add_protocol_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_mac_mgmt_msg_reg_req_decoder, tvb, offset, tlv_len, "HMAC Tuple");
 598                                         wimax_hmac_tuple_decoder(tlv_tree, tvb, tlv_offset, tlv_len);
 599                                         hmac_found = true;
 600                                         break;
 601                                 case CMAC_TUPLE:        /* Table 348b */
 602                                         /* decode and display the CMAC Tuple */
 603                                         tlv_tree = add_protocol_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_mac_mgmt_msg_reg_req_decoder, tvb, offset, tlv_len, "CMAC Tuple");
 604                                         wimax_cmac_tuple_decoder(tlv_tree, tvb, tlv_offset, tlv_len);
 605                                         break;
 606                                 default:
 607                                         add_tlv_subtree(&tlv_info, reg_req_tree, hf_tlv_type, tvb, offset, ENC_NA);
 608                                         break;
 609                         }
 610                         /* update the offset */
 611                         offset = tlv_len + tlv_offset;
 612                 } /* End while() looping through the tvb. */
 613                 if (!hmac_found)
 614                         proto_item_append_text(reg_req_tree, " (HMAC Tuple is missing !)");
 615         }
 616         return tvb_captured_length(tvb);
 617 }
 618
 619 /* Register Wimax Mac Payload Protocol and Dissector */
 620 void proto_register_mac_mgmt_msg_reg_req(void)
 621 {
 622         /* REG-REQ fields display */
 623         static hf_register_info hf[] =
 624         {
 625                 {
 626                         &hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_dhcp,
 627                         {
 628                                 "DHCP", "wmx.reg.alloc_sec_mgmt_dhcp",
 629                                 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x01, NULL, HFILL
 630                         }
 631                 },
 632                 {
 633                         &hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_dhcpv6,
 634                         {
 635                                 "DHCPv6", "wmx.reg.alloc_sec_mgmt_dhcpv6",
 636                                 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x04, NULL, HFILL
 637                         }
 638                 },
 639                 {
 640                         &hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_ipv6,
 641                         {
 642                                 "IPv6 Stateless Address Autoconfiguration", "wmx.reg.alloc_sec_mgmt_ipv6",
 643                                 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x08, NULL, HFILL
 644                         }
 645                 },
 646                 {
 647                         &hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_mobile_ipv4,
 648                         {
 649                                 "Mobile IPv4", "wmx.reg.alloc_sec_mgmt_mobile_ipv4",
 650                                 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x02, NULL, HFILL
 651                         }
 652                 },
 653                 {
 654                         &hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_rsvd,
 655                         {
 656                                 "Reserved", "wmx.reg.alloc_sec_mgmt_rsvd",
 657                                 FT_UINT8, BASE_DEC, NULL, 0xF0, NULL, HFILL
 658                         }
 659                 },
 660                 {
 661                         &hf_reg_arq,
 662                         {
 663                                 "ARQ support", "wmx.reg.arq",
 664                                 FT_BOOLEAN, BASE_NONE, TFS(&tfs_supported), 0x0, NULL, HFILL
 665                         }
 666                 },
 667                 {
 668                         &hf_reg_tlv_t_40_arq_ack_type_cumulative_ack_entry,
 669                         {
 670                                 "Cumulative ACK entry", "wmx.reg.arq_ack_type_cumulative_ack_entry",
 671                                 FT_UINT8, BASE_DEC, NULL, 0x2, NULL, HFILL
 672                         }
 673                 },
 674                 {
 675                         &hf_reg_tlv_t_40_arq_ack_type_cumulative_ack_with_block_sequence_ack,
 676                         {
 677                                 "Cumulative ACK with Block Sequence ACK", "wmx.reg.arq_ack_type_cumulative_ack_with_block_sequence_ack",
 678                                 FT_UINT8, BASE_DEC, NULL, 0x8, NULL, HFILL
 679                         }
 680                 },
 681                 {
 682                         &hf_reg_tlv_t_40_arq_ack_type_cumulative_with_selective_ack_entry,
 683                         {
 684                                 "Cumulative with Selective ACK entry", "wmx.reg.arq_ack_type_cumulative_with_selective_ack_entry",
 685                                 FT_UINT8, BASE_DEC, NULL, 0x4, NULL, HFILL
 686                         }
 687                 },
 688                 {
 689                         &hf_reg_tlv_t_40_arq_ack_type_reserved,
 690                         {
 691                                 "Reserved", "wmx.reg.arq_ack_type_reserved",
 692                                 FT_UINT8, BASE_DEC, NULL, 0xf0, NULL, HFILL
 693                         }
 694                 },
 695                 {
 696                         &hf_reg_tlv_t_40_arq_ack_type_selective_ack_entry,
 697                         {
 698                                 "Selective ACK entry", "wmx.reg.arq_ack_type_selective_ack_entry",
 699                                 FT_UINT8, BASE_DEC, NULL, 0x1, NULL, HFILL
 700                         }
 701                 },
 702                 {
 703                         &hf_reg_tlv_t_43_bandwidth_request_cinr_report_header_support,
 704                         {
 705                                 "Bandwidth request and CINR report header support", "wmx.reg.bandwidth_request_cinr_report_header_support",
 706                                 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x2, NULL, HFILL
 707                         }
 708                 },
 709                 {
 710                         &hf_reg_tlv_t_43_bandwidth_request_ul_sleep_control_header_support,
 711                         {
 712                                 "Bandwidth request and uplink sleep control header support", "wmx.reg.bandwidth_request_ul_sleep_control_header_support",
 713                                 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x10, NULL, HFILL
 714                         }
 715                 },
 716                 {
 717                         &hf_reg_tlv_t_43_cqich_allocation_request_header_support,
 718                         {
 719                                 "CQICH Allocation Request header support", "wmx.reg.cqich_allocation_request_header_support",
 720                                 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x4, NULL, HFILL
 721                         }
 722                 },
 723                 {
 724                         &hf_reg_tlv_t_43_dl_sleep_control_extended_subheader,
 725                         {
 726                                 "Downlink sleep control extended subheader", "wmx.reg.dl_sleep_control_extended_subheader",
 727                                 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x800, NULL, HFILL
 728                         }
 729                 },
 730                 {
 731                         &hf_reg_dsx_flow_control,
 732                         {
 733                                 "DSx flow control", "wmx.reg.dsx_flow_control",
 734                                 FT_UINT8, BASE_DEC|BASE_SPECIAL_VALS, VALS(unique_no_limit), 0x0, NULL, HFILL
 735                         }
 736                 },
 737                 /* When REG-REQ TLV 7 is length 2 */
 738                 {
 739                         &hf_reg_encap_802_1q_2,
 740                         {
 741                                 "Packet, 802.1Q VLAN", "wmx.reg.encap_802_1q",
 742                                 FT_UINT16, BASE_HEX, NULL, 0x0010, NULL, HFILL
 743                         }
 744                 },
 745                 {
 746                         &hf_reg_encap_802_3_2,
 747                         {
 748                                 "Packet, 802.3/Ethernet", "wmx.reg.encap_802_3",
 749                                 FT_UINT16, BASE_HEX, NULL, 0x00000008, NULL, HFILL
 750                         }
 751                 },
 752                 {
 753                         &hf_reg_encap_atm_2,
 754                         {
 755                                 "ATM", "wmx.reg.encap_atm",
 756                                 FT_UINT16, BASE_HEX, NULL, 0x00000001, NULL, HFILL
 757                         }
 758                 },
 759                 {
 760                         &hf_reg_encap_ipv4_2,
 761                         {
 762                                 "Packet, IPv4", "wmx.reg.encap_ipv4",
 763                                 FT_UINT16, BASE_HEX, NULL, 0x00000002, NULL, HFILL
 764                         }
 765                 },
 766                 {
 767                         &hf_reg_encap_ipv6_2,
 768                         {
 769                                 "Packet, IPv6", "wmx.reg.encap_ipv6",
 770                                 FT_UINT16, BASE_HEX, NULL, 0x00000004, NULL, HFILL
 771                         }
 772                 },
 773                 {
 774                         &hf_reg_encap_ipv4_802_1q_2,
 775                         {
 776                                 "Packet, IPv4 over 802.1Q VLAN", "wmx.reg.encap_ipv4_802_1q",
 777                                 FT_UINT16, BASE_HEX, NULL, 0x00000080, NULL, HFILL
 778                         }
 779                 },
 780                 {
 781                         &hf_reg_encap_ipv4_802_3_2,
 782                         {
 783                                 "Packet, IPv4 over 802.3/Ethernet", "wmx.reg.encap_ipv4_802_3",
 784                                 FT_UINT16, BASE_HEX, NULL, 0x00000020, NULL, HFILL
 785                         }
 786                 },
 787                 {
 788                         &hf_reg_encap_ipv6_802_1q_2,
 789                         {
 790                                 "Packet, IPv6 over 802.1Q VLAN", "wmx.reg.encap_ipv6_802_1q",
 791                                 FT_UINT16, BASE_HEX, NULL, 0x00000100, NULL, HFILL
 792                         }
 793                 },
 794                 {
 795                         &hf_reg_encap_ipv6_802_3_2,
 796                         {
 797                                 "Packet, IPv6 over 802.3/Ethernet", "wmx.reg.encap_ipv6_802_3",
 798                                 FT_UINT16, BASE_HEX, NULL, 0x00000040, NULL, HFILL
 799                         }
 800                 },
 801                 {
 802                         &hf_reg_encap_packet_8023_ethernet_and_ecrtp_header_compression_2,
 803                         {
 804                                 "Packet, 802.3/Ethernet (with optional 802.1Q VLAN tags) and ECRTP header compression", "wmx.reg.encap_packet_802_3_ethernet_and_ecrtp_header_compression",
 805                                 FT_UINT16, BASE_HEX, NULL, 0x00000400, NULL, HFILL
 806                         }
 807                 },
 808                 {
 809                         &hf_reg_encap_packet_8023_ethernet_and_rohc_header_compression_2,
 810                         {
 811                                 "Packet, 802.3/Ethernet (with optional 802.1Q VLAN tags) and ROHC header compression", "wmx.reg.encap_packet_802_3_ethernet_and_rohc_header_compression",
 812                                 FT_UINT16, BASE_HEX, NULL, 0x00000200, NULL, HFILL
 813                         }
 814                 },
 815                 {
 816                         &hf_reg_encap_packet_ip_ecrtp_header_compression_2,
 817                         {
 818                                 "Packet, IP (v4 or v6) with ECRTP header compression", "wmx.reg.encap_packet_ip_ecrtp_header_compression",
 819                                 FT_UINT16, BASE_HEX, NULL, 0x00001000, NULL, HFILL
 820                         }
 821                 },
 822                 {
 823                         &hf_reg_encap_packet_ip_rohc_header_compression_2,
 824                         {
 825                                 "Packet, IP (v4 or v6) with ROHC header compression", "wmx.reg.encap_packet_ip_rohc_header_compression",
 826                                 FT_UINT16, BASE_HEX, NULL, 0x00000800, NULL, HFILL
 827                         }
 828                 },
 829                 {
 830                         &hf_reg_encap_rsvd_2,
 831                         {
 832                                 "Reserved", "wmx.reg.encap_rsvd",
 833                                 FT_UINT16, BASE_HEX, NULL, 0x0000E000, NULL, HFILL
 834                         }
 835                 },
 836                 /* When REG-REQ TLV 7 is length 4 */
 837                 {
 838                         &hf_reg_encap_802_1q_4,
 839                         {
 840                                 "Packet, 802.1Q VLAN", "wmx.reg.encap_802_1q",
 841                                 FT_UINT32, BASE_HEX, NULL, 0x0010, NULL, HFILL
 842                         }
 843                 },
 844                 {
 845                         &hf_reg_encap_802_3_4,
 846                         {
 847                                 "Packet, 802.3/Ethernet", "wmx.reg.encap_802_3",
 848                                 FT_UINT32, BASE_HEX, NULL, 0x00000008, NULL, HFILL
 849                         }
 850                 },
 851                 {
 852                         &hf_reg_encap_atm_4,
 853                         {
 854                                 "ATM", "wmx.reg.encap_atm",
 855                                 FT_UINT32, BASE_HEX, NULL, 0x00000001, NULL, HFILL
 856                         }
 857                 },
 858                 {
 859                         &hf_reg_encap_ipv4_4,
 860                         {
 861                                 "Packet, IPv4", "wmx.reg.encap_ipv4",
 862                                 FT_UINT32, BASE_HEX, NULL, 0x00000002, NULL, HFILL
 863                         }
 864                 },
 865                 {
 866                         &hf_reg_encap_ipv4_802_1q_4,
 867                         {
 868                                 "Packet, IPv4 over 802.1Q VLAN", "wmx.reg.encap_ipv4_802_1q",
 869                                 FT_UINT32, BASE_HEX, NULL, 0x00000080, NULL, HFILL
 870                         }
 871                 },
 872                 {
 873                         &hf_reg_encap_ipv4_802_3_4,
 874                         {
 875                                 "Packet, IPv4 over 802.3/Ethernet", "wmx.reg.encap_ipv4_802_3",
 876                                 FT_UINT32, BASE_HEX, NULL, 0x00000020, NULL, HFILL
 877                         }
 878                 },
 879                 {
 880                         &hf_reg_encap_ipv6_4,
 881                         {
 882                                 "Packet, IPv6", "wmx.reg.encap_ipv6",
 883                                 FT_UINT32, BASE_HEX, NULL, 0x00000004, NULL, HFILL
 884                         }
 885                 },
 886                 {
 887                         &hf_reg_encap_ipv6_802_1q_4,
 888                         {
 889                                 "Packet, IPv6 over 802.1Q VLAN", "wmx.reg.encap_ipv6_802_1q",
 890                                 FT_UINT32, BASE_HEX, NULL, 0x00000100, NULL, HFILL
 891                         }
 892                 },
 893                 {
 894                         &hf_reg_encap_ipv6_802_3_4,
 895                         {
 896                                 "Packet, IPv6 over 802.3/Ethernet", "wmx.reg.encap_ipv6_802_3",
 897                                 FT_UINT32, BASE_HEX, NULL, 0x00000040, NULL, HFILL
 898                         }
 899                 },
 900                 {
 901                         &hf_reg_encap_packet_8023_ethernet_and_ecrtp_header_compression_4,
 902                         {
 903                                 "Packet, 802.3/Ethernet (with optional 802.1Q VLAN tags) and ECRTP header compression", "wmx.reg.encap_packet_802_3_ethernet_and_ecrtp_header_compression",
 904                                 FT_UINT32, BASE_HEX, NULL, 0x00000400, NULL, HFILL
 905                         }
 906                 },
 907                 {
 908                         &hf_reg_encap_packet_8023_ethernet_and_rohc_header_compression_4,
 909                         {
 910                                 "Packet, 802.3/Ethernet (with optional 802.1Q VLAN tags) and ROHC header compression", "wmx.reg.encap_packet_802_3_ethernet_and_rohc_header_compression",
 911                                 FT_UINT32, BASE_HEX, NULL, 0x00000200, NULL, HFILL
 912                         }
 913                 },
 914                 {
 915                         &hf_reg_encap_packet_ip_ecrtp_header_compression_4,
 916                         {
 917                                 "Packet, IP (v4 or v6) with ECRTP header compression", "wmx.reg.encap_packet_ip_ecrtp_header_compression",
 918                                 FT_UINT32, BASE_HEX, NULL, 0x00001000, NULL, HFILL
 919                         }
 920                 },
 921                 {
 922                         &hf_reg_encap_packet_ip_rohc_header_compression_4,
 923                         {
 924                                 "Packet, IP (v4 or v6) with ROHC header compression", "wmx.reg.encap_packet_ip_rohc_header_compression",
 925                                 FT_UINT32, BASE_HEX, NULL, 0x00000800, NULL, HFILL
 926                         }
 927                 },
 928                 {
 929                         &hf_reg_encap_rsvd_4,
 930                         {
 931                                 "Reserved", "wmx.reg.encap_rsvd",
 932                                 FT_UINT32, BASE_HEX, NULL, 0xFFFFE000, NULL, HFILL
 933                         }
 934                 },
 935                 {
 936                         &hf_reg_tlv_t_22_mac_extended_rtps_support,
 937                         {
 938                                 "MAC extended rtPS support", "wmx.reg.ext_rtps_support",
 939                                 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x01, NULL, HFILL
 940                         }
 941                 },
 942                 {
 943                         &hf_reg_tlv_t_27_handover_fbss_mdho_dl_rf_monitoring_maps,
 944                         {
 945                                 "FBSS/MDHO DL RF Combining with monitoring MAPs from active BSs", "wmx.reg.fbss_mdho_dl_rf_combining",
 946                                 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x02, NULL, HFILL
 947                         }
 948                 },
 949                 {
 950                         &hf_reg_tlv_t_43_bandwidth_request_ul_tx_power_report_header_support,
 951                         {
 952                                 "Bandwidth request and UL Tx Power Report header support",
 953                                 "wmx.reg.bandwidth_request_ul_tx_pwr_report_header_support",
 954                                 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x1, NULL, HFILL
 955                         }
 956                 },
 957                 {
 958                         &hf_reg_tlv_t_27_handover_fbss_mdho_ho_disable,
 959                         {
 960                                 "MDHO/FBSS HO. BS ignore all other bits when set to 1", "wmx.reg.fbss_mdho_ho_disable",
 961                                 FT_BOOLEAN, 8, TFS(&tfs_reg_fbss_mdho_ho_disable), 0x01, NULL, HFILL
 962                         }
 963                 },
 964                 {
 965                         &hf_reg_tlv_t_43_feedback_header_support,
 966                         {
 967                                 "Feedback header support", "wmx.reg.feedback_header_support",
 968                                 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x40, NULL, HFILL
 969                         }
 970                 },
 971                 {
 972                         &hf_reg_tlv_t_43_feedback_request_extended_subheader,
 973                         {
 974                                 "Feedback request extended subheader", "wmx.reg.feedback_request_extended_subheader",
 975                                 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x1000, NULL, HFILL
 976                         }
 977                 },
 978                 {
 979                         &hf_reg_tlv_t_46_handover_indication_readiness_timer,
 980                         {
 981                                 "Handover indication readiness timer", "wmx.reg.handover_indication_readiness_timer",
 982                                 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL
 983                         }
 984                 },
 985                 {
 986                         &hf_reg_tlv_t_27_handover_reserved,
 987                         {
 988                                 "Reserved", "wmx.reg.handover_reserved",
 989                                 FT_UINT8, BASE_DEC, NULL, 0xE0, NULL, HFILL
 990                         }
 991                 },
 992                 {
 993                         &hf_reg_tlv_t_41_ho_connections_param_processing_time,
 994                         {
 995                                 "MS HO connections parameters processing time", "wmx.reg.ho_connections_param_processing_time",
 996                                 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL
 997                         }
 998                 },
 999                 {
1000                         &hf_reg_tlv_t_29_ho_process_opt_ms_timer,
1001                         {
1002                                 "HO Process Optimization MS Timer", "wmx.reg.ho_process_opt_ms_timer",
1003                                 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL
1004                         }
1005                 },
1006                 {
1007                         &hf_reg_tlv_t_42_ho_tek_processing_time,
1008                         {
1009                                 "MS HO TEK processing time", "wmx.reg.ho_tek_processing_time",
1010                                 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL
1011                         }
1012                 },
1013                 {
1014                         &hf_idle_mode_timeout,
1015                         {
1016                                 "Idle Mode Timeout", "wmx.reg.idle_mode_timeout",
1017                                 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL
1018                         }
1019                 },
1020                 {
1021                         &hf_reg_ip_mgmt_mode,
1022                         {
1023                                 "IP management mode", "wmx.reg.ip_mgmt_mode",
1024                                 FT_BOOLEAN, BASE_NONE, TFS(&tfs_reg_ip_mgmt_mode), 0x0, NULL, HFILL
1025                         }
1026                 },
1027                 {
1028                         &hf_reg_ip_version,
1029                         {
1030                                 "IP version", "wmx.reg.ip_version",
1031                                 FT_UINT8, BASE_HEX, VALS(vals_reg_ip_version), 0x0, NULL, HFILL
1032                         }
1033                 },
1034                 {
1035                         &hf_reg_mac_address,
1036                         {
1037                                 "MAC Address of the SS", "wmx.reg.mac_address",
1038                                 FT_ETHER, BASE_NONE, NULL, 0x0, NULL, HFILL
1039                         }
1040                 },
1041                 {
1042                         &hf_reg_mac_crc_support,
1043                         {
1044                                 "MAC CRC", "wmx.reg.mac_crc_support",
1045                                 FT_BOOLEAN, BASE_NONE, TFS(&tfs_mac_crc_support), 0x0, NULL, HFILL
1046                         }
1047                 },
1048                 {
1049                         &hf_reg_max_classifiers,
1050                         {
1051                                 "Maximum number of classification rules", "wmx.reg.max_classifiers",
1052                                 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL
1053                         }
1054                 },
1055                 {
1056                         &hf_reg_tlv_t_23_max_num_bursts_concurrently_to_the_ms,
1057                         {
1058                                 "Maximum number of bursts transmitted concurrently to the MS", "wmx.reg.max_num_bursts_to_ms",
1059                                 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL
1060                         }
1061                 },
1062                 {
1063                         &hf_reg_mca_flow_control,
1064                         {
1065                                 "MCA flow control", "wmx.reg.mca_flow_control",
1066                                 FT_UINT8, BASE_DEC|BASE_SPECIAL_VALS, VALS(unique_no_limit), 0x0, NULL, HFILL
1067                         }
1068                 },
1069                 {
1070                         &hf_reg_mcast_polling_cids,
1071                         {
1072                                 "Multicast polling group CID support", "wmx.reg.mcast_polling_cids",
1073                                 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL
1074                         }
1075                 },
1076                 {
1077                         &hf_reg_tlv_t_27_handover_mdho_ul_multiple,
1078                         {
1079                                 "MDHO UL Multiple transmission", "wmx.reg.mdh_ul_multiple",
1080                                 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x10, NULL, HFILL
1081                         }
1082                 },
1083                 {
1084                         &hf_reg_tlv_t_27_handover_mdho_dl_monitoring_maps,
1085                         {
1086                                 "MDHO DL soft combining with monitoring MAPs from active BSs", "wmx.reg.mdho_dl_monitor_maps",
1087                                 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x08, NULL, HFILL
1088                         }
1089                 },
1090                 {
1091                         &hf_reg_tlv_t_27_handover_mdho_dl_monitoring_single_map,
1092                         {
1093                                 "MDHO DL soft Combining with monitoring single MAP from anchor BS", "wmx.reg.mdho_dl_monitor_single_map",
1094                                 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x04, NULL, HFILL
1095                         }
1096                 },
1097                 {
1098                         &hf_reg_tlv_t_43_mimo_mode_feedback_extended_subheader,
1099                         {
1100                                 "MIMO mode feedback request extended subheader", "wmx.reg.mimo_mode_feedback_request_extended_subheader",
1101                                 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x2000, NULL, HFILL
1102                         }
1103                 },
1104                 {
1105                         &hf_reg_tlv_t_43_mini_feedback_extended_subheader,
1106                         {
1107                                 "Mini-feedback extended subheader", "wmx.reg.mini_feedback_extended_subheader",
1108                                 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x8000, NULL, HFILL
1109                         }
1110                 },
1111                 {
1112                         &hf_reg_tlv_t_31_mobility_handover,
1113                         {
1114                                 "Mobility (handover)", "wmx.reg.mobility_handover",
1115                                 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x01, NULL, HFILL
1116                         }
1117                 },
1118                 {
1119                         &hf_reg_tlv_t_31_mobility_idle_mode,
1120                         {
1121                                 "Idle mode", "wmx.reg.mobility_idle_mode",
1122                                 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x04, NULL, HFILL
1123                         }
1124                 },
1125                 {
1126                         &hf_reg_tlv_t_31_mobility_sleep_mode,
1127                         {
1128                                 "Sleep mode", "wmx.reg.mobility_sleep_mode",
1129                                 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x02, NULL, HFILL
1130                         }
1131                 },
1132                 {
1133                         &hf_reg_num_dl_trans_cid,
1134                         {
1135                                 "Number of Downlink transport CIDs the SS can support", "wmx.reg.dl_cids_supported",
1136                                 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL
1137                         }
1138                 },
1139                 {
1140                         &hf_reg_tlv_t_21_packing_support,
1141                         {
1142                                 "Packing support", "wmx.reg.packing.support",
1143                                 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x01, NULL, HFILL
1144                         }
1145                 },
1146                 {
1147                         &hf_reg_tlv_t_43_pdu_sn_long_extended_subheader,
1148                         {
1149                                 "PDU SN (long) extended subheader", "wmx.reg.pdu_sn_long_extended_subheader",
1150                                 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x40000, NULL, HFILL
1151                         }
1152                 },
1153                 {
1154                         &hf_reg_tlv_t_43_pdu_sn_short_extended_subheader,
1155                         {
1156                                 "PDU SN (short) extended subheader", "wmx.reg.pdu_sn_short_extended_subheader",
1157                                 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x20000, NULL, HFILL
1158                         }
1159                 },
1160                 {
1161                         &hf_reg_phs,
1162                         {
1163                                 "PHS support", "wmx.reg.phs",
1164                                 FT_UINT8, BASE_DEC, VALS(vals_reg_phs_support), 0x0, NULL, HFILL
1165                         }
1166                 },
1167                 {
1168                         &hf_reg_tlv_t_43_phy_channel_report_header_support,
1169                         {
1170                                 "PHY channel report header support", "wmx.reg.phy_channel_report_header_support",
1171                                 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x8, NULL, HFILL
1172                         }
1173                 },
1174                 {
1175                         &hf_reg_tlv_t_43_reserved,
1176                         {
1177                                 "Reserved", "wmx.reg.reserved",
1178                                 FT_UINT24, BASE_DEC, NULL, 0xf80000, NULL, HFILL
1179                         }
1180                 },
1181                 {
1182                         &hf_reg_tlv_t_43_sdu_sn_extended_subheader_support_and_parameter,
1183                         {
1184                                 "SDU_SN extended subheader support", "wmx.reg.sdu_sn_extended_subheader_support",
1185                                 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x80, NULL, HFILL
1186                         }
1187                 },
1188                 {
1189                         &hf_reg_tlv_t_43_sdu_sn_parameter,
1190                         {
1191                                 "SDU_SN parameter", "wmx.reg.sdu_sn_parameter",
1192                                 FT_UINT24, BASE_DEC, NULL, 0x700, NULL, HFILL
1193                         }
1194                 },
1195                 {
1196                         &hf_reg_tlv_t_43_sn_report_header_support,
1197                         {
1198                                 "SN report header support", "wmx.reg.sn_report_header_support",
1199                                 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x20, NULL, HFILL
1200                         }
1201                 },
1202                 {
1203                         &hf_reg_tlv_t_43_sn_request_extended_subheader,
1204                         {
1205                                 "SN request extended subheader", "wmx.reg.sn_request_extended_subheader",
1206                                 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x10000, NULL, HFILL
1207                         }
1208                 },
1209                 {
1210                         &hf_reg_ss_mgmt_support,
1211                         {
1212                                 "SS management support", "wmx.reg.ss_mgmt_support",
1213                                 FT_BOOLEAN, BASE_NONE, TFS(&tfs_reg_ss_mgmt_support), 0x0, NULL, HFILL
1214                         }
1215                 },
1216                 {
1217                         &hf_reg_ul_cids,
1218                         {
1219                                 "Number of Uplink transport CIDs the SS can support", "wmx.reg.ul_cids_supported",
1220                                 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL
1221                         }
1222                 },
1223                 {
1224                         &hf_reg_tlv_t_43_ul_tx_power_report_extended_subheader,
1225                         {
1226                                 "UL Tx power report extended subheader", "wmx.reg.ul_tx_power_report_extended_subheader",
1227                                 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x4000, NULL, HFILL
1228                         }
1229                 },
1230                 {
1231                         &hf_tlv_type,
1232                         {
1233                                 "Unknown TLV Type", "wmx.reg.unknown_tlv_type",
1234                                 FT_BYTES, BASE_NONE, NULL, 0x00, NULL, HFILL
1235                         }
1236                 },
1237                 {
1238                         &hf_reg_invalid_tlv,
1239                         {
1240                                 "Invalid TLV", "wmx.reg_req.invalid_tlv",
1241                                 FT_BYTES, BASE_NONE, NULL, 0, NULL, HFILL
1242                         }
1243                 },
1244                 {
1245                         &hf_reg_tlv_t_20_1_max_mac_level_data_per_dl_frame,
1246                         {
1247                                 "Maximum MAC level DL data per frame", "wmx.reg_req.max_mac_dl_data",
1248                                 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL
1249                         }
1250                 },
1251                 {
1252                         &hf_reg_tlv_t_20_2_max_mac_level_data_per_ul_frame,
1253                         {
1254                                 "Maximum MAC level UL data per frame", "wmx.reg_req.max_mac_ul_data",
1255                                 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL
1256                         }
1257                 },
1258                 {
1259                         &hf_reg_req_min_time_for_inter_fa,
1260                         {
1261                                 "Minimum time for inter-FA HO, default=3", "wmx.reg_req.min_time_for_inter_fa",
1262                                 FT_UINT8, BASE_HEX, NULL, 0xF0, NULL, HFILL
1263                         }
1264                 },
1265                 {
1266                         &hf_reg_req_min_time_for_intra_fa,
1267                         {
1268                                 "Minimum time for intra-FA HO, default=2", "wmx.reg_req.min_time_for_intra_fa",
1269                                 FT_UINT8, BASE_HEX, NULL, 0x0F, NULL, HFILL
1270                         }
1271                 },
1272                 {
1273                         &hf_reg_req_tlv_t_45_ms_periodic_ranging_timer,
1274                         {
1275                                 "MS periodic ranging timer information", "wmx.reg_req.ms_periodic_ranging_timer_info",
1276                                 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL
1277                         }
1278                 },
1279                 {       /* IPv4 Mask */
1280                         &hf_ms_previous_ip_address_v4,
1281                         {
1282                                 "MS Previous IP address", "wmx.reg_req.ms_prev_ip_addr_v4",
1283                                 FT_IPv4, BASE_NONE, NULL, 0x0, NULL, HFILL
1284                         }
1285                 },
1286                 {       /* IPv6 Source Address */
1287                         &hf_ms_previous_ip_address_v6,
1288                         {
1289                                 "MS Previous IP address", "wmx.reg_req.ms_prev_ip_addr_v6",
1290                                 FT_IPv6, BASE_NONE, NULL, 0x0, NULL, HFILL
1291                         }
1292                 },
1293                 {
1294                         &hf_reg_req_secondary_mgmt_cid,
1295                         {
1296                                 "Secondary Management CID", "wmx.reg_req.secondary_mgmt_cid",
1297                                 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL
1298                         }
1299                 },
1300                 {
1301                         &hf_reg_req_tlv_t_32_sleep_mode_recovery_time,
1302                         {
1303                                 "Frames required for the MS to switch from sleep to awake-mode", "wmx.reg_req.sleep_recovery",
1304                                 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL
1305                         }
1306                 },
1307                 {
1308                         &hf_reg_power_saving_class_type_i,
1309                         {
1310                                 "Power saving class type I supported", "wmx.reg.power_saving_class_type_i",
1311                                 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x01, NULL, HFILL
1312                         }
1313                 },
1314                 {
1315                         &hf_reg_power_saving_class_type_ii,
1316                         {
1317                                 "Power saving class type II supported", "wmx.reg.power_saving_class_type_ii",
1318                                 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x02, NULL, HFILL
1319                         }
1320                 },
1321                 {
1322                         &hf_reg_power_saving_class_type_iii,
1323                         {
1324                                 "Power saving class type III supported", "wmx.reg.power_saving_class_type_iii",
1325                                 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x04, NULL, HFILL
1326                         }
1327                 },
1328                 {
1329                         &hf_reg_multi_active_power_saving_classes,
1330                         {
1331                                 "Multiple active power saving classes supported", "wmx.reg.multi_active_power_saving_classes",
1332                                 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x08, NULL, HFILL
1333                         }
1334                 },
1335                 {
1336                         &hf_reg_total_power_saving_class_instances,
1337                         {
1338                                 "Total number of power saving class instances of all", "wmx.reg_req.total_power_saving_class_instances",
1339                                 FT_UINT16, BASE_DEC, NULL, 0x1F0, NULL, HFILL
1340                         }
1341                 },
1342                 {
1343                         &hf_reg_power_saving_class_reserved,
1344                         {
1345                                 "Reserved", "wmx.reg.reserved",
1346                                 FT_UINT16, BASE_DEC, NULL, 0xFE00, NULL, HFILL
1347                         }
1348                 },
1349                 {
1350                         &hf_reg_power_saving_class_capability,
1351                         {
1352                                 "Power saving class capability", "wmx.reg.power_saving_class_capability",
1353                                 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL
1354                         }
1355                 },
1356                 {
1357                         &hf_reg_ip_phs_sdu_encap,
1358                         {
1359                                 "Classification/PHS options and SDU encapsulation support", "wmx.reg.ip_phs_sdu_encap",
1360                                 FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL
1361                         }
1362                 },
1363                 {
1364                         &hf_reg_tlv_t_26_method_alloc_ip_addr_secondary_mgmnt_conn,
1365                         {
1366                                 "Method for allocating IP address for the secondary management connection", "wmx.reg.method_alloc_ip_addr_secondary_mgmnt_conn",
1367                                 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL
1368                         }
1369                 },
1370                 {
1371                         &hf_reg_tlv_t_27_handover_supported,
1372                         {
1373                                 "Handover Support", "wmx.reg.handover_supported",
1374                                 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL
1375                         }
1376                 },
1377                 {
1378                         &hf_reg_tlv_t_31_mobility_features_supported,
1379                         {
1380                                 "Mobility Features Supported", "wmx.reg.mobility_features_supported",
1381                                 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL
1382                         }
1383                 },
1384                 {
1385                         &hf_reg_tlv_t_40_arq_ack_type,
1386                         {
1387                                 "ARQ ACK Type", "wmx.reg.arq_ack_type",
1388                                 FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL
1389                         }
1390                 },
1391                 {
1392                         &hf_reg_tlv_t_43_mac_header_ext_header_support,
1393                         {
1394                                 "MAC header and extended subheader support", "wmx.reg.mac_header_ext_header_support",
1395                                 FT_UINT24, BASE_DEC, NULL, 0x0, NULL, HFILL
1396                         }
1397                 },
1398                 {
1399                         &hf_reg_req_bs_switching_timer,
1400                         {
1401                                 "BS switching timer", "wmx.reg.bs_switching_timer",
1402                                 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL
1403                         }
1404                 },
1405         };
1406
1407         /* Setup protocol subtree array */
1408         static int *ett[] =
1409                 {
1410                         &ett_mac_mgmt_msg_reg_req_decoder
1411                 };
1412
1413
1414         proto_mac_mgmt_msg_reg_req_decoder = proto_register_protocol (
1415                 "WiMax REG-REQ Messages", /* name       */
1416                 "WiMax REG-REQ",          /* short name */
1417                 "wmx.reg_req"             /* abbrev     */
1418                 );
1419
1420         proto_register_field_array(proto_mac_mgmt_msg_reg_req_decoder, hf, array_length(hf));
1421         proto_register_subtree_array(ett, array_length(ett));
1422         reg_req_handle = register_dissector("mac_mgmt_msg_reg_req_handler", dissect_mac_mgmt_msg_reg_req_decoder, proto_mac_mgmt_msg_reg_req_decoder);
1423 }
1424
1425 void proto_reg_handoff_mac_mgmt_msg_reg_req(void)
1426 {
1427         dissector_add_uint("wmx.mgmtmsg", MAC_MGMT_MSG_REG_REQ, reg_req_handle);
1428 }
1429
1430 /*
1431  * Editor modelines  -  https://www.wireshark.org/tools/modelines.html
1432  *
1433  * Local variables:
1434  * c-basic-offset: 8
1435  * tab-width: 8
1436  * indent-tabs-mode: t
1437  * End:
1438  *
1439  * vi: set shiftwidth=8 tabstop=8 noexpandtab:
1440  * :indentSize=8:tabSize=8:noTabs=false:
1441  */