epan/dissectors/pidl/ C99 drsuapi
[wireshark-sm.git] / epan / dissectors / packet-nvme.c
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1 /* packet-nvme.c
2 * Routines for NVM Express dissection
3 * Copyright 2016
4 * Code by Parav Pandit
6 * Wireshark - Network traffic analyzer
7 * By Gerald Combs <gerald@wireshark.org>
8 * Copyright 1998 Gerald Combs
10 * SPDX-License-Identifier: GPL-2.0-or-later
13 /* This file dissects NVMe packets received from the underlying
14 * fabric such as RDMA, FC.
15 * This is fabric agnostic dissector and depends on cmd_ctx and q_ctx
16 * It currently aligns to below specification.
17 * http://www.nvmexpress.org/wp-content/uploads/NVM-Express-1_2a.pdf
20 #include "config.h"
22 #include <epan/packet.h>
23 #include <epan/tfs.h>
24 #include <epan/unit_strings.h>
26 #include <wsutil/array.h>
27 #include "packet-nvme.h"
29 void proto_register_nvme(void);
31 static int proto_nvme;
34 /* NVMeOF fields */
35 /* NVMe Fabric Cmd */
36 static int hf_nvmeof_cmd;
37 static int hf_nvmeof_cmd_opc;
38 static int hf_nvmeof_cmd_rsvd;
39 static int hf_nvmeof_cmd_cid;
40 static int hf_nvmeof_cmd_fctype;
41 static int hf_nvmeof_cmd_connect_rsvd1;
42 static int hf_nvmeof_cmd_connect_sgl1;
43 static int hf_nvmeof_cmd_connect_recfmt;
44 static int hf_nvmeof_cmd_connect_qid;
45 static int hf_nvmeof_cmd_connect_sqsize;
46 static int hf_nvmeof_cmd_connect_cattr[5];
47 static int hf_nvmeof_cmd_connect_rsvd2;
48 static int hf_nvmeof_cmd_connect_kato;
49 static int hf_nvmeof_cmd_connect_rsvd3;
50 static int hf_nvmeof_cmd_connect_data_hostid;
51 static int hf_nvmeof_cmd_connect_data_cntlid;
52 static int hf_nvmeof_cmd_connect_data_rsvd0;
53 static int hf_nvmeof_cmd_connect_data_subnqn;
54 static int hf_nvmeof_cmd_connect_data_hostnqn;
55 static int hf_nvmeof_cmd_connect_data_rsvd1;
57 static int hf_nvmeof_cmd_auth_rsdv1;
58 static int hf_nvmeof_cmd_auth_sgl1;
59 static int hf_nvmeof_cmd_auth_rsdv2;
60 static int hf_nvmeof_cmd_auth_spsp0;
61 static int hf_nvmeof_cmd_auth_spsp1;
62 static int hf_nvmeof_cmd_auth_secp;
63 static int hf_nvmeof_cmd_auth_al;
64 static int hf_nvmeof_cmd_auth_rsdv3;
66 static int hf_nvmeof_cmd_disconnect_rsvd0;
67 static int hf_nvmeof_cmd_disconnect_recfmt;
68 static int hf_nvmeof_cmd_disconnect_rsvd1;
70 static int hf_nvmeof_cmd_prop_get_set_rsvd0;
71 static int hf_nvmeof_cmd_prop_get_set_attrib[3];
72 static int hf_nvmeof_cmd_prop_get_set_rsvd1;
73 static int hf_nvmeof_cmd_prop_get_set_offset;
74 static int hf_nvmeof_cmd_prop_get_rsvd2;
76 static int hf_nvmeof_cmd_prop_set_rsvd;
78 static int hf_nvmeof_cmd_generic_rsvd1;
79 static int hf_nvmeof_cmd_generic_field;
81 static int hf_nvmeof_prop_get_set_data;
82 static int hf_nvmeof_prop_get_set_data_4B;
83 static int hf_nvmeof_prop_get_set_data_4B_rsvd;
84 static int hf_nvmeof_prop_get_set_data_8B;
85 static int hf_nvmeof_prop_get_set_cc[10];
86 static int hf_nvmeof_prop_get_set_csts[7];
87 static int hf_nvmeof_prop_get_set_nssr[2];
88 static int hf_nvmeof_prop_get_vs[4];
89 static int hf_nvmeof_prop_get_ccap[17];
92 /* NVMe Fabric CQE */
93 static int hf_nvmeof_cqe;
94 static int hf_nvmeof_cqe_sts;
96 static int hf_nvmeof_cqe_connect_cntlid;
97 static int hf_nvmeof_cqe_connect_authreq;
98 static int hf_nvmeof_cqe_connect_rsvd;
99 static int hf_nvmeof_cqe_prop_set_rsvd;
101 /* tracking Cmd and its respective CQE */
102 int hf_nvmeof_cmd_pkt;
103 int hf_nvmeof_data_req;
104 static int hf_nvmeof_data_tr[NVME_CMD_MAX_TRS];
105 static int hf_nvmeof_cqe_pkt;
106 static int hf_nvmeof_cmd_latency;
108 static const value_string fctype_tbl[] = {
109 { NVME_FCTYPE_PROP_SET, "Property Set" },
110 { NVME_FCTYPE_CONNECT, "Connect" },
111 { NVME_FCTYPE_PROP_GET, "Property Get" },
112 { NVME_FCTYPE_AUTH_SEND, "Authentication Send" },
113 { NVME_FCTYPE_AUTH_RECV, "Authentication Recv" },
114 { NVME_FCTYPE_DISCONNECT, "Disconnect" },
115 { 0, NULL}
118 static const value_string pclass_tbl[] = {
119 { 0x0, "Urgent" },
120 { 0x1, "High" },
121 { 0x2, "Medium" },
122 { 0x3, "Low", },
123 { 0, NULL}
126 static const value_string prop_offset_tbl[] = {
127 { 0x0, "Controller Capabilities"},
128 { 0x8, "Version"},
129 { 0xc, "Reserved"},
130 { 0x10, "Reserved"},
131 { 0x14, "Controller Configuration"},
132 { 0x18, "Reserved"},
133 { 0x1c, "Controller Status"},
134 { 0x20, "NVM Subsystem Reset"},
135 { 0x24, "Reserved"},
136 { 0x28, "Reserved"},
137 { 0x30, "Reserved"},
138 { 0x38, "Reserved"},
139 { 0x3c, "Reserved"},
140 { 0x40, "Reserved"},
141 { 0, NULL}
144 static const value_string attr_size_tbl[] = {
145 { 0, "4 bytes"},
146 { 1, "8 bytes"},
147 { 0, NULL}
150 static const value_string css_table[] = {
151 { 0x0, "NVM IO Command Set"},
152 { 0x1, "Admin Command Set Only"},
153 { 0x0, NULL}
155 static const value_string sn_table[] = {
156 { 0x0, "No Shutdown"},
157 { 0x1, "Normal Shutdown"},
158 { 0x2, "Abrupt Shutdown"},
159 { 0x3, "Reserved"},
160 { 0x0, NULL}
162 static const value_string ams_table[] = {
163 { 0x0, "Round Robin"},
164 { 0x1, "Weighted Round Robin with Urgent Priority Class"},
165 { 0x2, "Reserved"},
166 { 0x3, "Reserved"},
167 { 0x4, "Reserved"},
168 { 0x5, "Reserved"},
169 { 0x6, "Reserved"},
170 { 0x7, "Vendor Specific"},
171 { 0x0, NULL}
174 static const value_string shst_table[] = {
175 { 0x0, "No Shutdown"},
176 { 0x1, "Shutdown in Process"},
177 { 0x2, "Shutdown Complete"},
178 { 0x3, "Reserved"},
179 { 0x0, NULL}
182 /* NVMe Cmd fields */
183 static int hf_nvme_cmd_opc;
184 static int hf_nvme_cmd_rsvd;
185 static int hf_nvme_cmd_cid;
186 static int hf_nvme_cmd_fuse_op;
187 static int hf_nvme_cmd_psdt;
188 static int hf_nvme_cmd_nsid;
189 static int hf_nvme_cmd_rsvd1;
190 static int hf_nvme_cmd_mptr;
191 static int hf_nvme_cmd_sgl;
192 static int hf_nvme_cmd_sgl_desc_type;
193 static int hf_nvme_cmd_sgl_desc_sub_type;
194 static int hf_nvme_cmd_sgl_desc_addr;
195 static int hf_nvme_cmd_sgl_desc_addr_rsvd;
196 static int hf_nvme_cmd_sgl_desc_len;
197 static int hf_nvme_cmd_sgl_desc_rsvd;
198 static int hf_nvme_cmd_sgl_desc_key;
199 static int hf_nvme_cmd_dword10;
200 static int hf_nvme_cmd_dword11;
201 static int hf_nvme_cmd_dword12;
202 static int hf_nvme_cmd_dword13;
203 static int hf_nvme_cmd_dword14;
204 static int hf_nvme_cmd_dword15;
205 static int hf_nvme_cmd_slba;
206 static int hf_nvme_cmd_nlb;
207 static int hf_nvme_cmd_rsvd2;
208 static int hf_nvme_cmd_prinfo;
209 static int hf_nvme_cmd_prinfo_prchk_lbrtag;
210 static int hf_nvme_cmd_prinfo_prchk_apptag;
211 static int hf_nvme_cmd_prinfo_prchk_guard;
212 static int hf_nvme_cmd_prinfo_pract;
213 static int hf_nvme_cmd_fua;
214 static int hf_nvme_cmd_lr;
215 static int hf_nvme_cmd_eilbrt;
216 static int hf_nvme_cmd_elbat;
217 static int hf_nvme_cmd_elbatm;
218 static int hf_nvme_cmd_dsm;
219 static int hf_nvme_cmd_dsm_access_freq;
220 static int hf_nvme_cmd_dsm_access_lat;
221 static int hf_nvme_cmd_dsm_seq_req;
222 static int hf_nvme_cmd_dsm_incompressible;
223 static int hf_nvme_cmd_rsvd3;
224 static int hf_nvme_identify_dword10[4];
225 static int hf_nvme_identify_dword11[3];
226 static int hf_nvme_identify_dword14[3];
228 static int hf_nvme_get_logpage_dword10[6];
229 static int hf_nvme_get_logpage_numd;
230 static int hf_nvme_get_logpage_dword11[3];
231 static int hf_nvme_get_logpage_lpo;
232 static int hf_nvme_get_logpage_dword14[3];
233 static int hf_nvme_set_features_dword10[4];
234 static int hf_nvme_set_features_dword14[3];
235 static int hf_nvme_cmd_set_features_dword11_arb[6];
236 static int hf_nvme_cmd_set_features_dword11_pm[4];
237 static int hf_nvme_cmd_set_features_dword11_lbart[3];
238 static int hf_nvme_cmd_set_features_dword11_tt[5];
239 static int hf_nvme_cmd_set_features_dword11_erec[4];
240 static int hf_nvme_cmd_set_features_dword11_vwce[3];
241 static int hf_nvme_cmd_set_features_dword11_nq[3];
242 static int hf_nvme_cmd_set_features_dword11_irqc[3];
243 static int hf_nvme_cmd_set_features_dword11_irqv[4];
244 static int hf_nvme_cmd_set_features_dword11_wan[3];
245 static int hf_nvme_cmd_set_features_dword11_aec[11];
246 static int hf_nvme_cmd_set_features_dword11_apst[3];
247 static int hf_nvme_cmd_set_features_dword11_kat[2];
248 static int hf_nvme_cmd_set_features_dword11_hctm[3];
249 static int hf_nvme_cmd_set_features_dword11_nops[3];
250 static int hf_nvme_cmd_set_features_dword11_rrl[3];
251 static int hf_nvme_cmd_set_features_dword12_rrl[3];
252 static int hf_nvme_cmd_set_features_dword11_plmc[3];
253 static int hf_nvme_cmd_set_features_dword12_plmc[3];
254 static int hf_nvme_cmd_set_features_dword11_plmw[3];
255 static int hf_nvme_cmd_set_features_dword12_plmw[3];
256 static int hf_nvme_cmd_set_features_dword11_lbasi[3];
257 static int hf_nvme_cmd_set_features_dword11_san[3];
258 static int hf_nvme_cmd_set_features_dword11_eg[4];
259 static int hf_nvme_cmd_set_features_dword11_swp[3];
260 static int hf_nvme_cmd_set_features_dword11_hid[3];
261 static int hf_nvme_cmd_set_features_dword11_rsrvn[6];
262 static int hf_nvme_cmd_set_features_dword11_rsrvp[3];
263 static int hf_nvme_cmd_set_features_dword11_nswp[3];
264 static int hf_nvme_set_features_tr_lbart;
265 static int hf_nvme_set_features_tr_lbart_type;
266 static int hf_nvme_set_features_tr_lbart_attr[4];
267 static int hf_nvme_set_features_tr_lbart_rsvd0;
268 static int hf_nvme_set_features_tr_lbart_slba;
269 static int hf_nvme_set_features_tr_lbart_nlb;
270 static int hf_nvme_set_features_tr_lbart_guid;
271 static int hf_nvme_set_features_tr_lbart_rsvd1;
272 static int hf_nvme_set_features_tr_apst[5];
273 static int hf_nvme_set_features_tr_tst[3];
274 static int hf_nvme_set_features_tr_plmc;
275 static int hf_nvme_set_features_tr_plmc_ee[7];
276 static int hf_nvme_set_features_tr_plmc_rsvd0;
277 static int hf_nvme_set_features_tr_plmc_dtwinrt;
278 static int hf_nvme_set_features_tr_plmc_dtwinwt;
279 static int hf_nvme_set_features_tr_plmc_dtwintt;
280 static int hf_nvme_set_features_tr_plmc_rsvd1;
281 static int hf_nvme_set_features_tr_hbs;
282 static int hf_nvme_set_features_tr_hbs_acre;
283 static int hf_nvme_set_features_tr_hbs_rsvd;
284 static int hf_nvme_get_features_dword10[4];
285 static int hf_nvme_get_features_dword14[3];
286 static int hf_nvme_cmd_get_features_dword11_rrl[3];
287 static int hf_nvme_cmd_get_features_dword11_plmc[3];
288 static int hf_nvme_cmd_get_features_dword11_plmw[3];
289 static int hf_nvme_identify_ns_nsze;
290 static int hf_nvme_identify_ns_ncap;
291 static int hf_nvme_identify_ns_nuse;
292 static int hf_nvme_identify_ns_nsfeat;
293 static int hf_nvme_identify_ns_nlbaf;
294 static int hf_nvme_identify_ns_flbas;
295 static int hf_nvme_identify_ns_mc;
296 static int hf_nvme_identify_ns_dpc;
297 static int hf_nvme_identify_ns_dps;
298 static int hf_nvme_identify_ns_nmic;
299 static int hf_nvme_identify_ns_nguid;
300 static int hf_nvme_identify_ns_eui64;
301 static int hf_nvme_identify_ns_lbafs;
302 static int hf_nvme_identify_ns_lbaf;
303 static int hf_nvme_identify_ns_rsvd;
304 static int hf_nvme_identify_ns_vs;
305 static int hf_nvme_identify_ctrl_vid;
306 static int hf_nvme_identify_ctrl_ssvid;
307 static int hf_nvme_identify_ctrl_sn;
308 static int hf_nvme_identify_ctrl_mn;
309 static int hf_nvme_identify_ctrl_fr;
310 static int hf_nvme_identify_ctrl_rab;
311 static int hf_nvme_identify_ctrl_ieee;
312 static int hf_nvme_identify_ctrl_cmic[6];
313 static int hf_nvme_identify_ctrl_mdts;
314 static int hf_nvme_identify_ctrl_cntlid;
315 static int hf_nvme_identify_ctrl_ver;
316 static int hf_nvme_identify_ctrl_ver_min;
317 static int hf_nvme_identify_ctrl_ver_mjr;
318 static int hf_nvme_identify_ctrl_ver_ter;
319 static int hf_nvme_identify_ctrl_rtd3r;
320 static int hf_nvme_identify_ctrl_rtd3e;
321 static int hf_nvme_identify_ctrl_oaes[10];
322 static int hf_nvme_identify_ctrl_ctratt[12];
323 static int hf_nvme_identify_ctrl_rrls[17];
324 static int hf_nvme_identify_ctrl_rsvd0;
325 static int hf_nvme_identify_ctrl_cntrltype;
326 static int hf_nvme_identify_ctrl_fguid;
327 static int hf_nvme_identify_ctrl_fguid_vse;
328 static int hf_nvme_identify_ctrl_fguid_oui;
329 static int hf_nvme_identify_ctrl_fguid_ei;
330 static int hf_nvme_identify_ctrl_crdt1;
331 static int hf_nvme_identify_ctrl_crdt2;
332 static int hf_nvme_identify_ctrl_crdt3;
333 static int hf_nvme_identify_ctrl_rsvd1;
334 static int hf_nvme_identify_ctrl_mi;
335 static int hf_nvme_identify_ctrl_mi_rsvd;
336 static int hf_nvme_identify_ctrl_mi_nvmsr[4];
337 static int hf_nvme_identify_ctrl_mi_vwci[3];
338 static int hf_nvme_identify_ctrl_mi_mec[4];
339 static int hf_nvme_identify_ctrl_oacs[12];
340 static int hf_nvme_identify_ctrl_acl;
341 static int hf_nvme_identify_ctrl_aerl;
342 static int hf_nvme_identify_ctrl_frmw[5];
343 static int hf_nvme_identify_ctrl_lpa[7];
344 static int hf_nvme_identify_ctrl_elpe;
345 static int hf_nvme_identify_ctrl_npss;
346 static int hf_nvme_identify_ctrl_avscc[3];
347 static int hf_nvme_identify_ctrl_apsta[3];
348 static int hf_nvme_identify_ctrl_wctemp;
349 static int hf_nvme_identify_ctrl_cctemp;
350 static int hf_nvme_identify_ctrl_mtfa;
351 static int hf_nvme_identify_ctrl_hmpre;
352 static int hf_nvme_identify_ctrl_hmmin;
353 static int hf_nvme_identify_ctrl_tnvmcap;
354 static int hf_nvme_identify_ctrl_unvmcap;
355 static int hf_nvme_identify_ctrl_rpmbs[6];
356 static int hf_nvme_identify_ctrl_edstt;
357 static int hf_nvme_identify_ctrl_dsto[3];
358 static int hf_nvme_identify_ctrl_fwug;
359 static int hf_nvme_identify_ctrl_kas;
360 static int hf_nvme_identify_ctrl_hctma[3];
361 static int hf_nvme_identify_ctrl_mntmt;
362 static int hf_nvme_identify_ctrl_mxtmt;
363 static int hf_nvme_identify_ctrl_sanicap[7];
364 static int hf_nvme_identify_ctrl_hmmminds;
365 static int hf_nvme_identify_ctrl_hmmaxd;
366 static int hf_nvme_identify_ctrl_nsetidmax;
367 static int hf_nvme_identify_ctrl_endgidmax;
368 static int hf_nvme_identify_ctrl_anatt;
369 static int hf_nvme_identify_ctrl_anacap[9];
370 static int hf_nvme_identify_ctrl_anagrpmax;
371 static int hf_nvme_identify_ctrl_nanagrpid;
372 static int hf_nvme_identify_ctrl_pels;
373 static int hf_nvme_identify_ctrl_rsvd2;
374 static int hf_nvme_identify_ctrl_sqes[3];
375 static int hf_nvme_identify_ctrl_cqes[3];
376 static int hf_nvme_identify_ctrl_maxcmd;
377 static int hf_nvme_identify_ctrl_nn;
378 static int hf_nvme_identify_ctrl_oncs[10];
379 static int hf_nvme_identify_ctrl_fuses[3];
380 static int hf_nvme_identify_ctrl_fna[5];
381 static int hf_nvme_identify_ctrl_vwc[4];
382 static int hf_nvme_identify_ctrl_awun;
383 static int hf_nvme_identify_ctrl_awupf;
384 static int hf_nvme_identify_ctrl_nvscc[3];
385 static int hf_nvme_identify_ctrl_nwpc[5];
386 static int hf_nvme_identify_ctrl_acwu;
387 static int hf_nvme_identify_ctrl_rsvd3;
388 static int hf_nvme_identify_ctrl_sgls[11];
389 static int hf_nvme_identify_ctrl_mnan;
390 static int hf_nvme_identify_ctrl_rsvd4;
391 static int hf_nvme_identify_ctrl_subnqn;
392 static int hf_nvme_identify_ctrl_rsvd5;
393 static int hf_nvme_identify_ctrl_nvmeof;
394 static int hf_nvme_identify_ctrl_nvmeof_ioccsz;
395 static int hf_nvme_identify_ctrl_nvmeof_iorcsz;
396 static int hf_nvme_identify_ctrl_nvmeof_icdoff;
397 static int hf_nvme_identify_ctrl_nvmeof_fcatt[3];
398 static int hf_nvme_identify_ctrl_nvmeof_msdbd;
399 static int hf_nvme_identify_ctrl_nvmeof_ofcs[3];
400 static int hf_nvme_identify_ctrl_nvmeof_rsvd;
401 static int hf_nvme_identify_ctrl_psds;
402 static int hf_nvme_identify_ctrl_psd;
403 static int hf_nvme_identify_ctrl_psd_mp;
404 static int hf_nvme_identify_ctrl_psd_rsvd0;
405 static int hf_nvme_identify_ctrl_psd_mxps;
406 static int hf_nvme_identify_ctrl_psd_nops;
407 static int hf_nvme_identify_ctrl_psd_rsvd1;
408 static int hf_nvme_identify_ctrl_psd_enlat;
409 static int hf_nvme_identify_ctrl_psd_exlat;
410 static int hf_nvme_identify_ctrl_psd_rrt;
411 static int hf_nvme_identify_ctrl_psd_rsvd2;
412 static int hf_nvme_identify_ctrl_psd_rrl;
413 static int hf_nvme_identify_ctrl_psd_rsvd3;
414 static int hf_nvme_identify_ctrl_psd_rwt;
415 static int hf_nvme_identify_ctrl_psd_rsvd4;
416 static int hf_nvme_identify_ctrl_psd_rwl;
417 static int hf_nvme_identify_ctrl_psd_rsvd5;
418 static int hf_nvme_identify_ctrl_psd_idlp;
419 static int hf_nvme_identify_ctrl_psd_rsvd6;
420 static int hf_nvme_identify_ctrl_psd_ips;
421 static int hf_nvme_identify_ctrl_psd_rsvd7;
422 static int hf_nvme_identify_ctrl_psd_actp;
423 static int hf_nvme_identify_ctrl_psd_apw;
424 static int hf_nvme_identify_ctrl_psd_rsvd8;
425 static int hf_nvme_identify_ctrl_psd_aps;
426 static int hf_nvme_identify_ctrl_psd_rsvd9;
427 static int hf_nvme_identify_ctrl_vs;
429 static int hf_nvme_identify_nslist_nsid;
431 /* get logpage response */
432 static int hf_nvme_get_logpage_ify_genctr;
433 static int hf_nvme_get_logpage_ify_numrec;
434 static int hf_nvme_get_logpage_ify_recfmt;
435 static int hf_nvme_get_logpage_ify_rsvd;
436 static int hf_nvme_get_logpage_ify_rcrd;
437 static int hf_nvme_get_logpage_ify_rcrd_trtype;
438 static int hf_nvme_get_logpage_ify_rcrd_adrfam;
439 static int hf_nvme_get_logpage_ify_rcrd_subtype;
440 static int hf_nvme_get_logpage_ify_rcrd_treq[4];
441 static int hf_nvme_get_logpage_ify_rcrd_portid;
442 static int hf_nvme_get_logpage_ify_rcrd_cntlid;
443 static int hf_nvme_get_logpage_ify_rcrd_asqsz;
444 static int hf_nvme_get_logpage_ify_rcrd_rsvd0;
445 static int hf_nvme_get_logpage_ify_rcrd_trsvcid;
446 static int hf_nvme_get_logpage_ify_rcrd_rsvd1;
447 static int hf_nvme_get_logpage_ify_rcrd_subnqn;
448 static int hf_nvme_get_logpage_ify_rcrd_traddr;
449 static int hf_nvme_get_logpage_ify_rcrd_tsas;
450 static int hf_nvme_get_logpage_ify_rcrd_tsas_rdma_qptype;
451 static int hf_nvme_get_logpage_ify_rcrd_tsas_rdma_prtype;
452 static int hf_nvme_get_logpage_ify_rcrd_tsas_rdma_cms;
453 static int hf_nvme_get_logpage_ify_rcrd_tsas_rdma_rsvd0;
454 static int hf_nvme_get_logpage_ify_rcrd_tsas_rdma_pkey;
455 static int hf_nvme_get_logpage_ify_rcrd_tsas_rdma_rsvd1;
456 static int hf_nvme_get_logpage_ify_rcrd_tsas_tcp_sectype;
457 static int hf_nvme_get_logpage_ify_rcrd_tsas_tcp_rsvd;
458 static int hf_nvme_get_logpage_errinf_errcnt;
459 static int hf_nvme_get_logpage_errinf_sqid;
460 static int hf_nvme_get_logpage_errinf_cid;
461 static int hf_nvme_get_logpage_errinf_sf[3];
462 static int hf_nvme_get_logpage_errinf_pel[4];
463 static int hf_nvme_get_logpage_errinf_lba;
464 static int hf_nvme_get_logpage_errinf_ns;
465 static int hf_nvme_get_logpage_errinf_vsi;
466 static int hf_nvme_get_logpage_errinf_trtype;
467 static int hf_nvme_get_logpage_errinf_rsvd0;
468 static int hf_nvme_get_logpage_errinf_csi;
469 static int hf_nvme_get_logpage_errinf_tsi;
470 static int hf_nvme_get_logpage_errinf_rsvd1;
471 static int hf_nvme_get_logpage_smart_cw[8];
472 static int hf_nvme_get_logpage_smart_ct;
473 static int hf_nvme_get_logpage_smart_asc;
474 static int hf_nvme_get_logpage_smart_ast;
475 static int hf_nvme_get_logpage_smart_lpu;
476 static int hf_nvme_get_logpage_smart_egcws[6];
477 static int hf_nvme_get_logpage_smart_rsvd0;
478 static int hf_nvme_get_logpage_smart_dur;
479 static int hf_nvme_get_logpage_smart_duw;
480 static int hf_nvme_get_logpage_smart_hrc;
481 static int hf_nvme_get_logpage_smart_hwc;
482 static int hf_nvme_get_logpage_smart_cbt;
483 static int hf_nvme_get_logpage_smart_pc;
484 static int hf_nvme_get_logpage_smart_poh;
485 static int hf_nvme_get_logpage_smart_us;
486 static int hf_nvme_get_logpage_smart_mie;
487 static int hf_nvme_get_logpage_smart_ele;
488 static int hf_nvme_get_logpage_smart_wctt;
489 static int hf_nvme_get_logpage_smart_cctt;
490 static int hf_nvme_get_logpage_smart_ts[9];
491 static int hf_nvme_get_logpage_smart_tmt1c;
492 static int hf_nvme_get_logpage_smart_tmt2c;
493 static int hf_nvme_get_logpage_smart_tmt1t;
494 static int hf_nvme_get_logpage_smart_tmt2t;
495 static int hf_nvme_get_logpage_smart_rsvd1;
496 static int hf_nvme_get_logpage_fw_slot_afi[5];
497 static int hf_nvme_get_logpage_fw_slot_rsvd0;
498 static int hf_nvme_get_logpage_fw_slot_frs[8];
499 static int hf_nvme_get_logpage_fw_slot_rsvd1;
500 static int hf_nvme_get_logpage_changed_nslist;
501 static int hf_nvme_get_logpage_cmd_and_eff_cs;
502 static int hf_nvme_get_logpage_cmd_and_eff_cseds[10];
503 static int hf_nvme_get_logpage_selftest_csto[3];
504 static int hf_nvme_get_logpage_selftest_cstc[3];
505 static int hf_nvme_get_logpage_selftest_rsvd;
506 static int hf_nvme_get_logpage_selftest_res;
507 static int hf_nvme_get_logpage_selftest_res_status[3];
508 static int hf_nvme_get_logpage_selftest_res_sn;
509 static int hf_nvme_get_logpage_selftest_res_vdi[6];
510 static int hf_nvme_get_logpage_selftest_res_rsvd;
511 static int hf_nvme_get_logpage_selftest_res_poh;
512 static int hf_nvme_get_logpage_selftest_res_nsid;
513 static int hf_nvme_get_logpage_selftest_res_flba;
514 static int hf_nvme_get_logpage_selftest_res_sct[3];
515 static int hf_nvme_get_logpage_selftest_res_sc;
516 static int hf_nvme_get_logpage_selftest_res_vs;
517 static int hf_nvme_get_logpage_telemetry_li;
518 static int hf_nvme_get_logpage_telemetry_rsvd0;
519 static int hf_nvme_get_logpage_telemetry_ieee;
520 static int hf_nvme_get_logpage_telemetry_da1lb;
521 static int hf_nvme_get_logpage_telemetry_da2lb;
522 static int hf_nvme_get_logpage_telemetry_da3lb;
523 static int hf_nvme_get_logpage_telemetry_rsvd1;
524 static int hf_nvme_get_logpage_telemetry_da;
525 static int hf_nvme_get_logpage_telemetry_dgn;
526 static int hf_nvme_get_logpage_telemetry_ri;
527 static int hf_nvme_get_logpage_telemetry_db;
528 static int hf_nvme_get_logpage_egroup_cw[6];
529 static int hf_nvme_get_logpage_egroup_rsvd0;
530 static int hf_nvme_get_logpage_egroup_as;
531 static int hf_nvme_get_logpage_egroup_ast;
532 static int hf_nvme_get_logpage_egroup_pu;
533 static int hf_nvme_get_logpage_egroup_rsvd1;
534 static int hf_nvme_get_logpage_egroup_ee;
535 static int hf_nvme_get_logpage_egroup_dur;
536 static int hf_nvme_get_logpage_egroup_duw;
537 static int hf_nvme_get_logpage_egroup_muw;
538 static int hf_nvme_get_logpage_egroup_hrc;
539 static int hf_nvme_get_logpage_egroup_hwc;
540 static int hf_nvme_get_logpage_egroup_mdie;
541 static int hf_nvme_get_logpage_egroup_ele;
542 static int hf_nvme_get_logpage_egroup_rsvd2;
543 static int hf_nvme_get_logpage_pred_lat_status[3];
544 static int hf_nvme_get_logpage_pred_lat_rsvd0;
545 static int hf_nvme_get_logpage_pred_lat_etype[7];
546 static int hf_nvme_get_logpage_pred_lat_rsvd1;
547 static int hf_nvme_get_logpage_pred_lat_dtwin_rt;
548 static int hf_nvme_get_logpage_pred_lat_dtwin_wt;
549 static int hf_nvme_get_logpage_pred_lat_dtwin_tm;
550 static int hf_nvme_get_logpage_pred_lat_ndwin_tmh;
551 static int hf_nvme_get_logpage_pred_lat_ndwin_tml;
552 static int hf_nvme_get_logpage_pred_lat_rsvd2;
553 static int hf_nvme_get_logpage_pred_lat_dtwin_re;
554 static int hf_nvme_get_logpage_pred_lat_dtwin_we;
555 static int hf_nvme_get_logpage_pred_lat_dtwin_te;
556 static int hf_nvme_get_logpage_pred_lat_rsvd3;
557 static int hf_nvme_get_logpage_pred_lat_aggreg_ne;
558 static int hf_nvme_get_logpage_pred_lat_aggreg_nset;
559 static int hf_nvme_get_logpage_ana_chcnt;
560 static int hf_nvme_get_logpage_ana_ngd;
561 static int hf_nvme_get_logpage_ana_rsvd;
562 static int hf_nvme_get_logpage_ana_grp;
563 static int hf_nvme_get_logpage_ana_grp_id;
564 static int hf_nvme_get_logpage_ana_grp_nns;
565 static int hf_nvme_get_logpage_ana_grp_chcnt;
566 static int hf_nvme_get_logpage_ana_grp_anas[3];
567 static int hf_nvme_get_logpage_ana_grp_rsvd;
568 static int hf_nvme_get_logpage_ana_grp_nsid;
569 static int hf_nvme_get_logpage_lba_status_lslplen;
570 static int hf_nvme_get_logpage_lba_status_nlslne;
571 static int hf_nvme_get_logpage_lba_status_estulb;
572 static int hf_nvme_get_logpage_lba_status_rsvd;
573 static int hf_nvme_get_logpage_lba_status_lsgc;
574 static int hf_nvme_get_logpage_lba_status_nel;
575 static int hf_nvme_get_logpage_lba_status_nel_ne;
576 static int hf_nvme_get_logpage_lba_status_nel_ne_neid;
577 static int hf_nvme_get_logpage_lba_status_nel_ne_nlrd;
578 static int hf_nvme_get_logpage_lba_status_nel_ne_ratype;
579 static int hf_nvme_get_logpage_lba_status_nel_ne_rsvd;
580 static int hf_nvme_get_logpage_lba_status_nel_ne_rd;
581 static int hf_nvme_get_logpage_lba_status_nel_ne_rd_rslba;
582 static int hf_nvme_get_logpage_lba_status_nel_ne_rd_rnlb;
583 static int hf_nvme_get_logpage_lba_status_nel_ne_rd_rsvd;
584 static int hf_nvme_get_logpage_egroup_aggreg_ne;
585 static int hf_nvme_get_logpage_egroup_aggreg_eg;
586 static int hf_nvme_get_logpage_reserv_notif_lpc;
587 static int hf_nvme_get_logpage_reserv_notif_lpt;
588 static int hf_nvme_get_logpage_reserv_notif_nalp;
589 static int hf_nvme_get_logpage_reserv_notif_rsvd0;
590 static int hf_nvme_get_logpage_reserv_notif_nsid;
591 static int hf_nvme_get_logpage_reserv_notif_rsvd1;
592 static int hf_nvme_get_logpage_sanitize_sprog;
593 static int hf_nvme_get_logpage_sanitize_sstat[5];
594 static int hf_nvme_get_logpage_sanitize_scdw10;
595 static int hf_nvme_get_logpage_sanitize_eto;
596 static int hf_nvme_get_logpage_sanitize_etbe;
597 static int hf_nvme_get_logpage_sanitize_etce;
598 static int hf_nvme_get_logpage_sanitize_etond;
599 static int hf_nvme_get_logpage_sanitize_etbend;
600 static int hf_nvme_get_logpage_sanitize_etcend;
601 static int hf_nvme_get_logpage_sanitize_rsvd;
602 static int hf_nvme_get_logpage_disc_rcrd_eflags[4];
604 /* NVMe CQE fields */
605 static int hf_nvme_cqe_dword0;
606 static int hf_nvme_cqe_aev_dword0[6];
607 static int hf_nvme_cqe_dword0_sf_nq[3];
608 static int hf_nvme_cqe_dword0_sf_err;
610 static int hf_nvme_cqe_get_features_dword0_arb[6];
611 static int hf_nvme_cqe_get_features_dword0_pm[4];
612 static int hf_nvme_cqe_get_features_dword0_lbart[3];
613 static int hf_nvme_cqe_get_features_dword0_tt[5];
614 static int hf_nvme_cqe_get_features_dword0_erec[4];
615 static int hf_nvme_cqe_get_features_dword0_vwce[3];
616 static int hf_nvme_cqe_get_features_dword0_nq[3];
617 static int hf_nvme_cqe_get_features_dword0_irqc[3];
618 static int hf_nvme_cqe_get_features_dword0_irqv[4];
619 static int hf_nvme_cqe_get_features_dword0_wan[3];
620 static int hf_nvme_cqe_get_features_dword0_aec[11];
621 static int hf_nvme_cqe_get_features_dword0_apst[3];
622 static int hf_nvme_cqe_get_features_dword0_kat[2];
623 static int hf_nvme_cqe_get_features_dword0_hctm[3];
624 static int hf_nvme_cqe_get_features_dword0_nops[3];
625 static int hf_nvme_cqe_get_features_dword0_rrl[3];
626 static int hf_nvme_cqe_get_features_dword0_plmc[3];
627 static int hf_nvme_cqe_get_features_dword0_plmw[3];
628 static int hf_nvme_cqe_get_features_dword0_lbasi[3];
629 static int hf_nvme_cqe_get_features_dword0_san[3];
630 static int hf_nvme_cqe_get_features_dword0_eg[4];
631 static int hf_nvme_cqe_get_features_dword0_swp[3];
632 static int hf_nvme_cqe_get_features_dword0_hid[3];
633 static int hf_nvme_cqe_get_features_dword0_rsrvn[6];
634 static int hf_nvme_cqe_get_features_dword0_rsrvp[3];
635 static int hf_nvme_cqe_get_features_dword0_nswp[3];
637 static int hf_nvme_cqe_dword1;
638 static int hf_nvme_cqe_sqhd;
639 static int hf_nvme_cqe_sqid;
640 static int hf_nvme_cqe_cid;
641 static int hf_nvme_cqe_status[7];
642 static int hf_nvme_cqe_status_rsvd;
644 /* tracking Cmd and its respective CQE */
645 static int hf_nvme_cmd_pkt;
646 static int hf_nvme_data_req;
647 static int hf_nvme_data_tr[NVME_CMD_MAX_TRS];
648 static int hf_nvme_cqe_pkt;
649 static int hf_nvme_cmd_latency;
651 /* Data response fields */
652 static int hf_nvme_gen_data;
653 /* Initialize the subtree pointers */
654 static int ett_data;
656 #define NVME_AQ_OPC_DELETE_SQ 0x0
657 #define NVME_AQ_OPC_CREATE_SQ 0x1
658 #define NVME_AQ_OPC_GET_LOG_PAGE 0x2
659 #define NVME_AQ_OPC_DELETE_CQ 0x4
660 #define NVME_AQ_OPC_CREATE_CQ 0x5
661 #define NVME_AQ_OPC_IDENTIFY 0x6
662 #define NVME_AQ_OPC_ABORT 0x8
663 #define NVME_AQ_OPC_SET_FEATURES 0x9
664 #define NVME_AQ_OPC_GET_FEATURES 0xa
665 #define NVME_AQ_OPC_ASYNC_EVE_REQ 0xc
666 #define NVME_AQ_OPC_NS_MGMT 0xd
667 #define NVME_AQ_OPC_FW_COMMIT 0x10
668 #define NVME_AQ_OPC_FW_IMG_DOWNLOAD 0x11
669 #define NVME_AQ_OPC_NS_ATTACH 0x15
670 #define NVME_AQ_OPC_KEEP_ALIVE 0x18
672 #define NVME_IOQ_OPC_FLUSH 0x0
673 #define NVME_IOQ_OPC_WRITE 0x1
674 #define NVME_IOQ_OPC_READ 0x2
675 #define NVME_IOQ_OPC_WRITE_UNCORRECTABLE 0x4
676 #define NVME_IOQ_OPC_COMPARE 0x5
677 #define NVME_IOQ_OPC_WRITE_ZEROS 0x8
678 #define NVME_IOQ_OPC_DATASET_MGMT 0x9
679 #define NVME_IOQ_OPC_RESV_REG 0xd
680 #define NVME_IOQ_OPC_RESV_REPORT 0xe
681 #define NVME_IOQ_OPC_RESV_ACQUIRE 0x11
682 #define NVME_IOQ_OPC_RESV_RELEASE 0x15
684 #define NVME_IDENTIFY_CNS_IDENTIFY_NS 0x0
685 #define NVME_IDENTIFY_CNS_IDENTIFY_CTRL 0x1
686 #define NVME_IDENTIFY_CNS_IDENTIFY_NSLIST 0x2
688 typedef enum {
689 NVME_CQE_SCT_GENERIC = 0x0,
690 NVME_CQE_SCT_COMMAND = 0x1,
691 NVME_CQE_SCT_MEDIA = 0x2,
692 NVME_CQE_SCT_PATH = 0x3,
693 NVME_CQE_SCT_VENDOR = 0x7,
694 } nvme_cqe_sct_t;
696 typedef enum {
697 NVME_CQE_SC_GEN_CMD_OK = 0x00,
698 NVME_CQE_SC_CMD_INVALID_OPCODE = 0x01,
699 NVME_CQE_SC_GEN_CMD_INVALID_FIELD = 0x02,
700 NVME_CQE_SC_GEN_CMD_CID_CONFLICT = 0x03,
701 NVME_CQE_SC_GEN_DATA_TRANSFER_ERR = 0x04,
702 NVME_CQE_SC_GEN_ABORT_DUE_TO_POWER_LOSS = 0x05,
703 NVME_CQE_SC_GEN_INTERNAL_ERROR = 0x06,
704 NVME_CQE_SC_GEN_ABORT_REQUESTED = 0x07,
705 NVME_CQE_SC_GEN_ABORT_DUE_TO_SQ_DELETE = 0x08,
706 NVME_CQE_SC_GEN_ABORT_DUE_TO_FAILED_FUSE = 0x09,
707 NVME_CQE_SC_GEN_ABORT_DUE_TO_MISSED_FUSE = 0x0A,
708 NVME_CQE_SC_GEN_INVALID_NAMESPACE_OR_FMT = 0x0B,
709 NVME_CQE_SC_GEN_COMMAND_SEQUENCE_ERR = 0x0C,
710 NVME_CQE_SC_GEN_INVALID_SGL_SD = 0x0D,
711 NVME_CQE_SC_GEN_INVALID_SGL_SD_NUM = 0x0E,
712 NVME_CQE_SC_GEN_INVALID_SGL_LEN = 0x0F,
713 NVME_CQE_SC_GEN_INVALID_MDATA_SGL_LEN = 0x10,
714 NVME_CQE_SC_GEN_INVALID_SGL_SD_TYPE = 0x11,
715 NVME_CQE_SC_GEN_INVALID_USE_OF_MC_BUF = 0x12,
716 NVME_CQE_SC_GEN_INVALID_PRP_OFFSET = 0x13,
717 NVME_CQE_SC_GEN_ATOMIC_WRITE_UNIT_EXCEED = 0x14,
718 NVME_CQE_SC_GEN_OPERATION_DENIED = 0x15,
719 NVME_CQE_SC_GEN_INVALID_SGL_OFFSET = 0x16,
720 NVME_CQE_SC_GEN_RESERVED_17H = 0x17,
721 NVME_CQE_SC_GEN_HOST_ID_INVALID_FMT = 0x18,
722 NVME_CQE_SC_GEN_KEEP_ALLIVE_EXPIRED = 0x19,
723 NVME_CQE_SC_GEN_KEEP_ALIVE_INVALID = 0x1A,
724 NVME_CQE_SC_GEN_ABORT_DUE_TO_PREEMPT_ABRT = 0x1B,
725 NVME_CQE_SC_GEN_SANITIZE_FAILED = 0x1C,
726 NVME_CQE_SC_GEN_SANITZE_IN_PROGRESS = 0x1D,
727 NVME_CQE_SC_GEN_SGL_BLOCK_GRAN_INVALID = 0x1E,
728 NVME_CQE_SC_GEN_CMD_NOT_SUPP_IN_CMB = 0x1F,
729 NVME_CQE_SC_GEN_NAMESPACE_IS_WP = 0x20,
730 NVME_CQE_SC_GEN_COMMAND_INTERRUPTED = 0x21,
731 NVME_CQE_SC_GEN_TRANSIENT_TRASPORT_ERROR = 0x22,
732 NVME_CQE_SC_GEN_LBA_OUT_OF_RANGE = 0x80,
733 NVME_CQE_SC_GEN_CAPACITY_EXCEED = 0x81,
734 NVME_CQE_SC_GEN_NAMESPACE_NOT_ERADY = 0x82,
735 NVME_CQE_SC_GEN_RESERVATION_CONFLICT = 0x83,
736 NVME_CQE_SC_GEN_FMT_IN_PROGRESS = 0x84,
737 } nvme_cqe_sc_gen_t;
739 typedef enum {
740 NVME_CQE_SC_CMD_INVALID_CQ = 0x00,
741 NVME_CQE_SC_CMD_INVALID_QID = 0x01,
742 NVME_CQE_SC_CMD_INVALID_QUEUE_SIZE = 0x02,
743 NVME_CQE_SC_CMD_ABORT_LIMIT_EXCEED = 0x03,
744 NVME_CQE_SC_CMD_RESERVED_4H = 0x04,
745 NVME_CQE_SC_CMD_ASYNC_REQ_LIMIT_EXCEED = 0x05,
746 NVME_CQE_SC_CMD_INVALID_FW_SLOT = 0x06,
747 NVME_CQE_SC_CMD_INVALID_FW_IMAGE = 0x07,
748 NVME_CQE_SC_CMD_INVALID_IRQ_VECTOR = 0x08,
749 NVME_CQE_SC_CMD_INVALID_LOG_PAGE = 0x09,
750 NVME_CQE_SC_CMD_INVALID_FMT = 0x0A,
751 NVME_CQE_SC_CMD_FW_ACTIVATION_NEEDS_RESET = 0x0B,
752 NVME_CQE_SC_CMD_INVALID_QUEUE_DELETE = 0x0C,
753 NVME_CQE_SC_CMD_FEATURE_ID_NOT_SAVEABLE = 0x0D,
754 NVME_CQE_SC_CMD_FEATURE_NOT_CHANGEABLE = 0x0E,
755 NVME_CQE_SC_CMD_FEATURE_NOT_NAMESPACE = 0x0F,
756 NVME_CQE_SC_CMD_FEATURE_ACTIVATION_NEEDS_NVM_RESET = 0x10,
757 NVME_CQE_SC_CMD_FEATURE_ACTIVATION_NEEDS_CNTRL_RESET = 0x11,
758 NVME_CQE_SC_CMD_FW_ACTIVATION_NEED_MAX_TIME = 0x12,
759 NVME_CQE_SC_CMD_FW_ACTIVATION_PROHIBITED = 0x13,
760 NVME_CQE_SC_CMD_OVERLAPPING_RANGE = 0x14,
761 NVME_CQE_SC_CMD_NAMESPACE_INSUF_CAPACITY = 0x15,
762 NVME_CQE_SC_CMD_NAMESPACE_ID_NOT_AVAILABLE = 0x16,
763 NVME_CQE_SC_CMD_RESERVED_17H = 0x17,
764 NVME_CQE_SC_CMD_NAMESPACE_ALREADY_ATATCHED = 0x18,
765 NVME_CQE_SC_CMD_NAMESPACE_IS_PRIVATE = 0x19,
766 NVME_CQE_SC_CMD_NAMESPACE_NOT_ATTACHED = 0x1A,
767 NVME_CQE_SC_CMD_THIN_PROVISION_NOT_SUPP = 0x1B,
768 NVME_CQE_SC_CMD_INVALID_CNTRL_LIST = 0x1C,
769 NVME_CQE_SC_CMD_SELF_TEST_IN_PROGRESS = 0x1D,
770 NVME_CQE_SC_CMD_BOOT_PART_WRITE_PROHIBIT = 0x1E,
771 NVME_CQE_SC_CMD_INVALID_CNTRL_ID = 0x1F,
772 NVME_CQE_SC_CMD_INVALID_SECOND_CNTRL_STATE = 0x20,
773 NVME_CQE_SC_CMD_IBVALID_CNRL_RES_NUM = 0x21,
774 NVME_CQE_SC_CMD_INVALID_RESOURSE_ID = 0x22,
775 NVME_CQE_SC_CMD_SANITIZE_PROHIBIT_WITH_PMR = 0x23,
776 NVME_CQE_SC_CMD_INVALID_ANA_GROUP_ID = 0x24,
777 NVME_CQE_SC_CMD_ANA_ATTACH_FAILED = 0x25,
778 NVME_CQE_SC_CMD_CONFLICTING_ATTRS = 0x80,
779 NVME_CQE_SC_CMD_INVALID_PROTECTION_INF = 0x81,
780 NVME_CQE_SC_CMD_WRITE_TO_RO_REGION = 0x82,
781 } nvme_cqe_sc_cmd_t;
783 typedef enum {
784 NVMEOF_CQE_SC_CMD_INCOMPAT_FORMAT = 0x80,
785 NVMEOF_CQE_SC_CMD_CONT_BUSY = 0x81,
786 NVMEOF_CQE_SC_CMD_CNCT_INV_PARAMS = 0x82,
787 NVMEOF_CQE_SC_CMD_CNCT_RESTART_DISC = 0x83,
788 NVMEOF_CQE_SC_CMD_CNCT_INV_HOST = 0x84,
789 NVMEOF_CQE_SC_CMD_INV_QUEUE_TYPE = 0x85,
790 NVMEOF_CQE_SC_CMD_DISC_RESTART = 0x90,
791 NVMEOF_CQE_SC_CMD_AUTH_REQ = 0x91,
792 } nvmeof_cqe_sc_cmd_t;
794 typedef enum {
795 NVME_CQE_SC_MEDIA_WRITE_FAULT = 0x80,
796 NVME_CQE_SC_MEDIA_READ_FAULT = 0x81,
797 NVME_CQE_SC_MEDIA_ETE_GUARD_CHECK_ERR = 0x82,
798 NVME_CQE_SC_MEDIA_ETE_APPTAG_CHECK_ERR = 0x83,
799 NVME_CQE_SC_MEDIA_ETE_REFTAG_CHECK_ERR = 0x84,
800 NVME_CQE_SC_MEDIA_COMPARE_FAILURE = 0x85,
801 NVME_CQE_SC_MEDIA_ACCESS_DENIED = 0x86,
802 NVME_CQE_SC_MEDIA_DEALLOCATED_LBA = 0x87,
803 } nvme_cqe_sc_media_t;
805 typedef enum {
806 NVME_CQE_SC_PATH_INTERNAL_PATH_ERROR = 0x00,
807 NVME_CQE_SC_PATH_ANA_PERSISTENT_LOSS = 0x01,
808 NVME_CQE_SC_PATH_ANA_INACCESSIBLE = 0x02,
809 NVME_CQE_SC_PATH_ANA_TRANSIENT = 0x03,
810 NVME_CQE_SC_PATH_CNTRL_PATH_ERROR = 0x60,
811 NVME_CQE_SC_PATH_HOST_PATH_ERROR = 0x70,
812 NVME_CQE_SC_PATH_CMD_ABORT = 0x71,
813 } nvme_cqe_sc_path_t;
815 static const value_string nvme_cqe_sct_tbl[] = {
816 { NVME_CQE_SCT_GENERIC, "Generic Command Status" },
817 { NVME_CQE_SCT_COMMAND, "Command Specific Status" },
818 { NVME_CQE_SCT_MEDIA, "Media and Data Integrity Errors" },
819 { NVME_CQE_SCT_PATH, "Path Related Status" },
820 { NVME_CQE_SCT_VENDOR, "Vendor Specific" },
821 { 0, NULL },
824 static const value_string nvme_cqe_sc_gen_tbl[] = {
825 { NVME_CQE_SC_GEN_CMD_OK, "Successful Completion" },
826 { NVME_CQE_SC_CMD_INVALID_OPCODE, "Invalid opcode field" },
827 { NVME_CQE_SC_GEN_CMD_INVALID_FIELD, "Invalid Field in Command" },
828 { NVME_CQE_SC_GEN_CMD_CID_CONFLICT, "Command ID Conflict" },
829 { NVME_CQE_SC_GEN_DATA_TRANSFER_ERR, "Data Transfer Error" },
830 { NVME_CQE_SC_GEN_ABORT_DUE_TO_POWER_LOSS, "Commands Aborted due to Power Loss Notification" },
831 { NVME_CQE_SC_GEN_INTERNAL_ERROR, "Internal Error" },
832 { NVME_CQE_SC_GEN_ABORT_REQUESTED, "Command Abort Requested" },
833 { NVME_CQE_SC_GEN_ABORT_DUE_TO_SQ_DELETE, "Command Aborted due to SQ Deletion" },
834 { NVME_CQE_SC_GEN_ABORT_DUE_TO_FAILED_FUSE, "Command Aborted due to Failed Fused Command" },
835 { NVME_CQE_SC_GEN_ABORT_DUE_TO_MISSED_FUSE, "Command Aborted due to Missing Fused Command" },
836 { NVME_CQE_SC_GEN_INVALID_NAMESPACE_OR_FMT, "Invalid Namespace or Format" },
837 { NVME_CQE_SC_GEN_COMMAND_SEQUENCE_ERR, "Command Sequence Error" },
838 { NVME_CQE_SC_GEN_INVALID_SGL_SD, "Invalid SGL Segment Descriptor" },
839 { NVME_CQE_SC_GEN_INVALID_SGL_SD_NUM, "Invalid Number of SGL Descriptors" },
840 { NVME_CQE_SC_GEN_INVALID_SGL_LEN, "Data SGL Length Invalid" },
841 { NVME_CQE_SC_GEN_INVALID_MDATA_SGL_LEN, "Metadata SGL Length Invalid" },
842 { NVME_CQE_SC_GEN_INVALID_SGL_SD_TYPE, "SGL Descriptor Type Invalid" },
843 { NVME_CQE_SC_GEN_INVALID_USE_OF_MC_BUF, "Invalid Use of Controller Memory Buffer" },
844 { NVME_CQE_SC_GEN_INVALID_PRP_OFFSET, "PRP Offset Invalid" },
845 { NVME_CQE_SC_GEN_ATOMIC_WRITE_UNIT_EXCEED, "Atomic Write Unit Exceeded" },
846 { NVME_CQE_SC_GEN_OPERATION_DENIED, "Operation Denied" },
847 { NVME_CQE_SC_GEN_INVALID_SGL_OFFSET, "SGL Offset Invalid" },
848 { NVME_CQE_SC_GEN_RESERVED_17H, "Reserved" },
849 { NVME_CQE_SC_GEN_HOST_ID_INVALID_FMT, "Host Identifier Inconsistent Format" },
850 { NVME_CQE_SC_GEN_KEEP_ALLIVE_EXPIRED, "Keep Alive Timer Expired" },
851 { NVME_CQE_SC_GEN_KEEP_ALIVE_INVALID, "Keep Alive Timeout Invalid" },
852 { NVME_CQE_SC_GEN_ABORT_DUE_TO_PREEMPT_ABRT, "Command Aborted due to Preempt and Abort" },
853 { NVME_CQE_SC_GEN_SANITIZE_FAILED, "Sanitize Failed" },
854 { NVME_CQE_SC_GEN_SANITZE_IN_PROGRESS,"Sanitize In Progress" },
855 { NVME_CQE_SC_GEN_SGL_BLOCK_GRAN_INVALID, "SGL Data Block Granularity Invalid" },
856 { NVME_CQE_SC_GEN_CMD_NOT_SUPP_IN_CMB, "Command Not Supported for Queue in CMB" },
857 { NVME_CQE_SC_GEN_NAMESPACE_IS_WP, "Namespace is Write Protected" },
858 { NVME_CQE_SC_GEN_COMMAND_INTERRUPTED,"Command Interrupted" },
859 { NVME_CQE_SC_GEN_TRANSIENT_TRASPORT_ERROR, "Transient Transport Error"},
860 { NVME_CQE_SC_GEN_LBA_OUT_OF_RANGE, "LBA Out of Range" },
861 { NVME_CQE_SC_GEN_CAPACITY_EXCEED, "Capacity Exceeded" },
862 { NVME_CQE_SC_GEN_NAMESPACE_NOT_ERADY, "Namespace Not Ready" },
863 { NVME_CQE_SC_GEN_RESERVATION_CONFLICT, "Reservation Conflict" },
864 { NVME_CQE_SC_GEN_FMT_IN_PROGRESS, "Format In Progress"},
865 { 0, NULL },
868 static const value_string nvme_cqe_sc_cmd_tbl[] = {
869 { NVME_CQE_SC_CMD_INVALID_CQ, "Completion Queue Invalid" },
870 { NVME_CQE_SC_CMD_INVALID_QID, "Invalid Queue Identifier" },
871 { NVME_CQE_SC_CMD_INVALID_QUEUE_SIZE, "Invalid Queue Size" },
872 { NVME_CQE_SC_CMD_ABORT_LIMIT_EXCEED, "Abort Command Limit Exceeded" },
873 { NVME_CQE_SC_CMD_RESERVED_4H, "Reserved" },
874 { NVME_CQE_SC_CMD_ASYNC_REQ_LIMIT_EXCEED, "Asynchronous Event Request Limit Exceeded" },
875 { NVME_CQE_SC_CMD_INVALID_FW_SLOT, "Invalid Firmware Slot" },
876 { NVME_CQE_SC_CMD_INVALID_FW_IMAGE, "Invalid Firmware Image" },
877 { NVME_CQE_SC_CMD_INVALID_IRQ_VECTOR, "Invalid Interrupt Vector" },
878 { NVME_CQE_SC_CMD_INVALID_LOG_PAGE, "Invalid Log Page" },
879 { NVME_CQE_SC_CMD_INVALID_FMT, "Invalid Format" },
880 { NVME_CQE_SC_CMD_FW_ACTIVATION_NEEDS_RESET, "Firmware Activation Requires Conventional Reset" },
881 { NVME_CQE_SC_CMD_INVALID_QUEUE_DELETE, "Invalid Queue Deletion" },
882 { NVME_CQE_SC_CMD_FEATURE_ID_NOT_SAVEABLE, "Feature Identifier Not Saveable" },
883 { NVME_CQE_SC_CMD_FEATURE_NOT_CHANGEABLE, "Feature Not Changeable" },
884 { NVME_CQE_SC_CMD_FEATURE_NOT_NAMESPACE, "Feature Not Namespace Specific" },
885 { NVME_CQE_SC_CMD_FEATURE_ACTIVATION_NEEDS_NVM_RESET, "Firmware Activation Requires NVM Subsystem Reset" },
886 { NVME_CQE_SC_CMD_FEATURE_ACTIVATION_NEEDS_CNTRL_RESET, "Firmware Activation Requires Controller Level Reset" },
887 { NVME_CQE_SC_CMD_FW_ACTIVATION_NEED_MAX_TIME, "Firmware Activation Requires Maximum Time Violation" },
888 { NVME_CQE_SC_CMD_FW_ACTIVATION_PROHIBITED, "Firmware Activation Prohibited" },
889 { NVME_CQE_SC_CMD_OVERLAPPING_RANGE, "Overlapping Range" },
890 { NVME_CQE_SC_CMD_NAMESPACE_INSUF_CAPACITY, "Namespace Insufficient Capacity" },
891 { NVME_CQE_SC_CMD_NAMESPACE_ID_NOT_AVAILABLE, "Namespace Identifier Unavailable" },
892 { NVME_CQE_SC_CMD_RESERVED_17H, "Reserved" },
893 { NVME_CQE_SC_CMD_NAMESPACE_ALREADY_ATATCHED, "Namespace Already Attached" },
894 { NVME_CQE_SC_CMD_NAMESPACE_IS_PRIVATE, "Namespace Is Private" },
895 { NVME_CQE_SC_CMD_NAMESPACE_NOT_ATTACHED, "Namespace Not Attached" },
896 { NVME_CQE_SC_CMD_THIN_PROVISION_NOT_SUPP, "Thin Provisioning Not Supported" },
897 { NVME_CQE_SC_CMD_INVALID_CNTRL_LIST, "Controller List Invalid" },
898 { NVME_CQE_SC_CMD_SELF_TEST_IN_PROGRESS, "Device Self-test In Progress" },
899 { NVME_CQE_SC_CMD_BOOT_PART_WRITE_PROHIBIT, "Boot Partition Write Prohibited" },
900 { NVME_CQE_SC_CMD_INVALID_CNTRL_ID, "Invalid Controller Identifier" },
901 { NVME_CQE_SC_CMD_INVALID_SECOND_CNTRL_STATE, "Invalid Secondary Controller State" },
902 { NVME_CQE_SC_CMD_IBVALID_CNRL_RES_NUM, "Invalid Number of Controller Resources" },
903 { NVME_CQE_SC_CMD_INVALID_RESOURSE_ID, "Invalid Resource Identifier" },
904 { NVME_CQE_SC_CMD_SANITIZE_PROHIBIT_WITH_PMR, "Sanitize Prohibited While Persistent Memory Region is Enabled" },
905 { NVME_CQE_SC_CMD_INVALID_ANA_GROUP_ID, "ANA Group Identifier Invalid" },
906 { NVME_CQE_SC_CMD_ANA_ATTACH_FAILED, "ANA Attach Failed" },
907 { NVME_CQE_SC_CMD_CONFLICTING_ATTRS, "Conflicting Attributes" },
908 { NVME_CQE_SC_CMD_INVALID_PROTECTION_INF, "Invalid Protection Information" },
909 { NVME_CQE_SC_CMD_WRITE_TO_RO_REGION, "Attempted Write to Read Only Range" },
910 { 0, NULL },
913 static const value_string nvmeof_cqe_sc_cmd_tbl[] = {
914 { NVMEOF_CQE_SC_CMD_INCOMPAT_FORMAT, "Incompatible Format" },
915 { NVMEOF_CQE_SC_CMD_CONT_BUSY, "Controller Busy" },
916 { NVMEOF_CQE_SC_CMD_CNCT_INV_PARAMS, "Connect Invalid Parameters" },
917 { NVMEOF_CQE_SC_CMD_CNCT_RESTART_DISC, "Connect Restart Discovery" },
918 { NVMEOF_CQE_SC_CMD_CNCT_INV_HOST, "Connect Invalid Host" },
919 { NVMEOF_CQE_SC_CMD_INV_QUEUE_TYPE, "Invalid Queue Type" },
920 { NVMEOF_CQE_SC_CMD_DISC_RESTART, "Discover Restart" },
921 { NVMEOF_CQE_SC_CMD_AUTH_REQ, "Authentication Required" },
922 { 0, NULL },
925 static const value_string nvme_cqe_sc_media_tbl[] = {
926 { NVME_CQE_SC_MEDIA_WRITE_FAULT, "Write Fault" },
927 { NVME_CQE_SC_MEDIA_READ_FAULT, "Unrecovered Read Error" },
928 { NVME_CQE_SC_MEDIA_ETE_GUARD_CHECK_ERR, "End-to-end Guard Check Error" },
929 { NVME_CQE_SC_MEDIA_ETE_APPTAG_CHECK_ERR, "End-to-end Application Tag Check Error" },
930 { NVME_CQE_SC_MEDIA_ETE_REFTAG_CHECK_ERR, "End-to-end Reference Tag Check Error" },
931 { NVME_CQE_SC_MEDIA_COMPARE_FAILURE, "Compare Failure" },
932 { NVME_CQE_SC_MEDIA_ACCESS_DENIED, "Access Denied" },
933 { NVME_CQE_SC_MEDIA_DEALLOCATED_LBA, "Deallocated or Unwritten Logical Block" },
934 { 0, NULL },
937 static const value_string nvme_cqe_sc_path_tbl[] = {
938 { NVME_CQE_SC_PATH_INTERNAL_PATH_ERROR, "Internal Path Error" },
939 { NVME_CQE_SC_PATH_ANA_PERSISTENT_LOSS, "Asymmetric Access Persistent Loss" },
940 { NVME_CQE_SC_PATH_ANA_INACCESSIBLE, "Asymmetric Access Inaccessible" },
941 { NVME_CQE_SC_PATH_ANA_TRANSIENT, "Asymmetric Access Transition" },
942 { NVME_CQE_SC_PATH_CNTRL_PATH_ERROR, "Controller Pathing Error" },
943 { NVME_CQE_SC_PATH_HOST_PATH_ERROR, "Host Pathing Error" },
944 { NVME_CQE_SC_PATH_CMD_ABORT, "Command Aborted By Host" },
945 { 0, NULL },
948 static const value_string aq_opc_tbl[] = {
949 { NVME_AQ_OPC_DELETE_SQ, "Delete SQ"},
950 { NVME_AQ_OPC_CREATE_SQ, "Create SQ"},
951 { NVME_AQ_OPC_GET_LOG_PAGE, "Get Log Page"},
952 { NVME_AQ_OPC_DELETE_CQ, "Delete CQ"},
953 { NVME_AQ_OPC_CREATE_CQ, "Create CQ"},
954 { NVME_AQ_OPC_IDENTIFY, "Identify"},
955 { NVME_AQ_OPC_ABORT, "Abort"},
956 { NVME_AQ_OPC_SET_FEATURES, "Set Features"},
957 { NVME_AQ_OPC_GET_FEATURES, "Get Features"},
958 { NVME_AQ_OPC_ASYNC_EVE_REQ, "Async Event Request"},
959 { NVME_AQ_OPC_NS_MGMT, "Namespace Management"},
960 { NVME_AQ_OPC_FW_COMMIT, "Firmware Commit"},
961 { NVME_AQ_OPC_FW_IMG_DOWNLOAD, "Firmware Image Download"},
962 { NVME_AQ_OPC_NS_ATTACH, "Namespace attach"},
963 { NVME_AQ_OPC_KEEP_ALIVE, "Keep Alive"},
964 { 0, NULL}
967 static const value_string ioq_opc_tbl[] = {
968 { NVME_IOQ_OPC_FLUSH, "Flush"},
969 { NVME_IOQ_OPC_WRITE, "Write"},
970 { NVME_IOQ_OPC_READ, "Read"},
971 { NVME_IOQ_OPC_WRITE_UNCORRECTABLE, "Write Uncorrectable"},
972 { NVME_IOQ_OPC_COMPARE, "Compare"},
973 { NVME_IOQ_OPC_WRITE_ZEROS, "Write Zero"},
974 { NVME_IOQ_OPC_DATASET_MGMT, "Dataset Management"},
975 { NVME_IOQ_OPC_RESV_REG, "Reserve Register"},
976 { NVME_IOQ_OPC_RESV_REPORT, "Reserve Report"},
977 { NVME_IOQ_OPC_RESV_ACQUIRE, "Reserve Acquire"},
978 { NVME_IOQ_OPC_RESV_RELEASE, "Reserve Release"},
979 { 0, NULL}
982 #define NVME_CMD_SGL_DATA_DESC 0x0
983 #define NVME_CMD_SGL_BIT_BUCKET_DESC 0x1
984 #define NVME_CMD_SGL_SEGMENT_DESC 0x2
985 #define NVME_CMD_SGL_LAST_SEGMENT_DESC 0x3
986 #define NVME_CMD_SGL_KEYED_DATA_DESC 0x4
987 #define NVME_CMD_SGL_VENDOR_DESC 0xf
989 static const value_string sgl_type_tbl[] = {
990 { NVME_CMD_SGL_DATA_DESC, "Data Block"},
991 { NVME_CMD_SGL_BIT_BUCKET_DESC, "Bit Bucket"},
992 { NVME_CMD_SGL_SEGMENT_DESC, "Segment"},
993 { NVME_CMD_SGL_LAST_SEGMENT_DESC, "Last Segment"},
994 { NVME_CMD_SGL_KEYED_DATA_DESC, "Keyed Data Block"},
995 { NVME_CMD_SGL_VENDOR_DESC, "Vendor Specific"},
996 { 0, NULL}
999 #define NVME_CMD_SGL_SUB_DESC_ADDR 0x0
1000 #define NVME_CMD_SGL_SUB_DESC_OFFSET 0x1
1001 #define NVME_CMD_SGL_SUB_DESC_TRANSPORT 0xf
1003 static const value_string sgl_sub_type_tbl[] = {
1004 { NVME_CMD_SGL_SUB_DESC_ADDR, "Address"},
1005 { NVME_CMD_SGL_SUB_DESC_OFFSET, "Offset"},
1006 { NVME_CMD_SGL_SUB_DESC_TRANSPORT, "Transport specific"},
1007 { 0, NULL}
1011 static const value_string cns_table[] = {
1012 { 0, "Namespace"},
1013 { 1, "Controller"},
1014 { 2, "Active Namespace List"},
1015 { 3, "Namespace Identification Descriptor"},
1016 {4, "NVM Set List"},
1017 {0x10, "Allocated Namespace ID List"},
1018 {0x11, "Namespace Data Structure"},
1019 {0x12, "Controller List Attached to NSID"},
1020 {0x13, "Existing Controllers List"},
1021 {0x14, "Primary Controller Capabilities"},
1022 {0x15, "Secondary Controller List"},
1023 {0x16, "Namespace Granularity List"},
1024 {0x17, "UUID List"},
1025 {0, NULL}
1028 static const value_string dsm_acc_freq_tbl[] = {
1029 { 0, "No frequency"},
1030 { 1, "Typical"},
1031 { 2, "Infrequent Read/Write"},
1032 { 3, "Infrequent Writes, Frequent Reads"},
1033 { 4, "Frequent Writes, Infrequent Reads"},
1034 { 5, "Frequent Read/Write"},
1035 { 6, "One time read"},
1036 { 7, "Speculative read"},
1037 { 8, "Likely tobe overwritten"},
1038 { 0, NULL}
1041 static const value_string dsm_acc_lat_tbl[] = {
1042 { 0, "None"},
1043 { 1, "Idle (Longer)"},
1044 { 2, "Normal (Typical)"},
1045 { 3, "Low (Smallest)"},
1046 { 0, NULL}
1050 void
1051 nvme_publish_qid(proto_tree *tree, int field_index, uint16_t qid)
1053 proto_item *cmd_ref_item;
1055 cmd_ref_item = proto_tree_add_uint_format_value(tree, field_index, NULL,
1056 0, 0, qid,
1057 qid ? "%d (IOQ)" : "%d (AQ)",
1058 qid);
1060 proto_item_set_generated(cmd_ref_item);
1063 static void nvme_build_pending_cmd_key(wmem_tree_key_t *cmd_key, uint32_t *key)
1065 cmd_key[0].length = 1;
1066 cmd_key[0].key = key;
1067 cmd_key[1].length = 0;
1068 cmd_key[1].key = NULL;
1071 static void
1072 nvme_build_done_frame_key(wmem_tree_key_t *cmd_key, uint32_t *key, uint32_t *frame)
1074 unsigned idx = 0;
1075 if (key) {
1076 cmd_key[0].length = 1;
1077 cmd_key[0].key = key;
1078 idx = 1;
1080 cmd_key[idx].length = 1;
1081 cmd_key[idx].key = frame;
1082 idx++;
1084 cmd_key[idx].length = 0;
1085 cmd_key[idx].key = NULL;
1088 void
1089 nvme_add_cmd_to_pending_list(packet_info *pinfo, struct nvme_q_ctx *q_ctx,
1090 struct nvme_cmd_ctx *cmd_ctx,
1091 void *ctx, uint16_t cmd_id)
1093 wmem_tree_key_t cmd_key[3];
1094 uint32_t key = cmd_id;
1096 cmd_ctx->cmd_pkt_num = pinfo->num;
1097 cmd_ctx->cqe_pkt_num = 0;
1098 cmd_ctx->cmd_start_time = pinfo->abs_ts;
1099 nstime_set_zero(&cmd_ctx->cmd_end_time);
1101 /* this is a new cmd, create a new command context and map it to the
1102 unmatched table
1104 nvme_build_pending_cmd_key(cmd_key, &key);
1105 wmem_tree_insert32_array(q_ctx->pending_cmds, cmd_key, (void *)ctx);
1108 void* nvme_lookup_cmd_in_pending_list(struct nvme_q_ctx *q_ctx, uint16_t cmd_id)
1110 wmem_tree_key_t cmd_key[3];
1111 uint32_t key = cmd_id;
1113 nvme_build_pending_cmd_key(cmd_key, &key);
1114 return wmem_tree_lookup32_array(q_ctx->pending_cmds, cmd_key);
1118 static void nvme_build_pending_transfer_key(wmem_tree_key_t *key, struct keyed_data_req *req)
1120 key[0].length = 2;
1121 key[0].key = (uint32_t *)&req->addr;
1122 key[1].length = 1;
1123 key[1].key = &req->key;
1124 key[2].length = 1;
1125 key[2].key = &req->size;
1126 key[3].length = 0;
1127 key[3].key = NULL;
1130 void nvme_add_data_request(struct nvme_q_ctx *q_ctx, struct nvme_cmd_ctx *cmd_ctx,
1131 struct keyed_data_req *req)
1133 wmem_tree_key_t tr_key[4];
1135 memset(cmd_ctx->data_tr_pkt_num, 0, sizeof(cmd_ctx->data_tr_pkt_num));
1136 nvme_build_pending_transfer_key(tr_key, req);
1137 wmem_tree_insert32_array(q_ctx->data_requests, tr_key, (void *)cmd_ctx);
1140 struct nvme_cmd_ctx* nvme_lookup_data_request(struct nvme_q_ctx *q_ctx,
1141 struct keyed_data_req *req)
1143 wmem_tree_key_t tr_key[4];
1145 nvme_build_pending_transfer_key(tr_key, req);
1146 return (struct nvme_cmd_ctx*)wmem_tree_lookup32_array(q_ctx->data_requests, tr_key);
1149 void
1150 nvme_add_data_tr_pkt(struct nvme_q_ctx *q_ctx,
1151 struct nvme_cmd_ctx *cmd_ctx, uint32_t rkey, uint32_t frame_num)
1153 wmem_tree_key_t cmd_key[3];
1155 nvme_build_done_frame_key(cmd_key, rkey ? &rkey : NULL, &frame_num);
1156 wmem_tree_insert32_array(q_ctx->data_responses, cmd_key, (void*)cmd_ctx);
1159 struct nvme_cmd_ctx*
1160 nvme_lookup_data_tr_pkt(struct nvme_q_ctx *q_ctx,
1161 uint32_t rkey, uint32_t frame_num)
1163 wmem_tree_key_t cmd_key[3];
1165 nvme_build_done_frame_key(cmd_key, rkey ? &rkey : NULL, &frame_num);
1166 return (struct nvme_cmd_ctx*)wmem_tree_lookup32_array(q_ctx->data_responses, cmd_key);
1169 void
1170 nvme_add_data_tr_off(struct nvme_q_ctx *q_ctx, uint32_t off, uint32_t frame_num)
1172 wmem_tree_key_t cmd_key[2];
1174 nvme_build_done_frame_key(cmd_key, NULL, &frame_num);
1175 wmem_tree_insert32_array(q_ctx->data_offsets, cmd_key, GUINT_TO_POINTER(off));
1178 uint32_t
1179 nvme_lookup_data_tr_off(struct nvme_q_ctx *q_ctx, uint32_t frame_num)
1181 wmem_tree_key_t cmd_key[2];
1183 nvme_build_done_frame_key(cmd_key, NULL, &frame_num);
1184 return GPOINTER_TO_UINT(wmem_tree_lookup32_array(q_ctx->data_offsets, cmd_key));
1187 void
1188 nvme_add_cmd_cqe_to_done_list(struct nvme_q_ctx *q_ctx,
1189 struct nvme_cmd_ctx *cmd_ctx, uint16_t cmd_id)
1191 wmem_tree_key_t cmd_key[3];
1192 uint32_t key = cmd_id;
1193 uint32_t frame_num;
1195 nvme_build_done_frame_key(cmd_key, &key, &frame_num);
1197 /* found matchng entry. Add entries to the matched table for both cmd and cqe.
1199 frame_num = cmd_ctx->cqe_pkt_num;
1200 wmem_tree_insert32_array(q_ctx->done_cmds, cmd_key, (void*)cmd_ctx);
1202 frame_num = cmd_ctx->cmd_pkt_num;
1203 wmem_tree_insert32_array(q_ctx->done_cmds, cmd_key, (void*)cmd_ctx);
1206 void*
1207 nvme_lookup_cmd_in_done_list(packet_info *pinfo, struct nvme_q_ctx *q_ctx,
1208 uint16_t cmd_id)
1210 wmem_tree_key_t cmd_key[3];
1211 uint32_t key = cmd_id;
1212 uint32_t frame_num = pinfo->num;
1214 nvme_build_done_frame_key(cmd_key, &key, &frame_num);
1216 return wmem_tree_lookup32_array(q_ctx->done_cmds, cmd_key);
1219 void
1220 nvme_publish_cmd_latency(proto_tree *tree, struct nvme_cmd_ctx *cmd_ctx,
1221 int field_index)
1223 proto_item *cmd_ref_item;
1224 nstime_t ns;
1225 double cmd_latency;
1227 nstime_delta(&ns, &cmd_ctx->cmd_end_time, &cmd_ctx->cmd_start_time);
1228 cmd_latency = nstime_to_msec(&ns);
1229 cmd_ref_item = proto_tree_add_double_format_value(tree, field_index,
1230 NULL, 0, 0, cmd_latency,
1231 "%.3f ms", cmd_latency);
1232 proto_item_set_generated(cmd_ref_item);
1235 void nvme_update_cmd_end_info(packet_info *pinfo, struct nvme_cmd_ctx *cmd_ctx)
1237 cmd_ctx->cmd_end_time = pinfo->abs_ts;
1238 cmd_ctx->cqe_pkt_num = pinfo->num;
1241 void
1242 nvme_publish_link(proto_tree *tree, tvbuff_t *tvb, int hf_index,
1243 uint32_t pkt_no, bool zero_ok)
1245 proto_item *ref_item;
1247 if (pkt_no || zero_ok) {
1248 ref_item = proto_tree_add_uint(tree, hf_index,
1249 tvb, 0, 0, pkt_no);
1250 proto_item_set_generated(ref_item);
1254 void
1255 nvme_publish_to_cmd_link(proto_tree *tree, tvbuff_t *tvb,
1256 int hf_index, struct nvme_cmd_ctx *cmd_ctx)
1258 nvme_publish_link(tree, tvb, hf_index, cmd_ctx->cmd_pkt_num, true);
1261 void
1262 nvme_publish_to_cqe_link(proto_tree *tree, tvbuff_t *tvb,
1263 int hf_index, struct nvme_cmd_ctx *cmd_ctx)
1265 nvme_publish_link(tree, tvb, hf_index, cmd_ctx->cqe_pkt_num, false);
1268 void
1269 nvme_publish_to_data_req_link(proto_tree *tree, tvbuff_t *tvb,
1270 int hf_index, struct nvme_cmd_ctx *cmd_ctx)
1272 nvme_publish_link(tree, tvb, hf_index, cmd_ctx->data_req_pkt_num, false);
1275 static void
1276 nvme_publish_to_data_tr_links(proto_tree *tree, tvbuff_t *tvb,
1277 int *index_arr, struct nvme_cmd_ctx *cmd_ctx)
1279 unsigned i;
1280 for (i = 0; i < NVME_CMD_MAX_TRS; i++)
1281 nvme_publish_link(tree, tvb, index_arr[i], cmd_ctx->data_tr_pkt_num[i], false);
1284 void nvme_publish_to_data_resp_link(proto_tree *tree, tvbuff_t *tvb,
1285 int hf_index, struct nvme_cmd_ctx *cmd_ctx)
1287 nvme_publish_link(tree, tvb, hf_index, cmd_ctx->data_tr_pkt_num[0], false);
1290 void dissect_nvme_cmd_sgl(tvbuff_t *cmd_tvb, proto_tree *cmd_tree,
1291 int field_index, struct nvme_q_ctx *q_ctx, struct nvme_cmd_ctx *cmd_ctx, unsigned cmd_off, bool visited)
1293 proto_item *ti, *sgl_tree, *type_item, *sub_type_item;
1294 uint8_t sgl_identifier, desc_type, desc_sub_type;
1295 int offset = 24 + cmd_off;
1297 ti = proto_tree_add_item(cmd_tree, field_index, cmd_tvb, offset,
1298 16, ENC_NA);
1299 sgl_tree = proto_item_add_subtree(ti, ett_data);
1301 sgl_identifier = tvb_get_uint8(cmd_tvb, offset + 15);
1302 desc_type = (sgl_identifier & 0xff) >> 4;
1303 desc_sub_type = sgl_identifier & 0x0f;
1305 type_item = proto_tree_add_item(sgl_tree, hf_nvme_cmd_sgl_desc_type,
1306 cmd_tvb, offset + 15, 1, ENC_LITTLE_ENDIAN);
1307 proto_item_append_text(type_item, " %s",
1308 val_to_str_const(desc_type, sgl_type_tbl, "Reserved"));
1310 sub_type_item = proto_tree_add_item(sgl_tree, hf_nvme_cmd_sgl_desc_sub_type,
1311 cmd_tvb,
1312 offset + 15, 1, ENC_LITTLE_ENDIAN);
1313 proto_item_append_text(sub_type_item, " %s",
1314 val_to_str_const(desc_sub_type, sgl_sub_type_tbl, "Reserved"));
1316 switch (desc_type) {
1317 case NVME_CMD_SGL_DATA_DESC:
1318 case NVME_CMD_SGL_LAST_SEGMENT_DESC:
1319 case NVME_CMD_SGL_SEGMENT_DESC:
1320 proto_tree_add_item(sgl_tree, hf_nvme_cmd_sgl_desc_addr, cmd_tvb,
1321 offset, 8, ENC_LITTLE_ENDIAN);
1322 proto_tree_add_item(sgl_tree, hf_nvme_cmd_sgl_desc_len, cmd_tvb,
1323 offset + 8, 4, ENC_LITTLE_ENDIAN);
1324 proto_tree_add_item(sgl_tree, hf_nvme_cmd_sgl_desc_rsvd, cmd_tvb,
1325 offset + 12, 3, ENC_NA);
1326 break;
1327 case NVME_CMD_SGL_BIT_BUCKET_DESC:
1328 proto_tree_add_item(sgl_tree, hf_nvme_cmd_sgl_desc_addr_rsvd, cmd_tvb,
1329 offset, 8, ENC_LITTLE_ENDIAN);
1330 proto_tree_add_item(sgl_tree, hf_nvme_cmd_sgl_desc_len, cmd_tvb,
1331 offset + 8, 4, ENC_LITTLE_ENDIAN);
1332 proto_tree_add_item(sgl_tree, hf_nvme_cmd_sgl_desc_rsvd, cmd_tvb,
1333 offset + 12, 3, ENC_NA);
1334 break;
1335 case NVME_CMD_SGL_KEYED_DATA_DESC:
1337 struct keyed_data_req req;
1338 proto_tree_add_item_ret_uint64(sgl_tree, hf_nvme_cmd_sgl_desc_addr, cmd_tvb,
1339 offset, 8, ENC_LITTLE_ENDIAN, &req.addr);
1340 proto_tree_add_item_ret_uint(sgl_tree, hf_nvme_cmd_sgl_desc_len, cmd_tvb,
1341 offset + 8, 3, ENC_LITTLE_ENDIAN, &req.size);
1342 proto_tree_add_item_ret_uint(sgl_tree, hf_nvme_cmd_sgl_desc_key, cmd_tvb,
1343 offset + 11, 4, ENC_LITTLE_ENDIAN, &req.key);
1344 if (!visited && cmd_ctx && q_ctx && q_ctx->data_requests)
1345 nvme_add_data_request(q_ctx, cmd_ctx, &req);
1346 break;
1348 case NVME_CMD_SGL_VENDOR_DESC:
1349 default:
1350 break;
1354 static void
1355 dissect_nvme_rwc_common_word_10_11_12_14_15(tvbuff_t *cmd_tvb, proto_tree *cmd_tree)
1357 proto_item *ti, *prinfo_tree;
1358 uint16_t num_lba;
1360 /* word 10, 11 */
1361 proto_tree_add_item(cmd_tree, hf_nvme_cmd_slba, cmd_tvb,
1362 40, 8, ENC_LITTLE_ENDIAN);
1363 /* add 1 for readability, as its zero based value */
1364 num_lba = tvb_get_uint16(cmd_tvb, 48, ENC_LITTLE_ENDIAN) + 1;
1366 /* word 12 */
1367 proto_tree_add_uint(cmd_tree, hf_nvme_cmd_nlb,
1368 cmd_tvb, 48, 2, num_lba);
1370 proto_tree_add_item(cmd_tree, hf_nvme_cmd_rsvd2, cmd_tvb,
1371 50, 2, ENC_LITTLE_ENDIAN);
1373 ti = proto_tree_add_item(cmd_tree, hf_nvme_cmd_prinfo, cmd_tvb, 50,
1374 1, ENC_NA);
1375 prinfo_tree = proto_item_add_subtree(ti, ett_data);
1377 proto_tree_add_item(prinfo_tree, hf_nvme_cmd_prinfo_prchk_lbrtag, cmd_tvb,
1378 50, 2, ENC_LITTLE_ENDIAN);
1379 proto_tree_add_item(prinfo_tree, hf_nvme_cmd_prinfo_prchk_apptag, cmd_tvb,
1380 50, 2, ENC_LITTLE_ENDIAN);
1381 proto_tree_add_item(prinfo_tree, hf_nvme_cmd_prinfo_prchk_guard, cmd_tvb,
1382 50, 2, ENC_LITTLE_ENDIAN);
1383 proto_tree_add_item(prinfo_tree, hf_nvme_cmd_prinfo_pract, cmd_tvb,
1384 50, 2, ENC_LITTLE_ENDIAN);
1386 proto_tree_add_item(cmd_tree, hf_nvme_cmd_fua, cmd_tvb,
1387 50, 2, ENC_LITTLE_ENDIAN);
1388 proto_tree_add_item(cmd_tree, hf_nvme_cmd_lr, cmd_tvb,
1389 50, 2, ENC_LITTLE_ENDIAN);
1391 /* word 14, 15 */
1392 proto_tree_add_item(cmd_tree, hf_nvme_cmd_eilbrt, cmd_tvb,
1393 56, 4, ENC_LITTLE_ENDIAN);
1394 proto_tree_add_item(cmd_tree, hf_nvme_cmd_elbat, cmd_tvb,
1395 60, 2, ENC_LITTLE_ENDIAN);
1396 proto_tree_add_item(cmd_tree, hf_nvme_cmd_elbatm, cmd_tvb,
1397 62, 2, ENC_LITTLE_ENDIAN);
1400 static void dissect_nvme_identify_ns_lbafs(tvbuff_t *cmd_tvb, proto_tree *cmd_tree)
1402 proto_item *ti, *lbafs_tree, *item;
1403 int lbaf_off, i;
1404 uint8_t nlbaf, lbads;
1405 uint16_t ms;
1406 uint32_t lbaf_raw;
1408 nlbaf = tvb_get_uint8(cmd_tvb, 25) + 1; // +1 for zero-base value
1410 ti = proto_tree_add_item(cmd_tree, hf_nvme_identify_ns_lbafs, cmd_tvb,
1411 128, 64, ENC_NA);
1412 lbafs_tree = proto_item_add_subtree(ti, ett_data);
1414 for (i = 0; i < nlbaf; i++) {
1415 lbaf_off = 128 + i * 4;
1417 lbaf_raw = tvb_get_uint32(cmd_tvb, lbaf_off, ENC_LITTLE_ENDIAN);
1418 ms = lbaf_raw & 0xFF;
1419 lbads = (lbaf_raw >> 16) & 0xF;
1420 item = proto_tree_add_item(lbafs_tree, hf_nvme_identify_ns_lbaf,
1421 cmd_tvb, lbaf_off, 4, ENC_LITTLE_ENDIAN);
1422 proto_item_set_text(item, "LBAF%d: lbads %d ms %d", i, lbads, ms);
1426 static void dissect_nvme_identify_ns_resp(tvbuff_t *cmd_tvb,
1427 proto_tree *cmd_tree, unsigned off, unsigned len)
1429 proto_item *ti;
1430 unsigned start;
1431 if (!off) {
1432 /* minimal MTU fits this block */
1433 proto_tree_add_item(cmd_tree, hf_nvme_identify_ns_nsze, cmd_tvb,
1434 0, 8, ENC_LITTLE_ENDIAN);
1435 proto_tree_add_item(cmd_tree, hf_nvme_identify_ns_ncap, cmd_tvb,
1436 8, 8, ENC_LITTLE_ENDIAN);
1437 proto_tree_add_item(cmd_tree, hf_nvme_identify_ns_nuse, cmd_tvb,
1438 16, 8, ENC_LITTLE_ENDIAN);
1439 proto_tree_add_item(cmd_tree, hf_nvme_identify_ns_nsfeat, cmd_tvb,
1440 24, 1, ENC_LITTLE_ENDIAN);
1441 proto_tree_add_item(cmd_tree, hf_nvme_identify_ns_nlbaf, cmd_tvb,
1442 25, 1, ENC_LITTLE_ENDIAN);
1443 proto_tree_add_item(cmd_tree, hf_nvme_identify_ns_flbas, cmd_tvb,
1444 26, 1, ENC_LITTLE_ENDIAN);
1445 proto_tree_add_item(cmd_tree, hf_nvme_identify_ns_mc, cmd_tvb,
1446 27, 1, ENC_LITTLE_ENDIAN);
1447 proto_tree_add_item(cmd_tree, hf_nvme_identify_ns_dpc, cmd_tvb,
1448 28, 1, ENC_LITTLE_ENDIAN);
1449 proto_tree_add_item(cmd_tree, hf_nvme_identify_ns_dps, cmd_tvb,
1450 29, 1, ENC_LITTLE_ENDIAN);
1451 proto_tree_add_item(cmd_tree, hf_nvme_identify_ns_nmic, cmd_tvb,
1452 30, 1, ENC_LITTLE_ENDIAN);
1453 proto_tree_add_item(cmd_tree, hf_nvme_identify_ns_nguid, cmd_tvb,
1454 104, 16, ENC_NA);
1455 proto_tree_add_item(cmd_tree, hf_nvme_identify_ns_eui64, cmd_tvb,
1456 120, 8, ENC_NA);
1458 dissect_nvme_identify_ns_lbafs(cmd_tvb, cmd_tree);
1459 proto_tree_add_item(cmd_tree, hf_nvme_identify_ns_rsvd, cmd_tvb,
1460 192, 192, ENC_NA);
1462 if (off >= 384)
1463 start = 0;
1464 else
1465 start = 384 - off;
1466 ti = proto_tree_add_item(cmd_tree, hf_nvme_identify_ns_vs, cmd_tvb,
1467 start, len - start, ENC_NA);
1468 proto_item_append_text(ti, " (offset %u)", (off <= 384) ? 0 : off-384);
1471 static void dissect_nvme_identify_nslist_resp(tvbuff_t *cmd_tvb,
1472 proto_tree *cmd_tree, unsigned off, unsigned len)
1474 uint32_t nsid;
1475 proto_item *item;
1476 unsigned done = 0;
1478 for (; off < 4096 && (done + 4) <= len; off += 4) {
1479 nsid = tvb_get_uint32(cmd_tvb, done, ENC_LITTLE_ENDIAN);
1480 if (nsid == 0)
1481 break;
1483 item = proto_tree_add_item(cmd_tree, hf_nvme_identify_nslist_nsid,
1484 cmd_tvb, done, 4, ENC_LITTLE_ENDIAN);
1485 proto_item_set_text(item, "nsid[%u]: %u", off / 4, nsid);
1486 done += 4;
1490 #define ASPEC(_x_) _x_, array_length(_x_)
1492 static void add_group_mask_entry(tvbuff_t *tvb, proto_tree *tree, unsigned offset, unsigned bytes, int *array, unsigned array_len)
1494 proto_item *ti;
1495 proto_tree *grp;
1496 unsigned i;
1498 ti = proto_tree_add_item(tree, array[0], tvb, offset, bytes, ENC_LITTLE_ENDIAN);
1499 grp = proto_item_add_subtree(ti, ett_data);
1501 for (i = 1; i < array_len; i++)
1502 proto_tree_add_item(grp, array[i], tvb, offset, bytes, ENC_LITTLE_ENDIAN);
1505 static void add_ctrl_x16_bytes( char *result, uint32_t val)
1507 snprintf(result, ITEM_LABEL_LENGTH, "%x (%u bytes)", val, val * 16);
1510 static void dissect_nvme_identify_ctrl_resp_nvmeof(tvbuff_t *cmd_tvb, proto_tree *cmd_tree, uint32_t off)
1512 proto_item *ti;
1513 proto_tree *grp;
1515 ti = proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_nvmeof, cmd_tvb, 1792-off, 256, ENC_NA);
1516 grp = proto_item_add_subtree(ti, ett_data);
1518 proto_tree_add_item(grp, hf_nvme_identify_ctrl_nvmeof_ioccsz, cmd_tvb, 1792-off, 4, ENC_LITTLE_ENDIAN);
1519 proto_tree_add_item(grp, hf_nvme_identify_ctrl_nvmeof_iorcsz, cmd_tvb, 1796-off, 4, ENC_LITTLE_ENDIAN);
1520 proto_tree_add_item(grp, hf_nvme_identify_ctrl_nvmeof_icdoff, cmd_tvb, 1800-off, 2, ENC_LITTLE_ENDIAN);
1522 add_group_mask_entry(cmd_tvb, grp, 1802-off, 1, ASPEC(hf_nvme_identify_ctrl_nvmeof_fcatt));
1523 proto_tree_add_item(grp, hf_nvme_identify_ctrl_nvmeof_msdbd, cmd_tvb, 1803-off, 1, ENC_LITTLE_ENDIAN);
1524 add_group_mask_entry(cmd_tvb, grp, 1804-off, 2, ASPEC(hf_nvme_identify_ctrl_nvmeof_ofcs));
1525 proto_tree_add_item(grp, hf_nvme_identify_ctrl_nvmeof_rsvd, cmd_tvb, 1806-off, 242, ENC_NA);
1529 static const true_false_string units_watts = {
1530 "1 (0.0001 Watt units)",
1531 "0 (0.01 Watt units)"
1535 static const value_string power_scale_tbl[] = {
1536 { 0, "not reported for this power state" },
1537 { 1, "0.0001 Watt units" },
1538 { 2, "0.01 Watt units" },
1539 { 3, "reserved value" },
1540 { 0, NULL}
1543 static void dissect_nvme_identify_ctrl_resp_power_state_descriptor(tvbuff_t *cmd_tvb, proto_tree *tree, uint8_t idx, uint32_t off)
1545 proto_item *ti;
1546 proto_tree *grp;
1548 off = 2048 - off + idx *32;
1549 ti = proto_tree_add_bytes_format(tree, hf_nvme_identify_ctrl_psd, cmd_tvb, off, 32, NULL,
1550 "Power State %u Descriptor (PSD%u)", idx, idx);
1551 grp = proto_item_add_subtree(ti, ett_data);
1553 proto_tree_add_item(grp, hf_nvme_identify_ctrl_psd_mp, cmd_tvb, off, 2, ENC_LITTLE_ENDIAN);
1554 proto_tree_add_item(grp, hf_nvme_identify_ctrl_psd_rsvd0, cmd_tvb, off+2, 1, ENC_LITTLE_ENDIAN);
1556 proto_tree_add_item(grp, hf_nvme_identify_ctrl_psd_mxps, cmd_tvb, off+3, 1, ENC_LITTLE_ENDIAN);
1557 proto_tree_add_item(grp, hf_nvme_identify_ctrl_psd_nops, cmd_tvb, off+3, 1, ENC_LITTLE_ENDIAN);
1558 proto_tree_add_item(grp, hf_nvme_identify_ctrl_psd_rsvd1, cmd_tvb, off+3, 1, ENC_LITTLE_ENDIAN);
1560 proto_tree_add_item(grp, hf_nvme_identify_ctrl_psd_enlat, cmd_tvb, off+4, 4, ENC_LITTLE_ENDIAN);
1561 proto_tree_add_item(grp, hf_nvme_identify_ctrl_psd_exlat, cmd_tvb, off+8, 4, ENC_LITTLE_ENDIAN);
1562 proto_tree_add_item(grp, hf_nvme_identify_ctrl_psd_rrt, cmd_tvb, off+12, 1, ENC_LITTLE_ENDIAN);
1564 proto_tree_add_item(grp, hf_nvme_identify_ctrl_psd_rsvd2, cmd_tvb, off+12, 1, ENC_LITTLE_ENDIAN);
1565 proto_tree_add_item(grp, hf_nvme_identify_ctrl_psd_rrl, cmd_tvb, off+13, 1, ENC_LITTLE_ENDIAN);
1566 proto_tree_add_item(grp, hf_nvme_identify_ctrl_psd_rsvd3, cmd_tvb, off+13, 1, ENC_LITTLE_ENDIAN);
1568 proto_tree_add_item(grp, hf_nvme_identify_ctrl_psd_rwt, cmd_tvb, off+14, 1, ENC_LITTLE_ENDIAN);
1569 proto_tree_add_item(grp, hf_nvme_identify_ctrl_psd_rsvd4, cmd_tvb, off+14, 1, ENC_LITTLE_ENDIAN);
1570 proto_tree_add_item(grp, hf_nvme_identify_ctrl_psd_rwl, cmd_tvb, off+15, 1, ENC_LITTLE_ENDIAN);
1572 proto_tree_add_item(grp, hf_nvme_identify_ctrl_psd_rsvd5, cmd_tvb, off+15, 1, ENC_LITTLE_ENDIAN);
1573 proto_tree_add_item(grp, hf_nvme_identify_ctrl_psd_idlp, cmd_tvb, off+16, 2, ENC_LITTLE_ENDIAN);
1574 proto_tree_add_item(grp, hf_nvme_identify_ctrl_psd_rsvd6, cmd_tvb, off+18, 1, ENC_LITTLE_ENDIAN);
1576 proto_tree_add_item(grp, hf_nvme_identify_ctrl_psd_ips, cmd_tvb, off+18, 1, ENC_LITTLE_ENDIAN);
1577 proto_tree_add_item(grp, hf_nvme_identify_ctrl_psd_rsvd7, cmd_tvb, off+19, 1, ENC_LITTLE_ENDIAN);
1578 proto_tree_add_item(grp, hf_nvme_identify_ctrl_psd_actp, cmd_tvb, off+20, 2, ENC_LITTLE_ENDIAN);
1580 proto_tree_add_item(grp, hf_nvme_identify_ctrl_psd_apw, cmd_tvb, off+22, 1, ENC_LITTLE_ENDIAN);
1581 proto_tree_add_item(grp, hf_nvme_identify_ctrl_psd_rsvd8, cmd_tvb, off+22, 1, ENC_LITTLE_ENDIAN);
1582 proto_tree_add_item(grp, hf_nvme_identify_ctrl_psd_aps, cmd_tvb, off+22, 1, ENC_LITTLE_ENDIAN);
1583 proto_tree_add_item(grp, hf_nvme_identify_ctrl_psd_rsvd9, cmd_tvb, off+23, 9, ENC_NA);
1586 static void dissect_nvme_identify_ctrl_resp_power_state_descriptors(tvbuff_t *cmd_tvb, proto_tree *cmd_tree, uint32_t off)
1588 proto_item *ti;
1589 proto_tree *grp;
1590 unsigned i;
1592 ti = proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_psds, cmd_tvb, 2048-off, 1024, ENC_NA);
1593 grp = proto_item_add_subtree(ti, ett_data);
1594 for (i = 0; i < 32; i++)
1595 dissect_nvme_identify_ctrl_resp_power_state_descriptor(cmd_tvb, grp, i, off);
1599 static void add_ctrl_rab(char *result, uint32_t val)
1601 snprintf(result, ITEM_LABEL_LENGTH, "0x%x (%"PRIu64" command%s)", val, ((uint64_t)1) << val, val ? "s" : "");
1604 static void add_ctrl_mdts(char *result, uint32_t val)
1606 if (val)
1607 snprintf(result, ITEM_LABEL_LENGTH, "0x%x (%"PRIu64" pages)", val, ((uint64_t)1) << val);
1608 else
1609 snprintf(result, ITEM_LABEL_LENGTH, "0x%x (unlimited)", val);
1612 static void add_ctrl_rtd3(char *result, uint32_t val)
1614 if (!val)
1615 snprintf(result, ITEM_LABEL_LENGTH, "0 (not reported)");
1616 else
1617 snprintf(result, ITEM_LABEL_LENGTH, "%u (%u microsecond%s)", val, val, (val > 1) ? "%s" : "");
1620 static const value_string ctrl_type_tbl[] = {
1621 { 0, "Reserved (not reported)" },
1622 { 1, "I/O Controller" },
1623 { 2, "Discovery Controller" },
1624 { 3, "Administrative Controller" },
1625 { 0, NULL}
1628 static void add_ctrl_ms(char *result, uint32_t val)
1630 snprintf(result, ITEM_LABEL_LENGTH, "%u (%u ms)", val, val * 100);
1633 static void dissect_nvme_identify_ctrl_resp_ver(tvbuff_t *cmd_tvb, proto_tree *cmd_tree, uint32_t off)
1635 proto_item *ti;
1636 proto_tree *grp;
1638 ti = proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_ver, cmd_tvb, 80-off, 4, ENC_LITTLE_ENDIAN);
1639 grp = proto_item_add_subtree(ti, ett_data);
1641 proto_tree_add_item(grp, hf_nvme_identify_ctrl_ver_mjr, cmd_tvb, 82-off, 2, ENC_LITTLE_ENDIAN);
1642 proto_tree_add_item(grp, hf_nvme_identify_ctrl_ver_min, cmd_tvb, 81-off, 1, ENC_LITTLE_ENDIAN);
1643 proto_tree_add_item(grp, hf_nvme_identify_ctrl_ver_ter, cmd_tvb, 80-off, 1, ENC_LITTLE_ENDIAN);
1646 static void dissect_nvme_identify_ctrl_resp_fguid(tvbuff_t *cmd_tvb, proto_tree *cmd_tree, uint32_t off)
1648 proto_item *ti;
1649 proto_tree *grp;
1651 ti = proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_fguid, cmd_tvb, 112-off, 16, ENC_NA);
1652 grp = proto_item_add_subtree(ti, ett_data);
1653 proto_tree_add_item(grp, hf_nvme_identify_ctrl_fguid_vse, cmd_tvb, 112-off, 8, ENC_LITTLE_ENDIAN);
1654 proto_tree_add_item(grp, hf_nvme_identify_ctrl_fguid_oui, cmd_tvb, 120-off, 3, ENC_LITTLE_ENDIAN);
1655 proto_tree_add_item(grp, hf_nvme_identify_ctrl_fguid_ei, cmd_tvb, 123-off, 5, ENC_LITTLE_ENDIAN);
1658 static void dissect_nvme_identify_ctrl_resp_mi(tvbuff_t *cmd_tvb, proto_tree *cmd_tree, uint32_t off)
1660 proto_item *ti;
1661 proto_tree *grp;
1663 ti = proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_mi, cmd_tvb, 240-off, 16, ENC_NA);
1664 grp = proto_item_add_subtree(ti, ett_data);
1665 proto_tree_add_item(grp, hf_nvme_identify_ctrl_mi_rsvd, cmd_tvb, 240-off, 13, ENC_NA);
1666 add_group_mask_entry(cmd_tvb, grp, 253-off, 1, ASPEC(hf_nvme_identify_ctrl_mi_nvmsr));
1667 add_group_mask_entry(cmd_tvb, grp, 254-off, 1, ASPEC(hf_nvme_identify_ctrl_mi_vwci));
1668 add_group_mask_entry(cmd_tvb, grp, 255-off, 1, ASPEC(hf_nvme_identify_ctrl_mi_mec));
1671 static void add_ctrl_commands(char *result, uint32_t val)
1673 snprintf(result, ITEM_LABEL_LENGTH, "0x%x: (%u command%s)", val, val+1, val ? "s" : "");
1676 static void add_ctrl_events(char *result, uint32_t val)
1678 snprintf(result, ITEM_LABEL_LENGTH, "0x%x: (%u event%s)", val, val+1, val ? "s" : "");
1681 static void add_ctrl_entries(char *result, uint32_t val)
1683 snprintf(result, ITEM_LABEL_LENGTH, "0x%x: (%u entr%s)", val, val+1, val ? "ies" : "y");
1686 static void add_ctrl_states(char *result, uint32_t val)
1688 snprintf(result, ITEM_LABEL_LENGTH, "0x%x: (%u state%s)", val, val+1, val ? "s" : "");
1691 static void add_ctrl_hmpre(char *result, uint32_t val)
1693 snprintf(result, ITEM_LABEL_LENGTH, "0x%x (%"PRIu64" bytes)", val, ((uint64_t)(val)) * 4096);
1696 static void post_add_bytes_from_16bytes(proto_item *ti, tvbuff_t *tvb, unsigned off, uint8_t shiftl)
1698 uint64_t lo = tvb_get_uint64(tvb, off, 0);
1699 uint64_t hi = tvb_get_uint64(tvb, off, 8);
1701 if (shiftl) {
1702 hi = hi << shiftl;
1703 hi |= (lo >> (64-shiftl));
1704 lo = lo << shiftl;
1706 if (hi) {
1707 if (!(hi >> 10))
1708 proto_item_append_text(ti, " (%" PRIu64 " KiB)", (hi << 54) | (lo >> 10));
1709 else if (!(hi >> 20))
1710 proto_item_append_text(ti, " (%" PRIu64 " MiB)", (hi << 44) | (lo >> 20));
1711 else if (!(hi >> 30))
1712 proto_item_append_text(ti, " (%" PRIu64 " GiB)", (hi << 34) | (lo >> 30));
1713 else if (!(hi >> 40))
1714 proto_item_append_text(ti, " (%" PRIu64 " TiB)", (hi << 24) | (lo >> 40));
1715 else if (!(hi >> 50))
1716 proto_item_append_text(ti, " (%" PRIu64 " PiB)", (hi << 14) | (lo >> 50));
1717 else if (!(hi >> 60))
1718 proto_item_append_text(ti, " (%" PRIu64 " EiB)", (hi << 4) | (lo >> 60));
1719 else
1720 proto_item_append_text(ti, " (%" PRIu64 " ZiB)", hi >> 6);
1721 } else {
1722 proto_item_append_text(ti, " (%" PRIu64 " bytes)", lo);
1726 static void add_ctrl_tmt(char *result, uint32_t val)
1728 if (!val)
1729 snprintf(result, ITEM_LABEL_LENGTH, "0 (not supported)");
1730 else
1731 snprintf(result, ITEM_LABEL_LENGTH, "%u degrees K", val);
1734 static const value_string mmas_type_tbl[] = {
1735 { 0, "modification not defined" },
1736 { 1, "no modification after sanitize completion" },
1737 { 2, "additional modification after sanitize completion" },
1738 { 0, NULL}
1741 static void add_ctrl_pow2_bytes(char *result, uint32_t val)
1743 snprintf(result, ITEM_LABEL_LENGTH, "0x%x (%" PRIu64" bytes)", val, ((uint64_t)1) << val);
1746 static void add_ctrl_pow2_page_size(char *result, uint32_t val)
1748 snprintf(result, ITEM_LABEL_LENGTH, "0x%x (%" PRIu64" bytes)", val, ((uint64_t)1) << (12+val));
1751 static void add_ctrl_pow2_dstrd_size(char *result, uint32_t val)
1753 snprintf(result, ITEM_LABEL_LENGTH, "0x%x (%" PRIu64" bytes)", val, ((uint64_t)1) << (2+val));
1757 static const value_string fcb_type_tbl[] = {
1758 { 0, "support for the NSID field set to FFFFFFFFh is not indicated" },
1759 { 1, "reserved value" },
1760 { 2, "Flush command does not support the NSID field set to FFFFFFFFh" },
1761 { 3, "Flush command supports the NSID field set to FFFFFFFFh" },
1762 { 0, NULL}
1766 static void add_ctrl_lblocks(char *result, uint32_t val)
1768 snprintf(result, ITEM_LABEL_LENGTH, "%u logical block%s", val + 1, val ? "%s" : "");
1771 static const value_string sgls_ify_type_tbl[] = {
1772 { 0, "SGLs are not supported." },
1773 { 1, "SGLs are supported without alignment or granularity limitations" },
1774 { 2, "SGLs are supported with DWORD alignment and granularity limitation" },
1775 { 3, "reserved value" },
1776 { 0, NULL}
1779 #define CHECK_STOP_PARSE(__field_off__, __field_len__) \
1780 do { \
1781 if ((__field_off__ - off + __field_len__) > len) \
1782 return; \
1783 } while(0)
1785 static void dissect_nvme_identify_ctrl_resp(tvbuff_t *cmd_tvb,
1786 proto_tree *cmd_tree, unsigned off, unsigned len)
1788 proto_item *ti;
1790 if (!off) {
1791 CHECK_STOP_PARSE(0, 2);
1792 proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_vid, cmd_tvb, 0, 2, ENC_LITTLE_ENDIAN);
1794 if (off <= 2) {
1795 CHECK_STOP_PARSE(2, 2);
1796 proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_ssvid, cmd_tvb, 2-off, 2, ENC_LITTLE_ENDIAN);
1798 if (off <= 4) {
1799 CHECK_STOP_PARSE(4, 20);
1800 proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_sn, cmd_tvb, 4-off, 20, ENC_ASCII);
1802 if (off <= 24) {
1803 CHECK_STOP_PARSE(24, 40);
1804 proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_mn, cmd_tvb, 24-off, 40, ENC_ASCII);
1806 if (off <= 64) {
1807 CHECK_STOP_PARSE(64, 8);
1808 proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_fr, cmd_tvb, 64-off, 8, ENC_NA);
1810 if (off <= 72) {
1811 CHECK_STOP_PARSE(72, 1);
1812 proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_rab, cmd_tvb, 72-off, 1, ENC_LITTLE_ENDIAN);
1814 if (off <= 73) {
1815 CHECK_STOP_PARSE(73, 3);
1816 proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_ieee, cmd_tvb, 73-off, 3, ENC_LITTLE_ENDIAN);
1818 if (off <= 76) {
1819 CHECK_STOP_PARSE(76, 1);
1820 add_group_mask_entry(cmd_tvb, cmd_tree, 76-off, 1, ASPEC(hf_nvme_identify_ctrl_cmic));
1822 if (off <= 77) {
1823 CHECK_STOP_PARSE(77, 1);
1824 proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_mdts, cmd_tvb, 77-off, 1, ENC_LITTLE_ENDIAN);
1827 if (off <= 78) {
1828 CHECK_STOP_PARSE(78, 2);
1829 proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_cntlid, cmd_tvb, 78-off, 2, ENC_LITTLE_ENDIAN);
1831 if (off <= 80) {
1832 CHECK_STOP_PARSE(80, 4);
1833 dissect_nvme_identify_ctrl_resp_ver(cmd_tvb, cmd_tree, off);
1835 if (off <= 84) {
1836 CHECK_STOP_PARSE(84, 4);
1837 proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_rtd3r, cmd_tvb, 84-off, 4, ENC_LITTLE_ENDIAN);
1840 if (off <= 88) {
1841 CHECK_STOP_PARSE(88, 4);
1842 proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_rtd3e, cmd_tvb, 88-off, 4, ENC_LITTLE_ENDIAN);
1844 if (off <= 92) {
1845 CHECK_STOP_PARSE(92, 4);
1846 add_group_mask_entry(cmd_tvb, cmd_tree, 92-off, 4, ASPEC(hf_nvme_identify_ctrl_oaes));
1848 if (off <= 96) {
1849 CHECK_STOP_PARSE(96, 4);
1850 add_group_mask_entry(cmd_tvb, cmd_tree, 96-off, 4, ASPEC(hf_nvme_identify_ctrl_ctratt));
1853 if (off <= 100) {
1854 CHECK_STOP_PARSE(100, 2);
1855 add_group_mask_entry(cmd_tvb, cmd_tree, 100-off, 2, ASPEC(hf_nvme_identify_ctrl_rrls));
1857 if (off <= 102) {
1858 CHECK_STOP_PARSE(102, 9);
1859 proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_rsvd0, cmd_tvb, 102-off, 9, ENC_NA);
1861 if (off <= 111) {
1862 CHECK_STOP_PARSE(111, 1);
1863 proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_cntrltype, cmd_tvb, 111-off, 1, ENC_LITTLE_ENDIAN);
1865 if (off <= 112) {
1866 CHECK_STOP_PARSE(112, 16);
1867 dissect_nvme_identify_ctrl_resp_fguid(cmd_tvb, cmd_tree, off);
1870 if (off <= 128) {
1871 CHECK_STOP_PARSE(128, 2);
1872 proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_crdt1, cmd_tvb, 128-off, 2, ENC_LITTLE_ENDIAN);
1874 if (off <= 130) {
1875 CHECK_STOP_PARSE(130, 2);
1876 proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_crdt2, cmd_tvb, 130-off, 2, ENC_LITTLE_ENDIAN);
1878 if (off <= 132) {
1879 CHECK_STOP_PARSE(132, 2);
1880 proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_crdt3, cmd_tvb, 132-off, 2, ENC_LITTLE_ENDIAN);
1883 if (off <= 132) {
1884 CHECK_STOP_PARSE(134, 2);
1885 proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_rsvd1, cmd_tvb, 134-off, 106, ENC_NA);
1887 if (off <= 240) {
1888 CHECK_STOP_PARSE(240, 16);
1889 dissect_nvme_identify_ctrl_resp_mi(cmd_tvb, cmd_tree, off);
1891 if (off <= 256) {
1892 CHECK_STOP_PARSE(256, 2);
1893 add_group_mask_entry(cmd_tvb, cmd_tree, 256-off, 2, ASPEC(hf_nvme_identify_ctrl_oacs));
1896 if (off <= 258) {
1897 CHECK_STOP_PARSE(258, 1);
1898 proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_acl, cmd_tvb, 258-off, 1, ENC_LITTLE_ENDIAN);
1900 if (off <= 259) {
1901 CHECK_STOP_PARSE(259, 1);
1902 proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_aerl, cmd_tvb, 259-off, 1, ENC_LITTLE_ENDIAN);
1904 if (off <= 260) {
1905 CHECK_STOP_PARSE(260, 1);
1906 add_group_mask_entry(cmd_tvb, cmd_tree, 260, 1, ASPEC(hf_nvme_identify_ctrl_frmw));
1909 if (off <= 261) {
1910 CHECK_STOP_PARSE(261, 1);
1911 add_group_mask_entry(cmd_tvb, cmd_tree, 261-off, 1, ASPEC(hf_nvme_identify_ctrl_lpa));
1913 if (off <= 262) {
1914 CHECK_STOP_PARSE(262, 1);
1915 proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_elpe, cmd_tvb, 262-off, 1, ENC_LITTLE_ENDIAN);
1917 if (off <= 263) {
1918 CHECK_STOP_PARSE(263, 1);
1919 proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_npss, cmd_tvb, 263-off, 1, ENC_LITTLE_ENDIAN);
1922 if (off <= 264) {
1923 CHECK_STOP_PARSE(264, 1);
1924 add_group_mask_entry(cmd_tvb, cmd_tree, 264-off, 1, ASPEC(hf_nvme_identify_ctrl_avscc));
1926 if (off <= 265) {
1927 CHECK_STOP_PARSE(265, 1);
1928 add_group_mask_entry(cmd_tvb, cmd_tree, 265-off, 1, ASPEC(hf_nvme_identify_ctrl_apsta));
1930 if (off <= 266) {
1931 CHECK_STOP_PARSE(266, 1);
1932 proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_wctemp, cmd_tvb, 266-off, 2, ENC_LITTLE_ENDIAN);
1935 if (off <= 268) {
1936 CHECK_STOP_PARSE(268, 2);
1937 proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_cctemp, cmd_tvb, 268-off, 2, ENC_LITTLE_ENDIAN);
1939 if (off <= 270) {
1940 CHECK_STOP_PARSE(270, 2);
1941 proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_mtfa, cmd_tvb, 270-off, 2, ENC_LITTLE_ENDIAN);
1943 if (off <= 272) {
1944 CHECK_STOP_PARSE(272, 4);
1945 proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_hmpre, cmd_tvb, 272-off, 4, ENC_LITTLE_ENDIAN);
1947 if (off <= 276) {
1948 CHECK_STOP_PARSE(276, 4);
1949 proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_hmmin, cmd_tvb, 276-off, 4, ENC_LITTLE_ENDIAN);
1952 if (off <= 280) {
1953 CHECK_STOP_PARSE(280, 16);
1954 ti = proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_tnvmcap, cmd_tvb, 280-off, 16, ENC_NA);
1955 post_add_bytes_from_16bytes(ti, cmd_tvb, 280-off, 0);
1957 if (off <= 296) {
1958 CHECK_STOP_PARSE(296, 16);
1959 ti = proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_unvmcap, cmd_tvb, 296-off, 16, ENC_NA);
1960 post_add_bytes_from_16bytes(ti, cmd_tvb, 296-off, 0);
1963 if (off <= 312) {
1964 CHECK_STOP_PARSE(312, 4);
1965 add_group_mask_entry(cmd_tvb, cmd_tree, 312-off, 4, ASPEC(hf_nvme_identify_ctrl_rpmbs));
1967 if (off <= 316) {
1968 CHECK_STOP_PARSE(316, 2);
1969 proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_edstt, cmd_tvb, 316-off, 2, ENC_LITTLE_ENDIAN);
1971 if (off <= 318) {
1972 CHECK_STOP_PARSE(318, 1);
1973 add_group_mask_entry(cmd_tvb, cmd_tree, 318-off, 1, ASPEC(hf_nvme_identify_ctrl_dsto));
1976 if (off <= 319) {
1977 CHECK_STOP_PARSE(319, 1);
1978 proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_fwug, cmd_tvb, 319-off, 1, ENC_LITTLE_ENDIAN);
1980 if (off <= 320) {
1981 CHECK_STOP_PARSE(320, 2);
1982 proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_kas, cmd_tvb, 320-off, 2, ENC_LITTLE_ENDIAN);
1984 if (off <= 322) {
1985 CHECK_STOP_PARSE(322, 2);
1986 add_group_mask_entry(cmd_tvb, cmd_tree, 322-off, 2, ASPEC(hf_nvme_identify_ctrl_hctma));
1989 if (off <= 324) {
1990 CHECK_STOP_PARSE(324, 2);
1991 proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_mntmt, cmd_tvb, 324-off, 2, ENC_LITTLE_ENDIAN);
1993 if (off <= 326) {
1994 CHECK_STOP_PARSE(326, 2);
1995 proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_mxtmt, cmd_tvb, 326-off, 2, ENC_LITTLE_ENDIAN);
1997 if (off <= 328) {
1998 CHECK_STOP_PARSE(328, 2);
1999 add_group_mask_entry(cmd_tvb, cmd_tree, 328-off, 2, ASPEC(hf_nvme_identify_ctrl_sanicap));
2002 if (off <= 332) {
2003 CHECK_STOP_PARSE(332, 4);
2004 proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_hmmminds, cmd_tvb, 332-off, 4, ENC_LITTLE_ENDIAN);
2006 if (off <= 336) {
2007 CHECK_STOP_PARSE(336, 2);
2008 proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_hmmaxd, cmd_tvb, 336-off, 2, ENC_LITTLE_ENDIAN);
2010 if (off <= 338) {
2011 CHECK_STOP_PARSE(338, 2);
2012 proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_nsetidmax, cmd_tvb, 338-off, 2, ENC_LITTLE_ENDIAN);
2015 if (off <= 340) {
2016 CHECK_STOP_PARSE(340, 2);
2017 proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_endgidmax, cmd_tvb, 340-off, 2, ENC_LITTLE_ENDIAN);
2019 if (off <= 342) {
2020 CHECK_STOP_PARSE(342, 2);
2021 proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_anatt, cmd_tvb, 342-off, 1, ENC_LITTLE_ENDIAN);
2023 if (off <= 343) {
2024 CHECK_STOP_PARSE(343, 1);
2025 add_group_mask_entry(cmd_tvb, cmd_tree, 343-off, 1, ASPEC(hf_nvme_identify_ctrl_anacap));
2028 if (off <= 344) {
2029 CHECK_STOP_PARSE(344, 4);
2030 proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_anagrpmax, cmd_tvb, 344-off, 4, ENC_LITTLE_ENDIAN);
2032 if (off <= 348) {
2033 CHECK_STOP_PARSE(348, 4);
2034 proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_nanagrpid, cmd_tvb, 348-off, 4, ENC_LITTLE_ENDIAN);
2036 if (off <= 352) {
2037 CHECK_STOP_PARSE(352, 4);
2038 proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_pels, cmd_tvb, 352-off, 4, ENC_LITTLE_ENDIAN);
2041 if (off <= 356) {
2042 CHECK_STOP_PARSE(356, 156);
2043 proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_rsvd2, cmd_tvb, 356-off, 156, ENC_NA);
2045 if (off <= 512) {
2046 CHECK_STOP_PARSE(512, 1);
2047 add_group_mask_entry(cmd_tvb, cmd_tree, 512-off, 1, ASPEC(hf_nvme_identify_ctrl_sqes));
2049 if (off <= 513) {
2050 CHECK_STOP_PARSE(513, 1);
2051 add_group_mask_entry(cmd_tvb, cmd_tree, 513-off, 1, ASPEC(hf_nvme_identify_ctrl_cqes));
2054 if (off <= 514) {
2055 CHECK_STOP_PARSE(514, 2);
2056 proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_maxcmd, cmd_tvb, 514-off, 2, ENC_LITTLE_ENDIAN);
2058 if (off <= 516) {
2059 CHECK_STOP_PARSE(516, 4);
2060 proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_nn, cmd_tvb, 516-off, 4, ENC_LITTLE_ENDIAN);
2062 if (off <= 520) {
2063 CHECK_STOP_PARSE(520, 2);
2064 add_group_mask_entry(cmd_tvb, cmd_tree, 520-off, 2, ASPEC(hf_nvme_identify_ctrl_oncs));
2067 if (off <= 522) {
2068 CHECK_STOP_PARSE(522, 2);
2069 add_group_mask_entry(cmd_tvb, cmd_tree, 522-off, 2, ASPEC(hf_nvme_identify_ctrl_fuses));
2071 if (off <= 524) {
2072 CHECK_STOP_PARSE(524, 1);
2073 add_group_mask_entry(cmd_tvb, cmd_tree, 524-off, 1, ASPEC(hf_nvme_identify_ctrl_fna));
2075 if (off <= 525) {
2076 CHECK_STOP_PARSE(525, 1);
2077 add_group_mask_entry(cmd_tvb, cmd_tree, 525-off, 1, ASPEC(hf_nvme_identify_ctrl_vwc));
2080 if (off <= 526) {
2081 CHECK_STOP_PARSE(526, 2);
2082 proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_awun, cmd_tvb, 526-off, 2, ENC_LITTLE_ENDIAN);
2084 if (off <= 528) {
2085 CHECK_STOP_PARSE(528, 2);
2086 proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_awupf, cmd_tvb, 528-off, 2, ENC_LITTLE_ENDIAN);
2088 if (off <= 530) {
2089 CHECK_STOP_PARSE(530, 1);
2090 add_group_mask_entry(cmd_tvb, cmd_tree, 530-off, 1, ASPEC(hf_nvme_identify_ctrl_nvscc));
2093 if (off <= 531) {
2094 CHECK_STOP_PARSE(531, 1);
2095 add_group_mask_entry(cmd_tvb, cmd_tree, 531-off, 1, ASPEC(hf_nvme_identify_ctrl_nwpc));
2097 if (off <= 532) {
2098 CHECK_STOP_PARSE(532, 3);
2099 proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_acwu, cmd_tvb, 532-off, 2, ENC_LITTLE_ENDIAN);
2101 if (off <= 534) {
2102 CHECK_STOP_PARSE(534, 2);
2103 proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_rsvd3, cmd_tvb, 534-off, 2, ENC_NA);
2106 if (off <= 536) {
2107 CHECK_STOP_PARSE(536, 4);
2108 add_group_mask_entry(cmd_tvb, cmd_tree, 536-off, 4, ASPEC(hf_nvme_identify_ctrl_sgls));
2110 if (off <= 540) {
2111 CHECK_STOP_PARSE(540, 4);
2112 proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_mnan, cmd_tvb, 540-off, 4, ENC_LITTLE_ENDIAN);
2114 if (off <= 544) {
2115 CHECK_STOP_PARSE(544, 224);
2116 proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_rsvd4, cmd_tvb, 544-off, 224, ENC_NA);
2119 if (off <= 768) {
2120 CHECK_STOP_PARSE(768, 256);
2121 proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_subnqn, cmd_tvb, 768-off, 256, ENC_ASCII);
2123 if (off <= 1024) {
2124 CHECK_STOP_PARSE(1024, 768);
2125 proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_rsvd5, cmd_tvb, 1024-off, 768, ENC_NA);
2127 if (off <= 1792) {
2128 CHECK_STOP_PARSE(1792, 256);
2129 dissect_nvme_identify_ctrl_resp_nvmeof(cmd_tvb, cmd_tree, off);
2132 if (off <= 2048) {
2133 CHECK_STOP_PARSE(2048, 1024);
2134 dissect_nvme_identify_ctrl_resp_power_state_descriptors(cmd_tvb, cmd_tree, off);
2137 if (off <= 3072) {
2138 CHECK_STOP_PARSE(3072, 1024);
2139 proto_tree_add_item(cmd_tree, hf_nvme_identify_ctrl_vs, cmd_tvb, 3072-off, 1024, ENC_NA);
2143 static void dissect_nvme_identify_resp(tvbuff_t *cmd_tvb, proto_tree *cmd_tree,
2144 struct nvme_cmd_ctx *cmd_ctx, unsigned off, unsigned len)
2146 switch(cmd_ctx->cmd_ctx.cmd_identify.cns) {
2147 case NVME_IDENTIFY_CNS_IDENTIFY_NS:
2148 dissect_nvme_identify_ns_resp(cmd_tvb, cmd_tree, off, len);
2149 break;
2150 case NVME_IDENTIFY_CNS_IDENTIFY_CTRL:
2151 dissect_nvme_identify_ctrl_resp(cmd_tvb, cmd_tree, off, len);
2152 break;
2153 case NVME_IDENTIFY_CNS_IDENTIFY_NSLIST:
2154 dissect_nvme_identify_nslist_resp(cmd_tvb, cmd_tree, off, len);
2155 break;
2156 default:
2157 break;
2161 static void dissect_nvme_identify_cmd(tvbuff_t *cmd_tvb, proto_tree *cmd_tree)
2163 add_group_mask_entry(cmd_tvb, cmd_tree, 40, 4, ASPEC(hf_nvme_identify_dword10));
2164 add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_identify_dword11));
2166 proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword12, cmd_tvb, 48, 4, ENC_LITTLE_ENDIAN);
2167 proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword13, cmd_tvb, 52, 4, ENC_LITTLE_ENDIAN);
2169 add_group_mask_entry(cmd_tvb, cmd_tree, 56, 4, ASPEC(hf_nvme_identify_dword14));
2171 proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword15, cmd_tvb, 60, 4, ENC_LITTLE_ENDIAN);
2174 static const value_string logpage_tbl[] = {
2175 { 0, "Unspecified" },
2176 { 1, "Error Information" },
2177 { 2, "SMART/Health Information" },
2178 { 3, "Firmware Slot Information" },
2179 { 4, "Changed Namespace List" },
2180 { 5, "Commands Supported and Effects" },
2181 { 6, "Device Self-test" },
2182 { 7, "Telemetry Host-Initiated" },
2183 { 8, "Telemetry Controller-Initiated" },
2184 { 9, "Endurance Group Information" },
2185 { 10, "Predictable Latency Per NVM Set" },
2186 { 11, "Predictable Latency Event Aggregate" },
2187 { 12, "Asymmetric Namespace Access" },
2188 { 13, "Persistent Event Log" },
2189 { 14, "LBA Status Information" },
2190 { 15, "Endurance Group Event Aggregate" },
2191 { 0x70, "NVMeOF Discovery" },
2192 { 0x80, "Reservation Notification" },
2193 { 0x81, "Sanitize Status" },
2194 { 0, NULL }
2197 static const char *get_logpage_name(unsigned lid)
2199 if (lid > 0x70 && lid < 0x80)
2200 return "NVMeoF Reserved Page name";
2201 else if (lid > 0x81 && lid < 0xc0)
2202 return "IO Command Set Specific Page";
2203 else if (lid >= 0xc0)
2204 return "Vendor Specific Page";
2205 else
2206 return val_to_str_const(lid, logpage_tbl, "Reserved Page Name");
2209 static void add_logpage_lid(char *result, uint32_t val)
2211 snprintf(result, ITEM_LABEL_LENGTH, "%s (0x%x)", get_logpage_name(val), val);
2214 static const value_string sec_type_tbl[] = {
2215 { 0, "No security" },
2216 { 1, "Transport Layer Security (TLS) version >= 1.2" },
2217 { 0, NULL }
2220 static void dissect_nvme_get_logpage_ify_rcrd_tsas_tcp(tvbuff_t *cmd_tvb, proto_item *ti, unsigned off)
2222 proto_tree *grp = proto_item_add_subtree(ti, ett_data);
2223 proto_tree_add_item(grp, hf_nvme_get_logpage_ify_rcrd_tsas_tcp_sectype, cmd_tvb, off, 1, ENC_LITTLE_ENDIAN);
2224 proto_tree_add_item(grp, hf_nvme_get_logpage_ify_rcrd_tsas_tcp_rsvd, cmd_tvb, off+1, 255, ENC_NA);
2227 static const value_string qp_type_tbl[] = {
2228 { 1, "Reliable Connected" },
2229 { 2, "Reliable Datagram" },
2230 { 0, NULL }
2233 static const value_string pr_type_tbl[] = {
2234 { 1, "No provider specified" },
2235 { 2, "InfiniBand" },
2236 { 3, "RoCE (v1)" },
2237 { 4, "RoCE (v2)" },
2238 { 5, "iWARP" },
2239 { 0, NULL }
2242 static const value_string cms_type_tbl[] = {
2243 { 1, "RDMA_IP_CM" },
2244 { 0, NULL }
2247 static void dissect_nvme_get_logpage_ify_rcrd_tsas_rdma(tvbuff_t *cmd_tvb, proto_item *ti, unsigned off)
2249 proto_tree *grp;
2251 grp = proto_item_add_subtree(ti, ett_data);
2252 proto_tree_add_item(grp, hf_nvme_get_logpage_ify_rcrd_tsas_rdma_qptype, cmd_tvb, off, 1, ENC_LITTLE_ENDIAN);
2253 proto_tree_add_item(grp, hf_nvme_get_logpage_ify_rcrd_tsas_rdma_prtype, cmd_tvb, off+1, 1, ENC_LITTLE_ENDIAN);
2254 proto_tree_add_item(grp, hf_nvme_get_logpage_ify_rcrd_tsas_rdma_cms, cmd_tvb, off+2, 1, ENC_LITTLE_ENDIAN);
2255 proto_tree_add_item(grp, hf_nvme_get_logpage_ify_rcrd_tsas_rdma_rsvd0, cmd_tvb, off+3, 5, ENC_NA);
2256 proto_tree_add_item(grp, hf_nvme_get_logpage_ify_rcrd_tsas_rdma_pkey, cmd_tvb, off+8, 2, ENC_LITTLE_ENDIAN);
2257 proto_tree_add_item(grp, hf_nvme_get_logpage_ify_rcrd_tsas_rdma_rsvd1, cmd_tvb, off+10, 246, ENC_NA);
2260 static const value_string trt_type_tbl[] = {
2261 { 0, "Reserved" },
2262 { 1, "RDMA Transport" },
2263 { 2, "Fibre Channel Transport" },
2264 { 3, "TCP Transport" },
2265 { 254, "Itra-host Transport" },
2266 { 0, NULL }
2269 static const value_string adrfam_type_tbl[] = {
2270 { 0, "Reserved" },
2271 { 1, "AF_INET" },
2272 { 2, "AF_INET6" },
2273 { 3, "AF_IB" },
2274 { 4, "Fibre Channel" },
2275 { 254, "Intra-Host" },
2276 { 0, NULL }
2279 static const value_string sub_type_tbl[] = {
2280 { 0, "Reserved" },
2281 { 1, "Referral to another Discovery Subsystem" },
2282 { 2, "NVM subsystem with IO controllers" },
2283 { 3, "Current Discovery Subsystem" },
2284 { 0, NULL }
2287 static void dissect_nvme_get_logpage_ify_rcrd_resp(tvbuff_t *cmd_tvb, proto_tree *tree, uint64_t rcrd, unsigned roff, int off, unsigned len)
2289 proto_item *ti;
2290 proto_tree *grp;
2291 unsigned tr_type;
2293 ti = proto_tree_add_bytes_format(tree, hf_nvme_get_logpage_ify_rcrd, cmd_tvb, off,
2294 (len < 1024) ? len : 1024, NULL, "Discovery Log Entry %"PRIu64" (DLE%"PRIu64")", rcrd, rcrd);
2295 grp = proto_item_add_subtree(ti, ett_data);
2297 if (!roff)
2298 proto_tree_add_item_ret_uint(grp, hf_nvme_get_logpage_ify_rcrd_trtype, cmd_tvb, off, 1, ENC_LITTLE_ENDIAN, &tr_type);
2300 if (roff <= 1 && (2-roff) <= len)
2301 proto_tree_add_item(grp, hf_nvme_get_logpage_ify_rcrd_adrfam, cmd_tvb, off-roff+1, 1, ENC_LITTLE_ENDIAN);
2303 if (roff <= 2 && (3-roff) <= len)
2304 proto_tree_add_item(grp, hf_nvme_get_logpage_ify_rcrd_subtype, cmd_tvb, off-roff+2, 1, ENC_LITTLE_ENDIAN);
2306 if (roff <= 3 && (4-roff) <= len)
2307 add_group_mask_entry(cmd_tvb, grp, off-roff+3, 1, ASPEC(hf_nvme_get_logpage_ify_rcrd_treq));
2309 if (roff <= 4 && (6-roff) <= len)
2310 proto_tree_add_item(grp, hf_nvme_get_logpage_ify_rcrd_portid, cmd_tvb, off-roff+4, 2, ENC_LITTLE_ENDIAN);
2312 if (roff <= 6 && (8-roff) <= len)
2313 proto_tree_add_item(grp, hf_nvme_get_logpage_ify_rcrd_cntlid, cmd_tvb, off-roff+6, 2, ENC_LITTLE_ENDIAN);
2315 if (roff <= 8 && (10-roff) <= len)
2316 proto_tree_add_item(grp, hf_nvme_get_logpage_ify_rcrd_asqsz, cmd_tvb, off-roff+8, 2, ENC_LITTLE_ENDIAN);
2318 if (roff <= 10 && (12-roff) <= len)
2319 add_group_mask_entry(cmd_tvb, grp, off-roff+10, 2, ASPEC(hf_nvme_get_logpage_disc_rcrd_eflags));
2321 if (roff <= 12 && (32-roff) <= len)
2322 proto_tree_add_item(grp, hf_nvme_get_logpage_ify_rcrd_rsvd0, cmd_tvb, off-roff+12, 20, ENC_NA);
2324 if (roff <= 32 && (64-roff) <= len)
2325 proto_tree_add_item(grp, hf_nvme_get_logpage_ify_rcrd_trsvcid, cmd_tvb, off-roff+32, 32, ENC_ASCII);
2327 if (roff <= 64 && (256-roff) <= len)
2328 proto_tree_add_item(grp, hf_nvme_get_logpage_ify_rcrd_rsvd1, cmd_tvb, off-roff+64, 192, ENC_NA);
2330 if (roff <= 256 && (512-roff) <= len)
2331 proto_tree_add_item(grp, hf_nvme_get_logpage_ify_rcrd_subnqn, cmd_tvb, off-roff+256, 256, ENC_ASCII);
2333 if (roff <= 512 && (768-roff) <= len)
2334 proto_tree_add_item(grp, hf_nvme_get_logpage_ify_rcrd_traddr, cmd_tvb, off-roff+512, 256, ENC_ASCII);
2336 if (roff <= 768 && (1024-roff) <= len) {
2337 ti = proto_tree_add_item(grp, hf_nvme_get_logpage_ify_rcrd_tsas, cmd_tvb, off-roff+768, 256, ENC_NA);
2338 if (tr_type == 1)
2339 dissect_nvme_get_logpage_ify_rcrd_tsas_rdma(cmd_tvb, ti, off-roff+768);
2340 else if (tr_type == 3)
2341 dissect_nvme_get_logpage_ify_rcrd_tsas_tcp(cmd_tvb, ti, off-roff+768);
2345 static void dissect_nvme_get_logpage_ify_resp(proto_item *ti, tvbuff_t *cmd_tvb, struct nvme_cmd_ctx *cmd_ctx, unsigned tr_off, unsigned len)
2347 uint64_t off = cmd_ctx->cmd_ctx.get_logpage.off + tr_off;
2348 proto_tree *grp;
2349 unsigned poff;
2350 unsigned roff;
2351 unsigned max_bytes;
2352 uint64_t rcrd, rcrd_ctr = 0;
2353 uint64_t recnum = 0;
2355 grp = proto_item_add_subtree(ti, ett_data);
2357 if (!off && len >= 8)
2358 proto_tree_add_item(grp, hf_nvme_get_logpage_ify_genctr, cmd_tvb, 0, 8, ENC_LITTLE_ENDIAN);
2360 /* unsigned casts are to silence clang-11 compile errors */
2361 if (off <= 8 && (16 - (unsigned)off) <= len)
2362 proto_tree_add_item_ret_uint64(grp, hf_nvme_get_logpage_ify_numrec, cmd_tvb, (unsigned)(8-off), 8, ENC_LITTLE_ENDIAN, &recnum);
2364 if (off <= 16 && (18 - (unsigned)off) <= len) {
2365 proto_tree_add_item(grp, hf_nvme_get_logpage_ify_recfmt, cmd_tvb, (unsigned)(16-off), 2, ENC_LITTLE_ENDIAN);
2366 cmd_ctx->cmd_ctx.get_logpage.records = (recnum & 0xffffffff);
2367 } else if (tr_off) {
2368 recnum = cmd_ctx->cmd_ctx.get_logpage.records;
2371 if (off <= 18 && (1024 - (unsigned)off) <= len)
2372 proto_tree_add_item(grp, hf_nvme_get_logpage_ify_rsvd, cmd_tvb, (unsigned)(18-off), 1006, ENC_NA);
2374 if (off <= 1024) {
2375 poff = (1024 - (unsigned)off); /* clang-11 is so strange, hence the cast */
2376 if (poff >= len)
2377 return;
2378 max_bytes = 1024;
2379 rcrd = 0;
2380 roff = 0;
2381 len -= poff;
2382 } else {
2383 poff = 0;
2384 roff = (off & 1023);
2385 max_bytes = 1024 - (roff);
2386 rcrd = (off - roff) / 1024 - 1;
2389 max_bytes = (max_bytes <= len) ? max_bytes : len;
2390 dissect_nvme_get_logpage_ify_rcrd_resp(cmd_tvb, grp, rcrd, roff, poff, len);
2391 poff += max_bytes;
2392 len -= max_bytes;
2393 rcrd++;
2394 rcrd_ctr++;
2396 if (!recnum)
2397 recnum = (len + 1023) / 1024;
2399 while (len && rcrd_ctr <= recnum) {
2400 max_bytes = (len >= 1024) ? 1024 : len;
2401 dissect_nvme_get_logpage_ify_rcrd_resp(cmd_tvb, grp, rcrd, 0, poff, len);
2402 poff += max_bytes;
2403 len -= max_bytes;
2404 rcrd++;
2405 rcrd_ctr++;
2409 static void dissect_nvme_get_logpage_err_inf_resp(proto_item *ti, tvbuff_t *cmd_tvb, struct nvme_cmd_ctx *cmd_ctx, unsigned len)
2411 uint32_t off = cmd_ctx->cmd_ctx.get_logpage.off & 0xffffffff; /* need unsigned type to silence clang-11 errors */
2412 proto_tree *grp;
2414 grp = proto_item_add_subtree(ti, ett_data);
2416 if (cmd_ctx->cmd_ctx.get_logpage.off > 42)
2417 return; /* max allowed offset is 42, so we do not loose bits by casting to unsigned type */
2419 if (!off && len >= 8)
2420 proto_tree_add_item(grp, hf_nvme_get_logpage_errinf_errcnt, cmd_tvb, 0, 8, ENC_LITTLE_ENDIAN);
2421 if (off <= 8 && (10-off) <= len)
2422 proto_tree_add_item(grp, hf_nvme_get_logpage_errinf_sqid, cmd_tvb, 8-off, 2, ENC_LITTLE_ENDIAN);
2423 if (off <= 10 && (12-off) <= len)
2424 proto_tree_add_item(grp, hf_nvme_get_logpage_errinf_cid, cmd_tvb, 10-off, 2, ENC_LITTLE_ENDIAN);
2425 if (off <= 12 && (14-off) <= len)
2426 add_group_mask_entry(cmd_tvb, grp, 12-off, 2, ASPEC(hf_nvme_get_logpage_errinf_sf));
2427 if (off <= 14 && (16-off) <= len)
2428 add_group_mask_entry(cmd_tvb, grp, 14-off, 2, ASPEC(hf_nvme_get_logpage_errinf_pel));
2429 if (off <= 16 && (24-off) <= len)
2430 proto_tree_add_item(grp, hf_nvme_get_logpage_errinf_lba, cmd_tvb, 16-off, 8, ENC_LITTLE_ENDIAN);
2431 if (off <= 24 && (28-off) <= len)
2432 proto_tree_add_item(grp, hf_nvme_get_logpage_errinf_ns, cmd_tvb, 24-off, 4, ENC_LITTLE_ENDIAN);
2433 if (off <= 28 && (29-off) <= len)
2434 proto_tree_add_item(grp, hf_nvme_get_logpage_errinf_vsi, cmd_tvb, 28-off, 1, ENC_LITTLE_ENDIAN);
2435 if (off <= 29 && (30-off) <= len)
2436 proto_tree_add_item(grp, hf_nvme_get_logpage_errinf_trtype, cmd_tvb, 29-off, 1, ENC_LITTLE_ENDIAN);
2437 if (off <= 30 && (32-off) <= len)
2438 proto_tree_add_item(grp, hf_nvme_get_logpage_errinf_rsvd0, cmd_tvb, 30-off, 2, ENC_NA);
2439 if (off <= 32 && (40-off) <= len)
2440 proto_tree_add_item(grp, hf_nvme_get_logpage_errinf_csi, cmd_tvb, 32-off, 8, ENC_LITTLE_ENDIAN);
2441 if (off <= 40 && (42-off) <= len)
2442 proto_tree_add_item(grp, hf_nvme_get_logpage_errinf_tsi, cmd_tvb, 40-off, 2, ENC_LITTLE_ENDIAN);
2443 if (off <= 42 && (64-off) <= len)
2444 proto_tree_add_item(grp, hf_nvme_get_logpage_errinf_rsvd1, cmd_tvb, 42-off, 24, ENC_NA);
2447 static void post_add_intval_from_16bytes(proto_item *ti, tvbuff_t *tvb, unsigned off)
2449 uint64_t lo = tvb_get_uint64(tvb, off, 0);
2450 uint64_t hi = tvb_get_uint64(tvb, off, 8);
2451 double res;
2453 res = (double)hi;
2454 res *= (((uint64_t)1) << 63);
2455 res *= 2;
2456 res += lo;
2457 if (res > 99999999)
2458 proto_item_append_text(ti, " (%.8le)", res);
2459 else
2460 proto_item_append_text(ti, " (%.0lf)", res);
2463 static void decode_smart_resp_temps(proto_tree *grp, tvbuff_t *cmd_tvb, unsigned off, unsigned len)
2465 proto_item *ti;
2466 unsigned bytes;
2467 unsigned poff;
2468 unsigned max_bytes;
2469 unsigned i;
2472 poff = (off < 200) ? 200-off : off;
2474 if (off > 214 || (poff + 2) > len)
2475 return;
2477 bytes = len - poff;
2478 max_bytes = (off <= 200) ? 16 : (216 - off);
2480 if (bytes > max_bytes)
2481 bytes = max_bytes;
2483 ti = proto_tree_add_item(grp, hf_nvme_get_logpage_smart_ts[0], cmd_tvb, poff, bytes, ENC_NA);
2484 grp = proto_item_add_subtree(ti, ett_data);
2485 for (i = 0; i < 8; i++) {
2486 unsigned pos = 200 + i * 2;
2487 if (off <= pos && (off + pos + 2) <= len)
2488 proto_tree_add_item(grp, hf_nvme_get_logpage_smart_ts[i+1], cmd_tvb, pos - off, 2, ENC_LITTLE_ENDIAN);
2492 static void dissect_nvme_get_logpage_smart_resp(proto_item *ti, tvbuff_t *cmd_tvb, struct nvme_cmd_ctx *cmd_ctx, unsigned len)
2494 uint32_t off = cmd_ctx->cmd_ctx.get_logpage.off & 0xffffffff; /* need unsigned type to silence clang-11 errors */
2495 proto_tree *grp;
2497 if (cmd_ctx->cmd_ctx.get_logpage.off >= 512)
2498 return; /* max allowed offset is < 512, so we do not loose bits by casting to unsigned type */
2500 grp = proto_item_add_subtree(ti, ett_data);
2501 if (!off && len >= 1)
2502 add_group_mask_entry(cmd_tvb, grp, 0, 1, ASPEC(hf_nvme_get_logpage_smart_cw));
2503 if (off <= 1 && (3 -off) <= len)
2504 proto_tree_add_item(grp, hf_nvme_get_logpage_smart_ct, cmd_tvb, 1-off, 2, ENC_LITTLE_ENDIAN);
2505 if (off <= 3 && (4 -off) <= len)
2506 proto_tree_add_item(grp, hf_nvme_get_logpage_smart_asc, cmd_tvb, 3-off, 1, ENC_LITTLE_ENDIAN);
2507 if (off <= 4 && (5 -off) <= len)
2508 proto_tree_add_item(grp, hf_nvme_get_logpage_smart_ast, cmd_tvb, 4-off, 1, ENC_LITTLE_ENDIAN);
2509 if (off <= 5 && (6 -off) <= len)
2510 proto_tree_add_item(grp, hf_nvme_get_logpage_smart_lpu, cmd_tvb, 5-off, 1, ENC_LITTLE_ENDIAN);
2511 if (off <= 6 && (7 -off) <= len)
2512 add_group_mask_entry(cmd_tvb, grp, 6-off, 1, ASPEC(hf_nvme_get_logpage_smart_egcws));
2513 if (off <= 7 && (32 -off) <= len)
2514 proto_tree_add_item(grp, hf_nvme_get_logpage_smart_rsvd0, cmd_tvb, 7-off, 25, ENC_NA);
2515 if (off <= 32 && (48 -off) <= len) {
2516 ti = proto_tree_add_item(grp, hf_nvme_get_logpage_smart_dur, cmd_tvb, 32-off, 16, ENC_NA);
2517 post_add_bytes_from_16bytes(ti, cmd_tvb, 32-off, 16);
2519 if (off <= 48 && (64 -off) <= len) {
2520 ti = proto_tree_add_item(grp, hf_nvme_get_logpage_smart_duw, cmd_tvb, 48-off, 16, ENC_NA);
2521 post_add_bytes_from_16bytes(ti, cmd_tvb, 48-off, 16);
2523 if (off <= 64 && (80 -off) <= len) {
2524 ti = proto_tree_add_item(grp, hf_nvme_get_logpage_smart_hrc, cmd_tvb, 64-off, 16, ENC_NA);
2525 post_add_intval_from_16bytes(ti, cmd_tvb, 64-off);
2527 if (off <= 80 && (96 -off) <= len) {
2528 ti = proto_tree_add_item(grp, hf_nvme_get_logpage_smart_hwc, cmd_tvb, 80-off, 16, ENC_NA);
2529 post_add_intval_from_16bytes(ti, cmd_tvb, 80-off);
2531 if (off <= 96 && (112 -off) <= len) {
2532 ti = proto_tree_add_item(grp, hf_nvme_get_logpage_smart_cbt, cmd_tvb, 96-off, 16, ENC_NA);
2533 post_add_intval_from_16bytes(ti, cmd_tvb, 96-off);
2535 if (off <= 112 && (128 -off) <= len) {
2536 ti = proto_tree_add_item(grp, hf_nvme_get_logpage_smart_pc, cmd_tvb, 112-off, 16, ENC_NA);
2537 post_add_intval_from_16bytes(ti, cmd_tvb, 112-off);
2539 if (off <= 128 && (144 -off) <= len) {
2540 ti = proto_tree_add_item(grp, hf_nvme_get_logpage_smart_poh, cmd_tvb, 128-off, 16, ENC_NA);
2541 post_add_intval_from_16bytes(ti, cmd_tvb, 128-off);
2543 if (off <= 144 && (160 -off) <= len) {
2544 ti = proto_tree_add_item(grp, hf_nvme_get_logpage_smart_us, cmd_tvb, 144-off, 16, ENC_NA);
2545 post_add_intval_from_16bytes(ti, cmd_tvb, 144-off);
2547 if (off <= 160 && (176 -off) <= len) {
2548 ti = proto_tree_add_item(grp, hf_nvme_get_logpage_smart_mie, cmd_tvb, 160-off, 16, ENC_NA);
2549 post_add_intval_from_16bytes(ti, cmd_tvb, 160-off);
2551 if (off <= 176 && (192 -off) <= len) {
2552 ti = proto_tree_add_item(grp, hf_nvme_get_logpage_smart_ele, cmd_tvb, 176-off, 16, ENC_NA);
2553 post_add_intval_from_16bytes(ti, cmd_tvb, 176-off);
2555 if (off <= 192 && (196 -off) <= len)
2556 proto_tree_add_item(grp, hf_nvme_get_logpage_smart_wctt, cmd_tvb, 192-off, 4, ENC_LITTLE_ENDIAN);
2557 if (off <= 196 && (200 -off) <= len)
2558 proto_tree_add_item(grp, hf_nvme_get_logpage_smart_cctt, cmd_tvb, 196-off, 4, ENC_LITTLE_ENDIAN);
2560 decode_smart_resp_temps(grp, cmd_tvb, off, len);
2562 if (off <= 216 && (220 -off) <= len)
2563 proto_tree_add_item(grp, hf_nvme_get_logpage_smart_tmt1c, cmd_tvb, 216-off, 4, ENC_LITTLE_ENDIAN);
2564 if (off <= 220 && (224 -off) <= len)
2565 proto_tree_add_item(grp, hf_nvme_get_logpage_smart_tmt2c, cmd_tvb, 220-off, 4, ENC_LITTLE_ENDIAN);
2566 if (off <= 224 && (228 -off) <= len)
2567 proto_tree_add_item(grp, hf_nvme_get_logpage_smart_tmt1t, cmd_tvb, 224-off, 4, ENC_LITTLE_ENDIAN);
2568 if (off <= 228 && (232 -off) <= len)
2569 proto_tree_add_item(grp, hf_nvme_get_logpage_smart_tmt2t, cmd_tvb, 228-off, 4, ENC_LITTLE_ENDIAN);
2570 if (off < 512) {
2571 unsigned poff = (off < 232) ? 232 : off;
2572 unsigned max_len = (off <= 232) ? 280 : 512 - off;
2573 len -= poff;
2574 if (len > max_len)
2575 len = max_len;
2576 proto_tree_add_item(grp, hf_nvme_get_logpage_smart_rsvd1, cmd_tvb, poff, len, ENC_NA);
2580 static void decode_fw_slot_frs(proto_tree *grp, tvbuff_t *cmd_tvb, uint32_t off, unsigned len)
2582 proto_item *ti;
2583 unsigned bytes;
2584 unsigned poff;
2585 unsigned max_bytes;
2586 unsigned i;
2589 poff = (off < 8) ? 8-off : off;
2591 if (off > 56 || (poff + 8) > len)
2592 return;
2594 bytes = len - poff;
2595 max_bytes = (off <= 8) ? 56 : (64 - off);
2597 if (bytes > max_bytes)
2598 bytes = max_bytes;
2600 ti = proto_tree_add_item(grp, hf_nvme_get_logpage_fw_slot_frs[0], cmd_tvb, poff, bytes, ENC_NA);
2601 grp = proto_item_add_subtree(ti, ett_data);
2602 for (i = 0; i < 7; i++) {
2603 unsigned pos = 8 + i * 8;
2604 if (off <= pos && (pos + 8 - off) <= len)
2605 proto_tree_add_item(grp, hf_nvme_get_logpage_fw_slot_frs[i+1], cmd_tvb, pos - off, 8, ENC_LITTLE_ENDIAN);
2609 static void dissect_nvme_get_logpage_fw_slot_resp(proto_item *ti, tvbuff_t *cmd_tvb, struct nvme_cmd_ctx *cmd_ctx, unsigned len)
2611 uint32_t off = cmd_ctx->cmd_ctx.get_logpage.off & 0xffffffff; /* need unsigned type to silence clang-11 errors */
2612 proto_tree *grp;
2614 if (cmd_ctx->cmd_ctx.get_logpage.off >= 512)
2615 return; /* max allowed offset is < 512, so we do not loose bits by casting to unsigned type */
2617 grp = proto_item_add_subtree(ti, ett_data);
2619 if (!off && len > 1)
2620 add_group_mask_entry(cmd_tvb, grp, 0, 1, ASPEC(hf_nvme_get_logpage_fw_slot_afi));
2621 if (off <= 1 && (8-off) <= len)
2622 proto_tree_add_item(grp, hf_nvme_get_logpage_fw_slot_rsvd0, cmd_tvb, 1-off, 7, ENC_NA);
2624 decode_fw_slot_frs(grp, cmd_tvb, off, len);
2626 if (off < 512) {
2627 unsigned poff = (off < 64) ? 64 : off;
2628 unsigned max_len = (off <= 64) ? 448 : 512 - off;
2629 len -= poff;
2630 if (len > max_len)
2631 len = max_len;
2632 proto_tree_add_item(grp, hf_nvme_get_logpage_fw_slot_rsvd1, cmd_tvb, poff, len, ENC_NA);
2636 static void dissect_nvme_get_logpage_changed_nslist_resp(proto_item *ti, tvbuff_t *cmd_tvb, unsigned len)
2638 proto_tree *grp;
2639 unsigned off = 0;
2641 grp = proto_item_add_subtree(ti, ett_data);
2642 while (len >= 4) {
2643 proto_tree_add_item(grp, hf_nvme_get_logpage_changed_nslist, cmd_tvb, off, 4, ENC_LITTLE_ENDIAN);
2644 len -= 4;
2645 off += 4;
2649 static const value_string cmd_eff_cse_tbl[] = {
2650 { 0, "No command submission or execution restriction" },
2651 { 1, "One concurrent command per namespace" },
2652 { 2, "One concurrent command per system" },
2653 { 0, NULL}
2656 static void dissect_nvme_get_logpage_cmd_sup_and_eff_grp(proto_tree *grp, tvbuff_t *cmd_tvb, unsigned poff, unsigned nrec, unsigned fidx, bool acs)
2658 unsigned i;
2659 proto_item *ti;
2660 for (i = 0; i < nrec; i++) {
2661 if (acs)
2662 ti = proto_tree_add_bytes_format(grp, hf_nvme_get_logpage_cmd_and_eff_cs, cmd_tvb, poff, 4, NULL, "Admin Command Supported %u (ACS%u)", fidx+i, fidx+1);
2663 else
2664 ti = proto_tree_add_bytes_format(grp, hf_nvme_get_logpage_cmd_and_eff_cs, cmd_tvb, poff, 4, NULL, "I/0 Command Supported %u (IOCS%u)", fidx+i, fidx+1);
2665 grp = proto_item_add_subtree(ti, ett_data);
2666 add_group_mask_entry(cmd_tvb, grp, poff, 4, ASPEC(hf_nvme_get_logpage_cmd_and_eff_cseds));
2667 poff += 4;
2672 static void dissect_nvme_get_logpage_cmd_sup_and_eff_resp(proto_item *ti, tvbuff_t *cmd_tvb, struct nvme_cmd_ctx *cmd_ctx, unsigned tr_off, unsigned len)
2674 uint32_t off = cmd_ctx->cmd_ctx.get_logpage.off & 0xffffffff; /* need unsigned type to silence clang-11 errors */
2675 proto_tree *grp;
2676 unsigned nrec = 0;
2677 unsigned fidx;
2679 off += tr_off;
2680 if (cmd_ctx->cmd_ctx.get_logpage.off >= 4096)
2681 return; /* max allowed offset is < 4096, so we do not loose bits by casting to unsigned type */
2683 grp = proto_item_add_subtree(ti, ett_data);
2684 if (off <= 1024 && len >= 4) {
2685 fidx = off / 4;
2686 nrec = (1024-off) / 4;
2687 if (nrec > (len / 4))
2688 nrec = len / 4;
2689 dissect_nvme_get_logpage_cmd_sup_and_eff_grp(grp, cmd_tvb, 0, nrec, fidx, true);
2692 nrec = len / 4 - nrec;
2693 if (!nrec)
2694 return;
2695 if (nrec > 256)
2696 nrec = 256;
2698 fidx = (off > 1028) ? (off - 1028) / 4 : 0;
2699 off = (off < 1028) ? (1028 - off) : 0;
2701 dissect_nvme_get_logpage_cmd_sup_and_eff_grp(grp, cmd_tvb, off, nrec, fidx, false);
2704 static const value_string stest_type_active_tbl[] = {
2705 { 0, "No device self-test operation in progress" },
2706 { 1, "Short device self-test operation in progress" },
2707 { 2, "Extended device self-test operation in progress" },
2708 { 0xE, "Vendor Specific" },
2709 { 0, NULL}
2712 static const value_string stest_result_tbl[] = {
2713 { 0, "Operation completed without error" },
2714 { 1, "Operation was aborted by a Device Self-test command" },
2715 { 2, "Operation was aborted by a Controller Level Reset" },
2716 { 3, "Operation was aborted due to a removal of a namespace from the namespace inventory" },
2717 { 4, "Operation was aborted due to the processing of a Format NVM command" },
2718 { 5, "A fatal error or unknown test error occurred while the controller was executing the device self-test operation and the operation did not complete" },
2719 { 6, "Operation completed with a segment that failed and the segment that failed is not known" },
2720 { 7, "Operation completed with one or more failed segments and the first segment that failed is indicated in the Segment Number field" },
2721 { 8, "Operation was aborted for unknown reason" },
2722 { 9, "Operation was aborted due to a sanitize operation" },
2723 { 0xF, "Entry not used (does not contain a test result)" },
2724 { 0, NULL}
2727 static const value_string stest_type_done_tbl[] = {
2728 { 1, "Short device self-test operation in progress" },
2729 { 2, "Extended device self-test operation in progress" },
2730 { 0xE, "Vendor Specific" },
2731 { 0, NULL}
2734 static void dissect_nvme_get_logpage_selftest_result(proto_tree *grp, tvbuff_t *cmd_tvb, uint32_t off, unsigned tst_idx)
2736 proto_item *ti;
2738 ti = proto_tree_add_bytes_format(grp, hf_nvme_get_logpage_selftest_res, cmd_tvb, off, 24, NULL,
2739 "Latest Self-test Result Data Structure (latest %u)", tst_idx);
2740 grp = proto_item_add_subtree(ti, ett_data);
2741 add_group_mask_entry(cmd_tvb, grp, off, 1, ASPEC(hf_nvme_get_logpage_selftest_res_status));
2742 proto_tree_add_item(grp, hf_nvme_get_logpage_selftest_res_sn, cmd_tvb, off+1, 1, ENC_LITTLE_ENDIAN);
2743 add_group_mask_entry(cmd_tvb, grp, off+2, 1, ASPEC(hf_nvme_get_logpage_selftest_res_vdi));
2744 proto_tree_add_item(grp, hf_nvme_get_logpage_selftest_res_rsvd, cmd_tvb, off+3, 1, ENC_LITTLE_ENDIAN);
2745 proto_tree_add_item(grp, hf_nvme_get_logpage_selftest_res_poh, cmd_tvb, off+4, 8, ENC_LITTLE_ENDIAN);
2746 proto_tree_add_item(grp, hf_nvme_get_logpage_selftest_res_nsid, cmd_tvb, off+12, 4, ENC_LITTLE_ENDIAN);
2747 proto_tree_add_item(grp, hf_nvme_get_logpage_selftest_res_flba, cmd_tvb, off+16, 8, ENC_LITTLE_ENDIAN);
2748 add_group_mask_entry(cmd_tvb, grp, off+24, 1, ASPEC(hf_nvme_get_logpage_selftest_res_sct));
2749 proto_tree_add_item(grp, hf_nvme_get_logpage_selftest_res_sc, cmd_tvb, off+25, 1, ENC_LITTLE_ENDIAN);
2750 proto_tree_add_item(grp, hf_nvme_get_logpage_selftest_res_vs, cmd_tvb, off+26, 2, ENC_LITTLE_ENDIAN);
2753 static void dissect_nvme_get_logpage_selftest_resp(proto_item *ti, tvbuff_t *cmd_tvb, struct nvme_cmd_ctx *cmd_ctx, unsigned tr_off, unsigned len)
2755 uint32_t off = cmd_ctx->cmd_ctx.get_logpage.off & 0xffffffff; /* need unsigned type to silence clang-11 errors */
2756 proto_tree *grp;
2757 unsigned tst_idx;
2759 off += tr_off;
2760 if (cmd_ctx->cmd_ctx.get_logpage.off > 536)
2761 return; /* max offset is <= 536, so we do not loose bits by casting to unsigned type */
2763 grp = proto_item_add_subtree(ti, ett_data);
2765 if (!off && len >= 1)
2766 add_group_mask_entry(cmd_tvb, grp, 0, 1, ASPEC(hf_nvme_get_logpage_selftest_csto));
2767 if (off <= 1 && (2 - off) <= len)
2768 add_group_mask_entry(cmd_tvb, grp, 1-off, 1, ASPEC(hf_nvme_get_logpage_selftest_cstc));
2769 if (off <= 2 && (4 - off) <= len)
2770 proto_tree_add_item(grp, hf_nvme_get_logpage_selftest_rsvd, cmd_tvb, 2-off, 2, ENC_LITTLE_ENDIAN);
2772 if (off <= 4) {
2773 len -= (4-off);
2774 tst_idx = 0;
2775 off = 4;
2776 } else {
2777 tst_idx = (off - 4 + 27) / 28;
2778 len -= (tst_idx * 28 - (off - 4));
2779 off = 4 + (tst_idx * 8);
2781 while (len >= 28) {
2782 dissect_nvme_get_logpage_selftest_result(grp, cmd_tvb, off, tst_idx);
2783 off += 28;
2784 len -= 28;
2788 static void dissect_nvme_get_logpage_telemetry_resp(proto_item *ti, tvbuff_t *cmd_tvb, struct nvme_cmd_ctx *cmd_ctx, unsigned tr_off, unsigned len)
2790 uint32_t off = cmd_ctx->cmd_ctx.get_logpage.off & 0xffffffff; /* need unsigned type to silence clang-11 errors */
2791 proto_tree *grp;
2792 uint64_t next_block;
2793 uint32_t poff;
2794 const char *pfx = (cmd_ctx->cmd_ctx.get_logpage.lid == 0x7) ? "Host-Initiated" : "Controller-Initiated";
2796 off += tr_off;
2797 poff = 512 - (off & 0x1ff);
2798 next_block = (off + poff) / 512;
2800 grp = proto_item_add_subtree(ti, ett_data);
2803 if (poff >= len && cmd_ctx->cmd_ctx.get_logpage.off >= 384)
2804 return;
2806 if (!off && len >= 1)
2807 proto_tree_add_item(grp, hf_nvme_get_logpage_telemetry_li, cmd_tvb, 0, 1, ENC_LITTLE_ENDIAN);
2808 if (off <= 1 && (5 - off) <= len)
2809 proto_tree_add_item(grp, hf_nvme_get_logpage_telemetry_rsvd0, cmd_tvb, 1-off, 4, ENC_LITTLE_ENDIAN);
2810 if (off <= 5 && (8 - off) <= len)
2811 proto_tree_add_item(grp, hf_nvme_get_logpage_telemetry_ieee, cmd_tvb, 5-off, 3, ENC_LITTLE_ENDIAN);
2812 if (off <= 8 && (10 - off) <= len)
2813 proto_tree_add_item(grp, hf_nvme_get_logpage_telemetry_da1lb, cmd_tvb, 8-off, 2, ENC_LITTLE_ENDIAN);
2814 if (off <= 10 && (12 - off) <= len)
2815 proto_tree_add_item(grp, hf_nvme_get_logpage_telemetry_da2lb, cmd_tvb, 10-off, 2, ENC_LITTLE_ENDIAN);
2816 if (off <= 12 && (14 - off) <= len)
2817 proto_tree_add_item(grp, hf_nvme_get_logpage_telemetry_da3lb, cmd_tvb, 12-off, 2, ENC_LITTLE_ENDIAN);
2818 if (off <= 14 && (372 - off) <= len)
2819 proto_tree_add_item(grp, hf_nvme_get_logpage_telemetry_rsvd1, cmd_tvb, 14-off, 368, ENC_NA);
2820 if (off <= 382 && (383 - off) <= len)
2821 proto_tree_add_item(grp, hf_nvme_get_logpage_telemetry_da, cmd_tvb, 382-off, 1, ENC_LITTLE_ENDIAN);
2822 if (off <= 383 && (384 - off) <= len)
2823 proto_tree_add_item(grp, hf_nvme_get_logpage_telemetry_dgn, cmd_tvb, 383-off, 1, ENC_LITTLE_ENDIAN);
2824 if (off <= 384 && (512 - off) <= len)
2825 proto_tree_add_item(grp, hf_nvme_get_logpage_telemetry_ri, cmd_tvb, 384-off, 128, ENC_NA);
2827 len -= poff;
2828 while (len >= 512) {
2829 proto_tree_add_bytes_format_value(grp, hf_nvme_get_logpage_telemetry_db, cmd_tvb, poff, 512, NULL,
2830 "Telemetry %s data block %"PRIu64, pfx, next_block);
2831 len -= 512;
2832 next_block++;
2833 poff += 512;
2837 static void dissect_nvme_get_logpage_egroup_resp(proto_item *ti, tvbuff_t *cmd_tvb, struct nvme_cmd_ctx *cmd_ctx, unsigned len)
2839 uint32_t off = cmd_ctx->cmd_ctx.get_logpage.off & 0xffffffff; /* need unsigned type to silence clang-11 errors */
2840 proto_tree *grp;
2842 if (cmd_ctx->cmd_ctx.get_logpage.off >= 512)
2843 return; /* max allowed offset is < 512, so we do not loose bits by casting to unsigned type */
2845 grp = proto_item_add_subtree(ti, ett_data);
2846 if (!off && len >= 1)
2847 add_group_mask_entry(cmd_tvb, grp, 0, 1, ASPEC(hf_nvme_get_logpage_egroup_cw));
2848 if (off <= 1 && (3 - off) <= len)
2849 proto_tree_add_item(grp, hf_nvme_get_logpage_egroup_rsvd0, cmd_tvb, 1-off, 2, ENC_LITTLE_ENDIAN);
2850 if (off <= 3 && (4 - off) <= len)
2851 proto_tree_add_item(grp, hf_nvme_get_logpage_egroup_as, cmd_tvb, 3-off, 1, ENC_LITTLE_ENDIAN);
2852 if (off <= 4 && (5 - off) <= len)
2853 proto_tree_add_item(grp, hf_nvme_get_logpage_egroup_ast, cmd_tvb, 4-off, 1, ENC_LITTLE_ENDIAN);
2854 if (off <= 5 && (6 - off) <= len)
2855 proto_tree_add_item(grp, hf_nvme_get_logpage_egroup_pu, cmd_tvb, 5-off, 1, ENC_LITTLE_ENDIAN);
2856 if (off <= 6 && (32 - off) <= len)
2857 proto_tree_add_item(grp, hf_nvme_get_logpage_egroup_rsvd1, cmd_tvb, 6-off, 26, ENC_NA);
2858 if (off <= 32 && (48 - off) <= len) {
2859 ti = proto_tree_add_item(grp, hf_nvme_get_logpage_egroup_ee, cmd_tvb, 32-off, 16, ENC_NA);
2860 post_add_intval_from_16bytes(ti, cmd_tvb, 32-off);
2862 if (off <= 48 && (64 - off) <= len) {
2863 ti = proto_tree_add_item(grp, hf_nvme_get_logpage_egroup_dur, cmd_tvb, 48-off, 16, ENC_NA);
2864 post_add_intval_from_16bytes(ti, cmd_tvb, 48-off);
2866 if (off <= 64 && (80 - off) <= len) {
2867 ti = proto_tree_add_item(grp, hf_nvme_get_logpage_egroup_duw, cmd_tvb, 64-off, 16, ENC_NA);
2868 post_add_intval_from_16bytes(ti, cmd_tvb, 64-off);
2870 if (off <= 80 && (96 - off) <= len) {
2871 ti = proto_tree_add_item(grp, hf_nvme_get_logpage_egroup_muw, cmd_tvb, 80-off, 16, ENC_NA);
2872 post_add_intval_from_16bytes(ti, cmd_tvb, 80-off);
2874 if (off <= 96 && (112 - off) <= len) {
2875 ti = proto_tree_add_item(grp, hf_nvme_get_logpage_egroup_hrc, cmd_tvb, 96-off, 16, ENC_NA);
2876 post_add_intval_from_16bytes(ti, cmd_tvb, 96-off);
2878 if (off <= 112 && (128 - off) <= len) {
2879 ti = proto_tree_add_item(grp, hf_nvme_get_logpage_egroup_hwc, cmd_tvb, 112-off, 16, ENC_NA);
2880 post_add_intval_from_16bytes(ti, cmd_tvb, 112-off);
2882 if (off <= 128 && (144 - off) <= len) {
2883 ti = proto_tree_add_item(grp, hf_nvme_get_logpage_egroup_mdie, cmd_tvb, 128-off, 16, ENC_NA);
2884 post_add_intval_from_16bytes(ti, cmd_tvb, 128-off);
2886 if (off <= 144 && (160 - off) <= len) {
2887 ti = proto_tree_add_item(grp, hf_nvme_get_logpage_egroup_ele, cmd_tvb, 144-off, 16, ENC_NA);
2888 post_add_intval_from_16bytes(ti, cmd_tvb, 144-off);
2890 if (off <= 508 && (512 - off) <= len) {
2891 unsigned poff = (off <= 160) ? (160 - off) : (off - 160);
2892 proto_tree_add_item(grp, hf_nvme_get_logpage_egroup_rsvd2, cmd_tvb, poff, len - poff, ENC_NA);
2895 static const value_string plat_status_tbl[] = {
2896 { 0, "Predictable Latency Mode not Enabled" },
2897 { 1, "Deterministic Window (DTWIN)" },
2898 { 2, "Non-Deterministic Window (NDWIN)" },
2899 { 0, NULL}
2902 static void dissect_nvme_get_logpage_pred_lat_resp(proto_item *ti, tvbuff_t *cmd_tvb, struct nvme_cmd_ctx *cmd_ctx, unsigned len)
2904 uint32_t off = cmd_ctx->cmd_ctx.get_logpage.off & 0xffffffff; /* need unsigned type to silence clang-11 errors */
2905 proto_tree *grp;
2906 unsigned poff;
2908 if (cmd_ctx->cmd_ctx.get_logpage.off > 508)
2909 return; /* max allowed offset is < 508, so we do not loose bits by casting to unsigned type */
2911 grp = proto_item_add_subtree(ti, ett_data);
2912 if (!off && len >= 1)
2913 add_group_mask_entry(cmd_tvb, grp, 0, 1, ASPEC(hf_nvme_get_logpage_pred_lat_status));
2914 if (off <= 1 && (2 - off) <= len)
2915 proto_tree_add_item(grp, hf_nvme_get_logpage_pred_lat_rsvd0, cmd_tvb, 1-off, 1, ENC_LITTLE_ENDIAN);
2916 if (off <= 2 && (4 - off) <= len)
2917 add_group_mask_entry(cmd_tvb, grp, 2-off, 2, ASPEC(hf_nvme_get_logpage_pred_lat_etype));
2918 if (off <= 4 && (32 - off) <= len)
2919 proto_tree_add_item(grp, hf_nvme_get_logpage_pred_lat_rsvd1, cmd_tvb, 4-off, 28, ENC_NA);
2920 if (off <= 32 && (40 - off) <= len)
2921 proto_tree_add_item(grp, hf_nvme_get_logpage_pred_lat_dtwin_rt, cmd_tvb, 32-off, 8, ENC_LITTLE_ENDIAN);
2922 if (off <= 40 && (48 - off) <= len)
2923 proto_tree_add_item(grp, hf_nvme_get_logpage_pred_lat_dtwin_wt, cmd_tvb, 40-off, 8, ENC_LITTLE_ENDIAN);
2924 if (off <= 48 && (56 - off) <= len)
2925 proto_tree_add_item(grp, hf_nvme_get_logpage_pred_lat_dtwin_tm, cmd_tvb, 48-off, 8, ENC_LITTLE_ENDIAN);
2926 if (off <= 56 && (64 - off) <= len)
2927 proto_tree_add_item(grp, hf_nvme_get_logpage_pred_lat_ndwin_tmh, cmd_tvb, 56-off, 8, ENC_LITTLE_ENDIAN);
2928 if (off <= 64 && (72 - off) <= len)
2929 proto_tree_add_item(grp, hf_nvme_get_logpage_pred_lat_ndwin_tml, cmd_tvb, 64-off, 8, ENC_LITTLE_ENDIAN);
2930 if (off <= 72 && (128 - off) <= len)
2931 proto_tree_add_item(grp, hf_nvme_get_logpage_pred_lat_rsvd2, cmd_tvb, 72-off, 56, ENC_NA);
2932 if (off <= 128 && (136 - off) <= len)
2933 proto_tree_add_item(grp, hf_nvme_get_logpage_pred_lat_dtwin_re, cmd_tvb, 128-off, 8, ENC_LITTLE_ENDIAN);
2934 if (off <= 136 && (144 - off) <= len)
2935 proto_tree_add_item(grp, hf_nvme_get_logpage_pred_lat_dtwin_we, cmd_tvb, 136-off, 8, ENC_LITTLE_ENDIAN);
2936 if (off <= 144 && (152 - off) <= len)
2937 proto_tree_add_item(grp, hf_nvme_get_logpage_pred_lat_dtwin_te, cmd_tvb, 144-off, 8, ENC_LITTLE_ENDIAN);
2938 poff = (off <= 152) ? (152 - off) : 0;
2939 if (poff > len)
2940 return;
2941 proto_tree_add_item(grp, hf_nvme_get_logpage_pred_lat_rsvd3, cmd_tvb, poff, len - poff, ENC_NA);
2944 static void dissect_nvme_get_logpage_pred_lat_aggreg_resp(proto_item *ti, tvbuff_t *cmd_tvb, struct nvme_cmd_ctx *cmd_ctx, unsigned tr_off, unsigned len)
2946 uint64_t off = cmd_ctx->cmd_ctx.get_logpage.off;
2947 proto_tree *grp;
2948 unsigned poff;
2950 off += tr_off;
2951 if (off < 8) {
2952 poff = (cmd_ctx->cmd_ctx.get_logpage.off & 0x7);
2953 poff = 8 - poff;
2954 } else {
2955 poff = 0;
2957 if (len < (poff + 2) && off)
2958 return; /* nothing to display */
2960 grp = proto_item_add_subtree(ti, ett_data);
2961 if (!off && len >= 8)
2962 proto_tree_add_item(grp, hf_nvme_get_logpage_pred_lat_aggreg_ne, cmd_tvb, 0, 8, ENC_LITTLE_ENDIAN);
2963 len -= poff;
2964 while (len >= 2) {
2965 proto_tree_add_item(grp, hf_nvme_get_logpage_pred_lat_aggreg_nset, cmd_tvb, poff, 2, ENC_LITTLE_ENDIAN);
2966 poff += 2;
2967 len -= 2;
2971 static const value_string ana_state_tbl[] = {
2972 { 0x1, "ANA Optimized State" },
2973 { 0x2, "ANA Non-Optimized State" },
2974 { 0x3, "ANA Inaccessible State" },
2975 { 0x4, "ANA Persistent Loss State" },
2976 { 0xF, "ANA Change Sate" },
2977 { 0, NULL}
2980 static unsigned dissect_nvme_get_logpage_ana_resp_grp(proto_tree *grp, tvbuff_t *cmd_tvb, struct nvme_cmd_ctx *cmd_ctx, unsigned len, uint32_t poff)
2982 unsigned done = 0;
2983 unsigned bytes;
2984 proto_item *ti;
2985 unsigned group_id;
2986 unsigned nns;
2987 unsigned prev_off = cmd_ctx->cmd_ctx.get_logpage.tr_off;
2989 if (len < 4) {
2990 if (prev_off)
2991 cmd_ctx->cmd_ctx.get_logpage.tr_off += len;
2992 return 0;
2995 if (prev_off <= 4) {
2996 nns = tvb_get_uint32(cmd_tvb, poff+4-prev_off, ENC_LITTLE_ENDIAN);
2997 bytes = 32 + 4 * nns;
2998 cmd_ctx->cmd_ctx.get_logpage.tr_sub_entries = nns;
2999 } else if (prev_off ) {
3000 nns = cmd_ctx->cmd_ctx.get_logpage.tr_sub_entries;
3001 bytes = (prev_off > 32) ? 4 * nns : ((32-prev_off) + 4 * nns);
3002 } else {
3003 bytes = len;
3006 if (bytes > len)
3007 bytes = len;
3009 ti = proto_tree_add_bytes_format_value(grp, hf_nvme_get_logpage_ana_grp, cmd_tvb, poff, bytes, NULL,
3010 "ANA Group Descriptor");
3011 grp = proto_item_add_subtree(ti, ett_data);
3013 if (prev_off) {
3014 group_id = cmd_ctx->cmd_ctx.get_logpage.tr_rcrd_id;
3015 proto_item_append_text(ti, " %u (continued)", group_id);
3016 } else {
3017 proto_tree_add_item_ret_uint(grp, hf_nvme_get_logpage_ana_grp_id, cmd_tvb, poff, 4, ENC_LITTLE_ENDIAN, &group_id);
3018 done += 4;
3019 proto_item_append_text(ti, " %u", group_id);
3020 cmd_ctx->cmd_ctx.get_logpage.tr_rcrd_id = group_id;
3023 if (prev_off <= 4) {
3024 if ((len - done) < 4) {
3025 cmd_ctx->cmd_ctx.get_logpage.tr_off += done;
3026 return done;
3028 proto_tree_add_item(grp, hf_nvme_get_logpage_ana_grp_nns, cmd_tvb, poff+4-prev_off, 4, ENC_LITTLE_ENDIAN);
3029 done += 4;
3031 if (prev_off <= 8) {
3032 if ((len - done) < 8) {
3033 cmd_ctx->cmd_ctx.get_logpage.tr_off += done;
3034 return done;
3036 proto_tree_add_item(grp, hf_nvme_get_logpage_ana_grp_chcnt, cmd_tvb, poff+8-prev_off, 8, ENC_LITTLE_ENDIAN);
3037 done += 8;
3040 if (prev_off <= 16) {
3041 if ((len - done) < 1) {
3042 cmd_ctx->cmd_ctx.get_logpage.tr_off += done;
3043 return done;
3045 add_group_mask_entry(cmd_tvb, grp, poff+16-prev_off, 1, ASPEC(hf_nvme_get_logpage_ana_grp_anas));
3046 done += 1;
3049 if (prev_off <= 17) {
3050 if ((len - done) < 15) {
3051 cmd_ctx->cmd_ctx.get_logpage.tr_off += done;
3052 return done;
3054 proto_tree_add_item(grp, hf_nvme_get_logpage_ana_grp_rsvd, cmd_tvb, poff+17-prev_off, 15, ENC_NA);
3055 done += 15;
3058 poff += done;
3059 while ((len - done) >= 4 && nns) {
3060 proto_tree_add_item(grp, hf_nvme_get_logpage_ana_grp_nsid, cmd_tvb, poff, 4, ENC_LITTLE_ENDIAN);
3061 poff += 4;
3062 done += 4;
3063 nns--;
3065 if (nns) {
3066 cmd_ctx->cmd_ctx.get_logpage.tr_off += done;
3067 cmd_ctx->cmd_ctx.get_logpage.tr_sub_entries = nns;
3068 } else {
3069 cmd_ctx->cmd_ctx.get_logpage.tr_off = 0;
3070 cmd_ctx->cmd_ctx.get_logpage.tr_sub_entries = 0;
3071 cmd_ctx->cmd_ctx.get_logpage.tr_rcrd_id = 0;
3072 cmd_ctx->cmd_ctx.get_logpage.records--;
3074 return done;
3077 static unsigned dissect_nvme_get_logpage_ana_resp_header(proto_tree *grp, tvbuff_t *cmd_tvb, unsigned len, uint32_t off)
3079 unsigned groups=1;
3080 if (!off && len >= 8)
3081 proto_tree_add_item(grp, hf_nvme_get_logpage_ana_chcnt, cmd_tvb, off, 8, ENC_LITTLE_ENDIAN);
3082 if (off <= 8 && (10 - off) <= len)
3083 proto_tree_add_item_ret_uint(grp, hf_nvme_get_logpage_ana_ngd, cmd_tvb, 8-off, 2, ENC_LITTLE_ENDIAN, &groups);
3084 if (off <= 10 && (16 - off) <= len)
3085 proto_tree_add_item(grp, hf_nvme_get_logpage_ana_rsvd, cmd_tvb, 10-off, 6, ENC_LITTLE_ENDIAN);
3086 return groups;
3089 static void dissect_nvme_get_logpage_ana_resp(proto_item *ti, tvbuff_t *cmd_tvb, struct nvme_cmd_ctx *cmd_ctx, unsigned tr_off, unsigned len)
3091 uint32_t off = cmd_ctx->cmd_ctx.get_logpage.off & 0xffffffff; /* need unsigned type to silence clang-11 errors */
3092 proto_tree *grp;
3093 unsigned poff = 0;
3094 unsigned groups = 1;
3096 grp = proto_item_add_subtree(ti, ett_data);
3097 if (cmd_ctx->cmd_ctx.get_logpage.off < 16 && !tr_off) {
3098 groups = dissect_nvme_get_logpage_ana_resp_header(grp, cmd_tvb, len, off);
3099 cmd_ctx->cmd_ctx.get_logpage.records = groups;
3100 poff = 16 - off;
3101 } else if (tr_off) {
3102 groups = cmd_ctx->cmd_ctx.get_logpage.records;
3104 len -= poff;
3105 while (len >= 4 && groups) {
3106 unsigned done = dissect_nvme_get_logpage_ana_resp_grp(grp, cmd_tvb, cmd_ctx, len, poff);
3107 poff += done;
3108 len -= done;
3109 groups--;
3113 static void dissect_nvme_get_logpage_lba_status_resp_header(proto_tree *grp, tvbuff_t *cmd_tvb, unsigned len, uint32_t off)
3115 if (!off && len >= 4)
3116 proto_tree_add_item(grp, hf_nvme_get_logpage_lba_status_lslplen, cmd_tvb, off, 4, ENC_LITTLE_ENDIAN);
3117 if (off <= 4 && (8 - off) <= len)
3118 proto_tree_add_item(grp, hf_nvme_get_logpage_lba_status_nlslne, cmd_tvb, 4-off, 4, ENC_LITTLE_ENDIAN);
3119 if (off <= 8 && (12 - off) <= len)
3120 proto_tree_add_item(grp, hf_nvme_get_logpage_lba_status_estulb, cmd_tvb, 8-off, 4, ENC_LITTLE_ENDIAN);
3121 if (off <= 12 && (14 - off) <= len)
3122 proto_tree_add_item(grp, hf_nvme_get_logpage_lba_status_rsvd, cmd_tvb, 12-off, 2, ENC_LITTLE_ENDIAN);
3123 if (off <= 14 && (16 - off) <= len)
3124 proto_tree_add_item(grp, hf_nvme_get_logpage_lba_status_lsgc, cmd_tvb, 14-off, 2, ENC_LITTLE_ENDIAN);
3125 if (off <= 16 && (20 - off) <= len)
3126 proto_tree_add_item(grp, hf_nvme_get_logpage_lba_status_nel, cmd_tvb, 16-off, len - (16-off), ENC_NA);
3129 static unsigned dissect_nvme_get_logpage_lba_status_lba_range(proto_tree *grp, tvbuff_t *cmd_tvb, unsigned len, uint32_t poff)
3131 uint32_t slen;
3132 proto_item *ti;
3133 unsigned done;
3135 if (len >= 16) {
3136 slen = tvb_get_uint8(cmd_tvb, 4);
3137 if (!slen || slen == 0xffffffff)
3138 slen = 16;
3139 else
3140 slen = 16 * (slen + 1);
3141 if (slen > len)
3142 slen = len;
3143 } else {
3144 slen = len;
3146 ti = proto_tree_add_item(grp, hf_nvme_get_logpage_lba_status_nel_ne, cmd_tvb, poff, slen, ENC_NA);
3147 grp = proto_item_add_subtree(ti, ett_data);
3149 if (len >= 4)
3150 proto_tree_add_item(grp, hf_nvme_get_logpage_lba_status_nel_ne_neid, cmd_tvb, poff, 4, ENC_LITTLE_ENDIAN);
3151 if (len >= 8)
3152 proto_tree_add_item(grp, hf_nvme_get_logpage_lba_status_nel_ne_nlrd, cmd_tvb, poff+4, 4, ENC_LITTLE_ENDIAN);
3153 if (len >= 9)
3154 proto_tree_add_item(grp, hf_nvme_get_logpage_lba_status_nel_ne_ratype, cmd_tvb, poff+8, 1, ENC_LITTLE_ENDIAN);
3155 if (len >= 16)
3156 proto_tree_add_item(grp, hf_nvme_get_logpage_lba_status_nel_ne_rsvd, cmd_tvb, poff+9, 7, ENC_NA);
3158 if (len <= 16)
3159 return len;
3161 len -= 16;
3162 poff += 16;
3163 done = 16;
3164 while (len >= 8) {
3165 ti = proto_tree_add_item(grp, hf_nvme_get_logpage_lba_status_nel_ne_rd, cmd_tvb, poff, len >= 16 ? 16 : len, ENC_NA);
3166 grp = proto_item_add_subtree(ti, ett_data);
3167 proto_tree_add_item(grp, hf_nvme_get_logpage_lba_status_nel_ne_rd_rslba, cmd_tvb, poff, 8, ENC_LITTLE_ENDIAN);
3168 if (len >= 12)
3169 proto_tree_add_item(grp, hf_nvme_get_logpage_lba_status_nel_ne_rd_rnlb, cmd_tvb, poff+8, 4, ENC_LITTLE_ENDIAN);
3170 if (len >= 16)
3171 proto_tree_add_item(grp, hf_nvme_get_logpage_lba_status_nel_ne_rd_rsvd, cmd_tvb, poff+12, 4, ENC_LITTLE_ENDIAN);
3172 if (len >= 16) {
3173 done += 16;
3174 poff += 16;
3175 } else {
3176 done += len;
3177 len = 0;
3180 return done;
3183 static void dissect_nvme_get_logpage_lba_status_resp(proto_item *ti, tvbuff_t *cmd_tvb, struct nvme_cmd_ctx *cmd_ctx, unsigned tr_off, unsigned len)
3185 uint32_t off = cmd_ctx->cmd_ctx.get_logpage.off & 0xffffffff; /* need unsigned type to silence clang-11 errors */
3186 proto_tree *grp = NULL;
3187 unsigned poff = 0;
3189 off += tr_off;
3190 if (off < 16) {
3191 grp = proto_item_add_subtree(ti, ett_data);
3192 dissect_nvme_get_logpage_lba_status_resp_header(grp, cmd_tvb, len, off);
3193 poff = 16 - off;
3194 } else if (off & 15) {
3195 poff = 16 - (off & 15);
3198 if (len < (poff + 8))
3199 return;
3201 if (off >= 16)
3202 grp = proto_item_add_subtree(ti, ett_data);
3204 len -= poff;
3205 ti = proto_tree_add_item(grp, hf_nvme_get_logpage_lba_status_nel, cmd_tvb, poff, len, ENC_NA);
3206 grp = proto_item_add_subtree(ti, ett_data);
3208 while (len >= 8) {
3209 unsigned done = dissect_nvme_get_logpage_lba_status_lba_range(grp, cmd_tvb, len, poff);
3210 poff += done;
3211 len -= done;
3215 static void dissect_nvme_get_logpage_egroup_aggreg_resp(proto_item *ti, tvbuff_t *cmd_tvb, struct nvme_cmd_ctx *cmd_ctx, unsigned tr_off, unsigned len)
3217 proto_tree *grp;
3218 unsigned poff = 0;
3220 if (!tr_off) {
3221 if (cmd_ctx->cmd_ctx.get_logpage.off < 8) {
3222 poff = 8 - (unsigned)cmd_ctx->cmd_ctx.get_logpage.off;
3223 if (poff > len || (cmd_ctx->cmd_ctx.get_logpage.off && poff == len))
3224 return;
3225 } else if (len < 2) {
3226 return;
3230 len -= poff;
3231 grp = proto_item_add_subtree(ti, ett_data);
3232 if (!(cmd_ctx->cmd_ctx.get_logpage.off + tr_off))
3233 proto_tree_add_item(grp, hf_nvme_get_logpage_egroup_aggreg_ne, cmd_tvb, 0, 8, ENC_LITTLE_ENDIAN);
3234 while (len >= 2) {
3235 proto_tree_add_item(grp, hf_nvme_get_logpage_egroup_aggreg_eg, cmd_tvb, poff, 2, ENC_LITTLE_ENDIAN);
3236 len -= 2;
3237 poff += 2;
3241 static const value_string rnlpt_tbl[] = {
3242 { 0, "Empty Log Page" },
3243 { 1, "Registration Preempted" },
3244 { 2, "Reservation Released" },
3245 { 3, "Reservation Preempted" },
3246 { 0, NULL}
3249 static void dissect_nvme_get_logpage_reserv_notif_resp(proto_item *ti, tvbuff_t *cmd_tvb, struct nvme_cmd_ctx *cmd_ctx, unsigned len)
3251 uint32_t off = cmd_ctx->cmd_ctx.get_logpage.off & 0xffffffff; /* need unsigned type to silence clang-11 errors */
3252 proto_tree *grp;
3253 unsigned poff = 0;
3255 if (cmd_ctx->cmd_ctx.get_logpage.off > 60)
3256 return; /* max allowed offset is < 60, so we do not loose bits by casting to unsigned type */
3258 grp = proto_item_add_subtree(ti, ett_data);
3259 if (!off && len >= 8)
3260 proto_tree_add_item(grp, hf_nvme_get_logpage_reserv_notif_lpc, cmd_tvb, 0, 8, ENC_LITTLE_ENDIAN);
3261 if (off <= 8 && (9 - off) <= len)
3262 proto_tree_add_item(grp, hf_nvme_get_logpage_reserv_notif_lpt, cmd_tvb, 8-off, 1, ENC_LITTLE_ENDIAN);
3263 if (off <= 9 && (10 - off) <= len)
3264 proto_tree_add_item(grp, hf_nvme_get_logpage_reserv_notif_nalp, cmd_tvb, 9-off, 1, ENC_LITTLE_ENDIAN);
3265 if (off <= 10 && (12 - off) <= len)
3266 proto_tree_add_item(grp, hf_nvme_get_logpage_reserv_notif_rsvd0, cmd_tvb, 10-off, 2, ENC_LITTLE_ENDIAN);
3267 if (off <= 12 && (16 - off) <= len)
3268 proto_tree_add_item(grp, hf_nvme_get_logpage_reserv_notif_nsid, cmd_tvb, 12-off, 4, ENC_LITTLE_ENDIAN);
3269 if (off < 16) {
3270 poff = 16 - off;
3271 if (len <= poff)
3272 return;
3273 len -= poff;
3274 if (len > 48)
3275 len = 48; /* max padding size is 48 */
3276 } else {
3277 if (len > (64 - off))
3278 len = 64 - off; /* max padding size is 48 */
3280 proto_tree_add_item(grp, hf_nvme_get_logpage_reserv_notif_rsvd1, cmd_tvb, poff, len, ENC_NA);
3284 static const value_string san_mrst_tbl[] = {
3285 { 0, "The NVM subsystem has never been sanitized" },
3286 { 1, "The most recent sanitize operation completed successfully" },
3287 { 2, "A sanitize operation is currently in progress" },
3288 { 3, "The most recent sanitize operation failed" },
3289 { 4, "The most recent sanitize operation with No-Deallocate has completed successfully with deallocation of all logical blocks"},
3290 { 0, NULL}
3293 static void dissect_nvme_get_logpage_sanitize_resp(proto_item *ti, tvbuff_t *cmd_tvb, struct nvme_cmd_ctx *cmd_ctx, unsigned len)
3295 uint32_t off = cmd_ctx->cmd_ctx.get_logpage.off & 0xffffffff; /* need unsigned type to silence clang-11 errors */
3296 proto_tree *grp;
3297 unsigned poff = 0;
3299 if (cmd_ctx->cmd_ctx.get_logpage.off > 508)
3300 return; /* max allowed offset is < 508, so we do not loose bits by casting to unsigned type */
3302 grp = proto_item_add_subtree(ti, ett_data);
3303 if (!off && len >= 2)
3304 proto_tree_add_item(grp, hf_nvme_get_logpage_sanitize_sprog, cmd_tvb, 0, 2, ENC_LITTLE_ENDIAN);
3305 if (off <= 2 && (4 - off) <= len)
3306 add_group_mask_entry(cmd_tvb, grp, 2 - off, 2, ASPEC(hf_nvme_get_logpage_sanitize_sstat));
3307 if (off <= 4 && (8 - off) <= len)
3308 proto_tree_add_item(grp, hf_nvme_get_logpage_sanitize_scdw10, cmd_tvb, 4-off, 4, ENC_LITTLE_ENDIAN);
3309 if (off <= 8 && (12 - off) <= len)
3310 proto_tree_add_item(grp, hf_nvme_get_logpage_sanitize_eto, cmd_tvb, 8-off, 4, ENC_LITTLE_ENDIAN);
3311 if (off <= 12 && (16 - off) <= len)
3312 proto_tree_add_item(grp, hf_nvme_get_logpage_sanitize_etbe, cmd_tvb, 12-off, 4, ENC_LITTLE_ENDIAN);
3313 if (off <= 16 && (20 - off) <= len)
3314 proto_tree_add_item(grp, hf_nvme_get_logpage_sanitize_etce, cmd_tvb, 16-off, 4, ENC_LITTLE_ENDIAN);
3315 if (off <= 20 && (24 - off) <= len)
3316 proto_tree_add_item(grp, hf_nvme_get_logpage_sanitize_etond, cmd_tvb, 20-off, 4, ENC_LITTLE_ENDIAN);
3317 if (off <= 24 && (28 - off) <= len)
3318 proto_tree_add_item(grp, hf_nvme_get_logpage_sanitize_etbend, cmd_tvb, 24-off, 4, ENC_LITTLE_ENDIAN);
3319 if (off <= 28 && (32 - off) <= len)
3320 proto_tree_add_item(grp, hf_nvme_get_logpage_sanitize_etcend, cmd_tvb, 28-off, 4, ENC_LITTLE_ENDIAN);
3321 if (off < 32) {
3322 poff = 32 - off;
3323 if (poff <= len)
3324 return;
3325 len -= poff;
3326 if (len > (512 - poff))
3327 len = 512 - poff;
3328 } else {
3329 if (len > (512 - off))
3330 len = 512 - off;
3332 proto_tree_add_item(grp, hf_nvme_get_logpage_sanitize_rsvd, cmd_tvb, poff, len, ENC_NA);
3335 static void dissect_nvme_get_logpage_resp(tvbuff_t *cmd_tvb, proto_tree *cmd_tree, struct nvme_cmd_ctx *cmd_ctx, unsigned off, unsigned len)
3337 proto_item *ti = proto_tree_add_bytes_format_value(cmd_tree, hf_nvme_gen_data, cmd_tvb, 0, len, NULL,
3338 "NVMe Get Log Page (%s)", get_logpage_name(cmd_ctx->cmd_ctx.get_logpage.lid));
3339 switch(cmd_ctx->cmd_ctx.get_logpage.lid) {
3340 case 0x70:
3341 dissect_nvme_get_logpage_ify_resp(ti, cmd_tvb, cmd_ctx, off, len); break;
3342 case 0x1:
3343 /* fits smallest mtu */
3344 dissect_nvme_get_logpage_err_inf_resp(ti, cmd_tvb, cmd_ctx, len); break;
3345 case 0x2:
3346 /* fits smallest mtu */
3347 dissect_nvme_get_logpage_smart_resp(ti, cmd_tvb, cmd_ctx, len); break;
3348 case 0x3:
3349 /* fits smallest mtu */
3350 dissect_nvme_get_logpage_fw_slot_resp(ti, cmd_tvb, cmd_ctx, len); break;
3351 case 0x4:
3352 /* decodes array of integers, does need to know packet offset */
3353 dissect_nvme_get_logpage_changed_nslist_resp(ti, cmd_tvb, len); break;
3354 case 0x5:
3355 dissect_nvme_get_logpage_cmd_sup_and_eff_resp(ti, cmd_tvb, cmd_ctx, off, len); break;
3356 case 0x6:
3357 dissect_nvme_get_logpage_selftest_resp(ti, cmd_tvb, cmd_ctx, off, len); break;
3358 case 0x7:
3359 case 0x8:
3360 dissect_nvme_get_logpage_telemetry_resp(ti, cmd_tvb, cmd_ctx, off, len); break;
3361 case 0x9:
3362 /* fits smallest mtu */
3363 dissect_nvme_get_logpage_egroup_resp(ti, cmd_tvb, cmd_ctx, len); break;
3364 case 0xA:
3365 /* fits smallest mtu */
3366 dissect_nvme_get_logpage_pred_lat_resp(ti, cmd_tvb, cmd_ctx, len); break;
3367 case 0xB:
3368 dissect_nvme_get_logpage_pred_lat_aggreg_resp(ti, cmd_tvb, cmd_ctx, off, len); break;
3369 case 0xC:
3370 dissect_nvme_get_logpage_ana_resp(ti, cmd_tvb, cmd_ctx, off, len); break;
3371 case 0xE:
3372 dissect_nvme_get_logpage_lba_status_resp(ti, cmd_tvb, cmd_ctx, off, len); break;
3373 case 0xF:
3374 dissect_nvme_get_logpage_egroup_aggreg_resp(ti, cmd_tvb, cmd_ctx, off, len); break;
3375 case 0x80:
3376 /* fits smallest mtu */
3377 dissect_nvme_get_logpage_reserv_notif_resp(ti, cmd_tvb, cmd_ctx, len); break;
3378 case 0x81:
3379 /* fits smallest mtu */
3380 dissect_nvme_get_logpage_sanitize_resp(ti, cmd_tvb, cmd_ctx, len); break;
3381 default:
3382 return;
3386 static void dissect_nvme_get_logpage_cmd(tvbuff_t *cmd_tvb, proto_tree *cmd_tree,
3387 struct nvme_cmd_ctx *cmd_ctx)
3389 proto_item *ti;
3390 unsigned val;
3392 cmd_ctx->cmd_ctx.get_logpage.lid = tvb_get_uint8(cmd_tvb, 40);
3393 cmd_ctx->cmd_ctx.get_logpage.lsp = tvb_get_uint8(cmd_tvb, 41) & 0xf;
3394 cmd_ctx->cmd_ctx.get_logpage.lsi = tvb_get_uint16(cmd_tvb, 46, ENC_LITTLE_ENDIAN);
3395 cmd_ctx->cmd_ctx.get_logpage.uid_idx = tvb_get_uint8(cmd_tvb, 56) & 0x7f;
3397 add_group_mask_entry(cmd_tvb, cmd_tree, 40, 4, ASPEC(hf_nvme_get_logpage_dword10));
3398 ti = proto_tree_add_item_ret_uint(cmd_tree, hf_nvme_get_logpage_numd, cmd_tvb, 42, 4, ENC_LITTLE_ENDIAN, &val);
3399 proto_item_append_text(ti, " (%"PRIu64" bytes)", ((uint64_t)(val+1)) * 4);
3401 add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_get_logpage_dword11));
3403 proto_tree_add_item_ret_uint64(cmd_tree, hf_nvme_get_logpage_lpo, cmd_tvb, 48, 8, ENC_LITTLE_ENDIAN, &cmd_ctx->cmd_ctx.get_logpage.off);
3404 cmd_ctx->cmd_ctx.get_logpage.off &= (~((uint64_t)3)); /* clear two low bits, the target shall either deny the command or clear the bits */
3406 proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword13, cmd_tvb, 52, 4, ENC_LITTLE_ENDIAN);
3408 add_group_mask_entry(cmd_tvb, cmd_tree, 56, 4, ASPEC(hf_nvme_get_logpage_dword14));
3410 proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword15, cmd_tvb, 60, 4, ENC_LITTLE_ENDIAN);
3413 typedef enum {
3414 F_ARBITRATION = 0x01,
3415 F_POWER_MGMT = 0x02,
3416 F_LBA_RANGE_TYPE = 0x03,
3417 F_TEMP_THRESHOLD = 0x04,
3418 F_ERROR_RECOVERY = 0x05,
3419 F_VOLATILE_WC = 0x06,
3420 F_NUM_OF_QUEUES = 0x07,
3421 F_IRQ_COALESCING = 0x08,
3422 F_IRQ_VECTOR_CONF = 0x09,
3423 F_WRITE_ATOM_NORM = 0x0A,
3424 F_ASYNC_EVENT_CONF = 0x0B,
3425 F_AUTO_PS_TRANSITION = 0x0C,
3426 F_HOST_MEM_BUF = 0x0D,
3427 F_TIMESTAMP = 0x0E,
3428 F_KA_TIMER = 0x0F,
3429 F_HOST_CNTL_THERM_MGMT = 0x10,
3430 F_NO_POWER_STATE_CONF = 0x11,
3431 F_READ_REC_LEVEL_CONF = 0x12,
3432 F_PRED_LAT_MODE_CONF = 0x13,
3433 F_PRED_LAT_MODE_WIND = 0x14,
3434 F_LBA_ST_INF_REP_INT = 0x15,
3435 F_HOST_BEHV_SUPPORT = 0x16,
3436 F_SANITIZE_CON = 0x17,
3437 F_END_GROUP_EV_CONF = 0x18,
3438 F_SW_PR_MARKER = 0x80,
3439 F_HOST_ID = 0x81,
3440 F_RSRV_NOT_MASK = 0x82,
3441 F_RSRV_PRST = 0x83,
3442 F_NS_WRITE_CONF = 0x84,
3443 } nvme_setf_t;
3446 static const value_string fid_table[] = {
3447 { F_ARBITRATION, "Arbitration" },
3448 { F_POWER_MGMT, "Power Management" },
3449 { F_LBA_RANGE_TYPE, "LBA Range Type" },
3450 { F_TEMP_THRESHOLD, "Temperature Threshold" },
3451 { F_ERROR_RECOVERY, "Error Recovery" },
3452 { F_VOLATILE_WC, "Volatile Write Cache" },
3453 { F_NUM_OF_QUEUES, "Number of Queues" },
3454 { F_IRQ_COALESCING, "Interrupt Coalescing" },
3455 { F_IRQ_VECTOR_CONF, "Interrupt Vector Configuration" },
3456 { F_WRITE_ATOM_NORM, "Write Atomicity Normal" },
3457 { F_ASYNC_EVENT_CONF, "Asynchronous Event Configuration" },
3458 { F_AUTO_PS_TRANSITION, "Autonomous Power State Transition" },
3459 { F_HOST_MEM_BUF, "Host Memory Buffer" },
3460 { F_TIMESTAMP, "Timestamp" },
3461 { F_KA_TIMER, "Keep Alive Timer" },
3462 { F_HOST_CNTL_THERM_MGMT, "Host Controlled Thermal Management" },
3463 { F_NO_POWER_STATE_CONF, "Non-Operational Power State Config" },
3464 { F_READ_REC_LEVEL_CONF, "Read Recovery Level Config" },
3465 { F_PRED_LAT_MODE_CONF, "Predictable Latency Mode Config" },
3466 { F_PRED_LAT_MODE_WIND, "Predictable Latency Mode Window" },
3467 { F_LBA_ST_INF_REP_INT, "LBA Status Information Report Interval" },
3468 { F_HOST_BEHV_SUPPORT, "Host Behavior Support" },
3469 { F_SANITIZE_CON, "Sanitize Config" },
3470 { F_END_GROUP_EV_CONF, "Endurance Group Event Configuration" },
3471 { F_SW_PR_MARKER, "Software Progress Marker" },
3472 { F_HOST_ID, "Host Identifier" },
3473 { F_RSRV_NOT_MASK, "Reservation Notification Mask" },
3474 { F_RSRV_PRST, "Reservation Persistence" },
3475 { F_NS_WRITE_CONF, "Namespace Write Protection Config" },
3476 { 0, NULL },
3479 static const value_string sel_table[] = {
3480 { 0, "Current" },
3481 { 1, "Default" },
3482 { 2, "Saved" },
3483 { 3, "Supported Capabilities" },
3484 { 0, NULL },
3487 static const value_string sf_tmpsel_table[] = {
3488 { 0x0, "Composite Temperature" },
3489 { 0x1, "Temperature Sensor 1" },
3490 { 0x2, "Temperature Sensor 2" },
3491 { 0x3, "Temperature Sensor 3" },
3492 { 0x4, "Temperature Sensor 4" },
3493 { 0x5, "Temperature Sensor 5" },
3494 { 0x6, "Temperature Sensor 6" },
3495 { 0x7, "Temperature Sensor 7" },
3496 { 0x8, "Temperature Sensor 8" },
3497 { 0xF, "All Temperature Sensors" },
3498 { 0, NULL },
3501 static const value_string sf_thpsel_table[] = {
3502 { 0x0, "Over Temperature Threshold" },
3503 { 0x1, "Under Temperature Threshold" },
3504 { 0x2, "Reserved" },
3505 { 0x3, "Reserved" },
3506 { 0, NULL },
3509 static const value_string sf_ws_table[] = {
3510 { 0x0, "Reserved" },
3511 { 0x1, "Deterministic Window" },
3512 { 0x2, "Non-Deterministic Window" },
3513 { 0x3, "Reserved" },
3514 { 0x4, "Reserved" },
3515 { 0x5, "Reserved" },
3516 { 0x6, "Reserved" },
3517 { 0x7, "Reserved" },
3518 { 0, NULL },
3521 static const value_string sf_wps[] = {
3522 { 0x0, "No Write Protect" },
3523 { 0x1, "Write Protect" },
3524 { 0x2, "Write Protect Until Power Cycle" },
3525 { 0x3, "Permanent Write Protect" },
3526 { 0x4, "Reserved" },
3527 { 0x5, "Reserved" },
3528 { 0x6, "Reserved" },
3529 { 0x7, "Reserved" },
3530 { 0, NULL },
3533 static void add_nvme_queues(char *result, uint32_t val)
3535 snprintf(result, ITEM_LABEL_LENGTH, "%x (%u)", val, val+1);
3538 static void dissect_nvme_set_features_dword11(tvbuff_t *cmd_tvb, proto_tree *cmd_tree, unsigned fid)
3540 switch (fid) {
3541 case F_ARBITRATION: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_set_features_dword11_arb)); break;
3542 case F_POWER_MGMT: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_set_features_dword11_pm)); break;
3543 case F_LBA_RANGE_TYPE: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_set_features_dword11_lbart)); break;
3544 case F_TEMP_THRESHOLD: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_set_features_dword11_tt)); break;
3545 case F_ERROR_RECOVERY: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_set_features_dword11_erec)); break;
3546 case F_VOLATILE_WC: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_set_features_dword11_vwce)); break;
3547 case F_NUM_OF_QUEUES: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_set_features_dword11_nq)); break;
3548 case F_IRQ_COALESCING: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_set_features_dword11_irqc)); break;
3549 case F_IRQ_VECTOR_CONF: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_set_features_dword11_irqv)); break;
3550 case F_WRITE_ATOM_NORM: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_set_features_dword11_wan)); break;
3551 case F_ASYNC_EVENT_CONF: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_set_features_dword11_aec)); break;
3552 case F_AUTO_PS_TRANSITION: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_set_features_dword11_apst)); break;
3553 case F_KA_TIMER: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_set_features_dword11_kat)); break;
3554 case F_HOST_CNTL_THERM_MGMT: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_set_features_dword11_hctm)); break;
3555 case F_NO_POWER_STATE_CONF: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_set_features_dword11_nops)); break;
3556 case F_READ_REC_LEVEL_CONF: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_set_features_dword11_rrl)); break;
3557 case F_PRED_LAT_MODE_CONF: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_set_features_dword11_plmc)); break;
3558 case F_PRED_LAT_MODE_WIND: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_set_features_dword11_plmw)); break;
3559 case F_LBA_ST_INF_REP_INT: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_set_features_dword11_lbasi)); break;
3560 case F_SANITIZE_CON: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_set_features_dword11_san)); break;
3561 case F_END_GROUP_EV_CONF: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_set_features_dword11_eg)); break;
3562 case F_SW_PR_MARKER: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_set_features_dword11_swp)); break;
3563 case F_HOST_ID: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_set_features_dword11_hid)); break;
3564 case F_RSRV_NOT_MASK: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_set_features_dword11_rsrvn)); break;
3565 case F_RSRV_PRST: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_set_features_dword11_rsrvp)); break;
3566 case F_NS_WRITE_CONF: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_set_features_dword11_nswp)); break;
3567 default: proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword11, cmd_tvb, 44, 4, ENC_LITTLE_ENDIAN);
3571 static void dissect_nvme_set_features_dword12(tvbuff_t *cmd_tvb, proto_tree *cmd_tree, unsigned fid)
3573 switch (fid) {
3574 case F_READ_REC_LEVEL_CONF: add_group_mask_entry(cmd_tvb, cmd_tree, 48, 4, ASPEC(hf_nvme_cmd_set_features_dword12_rrl)); break;
3575 case F_PRED_LAT_MODE_CONF: add_group_mask_entry(cmd_tvb, cmd_tree, 48, 4, ASPEC(hf_nvme_cmd_set_features_dword12_plmc)); break;
3576 case F_PRED_LAT_MODE_WIND: add_group_mask_entry(cmd_tvb, cmd_tree, 48, 4, ASPEC(hf_nvme_cmd_set_features_dword12_plmw)); break;
3577 default: proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword12, cmd_tvb, 48, 4, ENC_LITTLE_ENDIAN);
3581 static void dissect_nvme_set_features_cmd(tvbuff_t *cmd_tvb, proto_tree *cmd_tree,
3582 struct nvme_cmd_ctx *cmd_ctx)
3584 cmd_ctx->cmd_ctx.set_features.fid = tvb_get_uint8(cmd_tvb, 40);
3585 add_group_mask_entry(cmd_tvb, cmd_tree, 40, 4, ASPEC(hf_nvme_set_features_dword10));
3586 dissect_nvme_set_features_dword11(cmd_tvb, cmd_tree, cmd_ctx->cmd_ctx.set_features.fid);
3587 dissect_nvme_set_features_dword12(cmd_tvb, cmd_tree, cmd_ctx->cmd_ctx.set_features.fid);
3588 proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword13, cmd_tvb, 52, 4, ENC_LITTLE_ENDIAN);
3589 add_group_mask_entry(cmd_tvb, cmd_tree, 56, 4, ASPEC(hf_nvme_set_features_dword14));
3590 proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword15, cmd_tvb, 60, 4, ENC_LITTLE_ENDIAN);
3593 static void dissect_nvme_get_features_cmd(tvbuff_t *cmd_tvb, proto_tree *cmd_tree,
3594 struct nvme_cmd_ctx *cmd_ctx)
3596 cmd_ctx->cmd_ctx.set_features.fid = tvb_get_uint8(cmd_tvb, 40);
3597 add_group_mask_entry(cmd_tvb, cmd_tree, 40, 4, ASPEC(hf_nvme_get_features_dword10));
3598 switch(cmd_ctx->cmd_ctx.set_features.fid) {
3599 case F_READ_REC_LEVEL_CONF: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_get_features_dword11_rrl)); break;
3600 case F_PRED_LAT_MODE_CONF: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_get_features_dword11_plmc)); break;
3601 case F_PRED_LAT_MODE_WIND: add_group_mask_entry(cmd_tvb, cmd_tree, 44, 4, ASPEC(hf_nvme_cmd_get_features_dword11_plmw)); break;
3602 default: proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword11, cmd_tvb, 44, 4, ENC_LITTLE_ENDIAN); break;
3604 proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword12, cmd_tvb, 48, 4, ENC_LITTLE_ENDIAN);
3605 proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword13, cmd_tvb, 52, 4, ENC_LITTLE_ENDIAN);
3606 add_group_mask_entry(cmd_tvb, cmd_tree, 56, 4, ASPEC(hf_nvme_get_features_dword14));
3607 proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword15, cmd_tvb, 60, 4, ENC_LITTLE_ENDIAN);
3610 static void dissect_nvme_rw_cmd(tvbuff_t *cmd_tvb, proto_tree *cmd_tree)
3612 proto_item *ti, *dsm_tree, *item;
3613 uint8_t val;
3615 dissect_nvme_rwc_common_word_10_11_12_14_15(cmd_tvb, cmd_tree);
3617 ti = proto_tree_add_item(cmd_tree, hf_nvme_cmd_dsm, cmd_tvb, 52,
3618 1, ENC_NA);
3619 dsm_tree = proto_item_add_subtree(ti, ett_data);
3621 val = tvb_get_uint8(cmd_tvb, 52) & 0x0f;
3622 item = proto_tree_add_item(dsm_tree, hf_nvme_cmd_dsm_access_freq, cmd_tvb,
3623 52, 1, ENC_LITTLE_ENDIAN);
3624 proto_item_append_text(item, " %s",
3625 val_to_str_const(val, dsm_acc_freq_tbl, "Reserved"));
3627 val = (tvb_get_uint8(cmd_tvb, 52) & 0x30) >> 4;
3628 item = proto_tree_add_item(dsm_tree, hf_nvme_cmd_dsm_access_lat, cmd_tvb,
3629 52, 1, ENC_LITTLE_ENDIAN);
3630 proto_item_append_text(item, " %s",
3631 val_to_str_const(val, dsm_acc_lat_tbl, "Reserved"));
3633 proto_tree_add_item(dsm_tree, hf_nvme_cmd_dsm_seq_req, cmd_tvb,
3634 52, 1, ENC_LITTLE_ENDIAN);
3635 proto_tree_add_item(dsm_tree, hf_nvme_cmd_dsm_incompressible, cmd_tvb,
3636 52, 1, ENC_LITTLE_ENDIAN);
3637 proto_tree_add_item(cmd_tree, hf_nvme_cmd_rsvd3, cmd_tvb,
3638 53, 3, ENC_NA);
3641 static const value_string sf_lbart_type_table[] = {
3642 { 0x0, "General Purpose" },
3643 { 0x1, "Filesystem" },
3644 { 0x2, "RAID" },
3645 { 0x3, "Cache" },
3646 { 0x4, "Swap" },
3647 { 0, NULL },
3650 static void dissect_nvme_set_features_transfer_lbart(tvbuff_t *tvb, proto_tree *tree, unsigned off, unsigned len)
3652 proto_tree *grp;
3653 proto_item *ti;
3654 unsigned done = 0;
3655 while (len >= 64) {
3656 ti = proto_tree_add_bytes_format_value(tree, hf_nvme_set_features_tr_lbart, tvb, 0, 64, NULL, "LBA Range Structure %u", (done + off) / 64);
3657 grp = proto_item_add_subtree(ti, ett_data);
3658 proto_tree_add_item(grp, hf_nvme_set_features_tr_lbart_type, tvb, done, 1, ENC_LITTLE_ENDIAN);
3659 add_group_mask_entry(tvb, grp, done+1, 1, ASPEC(hf_nvme_set_features_tr_lbart_attr));
3660 proto_tree_add_item(grp, hf_nvme_set_features_tr_lbart_rsvd0, tvb, done+2, 14, ENC_NA);
3661 proto_tree_add_item(grp, hf_nvme_set_features_tr_lbart_slba, tvb, done+16, 8, ENC_LITTLE_ENDIAN);
3662 proto_tree_add_item(grp, hf_nvme_set_features_tr_lbart_nlb, tvb, done+24, 8, ENC_LITTLE_ENDIAN);
3663 proto_tree_add_item(grp, hf_nvme_set_features_tr_lbart_guid, tvb, done+32, 16, ENC_NA);
3664 proto_tree_add_item(grp, hf_nvme_set_features_tr_lbart_rsvd1, tvb, done+48, 16, ENC_NA);
3665 len -= 64;
3666 done += 64;
3670 static void dissect_nvme_set_features_transfer_apst(tvbuff_t *tvb, proto_tree *tree, unsigned len)
3672 unsigned off = 0;
3673 while (len >= 8) {
3674 add_group_mask_entry(tvb, tree, off, 8, ASPEC(hf_nvme_set_features_tr_apst));
3675 len -= 8;
3676 off += 8;
3680 static void dissect_nvme_set_features_transfer_tst(tvbuff_t *tvb, proto_tree *tree)
3682 add_group_mask_entry(tvb, tree, 0, 8, ASPEC(hf_nvme_set_features_tr_tst));
3686 static void dissect_nvme_set_features_transfer_plmc(tvbuff_t *tvb, proto_tree *tree, unsigned len)
3688 proto_tree *grp;
3689 proto_item *ti;
3691 ti = proto_tree_add_item(tree, hf_nvme_set_features_tr_plmc, tvb, 0, len, ENC_NA);
3692 grp = proto_item_add_subtree(ti, ett_data);
3693 add_group_mask_entry(tvb, grp, 0, 2, ASPEC(hf_nvme_set_features_tr_plmc_ee));
3694 proto_tree_add_item(grp, hf_nvme_set_features_tr_plmc_rsvd0, tvb, 2, 30, ENC_NA);
3695 proto_tree_add_item(grp, hf_nvme_set_features_tr_plmc_dtwinrt, tvb, 32, 8, ENC_LITTLE_ENDIAN);
3696 proto_tree_add_item(grp, hf_nvme_set_features_tr_plmc_dtwinwt, tvb, 40, 8, ENC_LITTLE_ENDIAN);
3697 proto_tree_add_item(grp, hf_nvme_set_features_tr_plmc_dtwintt, tvb, 48, 8, ENC_LITTLE_ENDIAN);
3698 proto_tree_add_item(grp, hf_nvme_set_features_tr_plmc_rsvd1, tvb, 56, len-56, ENC_NA);
3701 static void dissect_nvme_set_features_transfer_hbs(tvbuff_t *tvb, proto_tree *tree, unsigned len)
3703 proto_tree *grp;
3704 proto_item *ti;
3706 ti = proto_tree_add_item(tree, hf_nvme_set_features_tr_hbs, tvb, 0, len, ENC_NA);
3707 grp = proto_item_add_subtree(ti, ett_data);
3708 proto_tree_add_item(grp, hf_nvme_set_features_tr_hbs_acre, tvb, 0, 1, ENC_LITTLE_ENDIAN);
3709 proto_tree_add_item(grp, hf_nvme_set_features_tr_hbs_rsvd, tvb, 1, len-1, ENC_NA);
3712 static void dissect_nvme_set_features_transfer(tvbuff_t *tvb, proto_tree *tree, struct nvme_cmd_ctx *cmd_ctx, unsigned off, unsigned len)
3714 switch(cmd_ctx->cmd_ctx.set_features.fid) {
3715 case F_LBA_RANGE_TYPE:
3716 dissect_nvme_set_features_transfer_lbart(tvb, tree, off, len);
3717 break;
3718 case F_AUTO_PS_TRANSITION:
3719 dissect_nvme_set_features_transfer_apst(tvb, tree, len);
3720 break;
3721 case F_TIMESTAMP:
3722 dissect_nvme_set_features_transfer_tst(tvb, tree);
3723 break;
3724 case F_PRED_LAT_MODE_CONF:
3725 dissect_nvme_set_features_transfer_plmc(tvb, tree, len);
3726 break;
3727 case F_HOST_BEHV_SUPPORT:
3728 dissect_nvme_set_features_transfer_hbs(tvb, tree, len);
3729 break;
3730 default:
3731 proto_tree_add_bytes_format_value(tree, hf_nvme_gen_data, tvb, 0, len, NULL,
3732 (cmd_ctx->opcode == NVME_AQ_OPC_SET_FEATURES) ? "Unhandled Set Features Transfer" : "Unhandled Get Features Transfer");
3733 break;
3738 void nvme_update_transfer_request(packet_info *pinfo, struct nvme_cmd_ctx *cmd, struct nvme_q_ctx *q_ctx)
3740 if (cmd->fabric) {
3741 col_append_sep_fstr(pinfo->cinfo, COL_INFO, "| ", "NVMeOF Data Request for %s",
3742 val_to_str_const(cmd->cmd_ctx.fabric_cmd.fctype, fctype_tbl, "Unknown Command"));
3743 return;
3745 if (!q_ctx->qid) {
3746 col_append_sep_fstr(pinfo->cinfo, COL_INFO, "| ", "NVMeOF Data Request for %s", val_to_str_const(cmd->opcode, aq_opc_tbl, "Unknown Command"));
3747 if (cmd->opcode == NVME_AQ_OPC_IDENTIFY)
3748 col_append_sep_fstr(pinfo->cinfo, COL_INFO, " ", "%s", val_to_str_const(cmd->cmd_ctx.cmd_identify.cns, cns_table, "Unknown"));
3749 else if (cmd->opcode == NVME_AQ_OPC_GET_LOG_PAGE)
3750 col_append_sep_fstr(pinfo->cinfo, COL_INFO, " ", "%s", get_logpage_name(cmd->cmd_ctx.get_logpage.lid));
3751 } else {
3752 col_append_sep_fstr(pinfo->cinfo, COL_INFO, "| ", "NVMeOF Data Request for %s", val_to_str_const(cmd->opcode, ioq_opc_tbl, "Unknown Command"));
3756 void
3757 dissect_nvme_data_response(tvbuff_t *nvme_tvb, packet_info *pinfo, proto_tree *root_tree,
3758 struct nvme_q_ctx *q_ctx, struct nvme_cmd_ctx *cmd_ctx, unsigned len, bool is_inline)
3760 proto_tree *cmd_tree;
3761 proto_item *ti;
3762 const uint8_t *str_opcode;
3763 uint32_t off;
3765 off = (PINFO_FD_VISITED(pinfo)) ? nvme_lookup_data_tr_off(q_ctx, pinfo->num) : cmd_ctx->tr_bytes;
3767 col_set_str(pinfo->cinfo, COL_PROTOCOL, "NVMe");
3768 ti = proto_tree_add_item(root_tree, proto_nvme, nvme_tvb, 0,
3769 len, ENC_NA);
3770 cmd_tree = proto_item_add_subtree(ti, ett_data);
3771 if (q_ctx->qid) { //IOQ
3772 str_opcode = val_to_str_const(cmd_ctx->opcode, ioq_opc_tbl,
3773 "Unknown Command");
3774 } else { //AQ
3775 str_opcode = val_to_str_const(cmd_ctx->opcode, aq_opc_tbl,
3776 "Unknown Command");
3777 switch (cmd_ctx->opcode) {
3778 case NVME_AQ_OPC_IDENTIFY:
3779 dissect_nvme_identify_resp(nvme_tvb, cmd_tree, cmd_ctx, off, len);
3780 break;
3781 case NVME_AQ_OPC_GET_LOG_PAGE:
3782 dissect_nvme_get_logpage_resp(nvme_tvb, cmd_tree, cmd_ctx, off, len);
3783 break;
3785 case NVME_AQ_OPC_SET_FEATURES:
3786 case NVME_AQ_OPC_GET_FEATURES:
3787 dissect_nvme_set_features_transfer(nvme_tvb, cmd_tree, cmd_ctx, off, len);
3788 break;
3790 default:
3791 proto_tree_add_bytes_format_value(cmd_tree, hf_nvme_gen_data,
3792 nvme_tvb, 0, len, NULL,
3793 "%s, offset %u", str_opcode, off);
3794 break;
3797 if (is_inline)
3798 return;
3799 col_append_sep_fstr(pinfo->cinfo, COL_INFO, "| ", "NVMeOF Data for %s", str_opcode);
3800 if (!q_ctx->qid) {
3801 if (cmd_ctx->opcode == NVME_AQ_OPC_IDENTIFY)
3802 col_append_sep_fstr(pinfo->cinfo, COL_INFO, " ", "%s, offset %u", val_to_str_const(cmd_ctx->cmd_ctx.cmd_identify.cns, cns_table, "Unknown"), off);
3803 else if (cmd_ctx->opcode == NVME_AQ_OPC_GET_LOG_PAGE)
3804 col_append_sep_fstr(pinfo->cinfo, COL_INFO, " ", "%s, offset %u", get_logpage_name(cmd_ctx->cmd_ctx.get_logpage.lid), off);
3805 } else {
3806 col_append_sep_fstr(pinfo->cinfo, COL_INFO, ", ", "offset %u", off);
3810 static void add_nvme_qid(char *result, uint32_t val)
3812 snprintf(result, ITEM_LABEL_LENGTH, "%x (%s)", val, val ? "IOQ" : "AQ");
3815 static void add_zero_base(char *result, uint32_t val)
3817 snprintf(result, ITEM_LABEL_LENGTH, "%u", val+1);
3820 static
3821 void dissect_nvmeof_fabric_connect_cmd(proto_tree *cmd_tree, packet_info *pinfo, tvbuff_t *cmd_tvb,
3822 struct nvme_q_ctx *q_ctx, struct nvme_cmd_ctx *cmd, unsigned off)
3824 uint32_t qid;
3826 proto_tree_add_item(cmd_tree, hf_nvmeof_cmd_connect_rsvd1, cmd_tvb,
3827 5+off, 19, ENC_NA);
3828 dissect_nvme_cmd_sgl(cmd_tvb, cmd_tree, hf_nvmeof_cmd_connect_sgl1,
3829 q_ctx, cmd, off, PINFO_FD_VISITED(pinfo));
3830 proto_tree_add_item(cmd_tree, hf_nvmeof_cmd_connect_recfmt, cmd_tvb,
3831 40+off, 2, ENC_LITTLE_ENDIAN);
3832 proto_tree_add_item_ret_uint(cmd_tree, hf_nvmeof_cmd_connect_qid, cmd_tvb,
3833 42+off, 2, ENC_LITTLE_ENDIAN, &qid);
3834 cmd->cmd_ctx.fabric_cmd.cnct.qid = qid;
3835 proto_tree_add_item(cmd_tree, hf_nvmeof_cmd_connect_sqsize, cmd_tvb,
3836 44+off, 2, ENC_LITTLE_ENDIAN);
3838 add_group_mask_entry(cmd_tvb, cmd_tree, 46+off, 1, ASPEC(hf_nvmeof_cmd_connect_cattr));
3839 proto_tree_add_item(cmd_tree, hf_nvmeof_cmd_connect_rsvd2, cmd_tvb,
3840 47+off, 1, ENC_NA);
3841 proto_tree_add_item(cmd_tree, hf_nvmeof_cmd_connect_kato, cmd_tvb,
3842 48+off, 4, ENC_LITTLE_ENDIAN);
3843 proto_tree_add_item(cmd_tree, hf_nvmeof_cmd_connect_rsvd3, cmd_tvb,
3844 52+off, 12, ENC_NA);
3847 static
3848 void dissect_nvmeof_fabric_auth_cmd(proto_tree *cmd_tree, packet_info *pinfo, tvbuff_t *cmd_tvb,
3849 struct nvme_q_ctx *q_ctx, struct nvme_cmd_ctx *cmd, unsigned off)
3851 proto_tree_add_item(cmd_tree, hf_nvmeof_cmd_auth_rsdv1, cmd_tvb,
3852 5+off, 19, ENC_NA);
3853 dissect_nvme_cmd_sgl(cmd_tvb, cmd_tree, hf_nvmeof_cmd_auth_sgl1,
3854 q_ctx, cmd, off, PINFO_FD_VISITED(pinfo));
3855 proto_tree_add_item(cmd_tree, hf_nvmeof_cmd_auth_rsdv2, cmd_tvb,
3856 40+off, 1, ENC_LITTLE_ENDIAN);
3857 proto_tree_add_item(cmd_tree, hf_nvmeof_cmd_auth_spsp0, cmd_tvb,
3858 41+off, 1, ENC_LITTLE_ENDIAN);
3859 proto_tree_add_item(cmd_tree, hf_nvmeof_cmd_auth_spsp1, cmd_tvb,
3860 42+off, 1, ENC_LITTLE_ENDIAN);
3861 proto_tree_add_item(cmd_tree, hf_nvmeof_cmd_auth_secp, cmd_tvb,
3862 43+off, 1, ENC_LITTLE_ENDIAN);
3863 proto_tree_add_item(cmd_tree, hf_nvmeof_cmd_auth_al, cmd_tvb,
3864 44+off, 4, ENC_LITTLE_ENDIAN);
3865 proto_tree_add_item(cmd_tree, hf_nvmeof_cmd_auth_rsdv3, cmd_tvb,
3866 48+off, 16, ENC_NA);
3869 static void dissect_nvme_fabric_disconnect_cmd(proto_tree *cmd_tree, tvbuff_t *cmd_tvb, unsigned off)
3871 proto_tree_add_item(cmd_tree, hf_nvmeof_cmd_disconnect_rsvd0, cmd_tvb,
3872 5+off, 35, ENC_NA);
3873 proto_tree_add_item(cmd_tree, hf_nvmeof_cmd_disconnect_recfmt, cmd_tvb,
3874 40+off, 2, ENC_LITTLE_ENDIAN);
3875 proto_tree_add_item(cmd_tree, hf_nvmeof_cmd_disconnect_rsvd1, cmd_tvb,
3876 42+off, 22, ENC_NA);
3879 static void dissect_nvme_fabric_prop_cmd_common(proto_tree *cmd_tree, tvbuff_t *cmd_tvb, unsigned off)
3881 proto_tree_add_item(cmd_tree, hf_nvmeof_cmd_prop_get_set_rsvd0, cmd_tvb,
3882 5+off, 35, ENC_NA);
3884 add_group_mask_entry(cmd_tvb, cmd_tree, 40+off, 1, ASPEC(hf_nvmeof_cmd_prop_get_set_attrib));
3886 proto_tree_add_item(cmd_tree, hf_nvmeof_cmd_prop_get_set_rsvd1, cmd_tvb,
3887 41+off, 3, ENC_NA);
3889 proto_tree_add_item(cmd_tree, hf_nvmeof_cmd_prop_get_set_offset, cmd_tvb,
3890 44+off, 4, ENC_LITTLE_ENDIAN);
3893 static void dissect_nvmeof_fabric_prop_get_cmd(proto_tree *cmd_tree, tvbuff_t *cmd_tvb, struct nvme_cmd_ctx *cmd, unsigned off)
3895 cmd->cmd_ctx.fabric_cmd.prop_get.offset = tvb_get_uint8(cmd_tvb, 44+off);
3896 dissect_nvme_fabric_prop_cmd_common(cmd_tree, cmd_tvb, off);
3897 proto_tree_add_item(cmd_tree, hf_nvmeof_cmd_prop_get_rsvd2, cmd_tvb,
3898 48+off, 16, ENC_NA);
3901 static void add_500ms_units(char *result, uint32_t val)
3903 snprintf(result, ITEM_LABEL_LENGTH, "%x (%u ms)", val, val * 500);
3906 static void add_ccap_css(char *result, uint32_t val)
3908 if (val & 0x1)
3909 snprintf(result, ITEM_LABEL_LENGTH, "%x (NVM IO Command Set)", val);
3910 else if (val & 0x80)
3911 snprintf(result, ITEM_LABEL_LENGTH, "%x (Admin Command Set Only)", val);
3912 else
3913 snprintf(result, ITEM_LABEL_LENGTH, "%x (Reserved)", val);
3916 static void dissect_nvmeof_fabric_prop_data(proto_tree *tree, tvbuff_t *tvb, unsigned off, unsigned prop_off, uint8_t attr)
3918 proto_item *ti, *grp;
3919 ti = proto_tree_add_item(tree, hf_nvmeof_prop_get_set_data, tvb, off, 8, ENC_NA);
3920 grp = proto_item_add_subtree(ti, ett_data);
3921 switch(prop_off) {
3922 case 0x0: add_group_mask_entry(tvb, grp, off, 8, ASPEC(hf_nvmeof_prop_get_ccap)); attr=1; break;
3923 case 0x8: add_group_mask_entry(tvb, grp, off, 4, ASPEC(hf_nvmeof_prop_get_vs)); attr=0; break;
3924 case 0x14: add_group_mask_entry(tvb, grp, off, 4, ASPEC(hf_nvmeof_prop_get_set_cc)); attr=0; break;
3925 case 0x1c: add_group_mask_entry(tvb, grp, off, 4, ASPEC(hf_nvmeof_prop_get_set_csts)); attr=0; break;
3926 case 0x20: add_group_mask_entry(tvb, grp, off, 4, ASPEC(hf_nvmeof_prop_get_set_nssr)); attr=0; break;
3927 default:
3929 if (attr == 0)
3930 proto_tree_add_item(grp, hf_nvmeof_prop_get_set_data_4B, tvb,
3931 off, 4, ENC_LITTLE_ENDIAN);
3932 else
3933 proto_tree_add_item(grp, hf_nvmeof_prop_get_set_data_8B, tvb,
3934 off, 8, ENC_LITTLE_ENDIAN);
3935 break;
3938 if (attr == 0)
3939 proto_tree_add_item(grp, hf_nvmeof_prop_get_set_data_4B_rsvd, tvb,
3940 off+4, 4, ENC_LITTLE_ENDIAN);
3942 static void dissect_nvmeof_fabric_prop_set_cmd(proto_tree *cmd_tree, tvbuff_t *cmd_tvb, struct nvme_cmd_ctx *cmd, unsigned off)
3944 uint8_t attr;
3945 uint32_t prop_off;
3947 dissect_nvme_fabric_prop_cmd_common(cmd_tree, cmd_tvb, off);
3948 attr = tvb_get_uint8(cmd_tvb, 40+off) & 0x7;
3949 prop_off = tvb_get_uint32(cmd_tvb, 44+off, ENC_LITTLE_ENDIAN);
3950 cmd->cmd_ctx.fabric_cmd.prop_get.offset = prop_off;
3951 dissect_nvmeof_fabric_prop_data(cmd_tree, cmd_tvb, 48+off, prop_off, attr);
3952 proto_tree_add_item(cmd_tree, hf_nvmeof_cmd_prop_set_rsvd, cmd_tvb,
3953 56+off, 8, ENC_NA);
3956 static void dissect_nvmeof_fabric_generic_cmd(proto_tree *cmd_tree, tvbuff_t *cmd_tvb, unsigned off)
3958 proto_tree_add_item(cmd_tree, hf_nvmeof_cmd_generic_rsvd1, cmd_tvb,
3959 5+off, 35, ENC_NA);
3960 proto_tree_add_item(cmd_tree, hf_nvmeof_cmd_generic_field, cmd_tvb,
3961 40+off, 24, ENC_NA);
3964 void dissect_nvmeof_fabric_cmd(tvbuff_t *nvme_tvb, packet_info *pinfo, proto_tree *nvme_tree,
3965 struct nvme_q_ctx *q_ctx, struct nvme_cmd_ctx *cmd, unsigned off, bool link_data_req)
3967 proto_tree *cmd_tree;
3968 proto_item *ti;
3969 uint8_t fctype;
3970 uint32_t prop_off;
3972 fctype = tvb_get_uint8(nvme_tvb, 4+off);
3973 cmd->cmd_ctx.fabric_cmd.fctype = fctype;
3975 ti = proto_tree_add_item(nvme_tree, hf_nvmeof_cmd, nvme_tvb, off,
3976 NVME_CMD_SIZE, ENC_NA);
3977 cmd_tree = proto_item_add_subtree(ti, ett_data);
3979 proto_tree_add_bytes_format(cmd_tree, hf_nvmeof_cmd_opc, nvme_tvb, off, 1, NULL, "Opcode: 0x%x (Fabric Command)",
3980 NVME_FABRIC_OPC);
3981 col_append_sep_fstr(pinfo->cinfo, COL_INFO, "| ", "NVMeOF %s", val_to_str_const(fctype, fctype_tbl, "Unknown Command"));
3982 prop_off = tvb_get_uint32(nvme_tvb, 44+off, ENC_LITTLE_ENDIAN);
3984 cmd->opcode = NVME_FABRIC_OPC;
3985 if (link_data_req)
3986 nvme_publish_to_data_req_link(cmd_tree, nvme_tvb, hf_nvmeof_data_req, cmd);
3987 nvme_publish_to_data_tr_links(cmd_tree, nvme_tvb, hf_nvmeof_data_tr, cmd);
3988 nvme_publish_to_cqe_link(cmd_tree, nvme_tvb, hf_nvmeof_cqe_pkt, cmd);
3990 proto_tree_add_item(cmd_tree, hf_nvmeof_cmd_rsvd, nvme_tvb,
3991 1+off, 1, ENC_NA);
3992 proto_tree_add_item(cmd_tree, hf_nvmeof_cmd_cid, nvme_tvb,
3993 2+off, 2, ENC_LITTLE_ENDIAN);
3995 proto_tree_add_item(cmd_tree, hf_nvmeof_cmd_fctype, nvme_tvb,
3996 4+off, 1, ENC_LITTLE_ENDIAN);
3997 switch(fctype) {
3998 case NVME_FCTYPE_CONNECT:
3999 dissect_nvmeof_fabric_connect_cmd(cmd_tree, pinfo, nvme_tvb, q_ctx, cmd, off);
4000 break;
4001 case NVME_FCTYPE_PROP_GET:
4002 col_append_sep_fstr(pinfo->cinfo, COL_INFO, " ", "%s", val_to_str_const(prop_off, prop_offset_tbl, "Unknown Property"));
4003 dissect_nvmeof_fabric_prop_get_cmd(cmd_tree, nvme_tvb, cmd, off);
4004 break;
4005 case NVME_FCTYPE_PROP_SET:
4006 col_append_sep_fstr(pinfo->cinfo, COL_INFO, " ", "%s", val_to_str_const(prop_off, prop_offset_tbl, "Unknown Property"));
4007 dissect_nvmeof_fabric_prop_set_cmd(cmd_tree, nvme_tvb, cmd, off);
4008 break;
4009 case NVME_FCTYPE_DISCONNECT:
4010 dissect_nvme_fabric_disconnect_cmd(cmd_tree, nvme_tvb, off);
4011 break;
4012 case NVME_FCTYPE_AUTH_RECV:
4013 case NVME_FCTYPE_AUTH_SEND:
4014 dissect_nvmeof_fabric_auth_cmd(cmd_tree, pinfo, nvme_tvb, q_ctx, cmd, off);
4015 break;
4016 default:
4017 dissect_nvmeof_fabric_generic_cmd(cmd_tree, nvme_tvb, off);
4018 break;
4022 static void
4023 dissect_nvmeof_fabric_connect_cmd_data(tvbuff_t *data_tvb, proto_tree *data_tree,
4024 unsigned pkt_off, unsigned off, unsigned len)
4026 if (!off) {
4027 CHECK_STOP_PARSE(0, 16);
4028 proto_tree_add_item(data_tree, hf_nvmeof_cmd_connect_data_hostid, data_tvb,
4029 pkt_off, 16, ENC_NA);
4031 if (off <= 16) {
4032 CHECK_STOP_PARSE(16, 2);
4033 proto_tree_add_item(data_tree, hf_nvmeof_cmd_connect_data_cntlid, data_tvb,
4034 pkt_off + 16 - off, 2, ENC_LITTLE_ENDIAN);
4036 if (off <= 18) {
4037 CHECK_STOP_PARSE(18, 238);
4038 proto_tree_add_item(data_tree, hf_nvmeof_cmd_connect_data_rsvd0, data_tvb,
4039 pkt_off + 18 - off, 238, ENC_NA);
4041 if (off <= 256) {
4042 CHECK_STOP_PARSE(256, 256);
4043 proto_tree_add_item(data_tree, hf_nvmeof_cmd_connect_data_subnqn, data_tvb,
4044 pkt_off + 256 - off, 256, ENC_ASCII | ENC_NA);
4046 if (off <= 512) {
4047 CHECK_STOP_PARSE(512, 256);
4048 proto_tree_add_item(data_tree, hf_nvmeof_cmd_connect_data_hostnqn, data_tvb,
4049 pkt_off + 512 - off, 256, ENC_ASCII | ENC_NA);
4051 if (off <= 768) {
4052 CHECK_STOP_PARSE(768, 256);
4053 proto_tree_add_item(data_tree, hf_nvmeof_cmd_connect_data_rsvd1, data_tvb,
4054 pkt_off + 768 - off, 256, ENC_NA);
4058 void
4059 dissect_nvmeof_cmd_data(tvbuff_t *data_tvb, packet_info *pinfo, proto_tree *data_tree,
4060 unsigned pkt_off, struct nvme_q_ctx *q_ctx, struct nvme_cmd_ctx *cmd, unsigned len)
4062 uint32_t tr_off = (PINFO_FD_VISITED(pinfo)) ? nvme_lookup_data_tr_off(q_ctx, pinfo->num) : cmd->tr_bytes;
4064 if (!pkt_off) {
4065 col_append_sep_fstr(pinfo->cinfo, COL_INFO, "| ", "NVMeoF Data for %s, offset %u",
4066 val_to_str_const(cmd->cmd_ctx.fabric_cmd.fctype, fctype_tbl, "Unknown Command"), tr_off);
4068 if (cmd->cmd_ctx.fabric_cmd.fctype == NVME_FCTYPE_CONNECT && len >= 768)
4069 dissect_nvmeof_fabric_connect_cmd_data(data_tvb, data_tree, pkt_off, tr_off, len);
4072 static void
4073 dissect_nvmeof_status_prop_get(proto_tree *cqe_tree, tvbuff_t *cqe_tvb, struct nvme_cmd_ctx *cmd, unsigned off)
4075 dissect_nvmeof_fabric_prop_data(cqe_tree, cqe_tvb, off, cmd->cmd_ctx.fabric_cmd.prop_get.offset, 1);
4078 static void
4079 dissect_nvmeof_cqe_status_8B(proto_tree *cqe_tree, tvbuff_t *cqe_tvb,
4080 struct nvme_cmd_ctx *cmd, unsigned off)
4082 switch (cmd->cmd_ctx.fabric_cmd.fctype) {
4083 case NVME_FCTYPE_CONNECT:
4084 proto_tree_add_item(cqe_tree, hf_nvmeof_cqe_connect_cntlid, cqe_tvb,
4085 0+off, 2, ENC_LITTLE_ENDIAN);
4086 proto_tree_add_item(cqe_tree, hf_nvmeof_cqe_connect_authreq, cqe_tvb,
4087 2+off, 2, ENC_LITTLE_ENDIAN);
4088 proto_tree_add_item(cqe_tree, hf_nvmeof_cqe_connect_rsvd, cqe_tvb,
4089 4+off, 4, ENC_NA);
4090 break;
4091 case NVME_FCTYPE_PROP_GET:
4092 dissect_nvmeof_status_prop_get(cqe_tree, cqe_tvb, cmd, off);
4093 break;
4094 case NVME_FCTYPE_PROP_SET:
4095 proto_tree_add_item(cqe_tree, hf_nvmeof_cqe_prop_set_rsvd, cqe_tvb,
4096 0+off, 8, ENC_NA);
4097 break;
4098 default:
4099 proto_tree_add_item(cqe_tree, hf_nvmeof_cqe_sts, cqe_tvb,
4100 0+off, 8, ENC_LITTLE_ENDIAN);
4101 break;
4106 const char *get_nvmeof_cmd_string(uint8_t fctype)
4108 return val_to_str_const(fctype, fctype_tbl, "Unknown Fabric Command");
4111 static void dissect_nvme_cqe_common(tvbuff_t *nvme_tvb, proto_tree *cqe_tree, unsigned off, bool nvmeof);
4113 void
4114 dissect_nvmeof_fabric_cqe(tvbuff_t *nvme_tvb, packet_info *pinfo,
4115 proto_tree *nvme_tree,
4116 struct nvme_cmd_ctx *cmd, unsigned off)
4118 proto_tree *cqe_tree;
4119 proto_item *ti;
4120 uint8_t fctype = cmd->cmd_ctx.fabric_cmd.fctype;
4122 ti = proto_tree_add_item(nvme_tree, hf_nvmeof_cqe, nvme_tvb,
4123 0+off, NVME_CQE_SIZE, ENC_NA);
4125 if (fctype != NVME_FCTYPE_PROP_GET && fctype != NVME_FCTYPE_PROP_SET)
4126 col_append_sep_fstr(pinfo->cinfo, COL_INFO, "| ", "NVMeOF CQE for %s", val_to_str_const(fctype, fctype_tbl, "Unknown Command"));
4127 else
4128 col_append_sep_fstr(pinfo->cinfo, COL_INFO, "| ", "NVMeOF CQE for Property %s %s",
4129 (fctype == NVME_FCTYPE_PROP_GET) ? "Get" : "Set",
4130 val_to_str_const(cmd->cmd_ctx.fabric_cmd.prop_get.offset, prop_offset_tbl, "Unknown Property"));
4132 proto_item_append_text(ti, " (For Cmd: %s)", val_to_str_const(fctype, fctype_tbl, "Unknown Cmd"));
4134 cqe_tree = proto_item_add_subtree(ti, ett_data);
4136 nvme_publish_to_cmd_link(cqe_tree, nvme_tvb, hf_nvmeof_cmd_pkt,
4137 cmd);
4138 nvme_publish_cmd_latency(cqe_tree, cmd, hf_nvmeof_cmd_latency);
4140 dissect_nvmeof_cqe_status_8B(cqe_tree, nvme_tvb, cmd, off);
4142 dissect_nvme_cqe_common(nvme_tvb, cqe_tree, off, true);
4145 static void dissect_nvme_unhandled_cmd(tvbuff_t *nvme_tvb, proto_tree *cmd_tree)
4147 proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword10, nvme_tvb, 40, 4, ENC_LITTLE_ENDIAN);
4148 proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword11, nvme_tvb, 44, 4, ENC_LITTLE_ENDIAN);
4149 proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword12, nvme_tvb, 48, 4, ENC_LITTLE_ENDIAN);
4150 proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword13, nvme_tvb, 52, 4, ENC_LITTLE_ENDIAN);
4151 proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword14, nvme_tvb, 56, 4, ENC_LITTLE_ENDIAN);
4152 proto_tree_add_item(cmd_tree, hf_nvme_cmd_dword15, nvme_tvb, 60, 4, ENC_LITTLE_ENDIAN);
4155 void
4156 dissect_nvme_cmd(tvbuff_t *nvme_tvb, packet_info *pinfo, proto_tree *root_tree,
4157 struct nvme_q_ctx *q_ctx, struct nvme_cmd_ctx *cmd_ctx)
4159 proto_tree *cmd_tree;
4160 proto_item *ti, *opc_item;
4162 col_set_str(pinfo->cinfo, COL_PROTOCOL, "NVMe");
4163 ti = proto_tree_add_item(root_tree, proto_nvme, nvme_tvb, 0,
4164 NVME_CMD_SIZE, ENC_NA);
4165 proto_item_append_text(ti, " (Cmd)");
4166 cmd_tree = proto_item_add_subtree(ti, ett_data);
4168 cmd_ctx->opcode = tvb_get_uint8(nvme_tvb, 0);
4169 opc_item = proto_tree_add_item(cmd_tree, hf_nvme_cmd_opc, nvme_tvb,
4170 0, 1, ENC_LITTLE_ENDIAN);
4171 if (q_ctx->qid) {
4172 proto_item_append_text(opc_item, " %s",
4173 val_to_str_const(cmd_ctx->opcode, ioq_opc_tbl, "Unknown"));
4174 col_append_sep_fstr(pinfo->cinfo, COL_INFO, "| ", "NVMe %s", val_to_str_const(cmd_ctx->opcode, ioq_opc_tbl, "Unknown Command"));
4175 } else {
4176 proto_item_append_text(opc_item, " %s",
4177 val_to_str_const(cmd_ctx->opcode, aq_opc_tbl, "Unknown"));
4178 col_append_sep_fstr(pinfo->cinfo, COL_INFO, "| ", "NVMe %s", val_to_str_const(cmd_ctx->opcode, aq_opc_tbl, "Unknown Command"));
4181 nvme_publish_to_data_req_link(cmd_tree, nvme_tvb, hf_nvme_data_req, cmd_ctx);
4182 nvme_publish_to_data_tr_links(cmd_tree, nvme_tvb, hf_nvme_data_tr, cmd_ctx);
4183 nvme_publish_to_cqe_link(cmd_tree, nvme_tvb, hf_nvme_cqe_pkt, cmd_ctx);
4185 proto_tree_add_item(cmd_tree, hf_nvme_cmd_fuse_op, nvme_tvb,
4186 1, 1, ENC_NA);
4187 proto_tree_add_item(cmd_tree, hf_nvme_cmd_rsvd, nvme_tvb,
4188 1, 1, ENC_NA);
4189 proto_tree_add_item(cmd_tree, hf_nvme_cmd_psdt, nvme_tvb,
4190 1, 1, ENC_NA);
4191 proto_tree_add_item(cmd_tree, hf_nvme_cmd_cid, nvme_tvb,
4192 2, 2, ENC_LITTLE_ENDIAN);
4193 proto_tree_add_item(cmd_tree, hf_nvme_cmd_nsid, nvme_tvb,
4194 4, 4, ENC_LITTLE_ENDIAN);
4195 proto_tree_add_item(cmd_tree, hf_nvme_cmd_rsvd1, nvme_tvb,
4196 8, 8, ENC_NA);
4197 proto_tree_add_item(cmd_tree, hf_nvme_cmd_mptr, nvme_tvb,
4198 16, 8, ENC_LITTLE_ENDIAN);
4200 dissect_nvme_cmd_sgl(nvme_tvb, cmd_tree, hf_nvme_cmd_sgl, q_ctx, cmd_ctx, 0, PINFO_FD_VISITED(pinfo));
4202 if (q_ctx->qid) { //IOQ
4203 switch (cmd_ctx->opcode) {
4204 case NVME_IOQ_OPC_READ:
4205 case NVME_IOQ_OPC_WRITE:
4206 dissect_nvme_rw_cmd(nvme_tvb, cmd_tree);
4207 break;
4208 default:
4209 dissect_nvme_unhandled_cmd(nvme_tvb, cmd_tree);
4210 break;
4212 } else { //AQ
4213 switch (cmd_ctx->opcode) {
4214 case NVME_AQ_OPC_IDENTIFY:
4215 cmd_ctx->cmd_ctx.cmd_identify.cns = tvb_get_uint16(nvme_tvb, 40, ENC_LITTLE_ENDIAN);
4216 col_append_sep_fstr(pinfo->cinfo, COL_INFO, " ", "%s", val_to_str_const(cmd_ctx->cmd_ctx.cmd_identify.cns, cns_table, "Unknown"));
4217 dissect_nvme_identify_cmd(nvme_tvb, cmd_tree);
4218 break;
4219 case NVME_AQ_OPC_GET_LOG_PAGE:
4220 col_append_sep_fstr(pinfo->cinfo, COL_INFO, " ", "%s", get_logpage_name(tvb_get_uint8(nvme_tvb, 40)));
4221 dissect_nvme_get_logpage_cmd(nvme_tvb, cmd_tree, cmd_ctx);
4222 break;
4223 case NVME_AQ_OPC_SET_FEATURES:
4224 dissect_nvme_set_features_cmd(nvme_tvb, cmd_tree, cmd_ctx);
4225 break;
4226 case NVME_AQ_OPC_GET_FEATURES:
4227 dissect_nvme_get_features_cmd(nvme_tvb, cmd_tree, cmd_ctx);
4228 break;
4229 default:
4230 dissect_nvme_unhandled_cmd(nvme_tvb, cmd_tree);
4231 break;
4236 const char *nvme_get_opcode_string(uint8_t opcode, uint16_t qid)
4238 if (qid)
4239 return val_to_str_const(opcode, ioq_opc_tbl, "Reserved");
4240 else
4241 return val_to_str_const(opcode, aq_opc_tbl, "Reserved");
4245 nvme_is_io_queue_opcode(uint8_t opcode)
4247 return ((opcode == NVME_IOQ_OPC_FLUSH) ||
4248 (opcode == NVME_IOQ_OPC_WRITE) ||
4249 (opcode == NVME_IOQ_OPC_READ) ||
4250 (opcode == NVME_IOQ_OPC_WRITE_UNCORRECTABLE) ||
4251 (opcode == NVME_IOQ_OPC_COMPARE) ||
4252 (opcode == NVME_IOQ_OPC_WRITE_ZEROS) ||
4253 (opcode == NVME_IOQ_OPC_DATASET_MGMT) ||
4254 (opcode == NVME_IOQ_OPC_RESV_REG) ||
4255 (opcode == NVME_IOQ_OPC_RESV_REPORT) ||
4256 (opcode == NVME_IOQ_OPC_RESV_ACQUIRE) ||
4257 (opcode == NVME_IOQ_OPC_RESV_RELEASE));
4260 static const char *get_cqe_sc_string(unsigned sct, unsigned sc, bool nvmeof)
4262 switch (sct) {
4263 case NVME_CQE_SCT_GENERIC: return val_to_str_const(sc, nvme_cqe_sc_gen_tbl, "Unknown Status Code");
4264 case NVME_CQE_SCT_COMMAND: return (nvmeof) ? val_to_str_const(sc, nvmeof_cqe_sc_cmd_tbl, "Unknown Fabrics Status Code") :
4265 val_to_str_const(sc, nvme_cqe_sc_cmd_tbl, "Unknown Status Code");
4266 case NVME_CQE_SCT_MEDIA: return val_to_str_const(sc, nvme_cqe_sc_media_tbl, "Unknown Status Code");
4267 case NVME_CQE_SCT_PATH: return val_to_str_const(sc, nvme_cqe_sc_path_tbl, "Unknown Status Code");
4268 case NVME_CQE_SCT_VENDOR: return "Vendor Error";
4269 default: return "Unknown Status Code";
4273 static const value_string nvme_cqe_sc_sf_err_dword0_tbl[] = {
4274 { 0xD, "Feature Identifier Not Saveable" },
4275 { 0xE, "Feature Not Changeable" },
4276 { 0xF, "Feature Not Namespace Specific" },
4277 { 0x14, "Overlapping Range" },
4278 { 0, NULL },
4281 static const value_string nvme_cqe_aev_aet_dword0_tbl[] = {
4282 { 0x0, "Error status" },
4283 { 0x1, "SMART / Health status" },
4284 { 0x2, "Notice" },
4285 { 0x6, "IO Command Set specific status" },
4286 { 0x7, "Vendor specific" },
4287 { 0, NULL },
4290 static const value_string nvme_cqe_aev_status_error_tbl[] = {
4291 { 0x0, "Write to Invalid Doorbell Register" },
4292 { 0x1, "Invalid Doorbell Write Value" },
4293 { 0x2, "Diagnostic Failure" },
4294 { 0x3, "Persistent Internal Error"},
4295 { 0x4, "Transient Internal Error"},
4296 { 0x5, "Firmware Image Load Error"},
4297 { 0, NULL },
4300 static const value_string nvme_cqe_aev_status_smart_tbl[] = {
4301 { 0x0, "NVM subsystem Reliability" },
4302 { 0x1, "Temperature Threshold" },
4303 { 0x2, "Spare Below Threshold" },
4304 { 0, NULL },
4307 static const value_string nvme_cqe_aev_status_notice_tbl[] = {
4308 { 0x0, "Namespace Attribute Changed" },
4309 { 0x1, "Firmware Activation Starting" },
4310 { 0x2, "Telemetry Log Changed" },
4311 { 0x3, "Asymmetric Namespace Access Change" },
4312 { 0x4, "Predictable Latency Event Aggregate Log Change" },
4313 { 0x5, "LBA Status Information Alert" },
4314 { 0x6, "Endurance Group Event Aggregate Log Page Change" },
4315 { 0, NULL },
4318 static const value_string nvme_cqe_aev_status_nvm_tbl[] = {
4319 { 0x0, "Reservation Log Page Available" },
4320 { 0x1, "Sanitize Operation Completed" },
4321 { 0x2, "Sanitize Operation Completed With Unexpected Deallocation" },
4322 { 0, NULL },
4325 static void decode_dword0_cqe(tvbuff_t *nvme_tvb, proto_tree *cqe_tree, struct nvme_cmd_ctx *cmd_ctx)
4327 switch (cmd_ctx->opcode) {
4328 case NVME_AQ_OPC_SET_FEATURES:
4330 uint16_t sc = tvb_get_uint16(nvme_tvb, 14, ENC_LITTLE_ENDIAN);
4331 sc = ((sc & 0x1fe) >> 9);
4332 if (sc) {
4333 proto_tree_add_item(cqe_tree, hf_nvme_cqe_dword0_sf_err, nvme_tvb, 0, 4, ENC_LITTLE_ENDIAN);
4334 } else {
4335 if (cmd_ctx->cmd_ctx.set_features.fid == F_NUM_OF_QUEUES)
4336 add_group_mask_entry(nvme_tvb, cqe_tree, 0, 4, ASPEC(hf_nvme_cqe_dword0_sf_nq));
4337 else
4338 proto_tree_add_item(cqe_tree, hf_nvme_cqe_dword0, nvme_tvb, 0, 4, ENC_LITTLE_ENDIAN);
4340 break;
4342 case NVME_AQ_OPC_GET_FEATURES:
4343 switch (cmd_ctx->cmd_ctx.set_features.fid) {
4344 case F_ARBITRATION: add_group_mask_entry(nvme_tvb, cqe_tree, 0, 4, ASPEC(hf_nvme_cqe_get_features_dword0_arb)); break;
4345 case F_POWER_MGMT: add_group_mask_entry(nvme_tvb, cqe_tree, 0, 4, ASPEC(hf_nvme_cqe_get_features_dword0_pm)); break;
4346 case F_LBA_RANGE_TYPE: add_group_mask_entry(nvme_tvb, cqe_tree, 0, 4, ASPEC(hf_nvme_cqe_get_features_dword0_lbart)); break;
4347 case F_TEMP_THRESHOLD: add_group_mask_entry(nvme_tvb, cqe_tree, 0, 4, ASPEC(hf_nvme_cqe_get_features_dword0_tt)); break;
4348 case F_ERROR_RECOVERY: add_group_mask_entry(nvme_tvb, cqe_tree, 0, 4, ASPEC(hf_nvme_cqe_get_features_dword0_erec)); break;
4349 case F_VOLATILE_WC: add_group_mask_entry(nvme_tvb, cqe_tree, 0, 4, ASPEC(hf_nvme_cqe_get_features_dword0_vwce)); break;
4350 case F_NUM_OF_QUEUES: add_group_mask_entry(nvme_tvb, cqe_tree, 0, 4, ASPEC(hf_nvme_cqe_get_features_dword0_nq)); break;
4351 case F_IRQ_COALESCING: add_group_mask_entry(nvme_tvb, cqe_tree, 0, 4, ASPEC(hf_nvme_cqe_get_features_dword0_irqc)); break;
4352 case F_IRQ_VECTOR_CONF: add_group_mask_entry(nvme_tvb, cqe_tree, 0, 4, ASPEC(hf_nvme_cqe_get_features_dword0_irqv)); break;
4353 case F_WRITE_ATOM_NORM: add_group_mask_entry(nvme_tvb, cqe_tree, 0, 4, ASPEC(hf_nvme_cqe_get_features_dword0_wan)); break;
4354 case F_ASYNC_EVENT_CONF: add_group_mask_entry(nvme_tvb, cqe_tree, 0, 4, ASPEC(hf_nvme_cqe_get_features_dword0_aec)); break;
4355 case F_AUTO_PS_TRANSITION: add_group_mask_entry(nvme_tvb, cqe_tree, 0, 4, ASPEC(hf_nvme_cqe_get_features_dword0_apst)); break;
4356 case F_KA_TIMER: add_group_mask_entry(nvme_tvb, cqe_tree, 0, 4, ASPEC(hf_nvme_cqe_get_features_dword0_kat)); break;
4357 case F_HOST_CNTL_THERM_MGMT: add_group_mask_entry(nvme_tvb, cqe_tree, 0, 4, ASPEC(hf_nvme_cqe_get_features_dword0_hctm)); break;
4358 case F_NO_POWER_STATE_CONF: add_group_mask_entry(nvme_tvb, cqe_tree, 0, 4, ASPEC(hf_nvme_cqe_get_features_dword0_nops)); break;
4359 case F_READ_REC_LEVEL_CONF: add_group_mask_entry(nvme_tvb, cqe_tree, 0, 4, ASPEC(hf_nvme_cqe_get_features_dword0_rrl)); break;
4360 case F_PRED_LAT_MODE_CONF: add_group_mask_entry(nvme_tvb, cqe_tree, 0, 4, ASPEC(hf_nvme_cqe_get_features_dword0_plmc)); break;
4361 case F_PRED_LAT_MODE_WIND: add_group_mask_entry(nvme_tvb, cqe_tree, 0, 4, ASPEC(hf_nvme_cqe_get_features_dword0_plmw)); break;
4362 case F_LBA_ST_INF_REP_INT: add_group_mask_entry(nvme_tvb, cqe_tree, 0, 4, ASPEC(hf_nvme_cqe_get_features_dword0_lbasi)); break;
4363 case F_SANITIZE_CON: add_group_mask_entry(nvme_tvb, cqe_tree, 0, 4, ASPEC(hf_nvme_cqe_get_features_dword0_san)); break;
4364 case F_END_GROUP_EV_CONF: add_group_mask_entry(nvme_tvb, cqe_tree, 0, 4, ASPEC(hf_nvme_cqe_get_features_dword0_eg)); break;
4365 case F_SW_PR_MARKER: add_group_mask_entry(nvme_tvb, cqe_tree, 0, 4, ASPEC(hf_nvme_cqe_get_features_dword0_swp)); break;
4366 case F_HOST_ID: add_group_mask_entry(nvme_tvb, cqe_tree, 0, 4, ASPEC(hf_nvme_cqe_get_features_dword0_hid)); break;
4367 case F_RSRV_NOT_MASK: add_group_mask_entry(nvme_tvb, cqe_tree, 0, 4, ASPEC(hf_nvme_cqe_get_features_dword0_rsrvn)); break;
4368 case F_RSRV_PRST: add_group_mask_entry(nvme_tvb, cqe_tree, 0, 4, ASPEC(hf_nvme_cqe_get_features_dword0_rsrvp)); break;
4369 case F_NS_WRITE_CONF: add_group_mask_entry(nvme_tvb, cqe_tree, 0, 4, ASPEC(hf_nvme_cqe_get_features_dword0_nswp)); break;
4370 default: proto_tree_add_item(cqe_tree, hf_nvme_cqe_dword0, nvme_tvb, 0, 4, ENC_LITTLE_ENDIAN); break;
4372 break;
4373 case NVME_AQ_OPC_ASYNC_EVE_REQ:
4375 proto_item *ti;
4376 proto_tree *grp;
4377 unsigned i;
4378 uint8_t aet;
4379 uint8_t aei;
4380 ti = proto_tree_add_item(cqe_tree, hf_nvme_cqe_aev_dword0[0], nvme_tvb, 0, 4, ENC_LITTLE_ENDIAN);
4381 grp = proto_item_add_subtree(ti, ett_data);
4382 for (i = 1; i < 4; i++)
4383 ti = proto_tree_add_item(grp, hf_nvme_cqe_aev_dword0[i], nvme_tvb, 0, 4, ENC_LITTLE_ENDIAN);
4384 aet = tvb_get_uint8(nvme_tvb, 0) & 0x7;
4385 aei = tvb_get_uint8(nvme_tvb, 2);
4386 switch (aet) {
4387 case 0: proto_item_append_text(ti, " (%s)", val_to_str_const(aei, nvme_cqe_aev_status_error_tbl, "Unknown")); break;
4388 case 1: proto_item_append_text(ti, " (%s)", val_to_str_const(aei, nvme_cqe_aev_status_smart_tbl, "Unknown")); break;
4389 case 2: proto_item_append_text(ti, " (%s)", val_to_str_const(aei, nvme_cqe_aev_status_notice_tbl, "Unknown")); break;
4390 case 6: proto_item_append_text(ti, " (%s)", val_to_str_const(aei, nvme_cqe_aev_status_nvm_tbl, "Unknown")); break;
4392 proto_tree_add_item(grp, hf_nvme_cqe_aev_dword0[4], nvme_tvb, 0, 4, ENC_LITTLE_ENDIAN);
4393 proto_tree_add_item(grp, hf_nvme_cqe_aev_dword0[5], nvme_tvb, 0, 4, ENC_LITTLE_ENDIAN);
4394 break;
4396 default:
4397 proto_tree_add_item(cqe_tree, hf_nvme_cqe_dword0, nvme_tvb, 0, 4, ENC_LITTLE_ENDIAN);
4398 break;
4402 static void dissect_nvme_cqe_common(tvbuff_t *nvme_tvb, proto_tree *cqe_tree, unsigned off, bool nvmeof)
4404 proto_item *ti;
4405 proto_tree *grp;
4406 uint16_t val;
4407 unsigned i;
4409 val = tvb_get_uint16(nvme_tvb, off+14, ENC_LITTLE_ENDIAN);
4410 proto_tree_add_item(cqe_tree, hf_nvme_cqe_sqhd, nvme_tvb, off+8, 2, ENC_LITTLE_ENDIAN);
4411 proto_tree_add_item(cqe_tree, hf_nvme_cqe_sqid, nvme_tvb, off+10, 2, ENC_LITTLE_ENDIAN);
4412 proto_tree_add_item(cqe_tree, hf_nvme_cqe_cid, nvme_tvb, off+12, 2, ENC_LITTLE_ENDIAN);
4414 ti = proto_tree_add_item(cqe_tree, hf_nvme_cqe_status[0], nvme_tvb, off+14, 2, ENC_LITTLE_ENDIAN);
4415 grp = proto_item_add_subtree(ti, ett_data);
4416 if (nvmeof)
4417 proto_tree_add_item(grp, hf_nvme_cqe_status_rsvd, nvme_tvb, off+14, 2, ENC_LITTLE_ENDIAN);
4418 else
4419 proto_tree_add_item(grp, hf_nvme_cqe_status[1], nvme_tvb, off+14, 2, ENC_LITTLE_ENDIAN);
4421 ti = proto_tree_add_item(grp, hf_nvme_cqe_status[2], nvme_tvb, off+14, 2, ENC_LITTLE_ENDIAN);
4422 proto_item_append_text(ti, " (%s)", get_cqe_sc_string((val & 0xE00) >> 9, (val & 0x1FE) >> 1, nvmeof));
4424 for (i = 3; i < array_length(hf_nvme_cqe_status); i++)
4425 proto_tree_add_item(grp, hf_nvme_cqe_status[i], nvme_tvb, off+14, 2, ENC_LITTLE_ENDIAN);
4428 void dissect_nvme_cqe(tvbuff_t *nvme_tvb, packet_info *pinfo, proto_tree *root_tree, struct nvme_q_ctx *q_ctx, struct nvme_cmd_ctx *cmd_ctx)
4430 proto_tree *cqe_tree;
4431 proto_item *ti;
4433 if (q_ctx->qid)
4434 col_append_sep_fstr(pinfo->cinfo, COL_INFO, "| ", "NVMe CQE for %s", val_to_str_const(cmd_ctx->opcode, ioq_opc_tbl, "Unknown Command"));
4435 else
4436 col_append_sep_fstr(pinfo->cinfo, COL_INFO, "| ", "NVMe CQE for %s", val_to_str_const(cmd_ctx->opcode, aq_opc_tbl, "Unknown Command"));
4438 if (!q_ctx->qid) {
4439 if (cmd_ctx->opcode == NVME_AQ_OPC_IDENTIFY)
4440 col_append_sep_fstr(pinfo->cinfo, COL_INFO, " ", "%s", val_to_str_const(cmd_ctx->cmd_ctx.cmd_identify.cns, cns_table, "Unknown"));
4441 else if (cmd_ctx->opcode == NVME_AQ_OPC_GET_LOG_PAGE)
4442 col_append_sep_fstr(pinfo->cinfo, COL_INFO, " ", "%s", get_logpage_name(cmd_ctx->cmd_ctx.get_logpage.lid));
4444 col_set_str(pinfo->cinfo, COL_PROTOCOL, "NVMe");
4445 ti = proto_tree_add_item(root_tree, proto_nvme, nvme_tvb, 0,
4446 NVME_CQE_SIZE, ENC_NA);
4447 proto_item_append_text(ti, " (Cqe)");
4448 cqe_tree = proto_item_add_subtree(ti, ett_data);
4450 nvme_publish_to_cmd_link(cqe_tree, nvme_tvb, hf_nvme_cmd_pkt, cmd_ctx);
4451 nvme_publish_cmd_latency(cqe_tree, cmd_ctx, hf_nvme_cmd_latency);
4453 decode_dword0_cqe(nvme_tvb, cqe_tree, cmd_ctx);
4454 proto_tree_add_item(cqe_tree, hf_nvme_cqe_dword1, nvme_tvb, 4, 4, ENC_LITTLE_ENDIAN);
4455 dissect_nvme_cqe_common(nvme_tvb, cqe_tree, 0, false);
4458 void
4459 proto_register_nvme(void)
4461 static hf_register_info hf[] = {
4462 /* NVMeOF Fabric Command Fields */
4463 { &hf_nvmeof_cmd,
4464 { "Cmd", "nvme.fabrics.cmd",
4465 FT_NONE, BASE_NONE, NULL, 0x0, NULL, HFILL}
4467 { &hf_nvmeof_cmd_opc,
4468 { "Opcode", "nvme.fabrics.cmd.opc",
4469 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
4471 { &hf_nvmeof_cmd_rsvd,
4472 { "Reserved", "nvme.fabrics.cmd.rsvd",
4473 FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
4475 { &hf_nvmeof_cmd_cid,
4476 { "Command Identifier", "nvme.fabrics.cmd.cid",
4477 FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
4479 { &hf_nvmeof_cmd_fctype,
4480 { "Fabric Command Type", "nvme.fabrics.cmd.fctype",
4481 FT_UINT8, BASE_HEX, VALS(fctype_tbl), 0x0, NULL, HFILL}
4483 { &hf_nvmeof_cmd_connect_rsvd1,
4484 { "Reserved", "nvme.fabrics.cmd.connect.rsvd1",
4485 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
4487 { &hf_nvmeof_cmd_connect_sgl1,
4488 { "SGL1", "nvme.fabrics.cmd.connect.sgl1",
4489 FT_NONE, BASE_NONE, NULL, 0x0, NULL, HFILL}
4491 { &hf_nvmeof_cmd_connect_recfmt,
4492 { "Record Format", "nvme.fabrics.cmd.connect.recfmt",
4493 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
4495 { &hf_nvmeof_cmd_connect_qid,
4496 { "Queue ID", "nvme.fabrics.cmd.connect.qid",
4497 FT_UINT16, BASE_CUSTOM, CF_FUNC(add_nvme_qid), 0x0, NULL, HFILL}
4499 { &hf_nvmeof_cmd_connect_sqsize,
4500 { "Submission Queue Size", "nvme.fabrics.cmd.connect.sqsize",
4501 FT_UINT16, BASE_CUSTOM, CF_FUNC(add_zero_base), 0x0, NULL, HFILL}
4503 { &hf_nvmeof_cmd_connect_cattr[0],
4504 { "Connect Attributes", "nvme.fabrics.cmd.connect.cattr",
4505 FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
4507 { &hf_nvmeof_cmd_connect_cattr[1],
4508 { "Priority Class", "nvme.fabrics.cmd.connect.cattr.pc",
4509 FT_UINT8, BASE_HEX, VALS(pclass_tbl), 0x3, NULL, HFILL}
4511 { &hf_nvmeof_cmd_connect_cattr[2],
4512 { "Disable SQ Flow Control", "nvme.fabrics.cmd.connect.cattr.dfc",
4513 FT_UINT8, BASE_HEX, NULL, 0x4, NULL, HFILL}
4515 { &hf_nvmeof_cmd_connect_cattr[3],
4516 { "Support Deletion of IO Queues", "nvme.fabrics.cmd.connect.cattr.dioq",
4517 FT_UINT8, BASE_HEX, NULL, 0x8, NULL, HFILL}
4519 { &hf_nvmeof_cmd_connect_cattr[4],
4520 { "Reserved", "nvme.fabrics.cmd.connect.cattr.rsvd",
4521 FT_UINT8, BASE_HEX, NULL, 0xf0, NULL, HFILL}
4523 { &hf_nvmeof_cmd_connect_rsvd2,
4524 { "Reserved", "nvme.fabrics.cmd.connect.rsvd2",
4525 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
4527 { &hf_nvmeof_cmd_connect_kato,
4528 { "Keep Alive Timeout", "nvme.fabrics.cmd.connect.kato",
4529 FT_UINT32, BASE_DEC|BASE_UNIT_STRING, UNS(&units_milliseconds), 0x0, NULL, HFILL}
4531 { &hf_nvmeof_cmd_connect_rsvd3,
4532 { "Reserved", "nvme.fabrics.cmd.connect.rsvd3",
4533 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
4535 { &hf_nvmeof_cmd_connect_data_hostid,
4536 { "Host Identifier", "nvme.fabrics.cmd.connect.data.hostid",
4537 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
4539 { &hf_nvmeof_cmd_connect_data_cntlid,
4540 { "Controller ID", "nvme.fabrics.cmd.connect.data.cntrlid",
4541 FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
4543 { &hf_nvmeof_cmd_connect_data_rsvd0,
4544 { "Reserved", "nvme.fabrics.cmd.connect.data.rsvd0",
4545 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
4547 { &hf_nvmeof_cmd_connect_data_subnqn,
4548 { "Subsystem NQN", "nvme.fabrics.cmd.connect.data.subnqn",
4549 FT_STRING, BASE_NONE, NULL, 0x0, NULL, HFILL}
4551 { &hf_nvmeof_cmd_connect_data_hostnqn,
4552 { "Host NQN", "nvme.fabrics.cmd.connect.data.hostnqn",
4553 FT_STRING, BASE_NONE, NULL, 0x0, NULL, HFILL}
4555 { &hf_nvmeof_cmd_connect_data_rsvd1,
4556 { "Reserved", "nvme.fabrics.cmd.connect.data.rsvd1",
4557 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
4559 { &hf_nvmeof_cmd_auth_rsdv1,
4560 { "Reserved", "nvme.fabrics.cmd.auth.rsvd1",
4561 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
4563 { &hf_nvmeof_cmd_auth_sgl1,
4564 { "SGL1", "nvme.fabrics.cmd.auth.sgl1",
4565 FT_NONE, BASE_NONE, NULL, 0x0, NULL, HFILL}
4567 { &hf_nvmeof_cmd_auth_rsdv2,
4568 { "Reserved", "nvme.fabrics.cmd.auth.rsvd2",
4569 FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
4571 { &hf_nvmeof_cmd_auth_spsp0,
4572 { "SP Specific 0", "nvme.fabrics.cmd.auth.spsp0",
4573 FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
4575 { &hf_nvmeof_cmd_auth_spsp1,
4576 { "SP Specific 1", "nvme.fabrics.cmd.auth.spsp1",
4577 FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
4579 { &hf_nvmeof_cmd_auth_secp,
4580 { "Security Protocol", "nvme.fabrics.cmd.auth.secp",
4581 FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
4583 { &hf_nvmeof_cmd_auth_al,
4584 { "Allocation Length", "nvme.fabrics.cmd.auth.al",
4585 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL}
4587 { &hf_nvmeof_cmd_auth_rsdv3,
4588 { "Reserved", "nvme.fabrics.cmd.auth.rsvd3",
4589 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
4591 { &hf_nvmeof_cmd_disconnect_rsvd0,
4592 { "Reserved", "nvme.fabrics.cmd.disconnect.rsvd0",
4593 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
4595 { &hf_nvmeof_cmd_disconnect_recfmt,
4596 { "Record Format", "nvme.fabrics.cmd.disconnect.recfmt",
4597 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
4599 { &hf_nvmeof_cmd_disconnect_rsvd1,
4600 { "Reserved", "nvme.fabrics.cmd.disconnect.rsvd1",
4601 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
4603 { &hf_nvmeof_cmd_prop_get_set_rsvd0,
4604 { "Reserved", "nvme.fabrics.cmd.prop_get_set.rsvd0",
4605 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
4607 { &hf_nvmeof_cmd_prop_get_set_attrib[0],
4608 { "Attributes", "nvme.fabrics.cmd.prop_get_set.attrib",
4609 FT_UINT8, BASE_HEX, NULL, 0x7, NULL, HFILL}
4611 { &hf_nvmeof_cmd_prop_get_set_attrib[1],
4612 { "Property Size", "nvme.fabrics.cmd.prop_get_set.attrib.size",
4613 FT_UINT8, BASE_HEX, VALS(attr_size_tbl), 0x7, NULL, HFILL}
4615 { &hf_nvmeof_cmd_prop_get_set_attrib[2],
4616 { "Reserved", "nvme.fabrics.cmd.prop_get_set.attrib.rsvd",
4617 FT_UINT8, BASE_HEX, NULL, 0xf8, NULL, HFILL}
4619 { &hf_nvmeof_cmd_prop_get_set_rsvd1,
4620 { "Reserved", "nvme.fabrics.cmd.prop_get_set.rsvd1",
4621 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
4623 { &hf_nvmeof_cmd_prop_get_set_offset,
4624 { "Offset", "nvme.fabrics.cmd.prop_get_set.offset",
4625 FT_UINT32, BASE_HEX, VALS(prop_offset_tbl), 0x0, NULL, HFILL}
4627 { &hf_nvmeof_cmd_prop_get_rsvd2,
4628 { "Reserved", "nvme.fabrics.cmd.prop_get.rsvd2",
4629 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
4631 { &hf_nvmeof_prop_get_set_data,
4632 { "Property Data", "nvme.fabrics.prop_get_set.data",
4633 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
4635 { &hf_nvmeof_prop_get_set_data_4B,
4636 { "Value", "nvme.fabrics.prop_get_set.data.4B",
4637 FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
4639 { &hf_nvmeof_prop_get_set_data_4B_rsvd,
4640 { "Reserved", "nvme.fabrics.prop_get_set.data.rsvd",
4641 FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
4643 { &hf_nvmeof_prop_get_set_data_8B,
4644 { "Value", "nvme.fabrics.prop_get_set.data.8B",
4645 FT_UINT64, BASE_HEX, NULL, 0x0, NULL, HFILL}
4647 { &hf_nvmeof_prop_get_set_cc[0],
4648 { "Controller Configuration", "nvme.fabrics.prop_get_set.cc",
4649 FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
4651 { &hf_nvmeof_prop_get_set_cc[1],
4652 { "Enable", "nvme.fabrics.prop_get_set.cc.en",
4653 FT_UINT32, BASE_HEX, NULL, 0x1, NULL, HFILL}
4655 { &hf_nvmeof_prop_get_set_cc[2],
4656 { "Reserved", "nvme.fabrics.prop_get_set.cc.rsvd0",
4657 FT_UINT32, BASE_HEX, NULL, 0xE, NULL, HFILL}
4659 { &hf_nvmeof_prop_get_set_cc[3],
4660 { "IO Command Set Selected", "nvme.fabrics.prop_get_set.cc.css",
4661 FT_UINT32, BASE_HEX, VALS(css_table), 0x70, NULL, HFILL}
4663 { &hf_nvmeof_prop_get_set_cc[4],
4664 { "Memory Page Size", "nvme.fabrics.prop_get_set.cc.mps",
4665 FT_UINT32, BASE_CUSTOM, CF_FUNC(add_ctrl_pow2_page_size), 0x780, NULL, HFILL}
4667 { &hf_nvmeof_prop_get_set_cc[5],
4668 { "Arbitration Mechanism Selected", "nvme.fabrics.prop_get_set.cc.ams",
4669 FT_UINT32, BASE_HEX, VALS(ams_table), 0x3800, NULL, HFILL}
4671 { &hf_nvmeof_prop_get_set_cc[6],
4672 { "Shutdown Notification", "nvme.fabrics.prop_get_set.cc.shn",
4673 FT_UINT32, BASE_HEX, VALS(sn_table), 0xc000, NULL, HFILL}
4675 { &hf_nvmeof_prop_get_set_cc[7],
4676 { "IO Submission Queue Entry Size", "nvme.fabrics.prop_get_set.cc.iosqes",
4677 FT_UINT32, BASE_CUSTOM, CF_FUNC(add_ctrl_pow2_bytes), 0xF0000, NULL, HFILL}
4679 { &hf_nvmeof_prop_get_set_cc[8],
4680 { "IO Completion Queue Entry Size", "nvme.fabrics.prop_get_set.cc.iocqes",
4681 FT_UINT32, BASE_CUSTOM, CF_FUNC(add_ctrl_pow2_bytes), 0xF00000, NULL, HFILL}
4683 { &hf_nvmeof_prop_get_set_cc[9],
4684 { "Reserved", "nvme.fabrics.prop_get_set.cc.rsvd1",
4685 FT_UINT32, BASE_HEX, NULL, 0xff000000, NULL, HFILL}
4687 { &hf_nvmeof_prop_get_set_csts[0],
4688 { "Controller Status", "nvme.fabrics.prop_get_set.csts",
4689 FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
4691 { &hf_nvmeof_prop_get_set_csts[1],
4692 { "Ready", "nvme.fabrics.prop_get_set.csts.rdy",
4693 FT_UINT32, BASE_HEX, NULL, 0x1, NULL, HFILL}
4695 { &hf_nvmeof_prop_get_set_csts[2],
4696 { "Controller Fatal Status", "nvme.fabrics.prop_get_set.csts.cfs",
4697 FT_UINT32, BASE_HEX, NULL, 0x2, NULL, HFILL}
4699 { &hf_nvmeof_prop_get_set_csts[3],
4700 { "Shutdown Status", "nvme.fabrics.prop_get_set.csts.shst",
4701 FT_UINT32, BASE_HEX, VALS(shst_table), 0xC, NULL, HFILL}
4703 { &hf_nvmeof_prop_get_set_csts[4],
4704 { "NVM Subsystem Reset Occurred", "nvme.fabrics.prop_get_set.csts.nssro",
4705 FT_UINT32, BASE_HEX, NULL, 0x10, NULL, HFILL}
4707 { &hf_nvmeof_prop_get_set_csts[5],
4708 { "Processing Paused", "nvme.fabrics.prop_get_set.csts.pp",
4709 FT_UINT32, BASE_HEX, NULL, 0x20, NULL, HFILL}
4711 { &hf_nvmeof_prop_get_set_csts[6],
4712 { "Reserved", "nvme.fabrics.prop_get_set.csts.rsvd",
4713 FT_UINT32, BASE_HEX, NULL, 0xffffffC0, NULL, HFILL}
4715 { &hf_nvmeof_prop_get_set_nssr[0],
4716 { "NVM Subsystem Reset", "nvme.fabrics.cmd.prop_attr.set.nssr",
4717 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
4719 { &hf_nvmeof_prop_get_set_nssr[1],
4720 { "NVM Subsystem Reset Control", "nvme.fabrics.cmd.prop_attr.set.nssr.nssrc",
4721 FT_UINT32, BASE_HEX, NULL, 0xffffffff, NULL, HFILL}
4723 { &hf_nvmeof_cmd_prop_set_rsvd,
4724 { "Reserved", "nvme.fabrics.cmd.prop_set.rsvd",
4725 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
4727 { &hf_nvmeof_cmd_generic_rsvd1,
4728 { "Reserved", "nvme.fabrics.cmd.generic.rsvd1",
4729 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
4731 { &hf_nvmeof_cmd_generic_field,
4732 { "Fabric Cmd specific field", "nvme.fabrics.cmd.generic.field",
4733 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
4735 /* NVMeOF Fabric Commands CQE fields */
4736 { &hf_nvmeof_cqe,
4737 { "Cqe", "nvme.fabrics.cqe",
4738 FT_NONE, BASE_NONE, NULL, 0x0, NULL, HFILL}
4740 { &hf_nvmeof_cqe_sts,
4741 { "Cmd specific Status", "nvme.fabrics.cqe.sts",
4742 FT_UINT64, BASE_HEX, NULL, 0x0, NULL, HFILL}
4744 { &hf_nvmeof_prop_get_ccap[0],
4745 { "Controller Capabilities", "nvme.fabrics.prop_get.ccap",
4746 FT_UINT64, BASE_HEX, NULL, 0, NULL, HFILL}
4748 { &hf_nvmeof_prop_get_ccap[1],
4749 { "Maximum Queue Entries Supported", "nvme.fabrics.prop_get.ccap.mqes",
4750 FT_UINT64, BASE_CUSTOM, CF_FUNC(add_zero_base), 0xffff, NULL, HFILL}
4752 { &hf_nvmeof_prop_get_ccap[2],
4753 { "Contiguous Queues Required", "nvme.fabrics.prop_get.ccap.cqr",
4754 FT_BOOLEAN, 64, NULL, 0x10000, NULL, HFILL}
4756 { &hf_nvmeof_prop_get_ccap[3],
4757 { "Supports Arbitration Mechanism with Weighted Round Robin and Urgent Priority Class", "nvme.fabrics.prop_get.ccap.ams.wrr",
4758 FT_BOOLEAN, 64, NULL, 0x20000, NULL, HFILL}
4760 { &hf_nvmeof_prop_get_ccap[4],
4761 { "Supports Arbitration Mechanism Vendor Specific", "nvme.fabrics.prop_get.ccap.ams.vs",
4762 FT_BOOLEAN, 64, NULL, 0x40000, NULL, HFILL}
4764 { &hf_nvmeof_prop_get_ccap[5],
4765 { "Reserved", "nvme.fabrics.prop_get.ccap.rsvd0",
4766 FT_UINT64, BASE_HEX, NULL, 0xF80000, NULL, HFILL}
4768 { &hf_nvmeof_prop_get_ccap[6],
4769 { "Timeout (to ready status)", "nvme.fabrics.prop_get.ccap.to",
4770 FT_UINT64, BASE_CUSTOM, CF_FUNC(add_500ms_units), 0xFF000000, NULL, HFILL}
4772 { &hf_nvmeof_prop_get_ccap[7],
4773 { "Doorbell Stride", "nvme.fabrics.prop_get.ccap.dstrd",
4774 FT_UINT64, BASE_CUSTOM, CF_FUNC(add_ctrl_pow2_dstrd_size), 0xF00000000, NULL, HFILL}
4776 { &hf_nvmeof_prop_get_ccap[8],
4777 { "NVM Subsystem Reset Supported", "nvme.fabrics.prop_get.ccap.nssrs",
4778 FT_BOOLEAN, 64, NULL, 0x1000000000, NULL, HFILL}
4780 { &hf_nvmeof_prop_get_ccap[9],
4781 { "Command Sets Supported", "nvme.fabrics.prop_get.ccap.css",
4782 FT_UINT64, BASE_CUSTOM, CF_FUNC(add_ccap_css), 0x1FE000000000, NULL, HFILL}
4784 { &hf_nvmeof_prop_get_ccap[10],
4785 { "Boot Partition Support", "nvme.fabrics.prop_get.ccap.bps",
4786 FT_BOOLEAN, 64, NULL, 0x200000000000, NULL, HFILL}
4788 { &hf_nvmeof_prop_get_ccap[11],
4789 { "Reserved", "nvme.fabrics.prop_get.ccap.rsdv1",
4790 FT_UINT64, BASE_HEX, NULL, 0xC00000000000, NULL, HFILL}
4792 { &hf_nvmeof_prop_get_ccap[12],
4793 { "Memory Page Size Minimum", "nvme.fabrics.prop_get.ccap.mpsmin",
4794 FT_UINT64, BASE_CUSTOM, CF_FUNC(add_ctrl_pow2_page_size), 0xF000000000000, NULL, HFILL}
4796 { &hf_nvmeof_prop_get_ccap[13],
4797 { "Memory Page Size Maximum", "nvme.fabrics.prop_get.ccap.mpsmax",
4798 FT_UINT64, BASE_CUSTOM, CF_FUNC(add_ctrl_pow2_page_size), 0xF0000000000000, NULL, HFILL}
4800 { &hf_nvmeof_prop_get_ccap[14],
4801 { "Persistent Memory Region Supported", "nvme.fabrics.prop_get.ccap.pmrs",
4802 FT_BOOLEAN, 64, NULL, 0x100000000000000, NULL, HFILL}
4804 { &hf_nvmeof_prop_get_ccap[15],
4805 { "Controller Memory Buffer Supported", "nvme.fabrics.prop_get.ccap.cmbs",
4806 FT_BOOLEAN, 64, NULL, 0x200000000000000, NULL, HFILL}
4808 { &hf_nvmeof_prop_get_ccap[16],
4809 { "Reserved", "nvme.fabrics.prop_get.ccap.rsvd2",
4810 FT_UINT64, BASE_HEX, NULL, 0xFC00000000000000, NULL, HFILL}
4812 { &hf_nvmeof_prop_get_vs[0],
4813 { "Version", "nvme.fabrics.prop_get.vs",
4814 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
4816 { &hf_nvmeof_prop_get_vs[1],
4817 { "Tertiary Version", "nvme.fabrics.prop_get.vs.ter",
4818 FT_UINT32, BASE_DEC, NULL, 0xff, NULL, HFILL}
4820 { &hf_nvmeof_prop_get_vs[2],
4821 { "Minor Version", "nvme.fabrics.prop_get.vs.mnr",
4822 FT_UINT32, BASE_DEC, NULL, 0xff00, NULL, HFILL}
4824 { &hf_nvmeof_prop_get_vs[3],
4825 { "Major Version", "nvme.fabrics.prop_get.vs.mjr",
4826 FT_UINT32, BASE_DEC, NULL, 0xffff0000, NULL, HFILL}
4828 { &hf_nvmeof_cqe_connect_cntlid,
4829 { "Controller ID", "nvme.fabrics.cqe.connect.cntrlid",
4830 FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
4832 { &hf_nvmeof_cqe_connect_authreq,
4833 { "Authentication Required", "nvme.fabrics.cqe.connect.authreq",
4834 FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
4836 { &hf_nvmeof_cqe_connect_rsvd,
4837 { "Reserved", "nvme.fabrics.cqe.connect.rsvd",
4838 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
4840 { &hf_nvmeof_cqe_prop_set_rsvd,
4841 { "Reserved", "nvme.fabrics.cqe.prop_set.rsvd",
4842 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
4844 /* Tracking commands, completions and transfers */
4845 { &hf_nvmeof_cmd_pkt,
4846 { "Fabric Cmd in", "nvme.fabrics.cmd_pkt",
4847 FT_FRAMENUM, BASE_NONE, NULL, 0,
4848 "The Cmd for this transaction is in this frame", HFILL }
4850 { &hf_nvmeof_cqe_pkt,
4851 { "Fabric Cqe in", "nvme.fabrics.cqe_pkt",
4852 FT_FRAMENUM, BASE_NONE, NULL, 0,
4853 "The Cqe for this transaction is in this frame", HFILL }
4855 { &hf_nvmeof_data_req,
4856 { "DATA Transfer Request", "nvme.fabrics.data_req",
4857 FT_FRAMENUM, BASE_NONE, NULL, 0,
4858 "DATA transfer request for this transaction is in this frame", HFILL }
4860 { &hf_nvmeof_data_tr[0],
4861 { "DATA Transfer 0", "nvme.fabrics.data.tr0",
4862 FT_FRAMENUM, BASE_NONE, NULL, 0,
4863 "DATA transfer 0 for this transaction is in this frame", HFILL }
4865 { &hf_nvmeof_data_tr[1],
4866 { "DATA Transfer 1", "nvme.fabrics.data_tr1",
4867 FT_FRAMENUM, BASE_NONE, NULL, 0,
4868 "DATA transfer 1 for this transaction is in this frame", HFILL }
4870 { &hf_nvmeof_data_tr[2],
4871 { "DATA Transfer 2", "nvme.fabrics.data_tr2",
4872 FT_FRAMENUM, BASE_NONE, NULL, 0,
4873 "DATA transfer 2 for this transaction is in this frame", HFILL }
4875 { &hf_nvmeof_data_tr[3],
4876 { "DATA Transfer 3", "nvme.fabrics.data_tr3",
4877 FT_FRAMENUM, BASE_NONE, NULL, 0,
4878 "DATA transfer 3 for this transaction is in this frame", HFILL }
4880 { &hf_nvmeof_data_tr[4],
4881 { "DATA Transfer 4", "nvme.fabrics.data_tr4",
4882 FT_FRAMENUM, BASE_NONE, NULL, 0,
4883 "DATA transfer 4 for this transaction is in this frame", HFILL }
4885 { &hf_nvmeof_data_tr[5],
4886 { "DATA Transfer 5", "nvme.fabrics.data_tr5",
4887 FT_FRAMENUM, BASE_NONE, NULL, 0,
4888 "DATA transfer 5 for this transaction is in this frame", HFILL }
4890 { &hf_nvmeof_data_tr[6],
4891 { "DATA Transfer 6", "nvme.fabrics.data_tr6",
4892 FT_FRAMENUM, BASE_NONE, NULL, 0,
4893 "DATA transfer 6 for this transaction is in this frame", HFILL }
4895 { &hf_nvmeof_data_tr[7],
4896 { "DATA Transfer 7", "nvme.fabrics.data_tr7",
4897 FT_FRAMENUM, BASE_NONE, NULL, 0,
4898 "DATA transfer 7 for this transaction is in this frame", HFILL }
4900 { &hf_nvmeof_data_tr[8],
4901 { "DATA Transfer 8", "nvme.fabrics.data_tr8",
4902 FT_FRAMENUM, BASE_NONE, NULL, 0,
4903 "DATA transfer 8 for this transaction is in this frame", HFILL }
4905 { &hf_nvmeof_data_tr[9],
4906 { "DATA Transfer 9", "nvme.fabrics.data_tr9",
4907 FT_FRAMENUM, BASE_NONE, NULL, 0,
4908 "DATA transfer 9 for this transaction is in this frame", HFILL }
4910 { &hf_nvmeof_data_tr[10],
4911 { "DATA Transfer 10", "nvme.fabrics.data_tr10",
4912 FT_FRAMENUM, BASE_NONE, NULL, 0,
4913 "DATA transfer 10 for this transaction is in this frame", HFILL }
4915 { &hf_nvmeof_data_tr[11],
4916 { "DATA Transfer 11", "nvme.fabrics.data_tr11",
4917 FT_FRAMENUM, BASE_NONE, NULL, 0,
4918 "DATA transfer 11 for this transaction is in this frame", HFILL }
4920 { &hf_nvmeof_data_tr[12],
4921 { "DATA Transfer 12", "nvme.fabrics.data_tr12",
4922 FT_FRAMENUM, BASE_NONE, NULL, 0,
4923 "DATA transfer 12 for this transaction is in this frame", HFILL }
4925 { &hf_nvmeof_data_tr[13],
4926 { "DATA Transfer 13", "nvme.fabrics.data_tr13",
4927 FT_FRAMENUM, BASE_NONE, NULL, 0,
4928 "DATA transfer 13 for this transaction is in this frame", HFILL }
4930 { &hf_nvmeof_data_tr[14],
4931 { "DATA Transfer 14", "nvme.fabrics.data_tr14",
4932 FT_FRAMENUM, BASE_NONE, NULL, 0,
4933 "DATA transfer 14 for this transaction is in this frame", HFILL }
4935 { &hf_nvmeof_data_tr[15],
4936 { "DATA Transfer 15", "nvme.fabrics.data_tr15",
4937 FT_FRAMENUM, BASE_NONE, NULL, 0,
4938 "DATA transfer 15 for this transaction is in this frame", HFILL }
4940 { &hf_nvmeof_cmd_latency,
4941 { "Cmd Latency", "nvme.fabrics.cmd_latency",
4942 FT_DOUBLE, BASE_NONE, NULL, 0x0,
4943 "The time between the command and completion, in usec", HFILL }
4945 /* NVMe Command fields */
4946 { &hf_nvme_cmd_opc,
4947 { "Opcode", "nvme.cmd.opc",
4948 FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
4950 { &hf_nvme_cmd_fuse_op,
4951 { "Fuse Operation", "nvme.cmd.fuse_op",
4952 FT_UINT8, BASE_HEX, NULL, 0x3, NULL, HFILL}
4954 { &hf_nvme_cmd_rsvd,
4955 { "Reserved", "nvme.cmd.rsvd",
4956 FT_UINT8, BASE_HEX, NULL, 0x3c, NULL, HFILL}
4958 { &hf_nvme_cmd_psdt,
4959 { "PRP Or SGL", "nvme.cmd.psdt",
4960 FT_UINT8, BASE_HEX, NULL, 0xc0, NULL, HFILL}
4962 { &hf_nvme_cmd_cid,
4963 { "Command ID", "nvme.cmd.cid",
4964 FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
4966 { &hf_nvme_cmd_nsid,
4967 { "Namespace Id", "nvme.cmd.nsid",
4968 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
4970 { &hf_nvme_cmd_rsvd1,
4971 { "Reserved", "nvme.cmd.rsvd1",
4972 FT_BYTES, BASE_NONE, NULL, 0, NULL, HFILL}
4974 { &hf_nvme_cmd_mptr,
4975 { "Metadata Pointer", "nvme.cmd.mptr",
4976 FT_UINT64, BASE_HEX, NULL, 0, NULL, HFILL}
4978 { &hf_nvme_cmd_sgl,
4979 { "SGL1", "nvme.cmd.sgl1",
4980 FT_NONE, BASE_NONE, NULL, 0, NULL, HFILL}
4982 { &hf_nvme_cmd_sgl_desc_sub_type,
4983 { "Descriptor Sub Type", "nvme.cmd.sgl.subtype",
4984 FT_UINT8, BASE_HEX, NULL, 0x0f, NULL, HFILL}
4986 { &hf_nvme_cmd_sgl_desc_type,
4987 { "Descriptor Type", "nvme.cmd.sgl.type",
4988 FT_UINT8, BASE_HEX, NULL, 0xf0, NULL, HFILL}
4990 { &hf_nvme_cmd_sgl_desc_addr,
4991 { "Address", "nvme.cmd.sgl1.addr",
4992 FT_UINT64, BASE_HEX, NULL, 0, NULL, HFILL}
4994 { &hf_nvme_cmd_sgl_desc_addr_rsvd,
4995 { "Reserved", "nvme.cmd.sgl1.addr_rsvd",
4996 FT_UINT64, BASE_HEX, NULL, 0, NULL, HFILL}
4998 { &hf_nvme_cmd_sgl_desc_len,
4999 { "Length", "nvme.cmd.sgl1.len",
5000 FT_UINT32, BASE_DEC, NULL, 0, NULL, HFILL}
5002 { &hf_nvme_cmd_sgl_desc_key,
5003 { "Key", "nvme.cmd.sgl1.key",
5004 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
5006 { &hf_nvme_cmd_sgl_desc_rsvd,
5007 { "Reserved", "nvme.cmd.sgl1.rsvd",
5008 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
5010 { &hf_nvme_cmd_dword10,
5011 { "DWORD10", "nvme.cmd.dword10",
5012 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
5014 { &hf_nvme_cmd_dword11,
5015 { "DWORD11", "nvme.cmd.dword11",
5016 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
5018 { &hf_nvme_cmd_dword12,
5019 { "DWORD12", "nvme.cmd.dword12",
5020 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
5022 { &hf_nvme_cmd_dword13,
5023 { "DWORD13", "nvme.cmd.dword13",
5024 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
5026 { &hf_nvme_cmd_dword14,
5027 { "DWORD14", "nvme.cmd.dword14",
5028 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
5030 { &hf_nvme_cmd_dword15,
5031 { "DWORD15", "nvme.cmd.dword15",
5032 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
5034 { &hf_nvme_cmd_slba,
5035 { "Start LBA", "nvme.cmd.slba",
5036 FT_UINT64, BASE_HEX, NULL, 0, NULL, HFILL}
5038 { &hf_nvme_cmd_nlb,
5039 { "Absolute Number of Logical Blocks", "nvme.cmd.nlb",
5040 FT_UINT16, BASE_DEC_HEX, NULL, 0, NULL, HFILL}
5042 { &hf_nvme_cmd_rsvd2,
5043 { "Reserved", "nvme.cmd.rsvd2",
5044 FT_UINT16, BASE_HEX, NULL, 0x03ff, NULL, HFILL}
5046 { &hf_nvme_cmd_prinfo,
5047 { "Protection info fields",
5048 "nvme.cmd.prinfo",
5049 FT_UINT16, BASE_HEX, NULL, 0x0400, NULL, HFILL}
5051 { &hf_nvme_cmd_prinfo_prchk_lbrtag,
5052 { "check Logical block reference tag",
5053 "nvme.cmd.prinfo.lbrtag",
5054 FT_UINT16, BASE_HEX, NULL, 0x0400, NULL, HFILL}
5056 { &hf_nvme_cmd_prinfo_prchk_apptag,
5057 { "check application tag field",
5058 "nvme.cmd.prinfo.apptag",
5059 FT_UINT16, BASE_HEX, NULL, 0x0800, NULL, HFILL}
5061 { &hf_nvme_cmd_prinfo_prchk_guard,
5062 { "check guard field",
5063 "nvme.cmd.prinfo.guard",
5064 FT_UINT16, BASE_HEX, NULL, 0x1000, NULL, HFILL}
5066 { &hf_nvme_cmd_prinfo_pract,
5067 { "action",
5068 "nvme.cmd.prinfo.action",
5069 FT_UINT16, BASE_HEX, NULL, 0x2000, NULL, HFILL}
5071 { &hf_nvme_cmd_fua,
5072 { "Force Unit Access", "nvme.cmd.fua",
5073 FT_UINT16, BASE_HEX, NULL, 0x4000, NULL, HFILL}
5075 { &hf_nvme_cmd_lr,
5076 { "Limited Retry", "nvme.cmd.lr",
5077 FT_UINT16, BASE_HEX, NULL, 0x8000, NULL, HFILL}
5079 { &hf_nvme_cmd_eilbrt,
5080 { "Expected Initial Logical Block Reference Tag", "nvme.cmd.eilbrt",
5081 FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
5083 { &hf_nvme_cmd_elbat,
5084 { "Expected Logical Block Application Tag Mask", "nvme.cmd.elbat",
5085 FT_UINT16, BASE_HEX, NULL, 0, NULL, HFILL}
5087 { &hf_nvme_cmd_elbatm,
5088 { "Expected Logical Block Application Tag", "nvme.cmd.elbatm",
5089 FT_UINT16, BASE_HEX, NULL, 0, NULL, HFILL}
5091 { &hf_nvme_cmd_dsm,
5092 { "DSM Flags", "nvme.cmd.dsm",
5093 FT_NONE, BASE_NONE, NULL, 0, NULL, HFILL}
5095 { &hf_nvme_cmd_dsm_access_freq,
5096 { "Access frequency", "nvme.cmd.dsm.access_freq",
5097 FT_UINT8, BASE_HEX, NULL, 0x0f, NULL, HFILL}
5099 { &hf_nvme_cmd_dsm_access_lat,
5100 { "Access latency", "nvme.cmd.dsm.access_lat",
5101 FT_UINT8, BASE_HEX, NULL, 0x30, NULL, HFILL}
5103 { &hf_nvme_cmd_dsm_seq_req,
5104 { "Sequential Request", "nvme.cmd.dsm.seq_req",
5105 FT_UINT8, BASE_HEX, NULL, 0x40, NULL, HFILL}
5107 { &hf_nvme_cmd_dsm_incompressible,
5108 { "Incompressible", "nvme.cmd.dsm.incompressible",
5109 FT_UINT8, BASE_HEX, NULL, 0x40, NULL, HFILL}
5111 { &hf_nvme_cmd_rsvd3 ,
5112 { "Reserved", "nvme.cmd.rsvd3",
5113 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
5115 { &hf_nvme_identify_dword10[0],
5116 { "DWORD10", "nvme.cmd.identify.dword10",
5117 FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
5119 { &hf_nvme_identify_dword10[1],
5120 { "Controller or Namespace Structure (CNS)", "nvme.cmd.identify.dword10.cns",
5121 FT_UINT32, BASE_HEX, VALS(cns_table), 0xff, NULL, HFILL}
5123 { &hf_nvme_identify_dword10[2],
5124 { "Reserved", "nvme.cmd.identify.dword10.rsvd",
5125 FT_UINT32, BASE_HEX, NULL, 0xff00, NULL, HFILL}
5127 { &hf_nvme_identify_dword10[3],
5128 { "Controller Identifier (CNTID)", "nvme.cmd.identify.dword10.cntid",
5129 FT_UINT32, BASE_HEX, NULL, 0xffff0000, NULL, HFILL}
5131 { &hf_nvme_identify_dword11[0],
5132 { "DWORD11", "nvme.cmd.identify.dword11",
5133 FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
5135 { &hf_nvme_identify_dword11[1],
5136 { "NVM Set Identifier (NVMSETID)", "nvme.cmd.identify.dwrod11.nvmesetid",
5137 FT_UINT32, BASE_HEX, NULL, 0xffff, NULL, HFILL}
5139 { &hf_nvme_identify_dword11[2],
5140 { "Reserved", "nvme.cmd.identify.dword11.rsvd",
5141 FT_UINT32, BASE_HEX, NULL, 0xffff0000, NULL, HFILL}
5143 { &hf_nvme_identify_dword14[0],
5144 { "DWORD14", "nvme.cmd.identify.dword14",
5145 FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
5147 { &hf_nvme_identify_dword14[1],
5148 { "UUID Index", "nvme.cmd.identify.dword14.uuid_index",
5149 FT_UINT32, BASE_HEX, NULL, 0x7f, NULL, HFILL}
5151 { &hf_nvme_identify_dword14[2],
5152 { "UUID Index", "nvme.cmd.identify.dword14.rsvd",
5153 FT_UINT32, BASE_HEX, NULL, 0xffffff80, NULL, HFILL}
5155 /* get log page */
5156 { &hf_nvme_get_logpage_dword10[0],
5157 { "DWORD 10", "nvme.cmd.get_logpage.dword10",
5158 FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
5160 { &hf_nvme_get_logpage_dword10[1],
5161 { "Log Page Identifier (LID)", "nvme.cmd.get_logpage.dword10.id",
5162 FT_UINT32, BASE_CUSTOM, CF_FUNC(add_logpage_lid), 0xff, NULL, HFILL}
5164 { &hf_nvme_get_logpage_dword10[2],
5165 { "Log Specific Field (LSP)", "nvme.cmd.get_logpage.dword10.lsp",
5166 FT_UINT32, BASE_HEX, NULL, 0x1f00, NULL, HFILL}
5168 { &hf_nvme_get_logpage_dword10[3],
5169 { "Reserved", "nvme.cmd.get_logpage.dword10.rsvd",
5170 FT_UINT32, BASE_HEX, NULL, 0x6000, NULL, HFILL}
5172 { &hf_nvme_get_logpage_dword10[4],
5173 { "Retain Asynchronous Event (RAE)", "nvme.cmd.get_logpage.dword10.rae",
5174 FT_BOOLEAN, 32, NULL, 0x8000, NULL, HFILL}
5176 { &hf_nvme_get_logpage_dword10[5],
5177 { "Number of Dwords Lower (NUMDL)", "nvme.cmd.get_logpage.dword10.numdl",
5178 FT_UINT32, BASE_HEX, NULL, 0xffff0000, NULL, HFILL}
5180 { &hf_nvme_get_logpage_numd,
5181 { "Number of Dwords", "nvme.cmd.get_logpage.numd",
5182 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL}
5184 { &hf_nvme_get_logpage_dword11[0],
5185 { "DWORD 11", "nvme.cmd.get_logpage.dword11",
5186 FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
5188 { &hf_nvme_get_logpage_dword11[1],
5189 { "Number of Dwords Upper (NUMDU)", "nvme.cmd.get_logpage.dword11.numdu",
5190 FT_UINT32, BASE_HEX, NULL, 0xffff, NULL, HFILL}
5192 { &hf_nvme_get_logpage_dword11[2],
5193 { "Log Specific Identifier", "nvme.cmd.get_logpage.dword11.lsi",
5194 FT_UINT32, BASE_HEX, NULL, 0xffff0000, NULL, HFILL}
5196 { &hf_nvme_get_logpage_lpo,
5197 { "Log Page Offset (DWORD 12 and DWORD 13)", "nvme.cmd.get_logpage.lpo",
5198 FT_UINT64, BASE_DEC, NULL, 0x0, NULL, HFILL}
5200 { &hf_nvme_get_logpage_dword14[0],
5201 { "DWORD 14", "nvme.cmd.get_logpage.dword14",
5202 FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
5204 { &hf_nvme_get_logpage_dword14[1],
5205 { "UUID Index", "nvme.cmd.identify.get_logpage.dword14.uuid_index",
5206 FT_UINT32, BASE_HEX, NULL, 0x3f, NULL, HFILL}
5208 { &hf_nvme_get_logpage_dword14[2],
5209 { "Reserved", "nvme.cmd.identify.get_logpage.dword14.rsvd",
5210 FT_UINT32, BASE_HEX, NULL, 0xffffffc0, NULL, HFILL}
5212 /* Set Features */
5213 { &hf_nvme_set_features_dword10[0],
5214 { "DWORD 10", "nvme.cmd.set_features.dword10",
5215 FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
5217 { &hf_nvme_set_features_dword10[1],
5218 { "Feature Identifier", "nvme.cmd.set_features.dword10.fid",
5219 FT_UINT32, BASE_HEX, VALS(fid_table), 0xff, NULL, HFILL}
5221 { &hf_nvme_set_features_dword10[2],
5222 { "Reserved", "nvme.cmd.set_features.dword10.rsvd",
5223 FT_UINT32, BASE_HEX, NULL, 0x7fffff00, NULL, HFILL}
5225 { &hf_nvme_set_features_dword10[3],
5226 { "Save", "nvme.cmd.set_features.dword10.sv",
5227 FT_UINT32, BASE_HEX, NULL, 0x80000000, NULL, HFILL}
5229 { &hf_nvme_set_features_dword14[0],
5230 { "DWORD 14", "nvme.cmd.set_features.dword14",
5231 FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
5233 { &hf_nvme_set_features_dword14[1],
5234 { "UUID Index", "nvme.cmd.set_features.dword14.uuid",
5235 FT_UINT32, BASE_HEX, NULL, 0x7f, NULL, HFILL}
5237 { &hf_nvme_set_features_dword14[2],
5238 { "Reserved", "nvme.cmd.set_features.dword14.rsvd",
5239 FT_UINT32, BASE_HEX, NULL, 0xffffff80, NULL, HFILL}
5241 { &hf_nvme_cmd_set_features_dword11_arb[0],
5242 { "DWORD11", "nvme.cmd.set_features.dword11.arb",
5243 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
5245 { &hf_nvme_cmd_set_features_dword11_arb[1],
5246 { "Arbitration Burst", "nvme.cmd.set_features.dword11.arb.ab",
5247 FT_UINT32, BASE_HEX, NULL, 0x7, NULL, HFILL}
5249 { &hf_nvme_cmd_set_features_dword11_arb[3],
5250 { "Low Priority Weight", "nvme.cmd.set_features.dword11.arb.lpw",
5251 FT_UINT32, BASE_HEX, NULL, 0xff00, NULL, HFILL}
5253 { &hf_nvme_cmd_set_features_dword11_arb[4],
5254 { "Medium Priority Weight", "nvme.cmd.set_features.dword11.arb.mpw",
5255 FT_UINT32, BASE_HEX, NULL, 0xff0000, NULL, HFILL}
5257 { &hf_nvme_cmd_set_features_dword11_arb[5],
5258 { "High Priority Weight", "nvme.cmd.set_features.dword11.arb.hpw",
5259 FT_UINT32, BASE_HEX, NULL, 0xff000000, NULL, HFILL}
5261 { &hf_nvme_cmd_set_features_dword11_pm[0],
5262 { "DWORD11", "nvme.cmd.set_features.dword11.pm",
5263 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
5265 { &hf_nvme_cmd_set_features_dword11_pm[1],
5266 { "Power State", "nvme.cmd.set_features.dword11.pm.ps",
5267 FT_UINT32, BASE_HEX, NULL, 0x1f, NULL, HFILL}
5269 { &hf_nvme_cmd_set_features_dword11_pm[2],
5270 { "Work Hint", "nvme.cmd.set_features.dword11.pm.wh",
5271 FT_UINT32, BASE_HEX, NULL, 0xe0, NULL, HFILL}
5273 { &hf_nvme_cmd_set_features_dword11_pm[3],
5274 { "Work Hint", "nvme.cmd.set_features.dword11.pm.rsvd",
5275 FT_UINT32, BASE_HEX, NULL, 0xff000000, NULL, HFILL}
5277 { &hf_nvme_cmd_set_features_dword11_lbart[0],
5278 { "DWORD11", "nvme.cmd.set_features.dword11.lbart",
5279 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
5281 { &hf_nvme_cmd_set_features_dword11_lbart[1],
5282 { "DWORD11", "nvme.cmd.set_features.dword11.lbart.lbarn",
5283 FT_UINT32, BASE_HEX, NULL, 0x3f, NULL, HFILL}
5285 { &hf_nvme_cmd_set_features_dword11_lbart[2],
5286 { "DWORD11", "nvme.cmd.set_features.dword11.lbart.rsvd",
5287 FT_UINT32, BASE_HEX, NULL, 0xffffffc0, NULL, HFILL}
5289 { &hf_nvme_cmd_set_features_dword11_tt[0],
5290 { "DWORD11", "nvme.cmd.set_features.dword11.tt",
5291 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
5293 { &hf_nvme_cmd_set_features_dword11_tt[1],
5294 { "Temperature Threshold", "nvme.cmd.set_features.dword11.tt.tmpth",
5295 FT_UINT32, BASE_HEX, NULL, 0xffff, NULL, HFILL}
5297 { &hf_nvme_cmd_set_features_dword11_tt[2],
5298 { "Threshold Temperature Select", "nvme.cmd.set_features.dword11.tt.tmpsel",
5299 FT_UINT32, BASE_HEX, VALS(sf_tmpsel_table), 0xf0000, NULL, HFILL}
5301 { &hf_nvme_cmd_set_features_dword11_tt[3],
5302 { "Threshold Type Select", "nvme.cmd.set_features.dword11.tt.thpsel",
5303 FT_UINT32, BASE_HEX, VALS(sf_thpsel_table), 0x300000, NULL, HFILL}
5305 { &hf_nvme_cmd_set_features_dword11_tt[4],
5306 { "Reserved", "nvme.cmd.set_features.dword11.tt.rsvd",
5307 FT_UINT32, BASE_HEX, NULL, 0xc00000, NULL, HFILL}
5309 { &hf_nvme_cmd_set_features_dword11_erec[0],
5310 { "DWORD11", "nvme.cmd.set_features.dword11.erec",
5311 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
5313 { &hf_nvme_cmd_set_features_dword11_erec[1],
5314 { "Time Limited Error Recovery (100 ms units)", "nvme.cmd.set_features.dword11.erec.tler",
5315 FT_UINT32, BASE_HEX, NULL, 0xffff, NULL, HFILL}
5317 { &hf_nvme_cmd_set_features_dword11_erec[2],
5318 { "Deallocated or Unwritten Logical Block Error Enable", "nvme.cmd.set_features.dword11.erec.dulbe",
5319 FT_BOOLEAN, 32, NULL, 0x10000, NULL, HFILL}
5321 { &hf_nvme_cmd_set_features_dword11_erec[3],
5322 { "Reserved", "nvme.cmd.set_features.dword11.erec.rsvd",
5323 FT_UINT32, BASE_HEX, NULL, 0xfe0000, NULL, HFILL}
5325 { &hf_nvme_cmd_set_features_dword11_vwce[0],
5326 { "DWORD11", "nvme.cmd.set_features.dword11.vwce",
5327 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
5329 { &hf_nvme_cmd_set_features_dword11_vwce[1],
5330 { "Volatile Write Cache Enable", "nvme.cmd.set_features.dword11.vwce.wce",
5331 FT_BOOLEAN, 32, NULL, 0x1, NULL, HFILL}
5333 { &hf_nvme_cmd_set_features_dword11_vwce[2],
5334 { "Volatile Write Cache Enable", "nvme.cmd.set_features.dword11.vwce.rsvd",
5335 FT_UINT32, BASE_HEX, NULL, 0xfffffffe, NULL, HFILL}
5337 { &hf_nvme_cmd_set_features_dword11_nq[0],
5338 { "DWORD11", "nvme.cmd.set_features.dword11.nq",
5339 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
5341 { &hf_nvme_cmd_set_features_dword11_nq[1],
5342 { "Number of IO Submission Queues Requested", "nvme.cmd.set_features.dword11.nq.nsqr",
5343 FT_UINT32, BASE_CUSTOM, CF_FUNC(add_nvme_queues), 0xffff, NULL, HFILL}
5345 { &hf_nvme_cmd_set_features_dword11_nq[2],
5346 { "Number of IO Completion Queues Requested", "nvme.cmd.set_features.dword11.nq.ncqr",
5347 FT_UINT32, BASE_CUSTOM, CF_FUNC(add_nvme_queues), 0xffff0000, NULL, HFILL}
5349 { &hf_nvme_cmd_set_features_dword11_irqc[0],
5350 { "DWORD11", "nvme.cmd.set_features.dword11.irqc",
5351 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
5353 { &hf_nvme_cmd_set_features_dword11_irqc[1],
5354 { "Aggregation Threshold", "nvme.cmd.set_features.dword11.irqc.thr",
5355 FT_UINT32, BASE_HEX, NULL, 0xffff, NULL, HFILL}
5357 { &hf_nvme_cmd_set_features_dword11_irqc[2],
5358 { "Aggregation Time (100 us units)", "nvme.cmd.set_features.dword11.irqc.time",
5359 FT_UINT32, BASE_HEX, NULL, 0xffff0000, NULL, HFILL}
5361 { &hf_nvme_cmd_set_features_dword11_irqv[0],
5362 { "DWORD11", "nvme.cmd.set_features.dword11.irqv",
5363 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
5365 { &hf_nvme_cmd_set_features_dword11_irqv[1],
5366 { "IRQ Vector", "nvme.cmd.set_features.dword11.irqv.iv",
5367 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
5369 { &hf_nvme_cmd_set_features_dword11_irqv[2],
5370 { "Coalescing Disable", "nvme.cmd.set_features.dword11.irqv.cd",
5371 FT_BOOLEAN, 32, NULL, 0x1ffff, NULL, HFILL}
5373 { &hf_nvme_cmd_set_features_dword11_irqv[3],
5374 { "Reserved", "nvme.cmd.set_features.dword11.irqv.rsvd",
5375 FT_UINT32, BASE_HEX, NULL, 0xfffe0000, NULL, HFILL}
5377 { &hf_nvme_cmd_set_features_dword11_wan[0],
5378 { "DWORD11", "nvme.cmd.set_features.dword11.wan",
5379 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
5381 { &hf_nvme_cmd_set_features_dword11_wan[1],
5382 { "Disable Normal", "nvme.cmd.set_features.dword11.wan.dn",
5383 FT_BOOLEAN, 32, NULL, 0x1, NULL, HFILL}
5385 { &hf_nvme_cmd_set_features_dword11_wan[2],
5386 { "Reserved", "nvme.cmd.set_features.dword11.wan.rsvd",
5387 FT_UINT32, BASE_HEX, NULL, 0xfffffffe, NULL, HFILL}
5389 { &hf_nvme_cmd_set_features_dword11_aec[0],
5390 { "DWORD11", "nvme.cmd.set_features.dword11.aec",
5391 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
5393 { &hf_nvme_cmd_set_features_dword11_aec[1],
5394 { "SMART and Health Critical Warnings Bitmask", "nvme.cmd.set_features.dword11.aec.smart",
5395 FT_UINT32, BASE_HEX, NULL, 0xff, NULL, HFILL}
5397 { &hf_nvme_cmd_set_features_dword11_aec[2],
5398 { "Namespace Attribute Notices", "nvme.cmd.set_features.dword11.aec.ns",
5399 FT_BOOLEAN, 32, NULL, 0x100, NULL, HFILL}
5401 { &hf_nvme_cmd_set_features_dword11_aec[3],
5402 { "Firmware Activation Notices", "nvme.cmd.set_features.dword11.aec.fwa",
5403 FT_BOOLEAN, 32, NULL, 0x200, NULL, HFILL}
5405 { &hf_nvme_cmd_set_features_dword11_aec[4],
5406 { "Telemetry Log Notices", "nvme.cmd.set_features.dword11.aec.tel",
5407 FT_BOOLEAN, 32, NULL, 0x400, NULL, HFILL}
5409 { &hf_nvme_cmd_set_features_dword11_aec[5],
5410 { "ANA Change Notices", "nvme.cmd.set_features.dword11.aec.ana",
5411 FT_BOOLEAN, 32, NULL, 0x800, NULL, HFILL}
5413 { &hf_nvme_cmd_set_features_dword11_aec[6],
5414 { "Predictable Latency Event Aggregate Log Change Notices", "nvme.cmd.set_features.dword11.aec.plat",
5415 FT_BOOLEAN, 32, NULL, 0x1000, NULL, HFILL}
5417 { &hf_nvme_cmd_set_features_dword11_aec[7],
5418 { "LBA Status Information Notices", "nvme.cmd.set_features.dword11.aec.lba",
5419 FT_BOOLEAN, 32, NULL, 0x2000, NULL, HFILL}
5421 { &hf_nvme_cmd_set_features_dword11_aec[8],
5422 { "Endurance Group Event Aggregate Log Change Notices", "nvme.cmd.set_features.dword11.aec.eg",
5423 FT_BOOLEAN, 32, NULL, 0x4000, NULL, HFILL}
5425 { &hf_nvme_cmd_set_features_dword11_aec[9],
5426 { "Reserved", "nvme.cmd.set_features.dword11.aec.rsvd",
5427 FT_UINT32, BASE_HEX, NULL, 0x7fff8000, NULL, HFILL}
5429 { &hf_nvme_cmd_set_features_dword11_aec[10],
5430 { "Discovery Log Page Change Notification", "nvme.cmd.set_features.dword11.aec.disc",
5431 FT_BOOLEAN, 32, NULL, 0x80000000, NULL, HFILL}
5433 { &hf_nvme_cmd_set_features_dword11_apst[0],
5434 { "DWORD11", "nvme.cmd.set_features.dword11.apst",
5435 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
5437 { &hf_nvme_cmd_set_features_dword11_apst[1],
5438 { "Autonomous Power State Transition Enable", "nvme.cmd.set_features.dword11.apst.apste",
5439 FT_BOOLEAN, 32, NULL, 0x1, NULL, HFILL}
5441 { &hf_nvme_cmd_set_features_dword11_apst[2],
5442 { "Reserved", "nvme.cmd.set_features.dword11.apst.rsvd",
5443 FT_UINT32, BASE_HEX, NULL, 0xfffffffe, NULL, HFILL}
5445 { &hf_nvme_cmd_set_features_dword11_kat[0],
5446 { "DWORD11", "nvme.cmd.set_features.dword11.kat",
5447 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
5449 { &hf_nvme_cmd_set_features_dword11_kat[1],
5450 { "Keep Alive Timeout", "nvme.cmd.set_features.dword11.kat.kato",
5451 FT_UINT32, BASE_DEC|BASE_UNIT_STRING, UNS(&units_milliseconds), 0, NULL, HFILL}
5453 { &hf_nvme_cmd_set_features_dword11_hctm[0],
5454 { "DWORD11", "nvme.cmd.set_features.dword11.hctm",
5455 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
5457 { &hf_nvme_cmd_set_features_dword11_hctm[1],
5458 { "Thermal Management Temperature 2 (K)", "nvme.cmd.set_features.dword11.hctm.tmt2",
5459 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
5461 { &hf_nvme_cmd_set_features_dword11_hctm[2],
5462 { "Thermal Management Temperature 1 (K)", "nvme.cmd.set_features.dword11.hctm.tmt1",
5463 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
5465 { &hf_nvme_cmd_set_features_dword11_nops[0],
5466 { "DWORD11", "nvme.cmd.set_features.dword11.nops",
5467 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
5469 { &hf_nvme_cmd_set_features_dword11_nops[1],
5470 { "Non-Operational Power State Permissive Mode Enable", "nvme.cmd.set_features.dword11.nops.noppme",
5471 FT_UINT32, BASE_HEX, NULL, 0x1, NULL, HFILL}
5473 { &hf_nvme_cmd_set_features_dword11_nops[2],
5474 { "Reserved", "nvme.cmd.set_features.dword11.nops.rsvd",
5475 FT_UINT32, BASE_HEX, NULL, 0xfffffffe, NULL, HFILL}
5477 { &hf_nvme_cmd_set_features_dword11_rrl[0],
5478 { "DWORD11", "nvme.cmd.set_features.dword11.rrl",
5479 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
5481 { &hf_nvme_cmd_set_features_dword11_rrl[1],
5482 { "NVM Set Identifier", "nvme.cmd.set_features.dword11.rrl.nvmsetid",
5483 FT_UINT32, BASE_HEX, NULL, 0xffff, NULL, HFILL}
5485 { &hf_nvme_cmd_set_features_dword11_rrl[2],
5486 { "Reserved", "nvme.cmd.set_features.dword11.rrl.rsvd",
5487 FT_UINT32, BASE_HEX, NULL, 0xffff0000, NULL, HFILL}
5489 { &hf_nvme_cmd_set_features_dword12_rrl[0],
5490 { "DWORD12", "nvme.cmd.set_features.dword12.rrl",
5491 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
5493 { &hf_nvme_cmd_set_features_dword12_rrl[1],
5494 { "Read Recovery Level", "nvme.cmd.set_features.dword12.rrl.rrl",
5495 FT_UINT32, BASE_HEX, NULL, 0xf, NULL, HFILL}
5497 { &hf_nvme_cmd_set_features_dword12_rrl[2],
5498 { "Reserved", "nvme.cmd.set_features.dword12.rrl.rsvd",
5499 FT_UINT32, BASE_HEX, NULL, 0xfffffff0, NULL, HFILL}
5501 { &hf_nvme_cmd_set_features_dword11_plmc[0],
5502 { "DWORD11", "nvme.cmd.set_features.dword11.plmc",
5503 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
5505 { &hf_nvme_cmd_set_features_dword11_plmc[1],
5506 { "NVM Set Identifier", "nvme.cmd.set_features.dword11.plmc.nvmsetid",
5507 FT_UINT32, BASE_HEX, NULL, 0xffff, NULL, HFILL}
5509 { &hf_nvme_cmd_set_features_dword11_plmc[2],
5510 { "Reserved", "nvme.cmd.set_features.dword11.plmc.rsvd",
5511 FT_UINT32, BASE_HEX, NULL, 0xffff0000, NULL, HFILL}
5513 { &hf_nvme_cmd_set_features_dword12_plmc[0],
5514 { "DWORD12", "nvme.cmd.set_features.dword12.plmc",
5515 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
5517 { &hf_nvme_cmd_set_features_dword12_plmc[1],
5518 { "Predictable Latency Enable", "nvme.cmd.set_features.dword12.plmc.ple",
5519 FT_BOOLEAN, 32, NULL, 0x1, NULL, HFILL}
5521 { &hf_nvme_cmd_set_features_dword12_plmc[2],
5522 { "Reserved", "nvme.cmd.set_features.dword12.plmc.rsvd",
5523 FT_UINT32, BASE_HEX, NULL, 0xfffffffe, NULL, HFILL}
5525 { &hf_nvme_cmd_set_features_dword11_plmw[0],
5526 { "DWORD11", "nvme.cmd.set_features.dword11.plmw",
5527 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
5529 { &hf_nvme_cmd_set_features_dword11_plmw[1],
5530 { "NVM Set Identifier", "nvme.cmd.set_features.dword11.plmw.nvmsetid",
5531 FT_UINT32, BASE_HEX, NULL, 0xffff, NULL, HFILL}
5533 { &hf_nvme_cmd_set_features_dword11_plmw[2],
5534 { "Reserved", "nvme.cmd.set_features.dword11.plmw.rsvd",
5535 FT_UINT32, BASE_HEX, NULL, 0xffff0000, NULL, HFILL}
5537 { &hf_nvme_cmd_set_features_dword12_plmw[0],
5538 { "DWORD12", "nvme.cmd.set_features.dword12.plmw",
5539 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
5541 { &hf_nvme_cmd_set_features_dword12_plmw[1],
5542 { "DWORD12", "nvme.cmd.set_features.dword12.plmw.ws",
5543 FT_UINT32, BASE_HEX, VALS(sf_ws_table), 0x7, NULL, HFILL}
5545 { &hf_nvme_cmd_set_features_dword12_plmw[2],
5546 { "Reserved", "nvme.cmd.set_features.dword12.plmw.rsvd",
5547 FT_UINT32, BASE_HEX, NULL, 0xfffffff8, NULL, HFILL}
5549 { &hf_nvme_cmd_set_features_dword11_lbasi[0],
5550 { "DWORD11", "nvme.cmd.set_features.dword11.lbasi",
5551 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
5553 { &hf_nvme_cmd_set_features_dword11_lbasi[1],
5554 { "LBA Status Information Report Interval (100 ms)", "nvme.cmd.set_features.dword11.lbasi.lsiri",
5555 FT_UINT32, BASE_HEX, NULL, 0xffff, NULL, HFILL}
5557 { &hf_nvme_cmd_set_features_dword11_lbasi[2],
5558 { "LBA Status Information Poll Interval (100 ms)", "nvme.cmd.set_features.dword11.lbasi.lsipi",
5559 FT_UINT32, BASE_HEX, NULL, 0xffff0000, NULL, HFILL}
5561 { &hf_nvme_cmd_set_features_dword11_san[0],
5562 { "DWORD11", "nvme.cmd.set_features.dword11.san",
5563 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
5565 { &hf_nvme_cmd_set_features_dword11_san[1],
5566 { "No-Deallocate Response Mode", "nvme.cmd.set_features.dword11.san.nodrm",
5567 FT_BOOLEAN, 32, NULL, 0x1, NULL, HFILL}
5569 { &hf_nvme_cmd_set_features_dword11_san[2],
5570 { "Reserved", "nvme.cmd.set_features.dword11.san.rsvd",
5571 FT_UINT32, BASE_HEX, NULL, 0xfffffffe, NULL, HFILL}
5573 { &hf_nvme_cmd_set_features_dword11_eg[0],
5574 { "DWORD11", "nvme.cmd.set_features.dword11.eg",
5575 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
5577 { &hf_nvme_cmd_set_features_dword11_eg[1],
5578 { "Endurance Group Identifier", "nvme.cmd.set_features.dword11.eg.endgid",
5579 FT_UINT32, BASE_HEX, NULL, 0xffff, NULL, HFILL}
5581 { &hf_nvme_cmd_set_features_dword11_eg[2],
5582 { "Endurance Group Critical Warnings Bitmask", "nvme.cmd.set_features.dword11.eg.egcw",
5583 FT_UINT32, BASE_HEX, NULL, 0xff0000, NULL, HFILL}
5585 { &hf_nvme_cmd_set_features_dword11_eg[3],
5586 { "Reserved", "nvme.cmd.set_features.dword11.eg.rsvd",
5587 FT_UINT32, BASE_HEX, NULL, 0xff000000, NULL, HFILL}
5589 { &hf_nvme_cmd_set_features_dword11_swp[0],
5590 { "DWORD11", "nvme.cmd.set_features.dword11.swp",
5591 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
5593 { &hf_nvme_cmd_set_features_dword11_swp[1],
5594 { "Pre-boot Software Load Count", "nvme.cmd.set_features.dword11.swp.pbslc",
5595 FT_UINT32, BASE_HEX, NULL, 0xff, NULL, HFILL}
5597 { &hf_nvme_cmd_set_features_dword11_swp[2],
5598 { "Reserved", "nvme.cmd.set_features.dword11.swp.rsvd",
5599 FT_UINT32, BASE_HEX, NULL, 0xffffff00, NULL, HFILL}
5601 { &hf_nvme_cmd_set_features_dword11_hid[0],
5602 { "DWORD11", "nvme.cmd.set_features.dword11.hid",
5603 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
5605 { &hf_nvme_cmd_set_features_dword11_hid[1],
5606 { "Enable Extended Host Identifier", "nvme.cmd.set_features.dword11.hid.exhid",
5607 FT_BOOLEAN, 32, NULL, 0x1, NULL, HFILL}
5609 { &hf_nvme_cmd_set_features_dword11_hid[2],
5610 { "Reserved", "nvme.cmd.set_features.dword11.hid.rsvd",
5611 FT_UINT32, BASE_HEX, NULL, 0xfffffffe, NULL, HFILL}
5613 { &hf_nvme_cmd_set_features_dword11_rsrvn[0],
5614 { "DWORD11", "nvme.cmd.set_features.dword11.rsrvn",
5615 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
5617 { &hf_nvme_cmd_set_features_dword11_rsrvn[1],
5618 { "Reserved", "nvme.cmd.set_features.dword11.rsrvn.rsvd0",
5619 FT_UINT32, BASE_HEX, NULL, 0x1, NULL, HFILL}
5621 { &hf_nvme_cmd_set_features_dword11_rsrvn[2],
5622 { "Mask Registration Preempted Notification" , "nvme.cmd.set_features.dword11.rsrvn.regpre",
5623 FT_BOOLEAN, 32, NULL, 0x2, NULL, HFILL}
5625 { &hf_nvme_cmd_set_features_dword11_rsrvn[3],
5626 { "Mask Reservation Released Notification", "nvme.cmd.set_features.dword11.rsrvn.resrel",
5627 FT_BOOLEAN, 32, NULL, 0x4, NULL, HFILL}
5629 { &hf_nvme_cmd_set_features_dword11_rsrvn[4],
5630 { "Mask Reservation Preempted Notification", "nvme.cmd.set_features.dword11.rsrvn.resrpe",
5631 FT_BOOLEAN, 32, NULL, 0x8, NULL, HFILL}
5633 { &hf_nvme_cmd_set_features_dword11_rsrvn[5],
5634 { "Reserved", "nvme.cmd.set_features.dword11.rsrvn.rsvd1",
5635 FT_UINT32, BASE_HEX, NULL, 0xfffff0, NULL, HFILL}
5637 { &hf_nvme_cmd_set_features_dword11_rsrvp[0],
5638 { "DWORD11", "nvme.cmd.set_features.dword11.rsrvp",
5639 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
5641 { &hf_nvme_cmd_set_features_dword11_rsrvp[1],
5642 { "Persist Through Power Loss", "nvme.cmd.set_features.dword11.rsrvp.ptpl",
5643 FT_BOOLEAN, 32, NULL, 0x1, NULL, HFILL}
5645 { &hf_nvme_cmd_set_features_dword11_rsrvp[2],
5646 { "Reserved", "nvme.cmd.set_features.dword11.rsrvp.rsvd",
5647 FT_UINT32, BASE_HEX, NULL, 0xfffffffe, NULL, HFILL}
5649 { &hf_nvme_cmd_set_features_dword11_nswp[0],
5650 { "DWORD11", "nvme.cmd.set_features.dword11.nswp",
5651 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
5653 { &hf_nvme_cmd_set_features_dword11_nswp[1],
5654 { "DWORD11", "nvme.cmd.set_features.dword11.nswp.wps",
5655 FT_UINT32, BASE_HEX, VALS(sf_wps), 0x7, NULL, HFILL}
5657 { &hf_nvme_cmd_set_features_dword11_nswp[2],
5658 { "DWORD11", "nvme.cmd.set_features.dword11.nswp.rsvd",
5659 FT_UINT32, BASE_HEX, NULL, 0xfffffff8, NULL, HFILL}
5661 /* Set Features Transfers */
5662 { &hf_nvme_set_features_tr_lbart,
5663 { "LBA Range Structure", "nvme.set_features.lbart",
5664 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
5666 { &hf_nvme_set_features_tr_lbart_type,
5667 { "Type", "nvme.set_features.lbart.type",
5668 FT_UINT8, BASE_HEX, VALS(sf_lbart_type_table), 0x0, NULL, HFILL}
5670 { &hf_nvme_set_features_tr_lbart_attr[0],
5671 { "Attributes", "nvme.set_features.lbart.attr",
5672 FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
5674 { &hf_nvme_set_features_tr_lbart_attr[1],
5675 { "LBA Range may be overwritten", "nvme.set_features.lbart.attr.ovw",
5676 FT_BOOLEAN, 8, NULL, 0x1, NULL, HFILL}
5678 { &hf_nvme_set_features_tr_lbart_attr[2],
5679 { "LBA Range shall be hidden from OS/EFI/BIOS", "nvme.set_features.lbart.attr.hid",
5680 FT_BOOLEAN, 8, NULL, 0x2, NULL, HFILL}
5682 { &hf_nvme_set_features_tr_lbart_attr[3],
5683 { "Reserved", "nvme.set_features.lbart.attr.rsvd",
5684 FT_UINT8, BASE_HEX, NULL, 0xfc, NULL, HFILL}
5686 { &hf_nvme_set_features_tr_lbart_rsvd0,
5687 { "Reserved", "nvme.set_features.lbart.rsvd0",
5688 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
5690 { &hf_nvme_set_features_tr_lbart_slba,
5691 { "Starting LBA", "nvme.set_features.lbart.slba",
5692 FT_UINT64, BASE_HEX, NULL, 0x0, NULL, HFILL}
5694 { &hf_nvme_set_features_tr_lbart_nlb,
5695 { "Number of Logical Blocks", "nvme.set_features.lbart.nlb",
5696 FT_UINT64, BASE_HEX, NULL, 0x0, NULL, HFILL}
5698 { &hf_nvme_set_features_tr_lbart_guid,
5699 { "Unique Identifier", "nvme.set_features.lbart.guid",
5700 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
5702 { &hf_nvme_set_features_tr_lbart_rsvd1,
5703 { "Reserved", "nvme.set_features.lbart.rsvd1",
5704 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
5706 { &hf_nvme_set_features_tr_apst[0],
5707 { "Autonomous Power State Transition Structure", "nvme.set_features.lbart.apst",
5708 FT_UINT64, BASE_HEX, NULL, 0x0, NULL, HFILL}
5710 { &hf_nvme_set_features_tr_apst[1],
5711 { "Reserved", "nvme.set_features.lbart.apst.rsvd0",
5712 FT_UINT64, BASE_HEX, NULL, 0x7, NULL, HFILL}
5714 { &hf_nvme_set_features_tr_apst[2],
5715 { "Idle Transition Power State", "nvme.set_features.lbart.apst.itps",
5716 FT_UINT64, BASE_HEX, NULL, 0xf8, NULL, HFILL}
5718 { &hf_nvme_set_features_tr_apst[3],
5719 { "Idle Time Prior to Transition (us)", "nvme.set_features.lbart.apst.itpt",
5720 FT_UINT64, BASE_HEX, NULL, 0xfffff00, NULL, HFILL}
5722 { &hf_nvme_set_features_tr_apst[4],
5723 { "Reserved", "nvme.set_features.lbart.apst.rsvd1",
5724 FT_UINT64, BASE_HEX, NULL, 0xffffffff00000000, NULL, HFILL}
5726 { &hf_nvme_set_features_tr_tst[0],
5727 { "Timestamp Structure", "nvme.set_features.tst",
5728 FT_UINT64, BASE_HEX, NULL, 0x0, NULL, HFILL}
5730 { &hf_nvme_set_features_tr_tst[1],
5731 { "Timestamp (milliseconds since 01-Jan-1970)", "nvme.set_features.tst.ms",
5732 FT_UINT64, BASE_HEX, NULL, 0xffffffffffff, NULL, HFILL}
5734 { &hf_nvme_set_features_tr_tst[2],
5735 { "Reserved", "nvme.set_features.tst.rsvd",
5736 FT_UINT64, BASE_HEX, NULL, 0xffff000000000000, NULL, HFILL}
5738 { &hf_nvme_set_features_tr_plmc,
5739 { "Reserved", "nvme.set_features.plmc",
5740 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
5742 { &hf_nvme_set_features_tr_plmc_ee[0],
5743 { "Enable Event", "nvme.set_features.plmc.ee",
5744 FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
5746 { &hf_nvme_set_features_tr_plmc_ee[1],
5747 { "DTWIN Reads Warning", "nvme.set_features.plmc.ee.dtwinr",
5748 FT_BOOLEAN, 16, NULL, 0x1, NULL, HFILL}
5750 { &hf_nvme_set_features_tr_plmc_ee[2],
5751 { "DTWIN Writes Warning", "nvme.set_features.plmc.ee.dtwinw",
5752 FT_BOOLEAN, 16, NULL, 0x2, NULL, HFILL}
5754 { &hf_nvme_set_features_tr_plmc_ee[3],
5755 { "DTWIN Time Warning", "nvme.set_features.plmc.ee.dtwint",
5756 FT_BOOLEAN, 16, NULL, 0x4, NULL, HFILL}
5758 { &hf_nvme_set_features_tr_plmc_ee[4],
5759 { "Reserved", "nvme.set_features.plmc.ee.rsvd",
5760 FT_UINT16, BASE_HEX, NULL, 0x3ff8, NULL, HFILL}
5762 { &hf_nvme_set_features_tr_plmc_ee[5],
5763 { "DTWIN to NDWIN transition due to typical or maximum value exceeded", "nvme.set_features.plmc.ee.ndtwindv",
5764 FT_BOOLEAN, 16, NULL, 0x4000, NULL, HFILL}
5766 { &hf_nvme_set_features_tr_plmc_ee[6],
5767 { "DTWIN to NDWIN transition due to Deterministic Excursion", "nvme.set_features.plmc.ee.ndtwindde",
5768 FT_BOOLEAN, 16, NULL, 0x8000, NULL, HFILL}
5770 { &hf_nvme_set_features_tr_plmc_rsvd0,
5771 { "Reserved", "nvme.set_features.plmc.rsvd0",
5772 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
5774 { &hf_nvme_set_features_tr_plmc_dtwinrt,
5775 { "DTWIN Reads Threshold", "nvme.set_features.plmc.dtwinrt",
5776 FT_UINT64, BASE_HEX, NULL, 0x0, NULL, HFILL}
5778 { &hf_nvme_set_features_tr_plmc_dtwinwt,
5779 { "DTWIN Writes Threshold", "nvme.set_features.plmc.dtwinwt",
5780 FT_UINT64, BASE_HEX, NULL, 0x0, NULL, HFILL}
5782 { &hf_nvme_set_features_tr_plmc_dtwintt,
5783 { "DTWIN Time Threshold", "nvme.set_features.plmc.dtwintt",
5784 FT_UINT64, BASE_HEX, NULL, 0x0, NULL, HFILL}
5786 { &hf_nvme_set_features_tr_plmc_rsvd1,
5787 { "Reserved", "nvme.set_features.plmc.rsvd1",
5788 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
5790 { &hf_nvme_set_features_tr_hbs,
5791 { "Host Behavior Support Structure", "nvme.set_features.hbs",
5792 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
5794 { &hf_nvme_set_features_tr_hbs_acre,
5795 { "Advanced Command Retry Enable", "nvme.set_features.hbs.acre",
5796 FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
5798 { &hf_nvme_set_features_tr_hbs_rsvd,
5799 { "Reserved", "nvme.set_features.hbs.rsvd",
5800 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
5802 /* Get Features */
5803 { &hf_nvme_get_features_dword10[0],
5804 { "DWORD 10", "nvme.cmd.get_features.dword10",
5805 FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
5807 { &hf_nvme_get_features_dword10[1],
5808 { "Feature Identifier", "nvme.cmd.get_features.dword10.fid",
5809 FT_UINT32, BASE_HEX, VALS(fid_table), 0xff, NULL, HFILL}
5811 { &hf_nvme_get_features_dword10[2],
5812 { "Select", "nvme.cmd.set_features.dword10.sel",
5813 FT_UINT32, BASE_HEX, VALS(sel_table), 0x700, NULL, HFILL}
5815 { &hf_nvme_get_features_dword10[3],
5816 { "Reserved", "nvme.cmd.get_features.dword10.rsvd",
5817 FT_UINT32, BASE_HEX, NULL, 0xfffff800, NULL, HFILL}
5819 { &hf_nvme_get_features_dword14[0],
5820 { "DWORD 14", "nvme.cmd.get_features.dword14",
5821 FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
5823 { &hf_nvme_get_features_dword14[1],
5824 { "UUID Index", "nvme.cmd.get_features.dword14.uuid",
5825 FT_UINT32, BASE_HEX, NULL, 0x7f, NULL, HFILL}
5827 { &hf_nvme_get_features_dword14[2],
5828 { "Reserved", "nvme.cmd.get_features.dword14.rsvd",
5829 FT_UINT32, BASE_HEX, NULL, 0xffffff80, NULL, HFILL}
5831 { &hf_nvme_cmd_get_features_dword11_rrl[0],
5832 { "DWORD11", "nvme.cmd.get_features.dword11.rrl",
5833 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
5835 { &hf_nvme_cmd_get_features_dword11_rrl[1],
5836 { "NVM Set Identifier", "nvme.cmd_get_features.dword11.rrl.nvmsetid",
5837 FT_UINT32, BASE_HEX, NULL, 0xffff, NULL, HFILL}
5839 { &hf_nvme_cmd_get_features_dword11_rrl[2],
5840 { "Reserved", "nvme.cmd.get_features.dword11.rrl.rsvd",
5841 FT_UINT32, BASE_HEX, NULL, 0xffff0000, NULL, HFILL}
5843 { &hf_nvme_cmd_get_features_dword11_plmc[0],
5844 { "DWORD11", "nvme.cmd.get_features.dword11.plmc",
5845 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
5847 { &hf_nvme_cmd_get_features_dword11_plmc[1],
5848 { "NVM Set Identifier", "nvme.cmd.get_features.dword11.plmc.nvmsetid",
5849 FT_UINT32, BASE_HEX, NULL, 0xffff, NULL, HFILL}
5851 { &hf_nvme_cmd_get_features_dword11_plmc[2],
5852 { "Reserved", "nvme.cmd.get_features.dword11.plmc.rsvd",
5853 FT_UINT32, BASE_HEX, NULL, 0xffff0000, NULL, HFILL}
5855 { &hf_nvme_cmd_get_features_dword11_plmw[0],
5856 { "DWORD11", "nvme.cmd.get_features.dword11.plmw",
5857 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
5859 { &hf_nvme_cmd_get_features_dword11_plmw[1],
5860 { "NVM Set Identifier", "nvme.cmd.get_features.dword11.plmw.nvmsetid",
5861 FT_UINT32, BASE_HEX, NULL, 0xffff, NULL, HFILL}
5863 { &hf_nvme_cmd_get_features_dword11_plmw[2],
5864 { "Reserved", "nvme.cmd.get_features.dword11.plmw.rsvd",
5865 FT_UINT32, BASE_HEX, NULL, 0xffff0000, NULL, HFILL}
5867 /* Identify NS response */
5868 { &hf_nvme_identify_ns_nsze,
5869 { "Namespace Size (NSZE)", "nvme.cmd.identify.ns.nsze",
5870 FT_UINT64, BASE_DEC_HEX, NULL, 0x0, NULL, HFILL}
5872 { &hf_nvme_identify_ns_ncap,
5873 { "Namespace Capacity (NCAP)", "nvme.cmd.identify.ns.ncap",
5874 FT_UINT64, BASE_HEX, NULL, 0x0, NULL, HFILL}
5876 { &hf_nvme_identify_ns_nuse,
5877 { "Namespace Utilization (NUSE)", "nvme.cmd.identify.ns.nuse",
5878 FT_UINT64, BASE_HEX, NULL, 0x0, NULL, HFILL}
5880 { &hf_nvme_identify_ns_nsfeat,
5881 { "Namespace Features (NSFEAT)", "nvme.cmd.identify.ns.nsfeat",
5882 FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
5884 { &hf_nvme_identify_ns_nlbaf,
5885 { "Number of LBA Formats (NLBAF)", "nvme.cmd.identify.ns.nlbaf",
5886 FT_UINT8, BASE_DEC_HEX, NULL, 0x0, NULL, HFILL}
5888 { &hf_nvme_identify_ns_flbas,
5889 { "Formatted LBA Size (FLBAS)", "nvme.cmd.identify.ns.flbas",
5890 FT_UINT8, BASE_DEC_HEX, NULL, 0x0, NULL, HFILL}
5892 { &hf_nvme_identify_ns_mc,
5893 { "Metadata Capabilities (MC)", "nvme.cmd.identify.ns.mc",
5894 FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
5896 { &hf_nvme_identify_ns_dpc,
5897 { "End-to-end Data Protection Capabilities (DPC)", "nvme.cmd.identify.ns.dpc",
5898 FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
5900 { &hf_nvme_identify_ns_dps,
5901 { "End-to-end Data Protection Type Settings (DPS)", "nvme.cmd.identify.ns.dps",
5902 FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
5904 { &hf_nvme_identify_ns_nmic,
5905 { "Namespace Multi-path I/O and Namespace Sharing Capabilities (NMIC)",
5906 "nvme.cmd.identify.ns.nmic", FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
5908 { &hf_nvme_identify_ns_nguid,
5909 { "Namespace Globally Unique Identifier (NGUID)", "nvme.cmd.identify.ns.nguid",
5910 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
5912 { &hf_nvme_identify_ns_eui64,
5913 { "IEEE Extended Unique Identifier (EUI64)", "nvme.cmd.identify.ns.eui64",
5914 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
5916 { &hf_nvme_identify_ns_lbafs,
5917 { "LBA Formats", "nvme.cmd.identify.ns.lbafs",
5918 FT_NONE, BASE_NONE, NULL, 0, NULL, HFILL}
5920 { &hf_nvme_identify_ns_lbaf,
5921 { "LBA Format", "nvme.cmd.identify.ns.lbaf",
5922 FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
5924 { &hf_nvme_identify_ns_rsvd,
5925 { "Reserved", "nvme.cmd.identify.ns.rsvd",
5926 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
5928 { &hf_nvme_identify_ns_vs,
5929 { "Vendor Specific", "nvme.cmd.identify.ns.vs",
5930 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
5932 /* Identify Ctrl response */
5933 { &hf_nvme_identify_ctrl_vid,
5934 { "PCI Vendor ID (VID)", "nvme.cmd.identify.ctrl.vid",
5935 FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
5937 { &hf_nvme_identify_ctrl_ssvid,
5938 { "PCI Subsystem Vendor ID (SSVID)", "nvme.cmd.identify.ctrl.ssvid",
5939 FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
5941 { &hf_nvme_identify_ctrl_sn,
5942 { "Serial Number (SN)", "nvme.cmd.identify.ctrl.sn",
5943 FT_STRINGZ, BASE_NONE, NULL, 0x0, NULL, HFILL}
5945 { &hf_nvme_identify_ctrl_mn,
5946 { "Model Number (MN)", "nvme.cmd.identify.ctrl.mn",
5947 FT_STRINGZ, BASE_NONE, NULL, 0x0, NULL, HFILL}
5949 { &hf_nvme_identify_ctrl_fr,
5950 { "Firmware Revision (FR)", "nvme.cmd.identify.ctrl.fr",
5951 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
5953 { &hf_nvme_identify_ctrl_rab,
5954 { "Recommended Arbitration Burst (RAB)", "nvme.cmd.identify.ctrl.rab",
5955 FT_UINT16, BASE_CUSTOM, CF_FUNC(add_ctrl_rab), 0x0, NULL, HFILL}
5957 { &hf_nvme_identify_ctrl_ieee,
5958 { "IEEE OUI Identifier (IEEE)", "nvme.cmd.identify.ctrl.ieee",
5959 FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
5961 { &hf_nvme_identify_ctrl_cmic[0],
5962 { "Controller Multi-Path I/O and Namespace Sharing Capabilities (CMIC)", "nvme.cmd.identify.ctrl.cmic",
5963 FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
5965 { &hf_nvme_identify_ctrl_cmic[1],
5966 { "Multiple Ports Support", "nvme.cmd.identify.ctrl.cmic.mp",
5967 FT_BOOLEAN, 8, NULL, 0x1, NULL, HFILL}
5969 { &hf_nvme_identify_ctrl_cmic[2],
5970 { "Multiple Controllers Support", "nvme.cmd.identify.ctrl.cmic.mc",
5971 FT_BOOLEAN, 8, NULL, 0x2, NULL, HFILL}
5973 { &hf_nvme_identify_ctrl_cmic[3],
5974 { "SRIOV Association", "nvme.cmd.identify.ctrl.cmic.sriov",
5975 FT_BOOLEAN, 8, NULL, 0x4, NULL, HFILL}
5977 { &hf_nvme_identify_ctrl_cmic[4],
5978 { "ANA Reporting Support", "nvme.cmd.identify.ctrl.cmic.ana",
5979 FT_BOOLEAN, 8, NULL, 0x8, NULL, HFILL}
5981 { &hf_nvme_identify_ctrl_cmic[5],
5982 { "Reserved", "nvme.cmd.identify.ctrl.cmic.rsvd",
5983 FT_UINT8, BASE_HEX, NULL, 0xf0, NULL, HFILL}
5985 { &hf_nvme_identify_ctrl_mdts,
5986 { "Maximum Data Transfer Size (MDTS)", "nvme.cmd.identify.ctrl.mdts",
5987 FT_UINT8, BASE_CUSTOM, CF_FUNC(add_ctrl_mdts), 0x0, NULL, HFILL}
5989 { &hf_nvme_identify_ctrl_cntlid,
5990 { "Controller ID (CNTLID)", "nvme.cmd.identify.ctrl.cntlid",
5991 FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
5993 { &hf_nvme_identify_ctrl_ver,
5994 { "Version (VER)", "nvme.cmd.identify.ctrl.ver",
5995 FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
5997 { &hf_nvme_identify_ctrl_ver_ter,
5998 { "Tertiary Version Number (TER)", "nvme.cmd.identify.ctrl.ver.ter",
5999 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL}
6001 { &hf_nvme_identify_ctrl_ver_min,
6002 { "Minor Version Number (MNR)", "nvme.cmd.identify.ctrl.ver.min",
6003 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL}
6005 { &hf_nvme_identify_ctrl_ver_mjr,
6006 { "Major Version Number (MJR)", "nvme.cmd.identify.ctrl.ver.mjr",
6007 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
6009 { &hf_nvme_identify_ctrl_rtd3r,
6010 { "RTD3 Resume Latency (RTD3R)", "nvme.cmd.identify.ctrl.rtd3r",
6011 FT_UINT32, BASE_CUSTOM, CF_FUNC(add_ctrl_rtd3), 0x0, NULL, HFILL}
6013 { &hf_nvme_identify_ctrl_rtd3e,
6014 { "RTD3 Entry Latency (RTD3E)", "nvme.cmd.identify.ctrl.rtd3e",
6015 FT_UINT32, BASE_CUSTOM, CF_FUNC(add_ctrl_rtd3), 0x0, NULL, HFILL}
6017 { &hf_nvme_identify_ctrl_oaes[0],
6018 { "Optional Asynchronous Events Supported (OAES)", "nvme.cmd.identify.ctrl.oaes",
6019 FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
6021 { &hf_nvme_identify_ctrl_oaes[1],
6022 { "Reserved", "nvme.cmd.identify.ctrl.oaes.rsvd0",
6023 FT_UINT32, BASE_HEX, NULL, 0xff, NULL, HFILL}
6025 { &hf_nvme_identify_ctrl_oaes[2],
6026 { "Namespace Attribute Notices Supported", "nvme.cmd.identify.ctrl.oaes.nan",
6027 FT_BOOLEAN, 32, NULL, 0x100, NULL, HFILL}
6029 { &hf_nvme_identify_ctrl_oaes[3],
6030 { "Firmware Activation Supported", "nvme.cmd.identify.ctrl.oaes.fan",
6031 FT_BOOLEAN, 32, NULL, 0x200, NULL, HFILL}
6033 { &hf_nvme_identify_ctrl_oaes[4],
6034 { "Reserved", "nvme.cmd.identify.ctrl.oaes.rsvd1",
6035 FT_UINT32, BASE_HEX, NULL, 0x400, NULL, HFILL}
6037 { &hf_nvme_identify_ctrl_oaes[5],
6038 { "Asymmetric Namespace Access Change Notices Supported", "nvme.cmd.identify.ctrl.oaes.ana",
6039 FT_BOOLEAN, 32, NULL, 0x800, NULL, HFILL}
6041 { &hf_nvme_identify_ctrl_oaes[6],
6042 { "Predictable Latency Event Aggregate Log Change Notices Supported", "nvme.cmd.identify.ctrl.oaes.ple",
6043 FT_BOOLEAN, 32, NULL, 0x1000, NULL, HFILL}
6045 { &hf_nvme_identify_ctrl_oaes[7],
6046 { "LBA Status Information Notices Supported", "nvme.cmd.identify.ctrl.oaes.lba",
6047 FT_BOOLEAN, 32, NULL, 0x2000, NULL, HFILL}
6049 { &hf_nvme_identify_ctrl_oaes[8],
6050 { "Endurance Group Event Aggregate Log Page Change Notices Supported", "nvme.cmd.identify.ctrl.oaes.ege",
6051 FT_BOOLEAN, 32, NULL, 0x4000, NULL, HFILL}
6053 { &hf_nvme_identify_ctrl_oaes[9],
6054 { "Reserved", "nvme.cmd.identify.ctrl.oaes.rsvd2",
6055 FT_UINT32, BASE_HEX, NULL, 0xffff8000, NULL, HFILL}
6057 { &hf_nvme_identify_ctrl_ctratt[0],
6058 { "Controller Attributes (CTRATT)", "nvme.cmd.identify.ctrl.ctratt",
6059 FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
6061 { &hf_nvme_identify_ctrl_ctratt[1],
6062 { "128-bit Host Identifier Support", "nvme.cmd.identify.ctrl.ctratt.hi_128",
6063 FT_BOOLEAN, 32, NULL, 0x1, NULL, HFILL}
6065 { &hf_nvme_identify_ctrl_ctratt[2],
6066 { "Non-Operational Power State Permissive Mode Supported", "nvme.cmd.identify.ctrl.ctratt.nopspm",
6067 FT_BOOLEAN, 32, NULL, 0x2, NULL, HFILL}
6069 { &hf_nvme_identify_ctrl_ctratt[3],
6070 { "NVM Sets Supported", "nvme.cmd.identify.ctrl.ctratt.nvmset",
6071 FT_BOOLEAN, 32, NULL, 0x4, NULL, HFILL}
6073 { &hf_nvme_identify_ctrl_ctratt[4],
6074 { "Read Recovery Levels Supported", "nvme.cmd.identify.ctrl.ctratt.rrl",
6075 FT_BOOLEAN, 32, NULL, 0x8, NULL, HFILL}
6077 { &hf_nvme_identify_ctrl_ctratt[5],
6078 { "Endurance Groups Supported", "nvme.cmd.identify.ctrl.ctratt.eg",
6079 FT_BOOLEAN, 32, NULL, 0x10, NULL, HFILL}
6081 { &hf_nvme_identify_ctrl_ctratt[6],
6082 { "Predictable Latency Mode Supported", "nvme.cmd.identify.ctrl.ctratt.plm",
6083 FT_BOOLEAN, 32, NULL, 0x20, NULL, HFILL}
6085 { &hf_nvme_identify_ctrl_ctratt[7],
6086 { "Traffic Based Keep Alive Support (TBKAS)", "nvme.cmd.identify.ctrl.ctratt.tbkas",
6087 FT_BOOLEAN, 32, NULL, 0x40, NULL, HFILL}
6089 { &hf_nvme_identify_ctrl_ctratt[8],
6090 { "Namespace Granularity", "nvme.cmd.identify.ctrl.ctratt.ng",
6091 FT_BOOLEAN, 32, NULL, 0x80, NULL, HFILL}
6093 { &hf_nvme_identify_ctrl_ctratt[9],
6094 { "SQ Associations Support", "nvme.cmd.identify.ctrl.ctratt.sqa",
6095 FT_BOOLEAN, 32, NULL, 0x100, NULL, HFILL}
6097 { &hf_nvme_identify_ctrl_ctratt[10],
6098 { "UUID List Support", "nvme.cmd.identify.ctrl.ctratt.uuidl",
6099 FT_BOOLEAN, 32, NULL, 0x200, NULL, HFILL}
6101 { &hf_nvme_identify_ctrl_ctratt[11],
6102 { "Reserved", "nvme.cmd.identify.ctrl.ctratt.rsvd",
6103 FT_UINT32, BASE_HEX, NULL, 0xfffffc00, NULL, HFILL}
6105 { &hf_nvme_identify_ctrl_rrls[0],
6106 { "Read Recovery Levels Support (RRLS)", "nvme.cmd.identify.ctrl.rrls",
6107 FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
6109 { &hf_nvme_identify_ctrl_rrls[1],
6110 { "Read Recovery Level 0 Support", "nvme.cmd.identify.ctrl.rrls.rrls0",
6111 FT_BOOLEAN, 16, NULL, 0x1, NULL, HFILL}
6113 { &hf_nvme_identify_ctrl_rrls[2],
6114 { "Read Recovery Level 1 Support", "nvme.cmd.identify.ctrl.rrls.rrls1",
6115 FT_BOOLEAN, 16, NULL, 0x2, NULL, HFILL}
6117 { &hf_nvme_identify_ctrl_rrls[3],
6118 { "Read Recovery Level 2 Support", "nvme.cmd.identify.ctrl.rrls.rrls2",
6119 FT_BOOLEAN, 16, NULL, 0x4, NULL, HFILL}
6121 { &hf_nvme_identify_ctrl_rrls[4],
6122 { "Read Recovery Level 3 Support", "nvme.cmd.identify.ctrl.rrls.rrls3",
6123 FT_BOOLEAN, 16, NULL, 0x8, NULL, HFILL}
6125 { &hf_nvme_identify_ctrl_rrls[5],
6126 { "Read Recovery Level 4 (Default) Support", "nvme.cmd.identify.ctrl.rrls.rrls4",
6127 FT_BOOLEAN, 16, NULL, 0x10, NULL, HFILL}
6129 { &hf_nvme_identify_ctrl_rrls[6],
6130 { "Read Recovery Level 5 Support", "nvme.cmd.identify.ctrl.rrls.rrls5",
6131 FT_BOOLEAN, 16, NULL, 0x20, NULL, HFILL}
6133 { &hf_nvme_identify_ctrl_rrls[7],
6134 { "Read Recovery Level 6 Support", "nvme.cmd.identify.ctrl.rrls.rrls6",
6135 FT_BOOLEAN, 16, NULL, 0x40, NULL, HFILL}
6137 { &hf_nvme_identify_ctrl_rrls[8],
6138 { "Read Recovery Level 7 Support", "nvme.cmd.identify.ctrl.rrls.rrls7",
6139 FT_BOOLEAN, 16, NULL, 0x80, NULL, HFILL}
6141 { &hf_nvme_identify_ctrl_rrls[9],
6142 { "Read Recovery Level 8 Support", "nvme.cmd.identify.ctrl.rrls.rrls8",
6143 FT_BOOLEAN, 16, NULL, 0x100, NULL, HFILL}
6145 { &hf_nvme_identify_ctrl_rrls[10],
6146 { "Read Recovery Level 9 Support", "nvme.cmd.identify.ctrl.rrls.rrls9",
6147 FT_BOOLEAN, 16, NULL, 0x200, NULL, HFILL}
6149 { &hf_nvme_identify_ctrl_rrls[11],
6150 { "Read Recovery Level 10 Support", "nvme.cmd.identify.ctrl.rrls.rrls10",
6151 FT_BOOLEAN, 16, NULL, 0x400, NULL, HFILL}
6153 { &hf_nvme_identify_ctrl_rrls[12],
6154 { "Read Recovery Level 11 Support", "nvme.cmd.identify.ctrl.rrls.rrls11",
6155 FT_BOOLEAN, 16, NULL, 0x800, NULL, HFILL}
6157 { &hf_nvme_identify_ctrl_rrls[13],
6158 { "Read Recovery Level 12 Support", "nvme.cmd.identify.ctrl.rrls.rrls12",
6159 FT_BOOLEAN, 16, NULL, 0x1000, NULL, HFILL}
6161 { &hf_nvme_identify_ctrl_rrls[14],
6162 { "Read Recovery Level 13 Support", "nvme.cmd.identify.ctrl.rrls.rrls13",
6163 FT_BOOLEAN, 16, NULL, 0x2000, NULL, HFILL}
6165 { &hf_nvme_identify_ctrl_rrls[15],
6166 { "Read Recovery Level 14 Support", "nvme.cmd.identify.ctrl.rrls.rrls14",
6167 FT_BOOLEAN, 16, NULL, 0x4000, NULL, HFILL}
6169 { &hf_nvme_identify_ctrl_rrls[16],
6170 { "Read Recovery Level 15 (Fast Fail) Support", "nvme.cmd.identify.ctrl.rrls.rrls15",
6171 FT_BOOLEAN, 16, NULL, 0x8000, NULL, HFILL}
6173 { &hf_nvme_identify_ctrl_rsvd0,
6174 { "Reserved", "nvme.cmd.identify.ctrl.rsvd0",
6175 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
6177 { &hf_nvme_identify_ctrl_cntrltype,
6178 { "Controller Type (CNTRLTYPE)", "nvme.cmd.identify.ctrl.cntrltype",
6179 FT_UINT8, BASE_HEX, VALS(ctrl_type_tbl), 0x0, NULL, HFILL}
6181 { &hf_nvme_identify_ctrl_fguid,
6182 { "FRU Globally Unique Identifier (FGUID)", "nvme.cmd.identify.ctrl.fguid",
6183 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
6185 { &hf_nvme_identify_ctrl_fguid_vse,
6186 { "Vendor Specific Extension Identifier", "nvme.cmd.identify.ctrl.fguid.vse",
6187 FT_UINT64, BASE_HEX, NULL, 0x0, NULL, HFILL}
6189 { &hf_nvme_identify_ctrl_fguid_oui,
6190 { "Organizationally Unique Identifier", "nvme.cmd.identify.ctrl.fguid.oui",
6191 FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
6193 { &hf_nvme_identify_ctrl_fguid_ei,
6194 { "Extension Identifier", "nvme.cmd.identify.ctrl.fguid.ei",
6195 FT_UINT64, BASE_HEX, NULL, 0x0, NULL, HFILL}
6197 { &hf_nvme_identify_ctrl_crdt1,
6198 { "Command Retry Delay Time 1", "nvme.cmd.identify.ctrl.crdt1",
6199 FT_UINT16, BASE_CUSTOM, CF_FUNC(add_ctrl_ms), 0x0, NULL, HFILL}
6201 { &hf_nvme_identify_ctrl_crdt2,
6202 { "Command Retry Delay Time 2", "nvme.cmd.identify.ctrl.crdt2",
6203 FT_UINT16, BASE_CUSTOM, CF_FUNC(add_ctrl_ms), 0x0, NULL, HFILL}
6205 { &hf_nvme_identify_ctrl_crdt3,
6206 { "Command Retry Delay Time 3", "nvme.cmd.identify.ctrl.crdt3",
6207 FT_UINT16, BASE_CUSTOM, CF_FUNC(add_ctrl_ms), 0x0, NULL, HFILL}
6209 { &hf_nvme_identify_ctrl_rsvd1,
6210 { "Reserved", "nvme.cmd.identify.ctrl.rsvd1",
6211 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
6213 { &hf_nvme_identify_ctrl_mi,
6214 { "NVMe Management Interface", "nvme.cmd.identify.ctrl.mi",
6215 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
6217 { &hf_nvme_identify_ctrl_mi_rsvd,
6218 { "Reserved", "nvme.cmd.identify.ctrl.mi.rsvd",
6219 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
6221 { &hf_nvme_identify_ctrl_mi_nvmsr[0],
6222 { "NVM Subsystem Report (NVMSR)", "nvme.cmd.identify.ctrl.mi.nvmsr",
6223 FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
6225 { &hf_nvme_identify_ctrl_mi_nvmsr[1],
6226 { "NVMe Storage Device (NVMESD)", "nvme.cmd.identify.ctrl.mi.nvmsr.nvmesd",
6227 FT_BOOLEAN, 8, NULL, 0x1, NULL, HFILL}
6229 { &hf_nvme_identify_ctrl_mi_nvmsr[2],
6230 { "NVMe Enclosure (NVMEE)", "nvme.cmd.identify.ctrl.mi.nvmsr.nvmee",
6231 FT_BOOLEAN, 8, NULL, 0x2, NULL, HFILL}
6233 { &hf_nvme_identify_ctrl_mi_nvmsr[3],
6234 { "Reserved", "nvme.cmd.identify.ctrl.mi.nvmsr.rsvd",
6235 FT_UINT8, BASE_HEX, NULL, 0xfc, NULL, HFILL}
6237 { &hf_nvme_identify_ctrl_mi_vwci[0],
6238 { "VPD Write Cycle Information (VWCI)", "nvme.cmd.identify.ctrl.mi.vwci",
6239 FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
6241 { &hf_nvme_identify_ctrl_mi_vwci[1],
6242 { "VPD Write Cycles Remaining (VWCR)", "nvme.cmd.identify.ctrl.mi.vwci.vwcr",
6243 FT_UINT8, BASE_HEX, NULL, 0x7f, NULL, HFILL}
6245 { &hf_nvme_identify_ctrl_mi_vwci[2],
6246 { "VPD Write Cycle Remaining Valid (VWCRV)", "nvme.cmd.identify.ctrl.mi.vwci.vwcrv",
6247 FT_BOOLEAN, 8, NULL, 0x80, NULL, HFILL}
6249 { &hf_nvme_identify_ctrl_mi_mec[0],
6250 { "Management Endpoint Capabilities (MEC)", "nvme.cmd.identify.ctrl.mi.mec",
6251 FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
6253 { &hf_nvme_identify_ctrl_mi_mec[1],
6254 { "SMBus/I2C Port Management Endpoint (SMBUSME)", "nvme.cmd.identify.ctrl.mi.mec.smbusme",
6255 FT_BOOLEAN, 8, NULL, 0x1, NULL, HFILL}
6257 { &hf_nvme_identify_ctrl_mi_mec[2],
6258 { "PCIe Port Management Endpoint (PCIEME)", "nvme.cmd.identify.ctrl.mi.mec.pcieme",
6259 FT_BOOLEAN, 8, NULL, 0x2, NULL, HFILL}
6261 { &hf_nvme_identify_ctrl_mi_mec[3],
6262 { "Reserved", "nvme.cmd.identify.ctrl.mi.mec.rsvd",
6263 FT_UINT8, BASE_HEX, NULL, 0xfc, NULL, HFILL}
6265 { &hf_nvme_identify_ctrl_oacs[0],
6266 { "Optional Admin Command Support (OACS)", "nvme.cmd.identify.ctrl.oacs",
6267 FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
6269 { &hf_nvme_identify_ctrl_oacs[1],
6270 { "Security Send and Security Receive Support", "nvme.cmd.identify.ctrl.oacs.sec",
6271 FT_BOOLEAN, 16, NULL, 0x1, NULL, HFILL}
6273 { &hf_nvme_identify_ctrl_oacs[2],
6274 { "Format NVM Support", "nvme.cmd.identify.ctrl.oacs.fmt",
6275 FT_BOOLEAN, 16, NULL, 0x2, NULL, HFILL}
6277 { &hf_nvme_identify_ctrl_oacs[3],
6278 { "Firmware Download and Commit Support", "nvme.cmd.identify.ctrl.oacs.fw",
6279 FT_BOOLEAN, 16, NULL, 0x4, NULL, HFILL}
6281 { &hf_nvme_identify_ctrl_oacs[4],
6282 { "Namespace Management Support", "nvme.cmd.identify.ctrl.oacs.nsmgmt",
6283 FT_BOOLEAN, 16, NULL, 0x8, NULL, HFILL}
6285 { &hf_nvme_identify_ctrl_oacs[5],
6286 { "Device Self-Test Support", "nvme.cmd.identify.ctrl.oacs.stst",
6287 FT_BOOLEAN, 16, NULL, 0x10, NULL, HFILL}
6289 { &hf_nvme_identify_ctrl_oacs[6],
6290 { "Directive Send and Directive Receive Support", "nvme.cmd.identify.ctrl.oacs.dtv",
6291 FT_BOOLEAN, 16, NULL, 0x20, NULL, HFILL}
6293 { &hf_nvme_identify_ctrl_oacs[7],
6294 { "NVMe-MI Send and NVMe Receive Support", "nvme.cmd.identify.ctrl.oacs.mi",
6295 FT_BOOLEAN, 16, NULL, 0x40, NULL, HFILL}
6297 { &hf_nvme_identify_ctrl_oacs[8],
6298 { "Virtualization Management Support", "nvme.cmd.identify.ctrl.oacs.vm",
6299 FT_BOOLEAN, 16, NULL, 0x80, NULL, HFILL}
6301 { &hf_nvme_identify_ctrl_oacs[9],
6302 { "Dorbell Buffer Config Support", "nvme.cmd.identify.ctrl.oacs.db",
6303 FT_BOOLEAN, 16, NULL, 0x100, NULL, HFILL}
6305 { &hf_nvme_identify_ctrl_oacs[10],
6306 { "Get LBA Status Support", "nvme.cmd.identify.ctrl.oacs.sec.lba",
6307 FT_BOOLEAN, 16, NULL, 0x200, NULL, HFILL}
6309 { &hf_nvme_identify_ctrl_oacs[11],
6310 { "Reserved", "nvme.cmd.identify.ctrl.oacs.sec.rsvd",
6311 FT_UINT16, BASE_HEX, NULL, 0xfc00, NULL, HFILL}
6313 { &hf_nvme_identify_ctrl_acl,
6314 { "Abort Command Limit (ACL)", "nvme.cmd.identify.ctrl.acl",
6315 FT_UINT8, BASE_CUSTOM, CF_FUNC(add_ctrl_commands), 0x0, NULL, HFILL}
6317 { &hf_nvme_identify_ctrl_aerl,
6318 { "Asynchronous Event Request Limit (AERL)", "nvme.cmd.identify.ctrl.aerl",
6319 FT_UINT8, BASE_CUSTOM, CF_FUNC(add_ctrl_events), 0x0, NULL, HFILL}
6321 { &hf_nvme_identify_ctrl_frmw[0],
6322 { "Firmware Updates (FRMW)", "nvme.cmd.identify.ctrl.frmw",
6323 FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
6325 { &hf_nvme_identify_ctrl_frmw[1],
6326 { "First Firmware Slot Read-Only", "nvme.cmd.identify.ctrl.frmw.fro",
6327 FT_BOOLEAN, 8, NULL, 0x1, NULL, HFILL}
6329 { &hf_nvme_identify_ctrl_frmw[2],
6330 { "Number of Firmware Slots", "nvme.cmd.identify.ctrl.frmw.fsn",
6331 FT_UINT8, BASE_HEX, NULL, 0xe, NULL, HFILL}
6333 { &hf_nvme_identify_ctrl_frmw[3],
6334 { "Supports Activation Without Reset", "nvme.cmd.identify.ctrl.frmw.anr",
6335 FT_BOOLEAN, 8, NULL, 0x10, NULL, HFILL}
6337 { &hf_nvme_identify_ctrl_frmw[4],
6338 { "Reserved", "nvme.cmd.identify.ctrl.frmw.rsvd",
6339 FT_UINT8, BASE_HEX, NULL, 0xe0, NULL, HFILL}
6341 { &hf_nvme_identify_ctrl_lpa[0],
6342 { "Log Page Attributes (LPA)", "nvme.cmd.identify.ctrl.lpa",
6343 FT_BOOLEAN, 8, NULL, 0x0, NULL, HFILL}
6345 { &hf_nvme_identify_ctrl_lpa[1],
6346 { "Smart Log Page per Namespace Support", "nvme.cmd.identify.ctrl.lpa.smrt",
6347 FT_BOOLEAN, 8, NULL, 0x1, NULL, HFILL}
6349 { &hf_nvme_identify_ctrl_lpa[2],
6350 { "Commands Supported and Effects Log Page Support", "nvme.cmd.identify.ctrl.lpa.cmds",
6351 FT_BOOLEAN, 8, NULL, 0x2, NULL, HFILL}
6353 { &hf_nvme_identify_ctrl_lpa[3],
6354 { "Extended Data Get Log Page Support", "nvme.cmd.identify.ctrl.lpa.elp",
6355 FT_BOOLEAN, 8, NULL, 0x4, NULL, HFILL}
6357 { &hf_nvme_identify_ctrl_lpa[4],
6358 { "Telemetry Log Page and Notices Support", "nvme.cmd.identify.ctrl.lpa.tel",
6359 FT_BOOLEAN, 8, NULL, 0x8, NULL, HFILL}
6361 { &hf_nvme_identify_ctrl_lpa[5],
6362 { "Persistent Event Log Support", "nvme.cmd.identify.ctrl.lpa.ple",
6363 FT_BOOLEAN, 8, NULL, 0x10, NULL, HFILL}
6365 { &hf_nvme_identify_ctrl_lpa[6],
6366 { "Reserved", "nvme.cmd.identify.ctrl.lpa.rsvd",
6367 FT_UINT8, BASE_HEX, NULL, 0xe0, NULL, HFILL}
6369 { &hf_nvme_identify_ctrl_elpe,
6370 { "Error Log Page Entries (ELPE)", "nvme.cmd.identify.ctrl.elpe",
6371 FT_UINT8, BASE_CUSTOM, CF_FUNC(add_ctrl_entries), 0x0, NULL, HFILL}
6373 { &hf_nvme_identify_ctrl_npss,
6374 { "Number of Power States Supported (NPSS)", "nvme.cmd.identify.ctrl.npss",
6375 FT_UINT8, BASE_CUSTOM, CF_FUNC(add_ctrl_states), 0x0, NULL, HFILL}
6377 { &hf_nvme_identify_ctrl_avscc[0],
6378 { "Admin Vendor Specific Command Configuration (AVSCC)", "nvme.cmd.identify.ctrl.avscc",
6379 FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
6381 { &hf_nvme_identify_ctrl_avscc[1],
6382 { "Standard Command Format", "nvme.cmd.identify.ctrl.avscc.std",
6383 FT_BOOLEAN, 8, NULL, 0x1, NULL, HFILL}
6385 { &hf_nvme_identify_ctrl_avscc[2],
6386 { "Reserved", "nvme.cmd.identify.ctrl.avscc.rsvd",
6387 FT_UINT8, BASE_HEX, NULL, 0xfe, NULL, HFILL}
6389 { &hf_nvme_identify_ctrl_apsta[0],
6390 { "Autonomous Power State Transition Attributes (APSTA)", "nvme.cmd.identify.ctrl.apsta",
6391 FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
6393 { &hf_nvme_identify_ctrl_apsta[1],
6394 { "Autonomous Power State Transitions Supported", "nvme.cmd.identify.ctrl.apsta.aut",
6395 FT_BOOLEAN, 8, NULL, 0x1, NULL, HFILL}
6397 { &hf_nvme_identify_ctrl_apsta[2],
6398 { "Reserved", "nvme.cmd.identify.ctrl.apsta.rsvd",
6399 FT_UINT8, BASE_HEX, NULL, 0xfe, NULL, HFILL}
6401 { &hf_nvme_identify_ctrl_wctemp,
6402 { "Warning Composite Temperature Threshold (WCTEMP)", "nvme.cmd.identify.ctrl.wctemp",
6403 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
6405 { &hf_nvme_identify_ctrl_cctemp,
6406 { "Critical Composite Temperature Threshold (CCTEMP)", "nvme.cmd.identify.ctrl.cctemp",
6407 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
6409 { &hf_nvme_identify_ctrl_mtfa,
6410 { "Maximum Time for Firmware Activation (MTFA)", "nvme.cmd.identify.ctrl.mtfa",
6411 FT_UINT16, BASE_CUSTOM, CF_FUNC(add_ctrl_ms), 0x0, NULL, HFILL}
6413 { &hf_nvme_identify_ctrl_hmpre,
6414 { "Host Memory Buffer Preferred Size (HMPRE)", "nvme.cmd.identify.ctrl.hmpre",
6415 FT_UINT32, BASE_CUSTOM, CF_FUNC(add_ctrl_hmpre), 0x0, NULL, HFILL}
6417 { &hf_nvme_identify_ctrl_hmmin,
6418 { "Host Memory Buffer Minimum Size (HMMIN)", "nvme.cmd.identify.ctrl.hmmin",
6419 FT_UINT32, BASE_CUSTOM, CF_FUNC(add_ctrl_hmpre), 0x0, NULL, HFILL}
6421 { &hf_nvme_identify_ctrl_tnvmcap,
6422 { "Total NVM Capacity (TNVMCAP)", "nvme.cmd.identify.ctrl.tnvmcap",
6423 FT_BYTES, BASE_NO_DISPLAY_VALUE, NULL, 0x0, NULL, HFILL}
6425 { &hf_nvme_identify_ctrl_unvmcap,
6426 { "Unallocated NVM Capacity (UNVMCAP)", "nvme.cmd.identify.ctrl.unvmcap",
6427 FT_BYTES, BASE_NO_DISPLAY_VALUE, NULL, 0x0, NULL, HFILL}
6429 { &hf_nvme_identify_ctrl_rpmbs[0],
6430 { "Replay Protected Memory Block Support (RPMBS)", "nvme.cmd.identify.ctrl.rpmbs",
6431 FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
6433 { &hf_nvme_identify_ctrl_rpmbs[1],
6434 { "Number of RPMB Units", "nvme.cmd.identify.ctrl.rpmbs.nu",
6435 FT_UINT32, BASE_HEX, NULL, 0x7, NULL, HFILL}
6437 { &hf_nvme_identify_ctrl_rpmbs[2],
6438 { "Authentication Method", "nvme.cmd.identify.ctrl.rpmbs.au",
6439 FT_UINT32, BASE_HEX, NULL, 0x38, NULL, HFILL}
6441 { &hf_nvme_identify_ctrl_rpmbs[3],
6442 { "Reserved", "nvme.cmd.identify.ctrl.rpmbs.rsvd",
6443 FT_UINT32, BASE_HEX, NULL, 0xffc0, NULL, HFILL}
6445 { &hf_nvme_identify_ctrl_rpmbs[4],
6446 { "Total RPMB Unit Size (128 KiB blocks, zero based)", "nvme.cmd.identify.ctrl.rpmbs.ts",
6447 FT_UINT32, BASE_HEX, NULL, 0xff0000, NULL, HFILL}
6449 { &hf_nvme_identify_ctrl_rpmbs[5],
6450 { "Access Size (512-byte blocks, zero based)", "nvme.cmd.identify.ctrl.rpmbs.as",
6451 FT_UINT32, BASE_HEX, NULL, 0xff000000, NULL, HFILL}
6453 { &hf_nvme_identify_ctrl_edstt,
6454 { "Extended Device Self-test Time (EDSTT) (in minutes)", "nvme.cmd.identify.ctrl.edstt",
6455 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
6457 { &hf_nvme_identify_ctrl_dsto[0],
6458 { "Device Self-test Options (DSTO)", "nvme.cmd.identify.ctrl.dsto",
6459 FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
6461 { &hf_nvme_identify_ctrl_dsto[1],
6462 { "Concurrent Self-Tests for Multiple Devices Support", "nvme.cmd.identify.ctrl.dsto.mds",
6463 FT_BOOLEAN, 8, NULL, 0x1, NULL, HFILL}
6465 { &hf_nvme_identify_ctrl_dsto[2],
6466 { "Reserved", "nvme.cmd.identify.ctrl.dsto.rsvd",
6467 FT_UINT8, BASE_HEX, NULL, 0xfe, NULL, HFILL}
6469 { &hf_nvme_identify_ctrl_fwug,
6470 { "Firmware Update Granularity in 4 KiB Units (FWUG)", "nvme.cmd.identify.ctrl.fwug",
6471 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL}
6473 { &hf_nvme_identify_ctrl_kas,
6474 { "Keep Alive Support - Timer Value (KAS)", "nvme.cmd.identify.ctrl.kas",
6475 FT_UINT16, BASE_CUSTOM, CF_FUNC(add_ctrl_ms), 0x0, NULL, HFILL}
6477 { &hf_nvme_identify_ctrl_hctma[0],
6478 { "Host Controlled Thermal Management Attributes (HCTMA)", "nvme.cmd.identify.ctrl.hctma",
6479 FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
6481 { &hf_nvme_identify_ctrl_hctma[1],
6482 { "Controller Supports Thermal Management", "nvme.cmd.identify.ctrl.hctma.sup",
6483 FT_BOOLEAN, 16, NULL, 0x1, NULL, HFILL}
6485 { &hf_nvme_identify_ctrl_hctma[2],
6486 { "Reserved", "nvme.cmd.identify.ctrl.hctma.rsvd",
6487 FT_UINT16, BASE_HEX, NULL, 0xfffe, NULL, HFILL}
6489 { &hf_nvme_identify_ctrl_mntmt,
6490 { "Minimum Thermal Management Temperature (MNTMT)", "nvme.cmd.identify.ctrl.mntmt",
6491 FT_UINT16, BASE_CUSTOM, CF_FUNC(add_ctrl_tmt), 0x0, NULL, HFILL}
6493 { &hf_nvme_identify_ctrl_mxtmt,
6494 { "Maximum Thermal Management Temperature (MXTMT)", "nvme.cmd.identify.ctrl.mxtmt",
6495 FT_UINT16, BASE_CUSTOM, CF_FUNC(add_ctrl_tmt), 0x0, NULL, HFILL}
6497 { &hf_nvme_identify_ctrl_sanicap[0],
6498 { "Sanitize Capabilities (SANICAP)", "nvme.cmd.identify.ctrl.sanicap",
6499 FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
6501 { &hf_nvme_identify_ctrl_sanicap[1],
6502 { "Crypto Erase Support (CES)", "nvme.cmd.identify.ctrl.sanicap.ces",
6503 FT_BOOLEAN, 32, NULL, 0x1, NULL, HFILL}
6505 { &hf_nvme_identify_ctrl_sanicap[2],
6506 { "Block Erase Support (BES)", "nvme.cmd.identify.ctrl.sanicap.bes",
6507 FT_BOOLEAN, 32, NULL, 0x2, NULL, HFILL}
6509 { &hf_nvme_identify_ctrl_sanicap[3],
6510 { "Overwrite Support (OWS)", "nvme.cmd.identify.ctrl.sanicap.ows",
6511 FT_BOOLEAN, 32, NULL, 0x4, NULL, HFILL}
6513 { &hf_nvme_identify_ctrl_sanicap[4],
6514 { "Reserved", "nvme.cmd.identify.ctrl.sanicap.rsvd",
6515 FT_UINT32, BASE_HEX, NULL, 0x1ffffff8, NULL, HFILL}
6517 { &hf_nvme_identify_ctrl_sanicap[5],
6518 { "No-Deallocate Inhibited (NDI)", "nvme.cmd.identify.ctrl.sanicap.ndi",
6519 FT_BOOLEAN, 32, NULL, 0x20000000, NULL, HFILL}
6521 { &hf_nvme_identify_ctrl_sanicap[6],
6522 { "No-Deallocate Modifies Media After Sanitize (NODMMAS)", "nvme.cmd.identify.ctrl.sanicap.nodmmas",
6523 FT_UINT32, BASE_HEX, VALS(mmas_type_tbl), 0xc0000000, NULL, HFILL}
6525 { &hf_nvme_identify_ctrl_hmmminds,
6526 { "Host Memory Buffer Minimum Descriptor Entry Size in 4 KiB Units (HMMINDS)", "nvme.cmd.identify.ctrl.hmmminds",
6527 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL}
6529 { &hf_nvme_identify_ctrl_hmmaxd,
6530 { "Host Memory Maximum Descriptors Entries (HMMAXD)", "nvme.cmd.identify.ctrl.hmmaxd",
6531 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
6533 { &hf_nvme_identify_ctrl_nsetidmax,
6534 { "NVM Set Identifier Maximum (NSETIDMAX)", "nvme.cmd.identify.ctrl.nsetidmax",
6535 FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
6537 { &hf_nvme_identify_ctrl_endgidmax,
6538 { "Endurance Group Identifier Maximum (ENDGIDMAX)", "nvme.cmd.identify.ctrl.endgidmax",
6539 FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
6541 { &hf_nvme_identify_ctrl_anatt,
6542 { "ANA Transition Time in Seconds (ANATT)", "nvme.cmd.identify.ctrl.anatt",
6543 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL}
6545 { &hf_nvme_identify_ctrl_anacap[0],
6546 { "Asymmetric Namespace Access Capabilities (ANACAP)", "nvme.cmd.identify.ctrl.anacap",
6547 FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
6549 { &hf_nvme_identify_ctrl_anacap[1],
6550 { "Reports ANA Optimized State", "nvme.cmd.identify.ctrl.anacap.osr",
6551 FT_BOOLEAN, 8, NULL, 0x1, NULL, HFILL}
6553 { &hf_nvme_identify_ctrl_anacap[2],
6554 { "Reports ANA Non-Optimized State", "nvme.cmd.identify.ctrl.anacap.nosr",
6555 FT_BOOLEAN, 8, NULL, 0x2, NULL, HFILL}
6557 { &hf_nvme_identify_ctrl_anacap[3],
6558 { "Reports Innaccessible State", "nvme.cmd.identify.ctrl.anacap.isr",
6559 FT_BOOLEAN, 8, NULL, 0x4, NULL, HFILL}
6561 { &hf_nvme_identify_ctrl_anacap[4],
6562 { "Reports ANA Persistent Loss State", "nvme.cmd.identify.ctrl.anacap.plsr",
6563 FT_BOOLEAN, 8, NULL, 0x8, NULL, HFILL}
6565 { &hf_nvme_identify_ctrl_anacap[5],
6566 { "Reports ANA Change Sate", "nvme.cmd.identify.ctrl.anacap.csr",
6567 FT_BOOLEAN, 8, NULL, 0x10, NULL, HFILL}
6569 { &hf_nvme_identify_ctrl_anacap[6],
6570 { "Reserved", "nvme.cmd.identify.ctrl.anacap.rsvd",
6571 FT_BOOLEAN, 8, NULL, 0x20, NULL, HFILL}
6573 { &hf_nvme_identify_ctrl_anacap[7],
6574 { "ANAGRPID field in the Identify Namespace does not change", "nvme.cmd.identify.ctrl.anacap.panagrpid",
6575 FT_BOOLEAN, 8, NULL, 0x40, NULL, HFILL}
6577 { &hf_nvme_identify_ctrl_anacap[8],
6578 { "Supports non-zero value in the ANAGRPID field", "nvme.cmd.identify.ctrl.anacap.nzpanagrpid",
6579 FT_BOOLEAN, 8, NULL, 0x80, NULL, HFILL}
6581 { &hf_nvme_identify_ctrl_anagrpmax,
6582 { "ANA Group Identifier Maximum (ANAGRPMAX)", "nvme.cmd.identify.ctrl.anagrpmax",
6583 FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
6585 { &hf_nvme_identify_ctrl_nanagrpid,
6586 { "Number of ANA Group Identifiers (NANAGRPID)", "nvme.cmd.identify.ctrl.nanagrpid",
6587 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL}
6589 { &hf_nvme_identify_ctrl_pels,
6590 { "Persistent Event Log Size in 64 KiB Units (PELS)", "nvme.cmd.identify.ctrl.pels",
6591 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL}
6593 { &hf_nvme_identify_ctrl_rsvd2,
6594 { "Reserved", "nvme.cmd.identify.ctrl.rsvd2",
6595 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
6597 { &hf_nvme_identify_ctrl_sqes[0],
6598 { "Submission Queue Entry Size (SQES)", "nvme.cmd.identify.ctrl.sqes",
6599 FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
6601 { &hf_nvme_identify_ctrl_sqes[1],
6602 { "Minimum (required) Size", "nvme.cmd.identify.ctrl.sqes.mins",
6603 FT_UINT8, BASE_CUSTOM, CF_FUNC(add_ctrl_pow2_bytes), 0xf, NULL, HFILL}
6605 { &hf_nvme_identify_ctrl_sqes[2],
6606 { "Maximum (allowed) Size", "nvme.cmd.identify.ctrl.sqes.maxs",
6607 FT_UINT8, BASE_CUSTOM, CF_FUNC(add_ctrl_pow2_bytes), 0xf0, NULL, HFILL}
6609 { &hf_nvme_identify_ctrl_cqes[0],
6610 { "Completion Queue Entry Size (CQES)", "nvme.cmd.identify.ctrl.cqes",
6611 FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
6613 { &hf_nvme_identify_ctrl_cqes[1],
6614 { "Minimum (required) Size", "nvme.cmd.identify.ctrl.cqes.mins",
6615 FT_UINT8, BASE_CUSTOM, CF_FUNC(add_ctrl_pow2_bytes), 0xf, NULL, HFILL}
6617 { &hf_nvme_identify_ctrl_cqes[2],
6618 { "Maximum (allowed) Size", "nvme.cmd.identify.ctrl.cqes.maxs",
6619 FT_UINT8, BASE_CUSTOM, CF_FUNC(add_ctrl_pow2_bytes), 0xf0, NULL, HFILL}
6621 { &hf_nvme_identify_ctrl_maxcmd,
6622 { "Maximum Outstanding Commands (MAXCMD)", "nvme.cmd.identify.ctrl.maxcmd",
6623 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
6625 { &hf_nvme_identify_ctrl_nn,
6626 { "Number of Namespaces (NN)", "nvme.cmd.identify.ctrl.nn",
6627 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL}
6629 { &hf_nvme_identify_ctrl_oncs[0],
6630 { "Optional NVM Command Support (ONCS)", "nvme.cmd.identify.ctrl.oncs",
6631 FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
6633 { &hf_nvme_identify_ctrl_oncs[1],
6634 { "Supports Compare Command", "nvme.cmd.identify.ctrl.oncs.ccs",
6635 FT_BOOLEAN, 16, NULL, 0x1, NULL, HFILL}
6637 { &hf_nvme_identify_ctrl_oncs[2],
6638 { "Supports Write Uncorrectable Command", "nvme.cmd.identify.ctrl.oncs.wus",
6639 FT_BOOLEAN, 16, NULL, 0x2, NULL, HFILL}
6641 { &hf_nvme_identify_ctrl_oncs[3],
6642 { "Supports Dataset Management Command", "nvme.cmd.identify.ctrl.oncs.dsms",
6643 FT_BOOLEAN, 16, NULL, 0x4, NULL, HFILL}
6645 { &hf_nvme_identify_ctrl_oncs[4],
6646 { "Support Write Zeroes Command", "nvme.cmd.identify.ctrl.oncs.wzs",
6647 FT_BOOLEAN, 16, NULL, 0x8, NULL, HFILL}
6649 { &hf_nvme_identify_ctrl_oncs[5],
6650 { "Supports non-zero Save Field in Set/Get Features", "nvme.cmd.identify.ctrl.oncs.nzfs",
6651 FT_BOOLEAN, 16, NULL, 0x10, NULL, HFILL}
6653 { &hf_nvme_identify_ctrl_oncs[6],
6654 { "Supports Reservations", "nvme.cmd.identify.ctrl.oncs.ress",
6655 FT_BOOLEAN, 16, NULL, 0x20, NULL, HFILL}
6657 { &hf_nvme_identify_ctrl_oncs[7],
6658 { "Supports Timestamps", "nvme.cmd.identify.ctrl.oncs.tstmps",
6659 FT_BOOLEAN, 16, NULL, 0x40, NULL, HFILL}
6661 { &hf_nvme_identify_ctrl_oncs[8],
6662 { "Supports Verify Command", "nvme.cmd.identify.ctrl.oncs.vers",
6663 FT_BOOLEAN, 16, NULL, 0x80, NULL, HFILL}
6665 { &hf_nvme_identify_ctrl_oncs[9],
6666 { "Reserved", "nvme.cmd.identify.ctrl.oncs.rsvd",
6667 FT_UINT16, BASE_HEX, NULL, 0xff00, NULL, HFILL}
6669 { &hf_nvme_identify_ctrl_fuses[0],
6670 { "Fused Operation Support (FUSES)", "nvme.cmd.identify.ctrl.fuses",
6671 FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
6673 { &hf_nvme_identify_ctrl_fuses[1],
6674 { "Compare and Write Fused Operation Support", "nvme.cmd.identify.ctrl.fuses.cws",
6675 FT_BOOLEAN, 16, NULL, 0x1, NULL, HFILL}
6677 { &hf_nvme_identify_ctrl_fuses[2],
6678 { "Reserved", "nvme.cmd.identify.ctrl.fuses.rsvd",
6679 FT_UINT16, BASE_HEX, NULL, 0xfffe, NULL, HFILL}
6681 { &hf_nvme_identify_ctrl_fna[0],
6682 { "Format NVM Attributes (FNA)", "nvme.cmd.identify.ctrl.fna",
6683 FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
6685 { &hf_nvme_identify_ctrl_fna[1],
6686 { "Format Operation Applies to all Namespaces", "nvme.cmd.identify.ctrl.fna.fall",
6687 FT_BOOLEAN, 8, NULL, 0x1, NULL, HFILL}
6689 { &hf_nvme_identify_ctrl_fna[2],
6690 { "Secure Erase Operation Applies to all Namespaces", "nvme.cmd.identify.ctrl.fna.seall",
6691 FT_BOOLEAN, 8, NULL, 0x2, NULL, HFILL}
6693 { &hf_nvme_identify_ctrl_fna[3],
6694 { "Cryptographic Erase Supported", "nvme.cmd.identify.ctrl.fna.ces",
6695 FT_BOOLEAN, 8, NULL, 0x4, NULL, HFILL}
6697 { &hf_nvme_identify_ctrl_fna[4],
6698 { "Reserved", "nvme.cmd.identify.ctrl.fna.rsvd",
6699 FT_UINT8, BASE_HEX, NULL, 0xf8, NULL, HFILL}
6701 { &hf_nvme_identify_ctrl_vwc[0],
6702 { "Volatile Write Cache (VWC)", "nvme.cmd.identify.ctrl.vwc",
6703 FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
6705 { &hf_nvme_identify_ctrl_vwc[1],
6706 { "Volatile Write Cache Present", "nvme.cmd.identify.ctrl.vwc.cp",
6707 FT_BOOLEAN, 8, NULL, 0x1, NULL, HFILL}
6709 { &hf_nvme_identify_ctrl_vwc[2],
6710 { "Flush Command Behavior", "nvme.cmd.identify.ctrl.vwc.cfb",
6711 FT_UINT8, BASE_HEX, VALS(fcb_type_tbl), 0x6, NULL, HFILL}
6713 { &hf_nvme_identify_ctrl_vwc[3],
6714 { "Reserved", "nvme.cmd.identify.ctrl.vwc.rsvd",
6715 FT_UINT8, BASE_HEX, NULL, 0xf8, NULL, HFILL}
6717 { &hf_nvme_identify_ctrl_awun,
6718 { "Atomic Write Unit Normal (AWUN)", "nvme.cmd.identify.ctrl.awun",
6719 FT_UINT16, BASE_CUSTOM, CF_FUNC(add_ctrl_lblocks), 0x0, NULL, HFILL}
6721 { &hf_nvme_identify_ctrl_awupf,
6722 { "Atomic Write Unit Power Fail (AWUPF)", "nvme.cmd.identify.ctrl.awupf",
6723 FT_UINT16, BASE_CUSTOM, CF_FUNC(add_ctrl_lblocks), 0x0, NULL, HFILL}
6725 { &hf_nvme_identify_ctrl_nvscc[0],
6726 { "NVM Vendor Specific Command Configuration (NVSCC)", "nvme.cmd.identify.ctrl.nvscc",
6727 FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
6729 { &hf_nvme_identify_ctrl_nvscc[1],
6730 { "Standard Format Used for Vendor Specific Commands", "nvme.cmd.identify.ctrl.nvscc.std",
6731 FT_BOOLEAN, 8, NULL, 0x1, NULL, HFILL}
6733 { &hf_nvme_identify_ctrl_nvscc[2],
6734 { "Reserved", "nvme.cmd.identify.ctrl.nvscc.rsvd",
6735 FT_UINT8, BASE_HEX, NULL, 0xfe, NULL, HFILL}
6737 { &hf_nvme_identify_ctrl_nwpc[0],
6738 { "Namespace Write Protection Capabilities (NWPC)", "nvme.cmd.identify.ctrl.nwpc",
6739 FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
6741 { &hf_nvme_identify_ctrl_nwpc[1],
6742 { "No Write Protect and Write Protect namespace write protection states Support", "nvme.cmd.identify.ctrl.nwpc.wpss",
6743 FT_BOOLEAN, 8, NULL, 0x1, NULL, HFILL}
6745 { &hf_nvme_identify_ctrl_nwpc[2],
6746 { "Write Protect Until Power Cycle state Support", "nvme.cmd.identify.ctrl.nwpc.wppcs",
6747 FT_BOOLEAN, 8, NULL, 0x2, NULL, HFILL}
6749 { &hf_nvme_identify_ctrl_nwpc[3],
6750 { "Permanent Write Protect state Support", "nvme.cmd.identify.ctrl.nwpc.pwpss",
6751 FT_BOOLEAN, 8, NULL, 0x4, NULL, HFILL}
6753 { &hf_nvme_identify_ctrl_nwpc[4],
6754 { "Reserved", "nvme.cmd.identify.ctrl.nwpc.rsvd",
6755 FT_UINT8, BASE_HEX, NULL, 0xf8, NULL, HFILL}
6757 { &hf_nvme_identify_ctrl_acwu,
6758 { "Atomic Compare & Write Unit (ACWU)", "nvme.cmd.identify.ctrl.acwu",
6759 FT_UINT16, BASE_CUSTOM, CF_FUNC(add_ctrl_hmpre), 0x0, NULL, HFILL}
6761 { &hf_nvme_identify_ctrl_rsvd3,
6762 { "Reserved", "nvme.cmd.identify.ctrl.rsvd3",
6763 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
6765 { &hf_nvme_identify_ctrl_sgls[0],
6766 { "SGL Support (SGLS)", "nvme.cmd.identify.ctrl.sgls",
6767 FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
6769 { &hf_nvme_identify_ctrl_sgls[1],
6770 { "SGL Supported", "nvme.cmd.identify.ctrl.sgls.sgls",
6771 FT_UINT32, BASE_HEX, VALS(sgls_ify_type_tbl), 0x3, NULL, HFILL}
6773 { &hf_nvme_identify_ctrl_sgls[2],
6774 { "Supports Keyed SGL Data Block Descriptor", "nvme.cmd.identify.ctrl.sgls.kdbs",
6775 FT_BOOLEAN, 32, NULL, 0x4, NULL, HFILL}
6777 { &hf_nvme_identify_ctrl_sgls[3],
6778 { "Reserved", "nvme.cmd.identify.ctrl.sgls.rsvd0",
6779 FT_UINT32, BASE_HEX, NULL, 0xfff8, NULL, HFILL}
6781 { &hf_nvme_identify_ctrl_sgls[4],
6782 { "Supports SGL Bit Bucket Descriptor", "nvme.cmd.identify.ctrl.sgls.bbd",
6783 FT_BOOLEAN, 32, NULL, 0x10000, NULL, HFILL}
6785 { &hf_nvme_identify_ctrl_sgls[5],
6786 { "Supports byte aligned contiguous buffer in MPTR Field", "nvme.cmd.identify.ctrl.sgls.bufmptr",
6787 FT_BOOLEAN, 32, NULL, 0x20000, NULL, HFILL}
6789 { &hf_nvme_identify_ctrl_sgls[6],
6790 { "Supports Larger SGL List than Command Requires", "nvme.cmd.identify.ctrl.sgls.lsgl",
6791 FT_BOOLEAN, 32, NULL, 0x40000, NULL, HFILL}
6793 { &hf_nvme_identify_ctrl_sgls[7],
6794 { "Supports SGL Segment in MPTR Field", "nvme.cmd.identify.ctrl.sgls.kmptr",
6795 FT_BOOLEAN, 32, NULL, 0x80000, NULL, HFILL}
6797 { &hf_nvme_identify_ctrl_sgls[8],
6798 { "Supports Address Field as offset in Data Block, Segment and Last Segment SGLs", "nvme.cmd.identify.ctrl.sgls.offs",
6799 FT_BOOLEAN, 32, NULL, 0x100000, NULL, HFILL}
6801 { &hf_nvme_identify_ctrl_sgls[9],
6802 { "Supports Transport SGL Data Block Descriptor", "nvme.cmd.identify.ctrl.sgls.tdbd",
6803 FT_BOOLEAN, 32, NULL, 0x200000, NULL, HFILL}
6805 { &hf_nvme_identify_ctrl_sgls[10],
6806 { "Reserved", "nvme.cmd.identify.ctrl.sgls.rsvd1",
6807 FT_UINT32, BASE_HEX, NULL, 0xffc00000, NULL, HFILL}
6809 { &hf_nvme_identify_ctrl_mnan,
6810 { "Maximum Number of Allowed Namespaces (MNAN)", "nvme.cmd.identify.ctrl.mnan",
6811 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL}
6813 { &hf_nvme_identify_ctrl_rsvd4,
6814 { "Reserved", "nvme.cmd.identify.ctrl.rsvd4",
6815 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
6817 { &hf_nvme_identify_ctrl_subnqn,
6818 { "NVM Subsystem NVMe Qualified Name (SUBNQN)", "nvme.cmd.identify.ctrl.subnqn",
6819 FT_STRINGZ, BASE_NONE, NULL, 0x0, NULL, HFILL}
6821 { &hf_nvme_identify_ctrl_rsvd5,
6822 { "Reserved", "nvme.cmd.identify.ctrl.rsvd5",
6823 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
6825 { &hf_nvme_identify_ctrl_nvmeof,
6826 { "NVMeOF Attributes", "nvme.cmd.identify.ctrl.nvmeof",
6827 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
6829 { &hf_nvme_identify_ctrl_nvmeof_ioccsz,
6830 { "I/O Queue Command Capsule Supported Size (IOCCSZ)", "nvme.cmd.identify.ctrl.nvmeof.ioccsz",
6831 FT_UINT32, BASE_CUSTOM, CF_FUNC(add_ctrl_x16_bytes), 0x0, NULL, HFILL}
6833 { &hf_nvme_identify_ctrl_nvmeof_iorcsz,
6834 { "I/O Queue Response Capsule Supported Size (IORCSZ)", "nvme.cmd.identify.ctrl.nvmeof.iorcsz",
6835 FT_UINT32, BASE_CUSTOM, CF_FUNC(add_ctrl_x16_bytes), 0x0, NULL, HFILL}
6837 { &hf_nvme_identify_ctrl_nvmeof_icdoff,
6838 { "In Capsule Data Offset (ICDOFF)", "nvme.cmd.identify.ctrl.nvmeof.icdoff",
6839 FT_UINT16, BASE_CUSTOM, CF_FUNC(add_ctrl_x16_bytes), 0x0, NULL, HFILL}
6841 { &hf_nvme_identify_ctrl_nvmeof_fcatt[0],
6842 { "Fabrics Controller Attributes (FCATT)", "nvme.cmd.identify.ctrl.nvmeof.fcatt",
6843 FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
6845 { &hf_nvme_identify_ctrl_nvmeof_fcatt[1],
6846 { "Dynamic Controller Model", "nvme.cmd.identify.ctrl.nvmeof.fcatt.dcm",
6847 FT_BOOLEAN, 8, NULL, 0x1, NULL, HFILL}
6849 { &hf_nvme_identify_ctrl_nvmeof_fcatt[2],
6850 { "Reserved", "nvme.cmd.identify.ctrl.nvmeof.fcatt.rsvd",
6851 FT_UINT8, BASE_HEX, NULL, 0xfe, NULL, HFILL}
6853 { &hf_nvme_identify_ctrl_nvmeof_msdbd,
6854 { "Maximum SGL Data Block Descriptors (MSDBD)", "nvme.cmd.identify.ctrl.nvmeof.msdbd",
6855 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL}
6857 { &hf_nvme_identify_ctrl_nvmeof_ofcs[0],
6858 { "Optional Fabric Commands Support (OFCS)", "nvme.cmd.identify.ctrl.nvmeof.ofcs",
6859 FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
6861 { &hf_nvme_identify_ctrl_nvmeof_ofcs[1],
6862 { "Supports Disconnect Command", "nvme.cmd.identify.ctrl.nvmeof.ofcs.dcs",
6863 FT_BOOLEAN, 16, NULL, 0x1, NULL, HFILL}
6865 { &hf_nvme_identify_ctrl_nvmeof_ofcs[2],
6866 { "Reserved", "nvme.cmd.identify.ctrl.nvmeof.ofcs.rsvd",
6867 FT_UINT16, BASE_HEX, NULL, 0xfffe, NULL, HFILL}
6869 { &hf_nvme_identify_ctrl_nvmeof_rsvd,
6870 { "Reserved", "nvme.cmd.identify.ctrl.nvmeof.rsvd",
6871 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
6873 { &hf_nvme_identify_ctrl_psds,
6874 { "Power State Attributes", "nvme.cmd.identify.ctrl.psds",
6875 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
6877 { &hf_nvme_identify_ctrl_psd,
6878 { "Power State 0 Descriptor (PSD0)", "nvme.cmd.identify.ctrl.psds.psd",
6879 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
6881 { &hf_nvme_identify_ctrl_psd_mp,
6882 { "Maximum Power (MP)", "nvme.cmd.identify.ctrl.psds.psd.mp",
6883 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
6885 { &hf_nvme_identify_ctrl_psd_rsvd0,
6886 { "Reserved", "nvme.cmd.identify.ctrl.psds.psd.rsvd0",
6887 FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
6889 { &hf_nvme_identify_ctrl_psd_mxps,
6890 { "Max Power Scale (MXPS)", "nvme.cmd.identify.ctrl.psds.psd.mxps",
6891 FT_BOOLEAN, 8, TFS(&units_watts), 0x1, NULL, HFILL}
6893 { &hf_nvme_identify_ctrl_psd_nops,
6894 { "Non-Operational State (NOPS)", "nvme.cmd.identify.ctrl.psds.psd.nops",
6895 FT_BOOLEAN, 8, NULL, 0x2, NULL, HFILL}
6897 { &hf_nvme_identify_ctrl_psd_rsvd1,
6898 { "Reserved", "nvme.cmd.identify.ctrl.psds.psd.rsvd1",
6899 FT_UINT8, BASE_HEX, NULL, 0xfc, NULL, HFILL}
6901 { &hf_nvme_identify_ctrl_psd_enlat,
6902 { "Entry Latency (ENLAT)", "nvme.cmd.identify.ctrl.psds.psd.enlat",
6903 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL}
6905 { &hf_nvme_identify_ctrl_psd_exlat,
6906 { "Exit Latency (EXLAT)", "nvme.cmd.identify.ctrl.psds.psd.exlat",
6907 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL}
6909 { &hf_nvme_identify_ctrl_psd_rrt,
6910 { "Relative Read Throughput (RRT)", "nvme.cmd.identify.ctrl.psds.psd.rrt",
6911 FT_UINT8, BASE_DEC, NULL, 0x1f, NULL, HFILL}
6913 { &hf_nvme_identify_ctrl_psd_rsvd2,
6914 { "Reserved", "nvme.cmd.identify.ctrl.psds.psd.rsvd2",
6915 FT_UINT8, BASE_HEX, NULL, 0xe0, NULL, HFILL}
6917 { &hf_nvme_identify_ctrl_psd_rrl,
6918 { "Relative Read Latency (RRL)", "nvme.cmd.identify.ctrl.psds.psd.rrl",
6919 FT_UINT8, BASE_DEC, NULL, 0x1f, NULL, HFILL}
6921 { &hf_nvme_identify_ctrl_psd_rsvd3,
6922 { "Reserved", "nvme.cmd.identify.ctrl.psds.psd.rsvd3",
6923 FT_UINT8, BASE_HEX, NULL, 0xe0, NULL, HFILL}
6925 { &hf_nvme_identify_ctrl_psd_rwt,
6926 { "Relative Write Throughput (RWT)", "nvme.cmd.identify.ctrl.psds.psd.rwt",
6927 FT_UINT8, BASE_DEC, NULL, 0x1f, NULL, HFILL}
6929 { &hf_nvme_identify_ctrl_psd_rsvd4,
6930 { "Reserved", "nvme.cmd.identify.ctrl.psds.psd.rsvd4",
6931 FT_UINT8, BASE_HEX, NULL, 0xe0, NULL, HFILL}
6933 { &hf_nvme_identify_ctrl_psd_rwl,
6934 { "Relative Write Latency (RWL)", "nvme.cmd.identify.ctrl.psds.psd.rwl",
6935 FT_UINT8, BASE_DEC, NULL, 0x1f, NULL, HFILL}
6937 { &hf_nvme_identify_ctrl_psd_rsvd5,
6938 { "Reserved", "nvme.cmd.identify.ctrl.psds.psd.rsvd5",
6939 FT_UINT8, BASE_HEX, NULL, 0xe0, NULL, HFILL}
6941 { &hf_nvme_identify_ctrl_psd_idlp,
6942 { "Idle Power (IDLP)", "nvme.cmd.identify.ctrl.psds.psd.idlp",
6943 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
6945 { &hf_nvme_identify_ctrl_psd_rsvd6,
6946 { "Reserved", "nvme.cmd.identify.ctrl.psds.psd.rsvd6",
6947 FT_UINT8, BASE_HEX, NULL, 0x3f, NULL, HFILL}
6949 { &hf_nvme_identify_ctrl_psd_ips,
6950 { "Idle Power Scale (IPS)", "nvme.cmd.identify.ctrl.psds.psd.ips",
6951 FT_UINT8, BASE_HEX, VALS(power_scale_tbl), 0xc0, NULL, HFILL}
6953 { &hf_nvme_identify_ctrl_psd_rsvd7,
6954 { "Reserved", "nvme.cmd.identify.ctrl.psds.psd.rsvd7",
6955 FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
6957 { &hf_nvme_identify_ctrl_psd_actp,
6958 { "Active Power (ACTP)", "nvme.cmd.identify.ctrl.psds.psd.actp",
6959 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
6961 { &hf_nvme_identify_ctrl_psd_apw,
6962 { "Active Power Workload (APW)", "nvme.cmd.identify.ctrl.psds.psd.apw",
6963 FT_UINT8, BASE_HEX, NULL, 0x7, NULL, HFILL}
6965 { &hf_nvme_identify_ctrl_psd_rsvd8,
6966 { "Reserved", "nvme.cmd.identify.ctrl.psds.psd.rsvd8",
6967 FT_UINT8, BASE_HEX, NULL, 0x38, NULL, HFILL}
6969 { &hf_nvme_identify_ctrl_psd_aps,
6970 { "Active Power Scale (APS)", "nvme.cmd.identify.ctrl.psds.psd.aps",
6971 FT_UINT8, BASE_HEX, VALS(power_scale_tbl), 0xc0, NULL, HFILL}
6973 { &hf_nvme_identify_ctrl_psd_rsvd9,
6974 { "Reserved", "nvme.cmd.identify.ctrl.psds.psd.rsvd9",
6975 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
6977 { &hf_nvme_identify_ctrl_vs,
6978 { "Vendor Specific", "nvme.cmd.identify.ctrl.vs",
6979 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
6982 /* Identify nslist response */
6983 { &hf_nvme_identify_nslist_nsid,
6984 { "Namespace list element", "nvme.cmd.identify.nslist.nsid",
6985 FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
6987 /* get logpage response */
6988 /* Identify Response */
6989 { &hf_nvme_get_logpage_ify_genctr,
6990 { "Generation Counter (GENCTR)", "nvme.cmd.get_logpage.identify.genctr",
6991 FT_UINT64, BASE_DEC, NULL, 0x0, NULL, HFILL}
6993 { &hf_nvme_get_logpage_ify_numrec,
6994 { "Number of Records (NUMREC)", "nvme.cmd.get_logpage.identify.numrec",
6995 FT_UINT64, BASE_DEC, NULL, 0x0, NULL, HFILL}
6997 { &hf_nvme_get_logpage_ify_recfmt,
6998 { "Record Format (RECFMT)", "nvme.cmd.get_logpage.identify.recfmt",
6999 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
7001 { &hf_nvme_get_logpage_ify_rsvd,
7002 { "Reserved", "nvme.cmd.get_logpage.identify.rsvd",
7003 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
7005 { &hf_nvme_get_logpage_ify_rcrd,
7006 { "Discovery Log Entry", "nvme.cmd.get_logpage.identify.rcrd",
7007 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
7009 { &hf_nvme_get_logpage_ify_rcrd_trtype,
7010 { "Transport Type (TRTYPE)", "nvme.cmd.get_logpage.identify.rcrd.trtype",
7011 FT_UINT8, BASE_HEX, VALS(trt_type_tbl), 0x0, NULL, HFILL}
7013 { &hf_nvme_get_logpage_ify_rcrd_adrfam,
7014 { "Address Family (ADRFAM)", "nvme.cmd.get_logpage.identify.rcrd.adrfam",
7015 FT_UINT8, BASE_HEX, VALS(adrfam_type_tbl), 0x0, NULL, HFILL}
7017 { &hf_nvme_get_logpage_ify_rcrd_subtype,
7018 { "Subsystem Type (SUBTYPE)", "nvme.cmd.get_logpage.identify.rcrd.subtype",
7019 FT_UINT8, BASE_HEX, VALS(sub_type_tbl), 0x0, NULL, HFILL}
7021 { &hf_nvme_get_logpage_ify_rcrd_treq[0],
7022 { "Transport Requirements (TREQ)", "nvme.cmd.get_logpage.identify.rcrd.treq",
7023 FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
7025 { &hf_nvme_get_logpage_ify_rcrd_treq[1],
7026 { "Secure Channel Connection Requirement", "nvme.cmd.get_logpage.identify.rcrd.treq.secch",
7027 FT_BOOLEAN, 8, NULL, 0x1, NULL, HFILL}
7029 { &hf_nvme_get_logpage_ify_rcrd_treq[2],
7030 { "Disable SQ Flow Control Support", "nvme.cmd.get_logpage.identify.rcrd.treq.sqfc",
7031 FT_BOOLEAN, 8, NULL, 0x2, NULL, HFILL}
7033 { &hf_nvme_get_logpage_ify_rcrd_treq[3],
7034 { "Reserved", "nvme.cmd.get_logpage.identify.rcrd.treq.rsvd",
7035 FT_UINT8, BASE_HEX, NULL, 0xf8, NULL, HFILL}
7037 { &hf_nvme_get_logpage_ify_rcrd_portid,
7038 { "Port ID (PORTID)", "nvme.cmd.get_logpage.identify.rcrd.portid",
7039 FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
7041 { &hf_nvme_get_logpage_ify_rcrd_cntlid,
7042 { "Controller ID (CNTLID)", "nvme.cmd.get_logpage.identify.rcrd.cntlid",
7043 FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
7045 { &hf_nvme_get_logpage_ify_rcrd_asqsz,
7046 { "Admin Max SQ Size (ASQSZ)", "nvme.cmd.get_logpage.identify.rcrd.asqsz",
7047 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
7049 { &hf_nvme_get_logpage_disc_rcrd_eflags[0],
7050 { "Entry flags (EFLAGS)", "nvme.cmd.get_logpage.discovery.rcrd.eflags",
7051 FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
7053 { &hf_nvme_get_logpage_disc_rcrd_eflags[1],
7054 { "Duplicate Returned Information (DUPRETINFO)", "nvme.cmd.get_logpage.discovery.rcrd.eflags.dupretinfo",
7055 FT_BOOLEAN, 16, NULL, 0x1, NULL, HFILL}
7057 { &hf_nvme_get_logpage_disc_rcrd_eflags[2],
7058 { "Explicit Persistent Connection Support for Discovery (EPCSD)",
7059 "nvme.cmd.get_logpage.discovery.rcrd.eflags.epcsd",
7060 FT_BOOLEAN, 16, NULL, 0x2, NULL, HFILL}
7062 { &hf_nvme_get_logpage_disc_rcrd_eflags[3],
7063 { "Reserved", "nvme.cmd.get_logpage.discovery.rcrd.eflags.rsvd0",
7064 FT_UINT16, BASE_HEX, NULL, 0xfffc, NULL, HFILL}
7066 { &hf_nvme_get_logpage_ify_rcrd_rsvd0,
7067 { "Reserved", "nvme.cmd.get_logpage.identify.rcrd.rsvd0",
7068 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
7070 { &hf_nvme_get_logpage_ify_rcrd_trsvcid,
7071 { "Transport Service Identifier (TRSVCID)", "nvme.cmd.get_logpage.identify.rcrd.trsvcid",
7072 FT_STRING, BASE_NONE, NULL, 0x0, NULL, HFILL}
7074 { &hf_nvme_get_logpage_ify_rcrd_rsvd1,
7075 { "Reserved", "nvme.cmd.get_logpage.identify.rcrd.rsvd1",
7076 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
7078 { &hf_nvme_get_logpage_ify_rcrd_subnqn,
7079 { "NVM Subsystem Qualified Name (SUBNQN)", "nvme.cmd.get_logpage.identify.rcrd.subnqn",
7080 FT_STRINGZ, BASE_NONE, NULL, 0x0, NULL, HFILL}
7082 { &hf_nvme_get_logpage_ify_rcrd_traddr,
7083 { "Transport Address (TRADDR)", "nvme.cmd.get_logpage.identify.rcrd.traddr",
7084 FT_STRING, BASE_NONE, NULL, 0x0, NULL, HFILL}
7086 { &hf_nvme_get_logpage_ify_rcrd_tsas,
7087 { "Transport Specific Address Subtype (TSAS)", "nvme.cmd.get_logpage.identify.rcrd.tsas",
7088 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
7090 { &hf_nvme_get_logpage_ify_rcrd_tsas_rdma_qptype,
7091 { "RDMA QP Service Type (RDMA_QPTYPE)", "nvme.cmd.get_logpage.identify.rcrd.tsas.rdma_qptype",
7092 FT_UINT8, BASE_HEX, VALS(qp_type_tbl), 0x0, NULL, HFILL}
7094 { &hf_nvme_get_logpage_ify_rcrd_tsas_rdma_prtype,
7095 { "RDMA Provider Type (RDMA_PRTYPE)", "nvme.cmd.get_logpage.identify.rcrd.tsas.rdma_prtype",
7096 FT_UINT8, BASE_HEX, VALS(pr_type_tbl), 0x0, NULL, HFILL}
7098 { &hf_nvme_get_logpage_ify_rcrd_tsas_rdma_cms,
7099 { "RDMA Connection Management Service (RDMA_CMS)", "nvme.cmd.get_logpage.identify.rcrd.tsas.rdma_cms",
7100 FT_UINT8, BASE_HEX, VALS(cms_type_tbl), 0x0, NULL, HFILL}
7102 { &hf_nvme_get_logpage_ify_rcrd_tsas_rdma_rsvd0,
7103 { "Reserved", "nvme.cmd.get_logpage.identify.rcrd.tsas.rdma_rsvd0",
7104 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
7106 { &hf_nvme_get_logpage_ify_rcrd_tsas_rdma_pkey,
7107 { "RDMA Partition Key (RDMA_PKEY)", "nvme.cmd.get_logpage.identify.rcrd.tsas.rdma_pkey",
7108 FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
7110 { &hf_nvme_get_logpage_ify_rcrd_tsas_rdma_rsvd1,
7111 { "Reserved", "nvme.cmd.get_logpage.identify.rcrd.tsas.rdma_rsvd1",
7112 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
7114 { &hf_nvme_get_logpage_ify_rcrd_tsas_tcp_sectype,
7115 { "Security Type (SECTYPE)", "nvme.cmd.get_logpage.identify.rcrd.tsas.tcp_sectype",
7116 FT_UINT8, BASE_HEX, VALS(sec_type_tbl), 0x0, NULL, HFILL}
7118 { &hf_nvme_get_logpage_ify_rcrd_tsas_tcp_rsvd,
7119 { "Reserved", "nvme.cmd.get_logpage.identify.rcrd.tsas.tcp_rsvd",
7120 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
7122 /* Error Information Response */
7123 { &hf_nvme_get_logpage_errinf_errcnt,
7124 { "Error Count", "nvme.cmd.get_logpage.errinf.errcnt",
7125 FT_UINT64, BASE_DEC, NULL, 0x0, NULL, HFILL}
7127 { &hf_nvme_get_logpage_errinf_sqid,
7128 { "Submission Queue ID", "nvme.cmd.get_logpage.errinf.sqid",
7129 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
7131 { &hf_nvme_get_logpage_errinf_cid,
7132 { "Command ID", "nvme.cmd.get_logpage.errinf.cid",
7133 FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
7135 { &hf_nvme_get_logpage_errinf_sf[0],
7136 { "Status Field", "nvme.cmd.get_logpage.errinf.sf",
7137 FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
7139 { &hf_nvme_get_logpage_errinf_sf[1],
7140 { "Status Field Value", "nvme.cmd.get_logpage.errinf.sf.val",
7141 FT_UINT16, BASE_HEX, NULL, 0x7fff, NULL, HFILL}
7143 { &hf_nvme_get_logpage_errinf_sf[2],
7144 { "Status Field Phase Tag", "nvme.cmd.get_logpage.errinf.sf.ptag",
7145 FT_UINT16, BASE_HEX, NULL, 0x8000, NULL, HFILL}
7147 { &hf_nvme_get_logpage_errinf_pel[0],
7148 { "Parameter Error Location", "nvme.cmd.get_logpage.errinf.pel",
7149 FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
7151 { &hf_nvme_get_logpage_errinf_pel[1],
7152 { "Byte in command that contained the error", "nvme.cmd.get_logpage.errinf.pel.bytee",
7153 FT_UINT16, BASE_DEC, NULL, 0xff, NULL, HFILL}
7155 { &hf_nvme_get_logpage_errinf_pel[2],
7156 { "Bit in command that contained the error", "nvme.cmd.get_logpage.errinf.pel.bite",
7157 FT_UINT16, BASE_DEC, NULL, 0x7ff, NULL, HFILL}
7159 { &hf_nvme_get_logpage_errinf_pel[3],
7160 { "Reserved", "nvme.cmd.get_logpage.errinf.pel.rsvd",
7161 FT_UINT16, BASE_DEC, NULL, 0xf8ff, NULL, HFILL}
7163 { &hf_nvme_get_logpage_errinf_lba,
7164 { "LBA", "nvme.cmd.get_logpage.errinf.lba",
7165 FT_UINT64, BASE_HEX, NULL, 0x0, NULL, HFILL}
7167 { &hf_nvme_get_logpage_errinf_ns,
7168 { "Namespace ID", "nvme.cmd.get_logpage.errinf.nsid",
7169 FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
7171 { &hf_nvme_get_logpage_errinf_vsi,
7172 { "Namespace ID", "nvme.cmd.get_logpage.errinf.vsi",
7173 FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
7175 { &hf_nvme_get_logpage_errinf_trtype,
7176 { "Namespace ID", "nvme.cmd.get_logpage.errinf.trype",
7177 FT_UINT8, BASE_HEX, VALS(trt_type_tbl), 0x0, NULL, HFILL}
7179 { &hf_nvme_get_logpage_errinf_rsvd0,
7180 { "Reserved", "nvme.cmd.get_logpage.errinf.rsvd0",
7181 FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
7183 { &hf_nvme_get_logpage_errinf_csi,
7184 { "Command Specific Information", "nvme.cmd.get_logpage.errinf.csi",
7185 FT_UINT64, BASE_HEX, NULL, 0x0, NULL, HFILL}
7187 { &hf_nvme_get_logpage_errinf_tsi,
7188 { "Namespace ID", "nvme.cmd.get_logpage.errinf.tsi",
7189 FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
7191 { &hf_nvme_get_logpage_errinf_rsvd1,
7192 { "Namespace ID", "nvme.cmd.get_logpage.errinf.rsvd1",
7193 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
7195 /* Get LogPage SMART response */
7196 { &hf_nvme_get_logpage_smart_cw[0],
7197 { "Critical Warning", "nvme.cmd.get_logpage.smart.cw",
7198 FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
7200 { &hf_nvme_get_logpage_smart_cw[1],
7201 { "Spare Capacity Below Threshold", "nvme.cmd.get_logpage.smart.cw.sc",
7202 FT_BOOLEAN, 8, NULL, 0x1, NULL, HFILL}
7204 { &hf_nvme_get_logpage_smart_cw[2],
7205 { "Temperature Crossed Threshold", "nvme.cmd.get_logpage.smart.cw.temp",
7206 FT_BOOLEAN, 8, NULL, 0x2, NULL, HFILL}
7208 { &hf_nvme_get_logpage_smart_cw[3],
7209 { "Reliability Degraded due to Significant Media Errors", "nvme.cmd.get_logpage.smart.cw.sme",
7210 FT_BOOLEAN, 8, NULL, 0x4, NULL, HFILL}
7212 { &hf_nvme_get_logpage_smart_cw[4],
7213 { "Media Placed in RO State", "nvme.cmd.get_logpage.smart.cw.ro",
7214 FT_BOOLEAN, 8, NULL, 0x8, NULL, HFILL}
7216 { &hf_nvme_get_logpage_smart_cw[5],
7217 { "Volatile Memory Backup Device Has Failed", "nvme.cmd.get_logpage.smart.cw.bdf",
7218 FT_BOOLEAN, 8, NULL, 0x10, NULL, HFILL}
7220 { &hf_nvme_get_logpage_smart_cw[6],
7221 { "Persistent Memory Region Placed in RO State", "nvme.cmd.get_logpage.smart.cw.mrro",
7222 FT_BOOLEAN, 8, NULL, 0x20, NULL, HFILL}
7224 { &hf_nvme_get_logpage_smart_cw[7],
7225 { "Reserved", "nvme.cmd.get_logpage.smart.cw.rsvd",
7226 FT_UINT8, BASE_HEX, NULL, 0xe0, NULL, HFILL}
7228 { &hf_nvme_get_logpage_smart_ct,
7229 { "Composite Temperature (degrees K)", "nvme.cmd.get_logpage.smart.ct",
7230 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
7232 { &hf_nvme_get_logpage_smart_asc,
7233 { "Available Spare Capacity (%)", "nvme.cmd.get_logpage.smart.asc",
7234 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL}
7236 { &hf_nvme_get_logpage_smart_ast,
7237 { "Available Spare Capacity Threshold (%)", "nvme.cmd.get_logpage.smart.ast",
7238 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL}
7240 { &hf_nvme_get_logpage_smart_lpu,
7241 { "Life Age Estimate (%)", "nvme.cmd.get_logpage.smart.lae",
7242 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL}
7244 { &hf_nvme_get_logpage_smart_egcws[0],
7245 { "Endurance Group Critical Warning Summary", "nvme.cmd.get_logpage.smart.egcws",
7246 FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
7248 { &hf_nvme_get_logpage_smart_egcws[1],
7249 { "Spare Capacity of Endurance Group Below Threshold", "nvme.cmd.get_logpage.smart.egcws.sc",
7250 FT_BOOLEAN, 8, NULL, 0x1, NULL, HFILL}
7252 { &hf_nvme_get_logpage_smart_egcws[2],
7253 { "Reserved", "nvme.cmd.get_logpage.smart.egcws.rsvd0",
7254 FT_BOOLEAN, 8, NULL, 0x2, NULL, HFILL}
7256 { &hf_nvme_get_logpage_smart_egcws[3],
7257 { "Reliability of Endurance Group Degraded due to Media Errors", "nvme.cmd.get_logpage.smart.egcws.me",
7258 FT_BOOLEAN, 8, NULL, 0x4, NULL, HFILL}
7260 { &hf_nvme_get_logpage_smart_egcws[4],
7261 { "A Namespace in Endurance Group Placed in RO State", "nvme.cmd.get_logpage.smart.egcws.ro",
7262 FT_BOOLEAN, 8, NULL, 0x8, NULL, HFILL}
7264 { &hf_nvme_get_logpage_smart_egcws[5],
7265 { "Reserved", "nvme.cmd.get_logpage.smart.egcws.rsvd1",
7266 FT_UINT8, BASE_HEX, NULL, 0xf0, NULL, HFILL}
7268 { &hf_nvme_get_logpage_smart_rsvd0,
7269 { "Reserved", "nvme.cmd.get_logpage.smart.rsvd0",
7270 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
7272 { &hf_nvme_get_logpage_smart_dur,
7273 { "Data Units Read", "nvme.cmd.get_logpage.smart.dur",
7274 FT_BYTES, BASE_NO_DISPLAY_VALUE, NULL, 0x0, NULL, HFILL}
7276 { &hf_nvme_get_logpage_smart_duw,
7277 { "Data Units Written", "nvme.cmd.get_logpage.smart.duw",
7278 FT_BYTES, BASE_NO_DISPLAY_VALUE, NULL, 0x0, NULL, HFILL}
7280 { &hf_nvme_get_logpage_smart_hrc,
7281 { "Host Read Commands", "nvme.cmd.get_logpage.smart.hrc",
7282 FT_BYTES, BASE_NO_DISPLAY_VALUE, NULL, 0x0, NULL, HFILL}
7284 { &hf_nvme_get_logpage_smart_hwc,
7285 { "Host Write Commands", "nvme.cmd.get_logpage.smart.hwc",
7286 FT_BYTES, BASE_NO_DISPLAY_VALUE, NULL, 0x0, NULL, HFILL}
7288 { &hf_nvme_get_logpage_smart_cbt,
7289 { "Controller Busy Time (minutes)", "nvme.cmd.get_logpage.smart.cbt",
7290 FT_BYTES, BASE_NO_DISPLAY_VALUE, NULL, 0x0, NULL, HFILL}
7292 { &hf_nvme_get_logpage_smart_pc,
7293 { "Power Cycles", "nvme.cmd.get_logpage.smart.pc",
7294 FT_BYTES, BASE_NO_DISPLAY_VALUE, NULL, 0x0, NULL, HFILL}
7296 { &hf_nvme_get_logpage_smart_poh,
7297 { "Power On Hours", "nvme.cmd.get_logpage.smart.poh",
7298 FT_BYTES, BASE_NO_DISPLAY_VALUE, NULL, 0x0, NULL, HFILL}
7300 { &hf_nvme_get_logpage_smart_mie,
7301 { "Media Integrity Errors", "nvme.cmd.get_logpage.smart.mie",
7302 FT_BYTES, BASE_NO_DISPLAY_VALUE, NULL, 0x0, NULL, HFILL}
7304 { &hf_nvme_get_logpage_smart_us,
7305 { "Unsafe Shutdowns", "nvme.cmd.get_logpage.smart.us",
7306 FT_BYTES, BASE_NO_DISPLAY_VALUE, NULL, 0x0, NULL, HFILL}
7308 { &hf_nvme_get_logpage_smart_ele,
7309 { "Number of Error Information Log Entries", "nvme.cmd.get_logpage.smart.ele",
7310 FT_BYTES, BASE_NO_DISPLAY_VALUE, NULL, 0x0, NULL, HFILL}
7312 { &hf_nvme_get_logpage_smart_wctt,
7313 { "Warning Composite Temperature Time (minutes)", "nvme.cmd.get_logpage.smart.wctt",
7314 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL}
7316 { &hf_nvme_get_logpage_smart_cctt,
7317 { "Critical Composite Temperature Time (minutes)", "nvme.cmd.get_logpage.smart.cctt",
7318 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL}
7320 { &hf_nvme_get_logpage_smart_ts[0],
7321 { "Temperature Sensors", "nvme.cmd.get_logpage.smart.ts",
7322 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
7324 { &hf_nvme_get_logpage_smart_ts[1],
7325 { "Temperature Sensor 1 (degrees K)", "nvme.cmd.get_logpage.smart.ts.s1",
7326 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
7328 { &hf_nvme_get_logpage_smart_ts[2],
7329 { "Temperature Sensor 2 (degrees K)", "nvme.cmd.get_logpage.smart.ts.s2",
7330 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
7332 { &hf_nvme_get_logpage_smart_ts[3],
7333 { "Temperature Sensor 3 (degrees K)", "nvme.cmd.get_logpage.smart.ts.s3",
7334 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
7336 { &hf_nvme_get_logpage_smart_ts[4],
7337 { "Temperature Sensor 4 (degrees K)", "nvme.cmd.get_logpage.smart.ts.s4",
7338 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
7340 { &hf_nvme_get_logpage_smart_ts[5],
7341 { "Temperature Sensor 5 (degrees K)", "nvme.cmd.get_logpage.smart.ts.s5",
7342 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
7344 { &hf_nvme_get_logpage_smart_ts[6],
7345 { "Temperature Sensor 6 (degrees K)", "nvme.cmd.get_logpage.smart.ts.s6",
7346 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
7348 { &hf_nvme_get_logpage_smart_ts[7],
7349 { "Temperature Sensor 7 (degrees K)", "nvme.cmd.get_logpage.smart.ts.s7",
7350 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
7352 { &hf_nvme_get_logpage_smart_ts[8],
7353 { "Temperature Sensor 8 (degrees K)", "nvme.cmd.get_logpage.smart.ts.s8",
7354 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
7356 { &hf_nvme_get_logpage_smart_tmt1c,
7357 { "Thermal Management Temperature 1 Transition Count", "nvme.cmd.get_logpage.smart.tmt1c",
7358 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL}
7360 { &hf_nvme_get_logpage_smart_tmt2c,
7361 { "Thermal Management Temperature 2 Transition Count", "nvme.cmd.get_logpage.smart.tmt2c",
7362 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL}
7364 { &hf_nvme_get_logpage_smart_tmt1t,
7365 { "Total Time For Thermal Management Temperature 1 (seconds)", "nvme.cmd.get_logpage.smart.tmt1t",
7366 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL}
7368 { &hf_nvme_get_logpage_smart_tmt2t,
7369 { "Total Time For Thermal Management Temperature 2 (seconds)", "nvme.cmd.get_logpage.smart.tmt2t",
7370 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL}
7372 { &hf_nvme_get_logpage_smart_rsvd1,
7373 { "Reserved", "nvme.cmd.get_logpage.smart.rsvd1",
7374 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
7376 /* FW Slot Information Response */
7377 { &hf_nvme_get_logpage_fw_slot_afi[0],
7378 { "Active Firmware Info (AFI)", "nvme.cmd.get_logpage.fw_slot.afi",
7379 FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
7381 { &hf_nvme_get_logpage_fw_slot_afi[1],
7382 { "Active Firmware Slot", "nvme.cmd.get_logpage.fw_slot.afi.afs",
7383 FT_UINT8, BASE_HEX, NULL, 0x7, NULL, HFILL}
7385 { &hf_nvme_get_logpage_fw_slot_afi[2],
7386 { "Reserved", "nvme.cmd.get_logpage.fw_slot.afi.rsvd0",
7387 FT_UINT8, BASE_HEX, NULL, 0x8, NULL, HFILL}
7389 { &hf_nvme_get_logpage_fw_slot_afi[3],
7390 { "Next Reset Firmware Slot", "nvme.cmd.get_logpage.fw_slot.afi.nfs",
7391 FT_UINT8, BASE_HEX, NULL, 0x70, NULL, HFILL}
7393 { &hf_nvme_get_logpage_fw_slot_afi[4],
7394 { "Reserved", "nvme.cmd.get_logpage.fw_slot.afi.rsvd1",
7395 FT_UINT8, BASE_HEX, NULL, 0x80, NULL, HFILL}
7397 { &hf_nvme_get_logpage_fw_slot_rsvd0,
7398 { "Reserved", "nvme.cmd.get_logpage.fw_slot.rsvd0",
7399 FT_UINT64, BASE_HEX, NULL, 0x0, NULL, HFILL}
7401 { &hf_nvme_get_logpage_fw_slot_frs[0],
7402 { "Firmware Slot Revisions", "nvme.cmd.get_logpage.fw_slot.frs",
7403 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
7405 { &hf_nvme_get_logpage_fw_slot_frs[1],
7406 { "Firmware Revision for Slot 1", "nvme.cmd.get_logpage.fw_slot.frs.s1",
7407 FT_UINT64, BASE_HEX, NULL, 0x0, NULL, HFILL}
7409 { &hf_nvme_get_logpage_fw_slot_frs[2],
7410 { "Firmware Revision for Slot 2", "nvme.cmd.get_logpage.fw_slot.frs.s2",
7411 FT_UINT64, BASE_HEX, NULL, 0x0, NULL, HFILL}
7413 { &hf_nvme_get_logpage_fw_slot_frs[3],
7414 { "Firmware Revision for Slot 3", "nvme.cmd.get_logpage.fw_slot.frs.s3",
7415 FT_UINT64, BASE_HEX, NULL, 0x0, NULL, HFILL}
7417 { &hf_nvme_get_logpage_fw_slot_frs[4],
7418 { "Firmware Revision for Slot 4", "nvme.cmd.get_logpage.fw_slot.frs.s4",
7419 FT_UINT64, BASE_HEX, NULL, 0x0, NULL, HFILL}
7421 { &hf_nvme_get_logpage_fw_slot_frs[5],
7422 { "Firmware Revision for Slot 5", "nvme.cmd.get_logpage.fw_slot.frs.s5",
7423 FT_UINT64, BASE_HEX, NULL, 0x0, NULL, HFILL}
7425 { &hf_nvme_get_logpage_fw_slot_frs[6],
7426 { "Firmware Revision for Slot 6", "nvme.cmd.get_logpage.fw_slot.frs.s6",
7427 FT_UINT64, BASE_HEX, NULL, 0x0, NULL, HFILL}
7429 { &hf_nvme_get_logpage_fw_slot_frs[7],
7430 { "Firmware Revision for Slot 7", "nvme.cmd.get_logpage.fw_slot.frs.s7",
7431 FT_UINT64, BASE_HEX, NULL, 0x0, NULL, HFILL}
7433 { &hf_nvme_get_logpage_fw_slot_rsvd1,
7434 { "Reserved", "nvme.cmd.get_logpage.fw_slot.rsvd1",
7435 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
7437 /* Changed NameSpace List Response */
7438 { &hf_nvme_get_logpage_changed_nslist,
7439 { "Changed Namespace", "nvme.cmd.get_logpage.changed_nslist",
7440 FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
7442 /* Commands Supported and Effects Response */
7443 { &hf_nvme_get_logpage_cmd_and_eff_cs,
7444 { "Command Supported Entry", "nvme.cmd.get_logpage.cmd_and_eff.cs",
7445 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
7447 { &hf_nvme_get_logpage_cmd_and_eff_cseds[0],
7448 { "Commands Supported and Effects Data Structure", "nvme.cmd.get_logpage.cmd_and_eff.cseds",
7449 FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
7451 { &hf_nvme_get_logpage_cmd_and_eff_cseds[1],
7452 { "Command Supported (CSUPP)", "nvme.cmd.get_logpage.cmd_and_eff.cseds.csupp",
7453 FT_BOOLEAN, 32, NULL, 0x1, NULL, HFILL}
7455 { &hf_nvme_get_logpage_cmd_and_eff_cseds[2],
7456 { "Logical Block Content Change (LBCC)", "nvme.cmd.get_logpage.cmd_and_eff.cseds.lbcc",
7457 FT_BOOLEAN, 32, NULL, 0x2, NULL, HFILL}
7459 { &hf_nvme_get_logpage_cmd_and_eff_cseds[3],
7460 { "Namespace Capability Change (NCC)", "nvme.cmd.get_logpage.cmd_and_eff.cseds.ncc",
7461 FT_BOOLEAN, 32, NULL, 0x4, NULL, HFILL}
7463 { &hf_nvme_get_logpage_cmd_and_eff_cseds[4],
7464 { "Namespace Inventory Change (NIC)", "nvme.cmd.get_logpage.cmd_and_eff.cseds.nic",
7465 FT_BOOLEAN, 32, NULL, 0x8, NULL, HFILL}
7467 { &hf_nvme_get_logpage_cmd_and_eff_cseds[5],
7468 { "Controller Capability Change (CCC)", "nvme.cmd.get_logpage.cmd_and_eff.cseds.ccc",
7469 FT_BOOLEAN, 32, NULL, 0x10, NULL, HFILL}
7471 { &hf_nvme_get_logpage_cmd_and_eff_cseds[6],
7472 { "Reserved", "nvme.cmd.get_logpage.cmd_and_eff.cseds.rsvd0",
7473 FT_UINT32, BASE_HEX, NULL, 0xffe0, NULL, HFILL}
7475 { &hf_nvme_get_logpage_cmd_and_eff_cseds[7],
7476 { "Command Submission and Execution (CSE)", "nvme.cmd.get_logpage.cmd_and_eff.cseds.cse",
7477 FT_UINT32, BASE_HEX, VALS(cmd_eff_cse_tbl), 0x70000, NULL, HFILL}
7479 { &hf_nvme_get_logpage_cmd_and_eff_cseds[8],
7480 { "UUID Selection Supported", "nvme.cmd.get_logpage.cmd_and_eff.cseds.uss",
7481 FT_BOOLEAN, 32, NULL, 0x80000, NULL, HFILL}
7483 { &hf_nvme_get_logpage_cmd_and_eff_cseds[9],
7484 { "Reserved", "nvme.cmd.get_logpage.cmd_and_eff.cseds.rsvd1",
7485 FT_UINT32, BASE_HEX, NULL, 0xfff00000, NULL, HFILL}
7487 /* Device Self-Test Response */
7488 { &hf_nvme_get_logpage_selftest_csto[0],
7489 { "Current Device Self-Test Operation", "nvme.cmd.get_logpage.selftest.csto",
7490 FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
7492 { &hf_nvme_get_logpage_selftest_csto[1],
7493 { "Current Self-Test Operation Status", "nvme.cmd.get_logpage.selftest.csto.st",
7494 FT_UINT8, BASE_HEX, VALS(stest_type_active_tbl), 0xf, NULL, HFILL}
7496 { &hf_nvme_get_logpage_selftest_csto[2],
7497 { "Reserved", "nvme.cmd.get_logpage.selftest.csto.rsvd",
7498 FT_UINT8, BASE_HEX, NULL, 0xf0, NULL, HFILL}
7500 { &hf_nvme_get_logpage_selftest_cstc[0],
7501 { "Current Device Self-Test Completion", "nvme.cmd.get_logpage.selftest.cstc",
7502 FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
7504 { &hf_nvme_get_logpage_selftest_cstc[1],
7505 { "Self-Test Completion Percent", "nvme.cmd.get_logpage.selftest.cstc.pcnt",
7506 FT_UINT8, BASE_DEC, NULL, 0x7f, NULL, HFILL}
7508 { &hf_nvme_get_logpage_selftest_cstc[2],
7509 { "Reserved", "nvme.cmd.get_logpage.selftest.cstc.rsvd",
7510 FT_UINT8, BASE_HEX, NULL, 0x80, NULL, HFILL}
7512 { &hf_nvme_get_logpage_selftest_rsvd,
7513 { "Self-Test Completion Percent", "nvme.cmd.get_logpage.selftest.rsvd",
7514 FT_UINT16, BASE_HEX, NULL, 0x80, NULL, HFILL}
7516 { &hf_nvme_get_logpage_selftest_res,
7517 { "Latest Self-test Result Data Structure", "nvme.cmd.get_logpage.selftest.res",
7518 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
7520 { &hf_nvme_get_logpage_selftest_res_status[0],
7521 { "Device Self-test Status", "nvme.cmd.get_logpage.selftest.res.status",
7522 FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
7524 { &hf_nvme_get_logpage_selftest_res_status[1],
7525 { "Device Self-test Result", "nvme.cmd.get_logpage.selftest.res.status.result",
7526 FT_UINT8, BASE_HEX, VALS(stest_result_tbl), 0xf, NULL, HFILL}
7528 { &hf_nvme_get_logpage_selftest_res_status[2],
7529 { "Device Self-test Type", "nvme.cmd.get_logpage.selftest.res.status.type",
7530 FT_UINT8, BASE_HEX, VALS(stest_type_done_tbl), 0xf0, NULL, HFILL}
7532 { &hf_nvme_get_logpage_selftest_res_sn,
7533 { "Segment Number", "nvme.cmd.get_logpage.selftest.res.sn",
7534 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL}
7536 { &hf_nvme_get_logpage_selftest_res_vdi[0],
7537 { "Valid Diagnostic Information", "nvme.cmd.get_logpage.selftest.res.vdi",
7538 FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
7540 { &hf_nvme_get_logpage_selftest_res_vdi[1],
7541 { "Namespace Identifier (NSID) Field Valid", "nvme.cmd.get_logpage.selftest.res.vdi.nsid",
7542 FT_BOOLEAN, 8, NULL, 0x1, NULL, HFILL}
7544 { &hf_nvme_get_logpage_selftest_res_vdi[2],
7545 { "Failing LBA (FLBA) Field Valid", "nvme.cmd.get_logpage.selftest.res.vdi.flba",
7546 FT_BOOLEAN, 8, NULL, 0x2, NULL, HFILL}
7548 { &hf_nvme_get_logpage_selftest_res_vdi[3],
7549 { "Status Code Type (SCT) Field Valid", "nvme.cmd.get_logpage.selftest.res.vdi.sct",
7550 FT_BOOLEAN, 8, NULL, 0x4, NULL, HFILL}
7552 { &hf_nvme_get_logpage_selftest_res_vdi[4],
7553 { "Status Code (SC) Field Valid", "nvme.cmd.get_logpage.selftest.res.vdi.sc",
7554 FT_BOOLEAN, 8, NULL, 0x8, NULL, HFILL}
7556 { &hf_nvme_get_logpage_selftest_res_vdi[5],
7557 { "Reserved", "nvme.cmd.get_logpage.selftest.res.vdi.rsvd",
7558 FT_BOOLEAN, 8, NULL, 0xf0, NULL, HFILL}
7560 { &hf_nvme_get_logpage_selftest_res_rsvd,
7561 { "Reserved", "nvme.cmd.get_logpage.selftest.res.rsvd",
7562 FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
7564 { &hf_nvme_get_logpage_selftest_res_poh,
7565 { "Power On Hours (POH)", "nvme.cmd.get_logpage.selftest.res.poh",
7566 FT_UINT64, BASE_DEC, NULL, 0x0, NULL, HFILL}
7568 { &hf_nvme_get_logpage_selftest_res_nsid,
7569 { "Namespace Identifier (NSID)", "nvme.cmd.get_logpage.selftest.res.nsid",
7570 FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
7572 { &hf_nvme_get_logpage_selftest_res_flba,
7573 { "Failing LBA", "nvme.cmd.get_logpage.selftest.res.flba",
7574 FT_UINT64, BASE_HEX, NULL, 0x0, NULL, HFILL}
7576 { &hf_nvme_get_logpage_selftest_res_sct[0],
7577 { "Status Code Type", "nvme.cmd.get_logpage.selftest.res.sct",
7578 FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
7580 { &hf_nvme_get_logpage_selftest_res_sct[1],
7581 { "Additional Information", "nvme.cmd.get_logpage.selftest.res.sct.ai",
7582 FT_UINT8, BASE_HEX, NULL, 0x7, NULL, HFILL}
7584 { &hf_nvme_get_logpage_selftest_res_sct[2],
7585 { "Reserved", "nvme.cmd.get_logpage.selftest.res.sct.rsvd",
7586 FT_UINT8, BASE_HEX, NULL, 0xf8, NULL, HFILL}
7588 { &hf_nvme_get_logpage_selftest_res_sc,
7589 { "Status Code", "nvme.cmd.get_logpage.selftest.res.sc",
7590 FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
7592 { &hf_nvme_get_logpage_selftest_res_vs,
7593 { "Vendor Specific", "nvme.cmd.get_logpage.selftest.res.vs",
7594 FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
7596 /* Telemetry Log Response */
7597 { &hf_nvme_get_logpage_telemetry_li,
7598 { "Log Identifier", "nvme.cmd.get_logpage.telemetry.li",
7599 FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
7601 { &hf_nvme_get_logpage_telemetry_rsvd0,
7602 { "Reserved", "nvme.cmd.get_logpage.telemetry.rsvd0",
7603 FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
7605 { &hf_nvme_get_logpage_telemetry_ieee,
7606 { "IEEE OUI Identifier (IEEE)", "nvme.cmd.get_logpage.telemetry.ieee",
7607 FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
7609 { &hf_nvme_get_logpage_telemetry_da1lb,
7610 { "Telemetry Data Area 1 Last Block", "nvme.cmd.get_logpage.telemetry.da1b",
7611 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
7613 { &hf_nvme_get_logpage_telemetry_da2lb,
7614 { "Telemetry Data Area 2 Last Block", "nvme.cmd.get_logpage.telemetry.da2b",
7615 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
7617 { &hf_nvme_get_logpage_telemetry_da3lb,
7618 { "Telemetry Data Area 3 Last Block", "nvme.cmd.get_logpage.telemetry.da3b",
7619 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
7621 { &hf_nvme_get_logpage_telemetry_rsvd1,
7622 { "Reserved", "nvme.cmd.get_logpage.telemetry.rsvd1",
7623 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
7625 { &hf_nvme_get_logpage_telemetry_da,
7626 { "Telemetry Data Available", "nvme.cmd.get_logpage.telemetry.da",
7627 FT_BOOLEAN, BASE_NONE, NULL, 0x0, NULL, HFILL}
7629 { &hf_nvme_get_logpage_telemetry_dgn,
7630 { "Telemetry Data Generation Number", "nvme.cmd.get_logpage.telemetry.dgn",
7631 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL}
7633 { &hf_nvme_get_logpage_telemetry_ri,
7634 { "Reason Identifier", "nvme.cmd.get_logpage.telemetry.ri",
7635 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
7637 { &hf_nvme_get_logpage_telemetry_db,
7638 { "Telemetry Data Block", "nvme.cmd.get_logpage.telemetry.db",
7639 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
7641 /* Endurance Group Response */
7642 { &hf_nvme_get_logpage_egroup_cw[0],
7643 { "Critical Warning", "nvme.cmd.get_logpage.egroup.cw",
7644 FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
7646 { &hf_nvme_get_logpage_egroup_cw[1],
7647 { "Available Spare Capacity Below Threshold", "nvme.cmd.get_logpage.egroup.cw.asc",
7648 FT_BOOLEAN, 8, NULL, 0x1, NULL, HFILL}
7650 { &hf_nvme_get_logpage_egroup_cw[2],
7651 { "Reserved", "nvme.cmd.get_logpage.egroup.cw.rsvd0",
7652 FT_BOOLEAN, 8, NULL, 0x2, NULL, HFILL}
7654 { &hf_nvme_get_logpage_egroup_cw[3],
7655 { "Reliability of Endurance Group Degraded due to Media Errors", "nvme.cmd.get_logpage.egroup.cw.rd",
7656 FT_BOOLEAN, 8, NULL, 0x4, NULL, HFILL}
7658 { &hf_nvme_get_logpage_egroup_cw[4],
7659 { "All Namespaces in Endurance Group Placed in RO State", "nvme.cmd.get_logpage.egroup.cw.ro",
7660 FT_BOOLEAN, 8, NULL, 0x8, NULL, HFILL}
7662 { &hf_nvme_get_logpage_egroup_cw[5],
7663 { "Reserved", "nvme.cmd.get_logpage.egroup.cw.rsvd1",
7664 FT_BOOLEAN, 8, NULL, 0xf0, NULL, HFILL}
7666 { &hf_nvme_get_logpage_egroup_rsvd0,
7667 { "Reserved", "nvme.cmd.get_logpage.egroup.rsvd0",
7668 FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
7670 { &hf_nvme_get_logpage_egroup_as,
7671 { "Available Spare Capacity %", "nvme.cmd.get_logpage.egroup.as",
7672 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL}
7674 { &hf_nvme_get_logpage_egroup_ast,
7675 { "Available Spare Threshold %", "nvme.cmd.get_logpage.egroup.ast",
7676 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL}
7678 { &hf_nvme_get_logpage_egroup_pu,
7679 { "Life Age (Percentage Used) %", "nvme.cmd.get_logpage.egroup.pu",
7680 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL}
7682 { &hf_nvme_get_logpage_egroup_rsvd1,
7683 { "Reserved", "nvme.cmd.get_logpage.egroup.rsvd1",
7684 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
7686 { &hf_nvme_get_logpage_egroup_ee,
7687 { "Endurance Estimate (GB that may be written)", "nvme.cmd.get_logpage.egroup.ee",
7688 FT_BYTES, BASE_NO_DISPLAY_VALUE, NULL, 0x0, NULL, HFILL}
7690 { &hf_nvme_get_logpage_egroup_dur,
7691 { "Data Units Read (GB)", "nvme.cmd.get_logpage.egroup.dur",
7692 FT_BYTES, BASE_NO_DISPLAY_VALUE, NULL, 0x0, NULL, HFILL}
7694 { &hf_nvme_get_logpage_egroup_duw,
7695 { "Data Units Written (GB)", "nvme.cmd.get_logpage.egroup.duw",
7696 FT_BYTES, BASE_NO_DISPLAY_VALUE, NULL, 0x0, NULL, HFILL}
7698 { &hf_nvme_get_logpage_egroup_muw,
7699 { "Media Units Written (GB)", "nvme.cmd.get_logpage.egroup.muw",
7700 FT_BYTES, BASE_NO_DISPLAY_VALUE, NULL, 0x0, NULL, HFILL}
7702 { &hf_nvme_get_logpage_egroup_hrc,
7703 { "Host Read Commands", "nvme.cmd.get_logpage.egroup.hrc",
7704 FT_BYTES, BASE_NO_DISPLAY_VALUE, NULL, 0x0, NULL, HFILL}
7706 { &hf_nvme_get_logpage_egroup_hwc,
7707 { "Host Write Commands", "nvme.cmd.get_logpage.egroup.hwc",
7708 FT_BYTES, BASE_NO_DISPLAY_VALUE, NULL, 0x0, NULL, HFILL}
7710 { &hf_nvme_get_logpage_egroup_mdie,
7711 { "Media and Data Integrity Errors", "nvme.cmd.get_logpage.egroup.mdie",
7712 FT_BYTES, BASE_NO_DISPLAY_VALUE, NULL, 0x0, NULL, HFILL}
7714 { &hf_nvme_get_logpage_egroup_ele,
7715 { "Media and Data Integrity Errors", "nvme.cmd.get_logpage.egroup.ele",
7716 FT_BYTES, BASE_NO_DISPLAY_VALUE, NULL, 0x0, NULL, HFILL}
7718 { &hf_nvme_get_logpage_egroup_rsvd2,
7719 { "Reserved", "nvme.cmd.get_logpage.egroup.rsvd2",
7720 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
7722 /* Predictable Latency NVMSet Response */
7723 { &hf_nvme_get_logpage_pred_lat_status[0],
7724 { "Predictable Latency NVM Set Status", "nvme.cmd.get_logpage.pred_lat.status",
7725 FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
7727 { &hf_nvme_get_logpage_pred_lat_status[1],
7728 { "Enabled Window Setting", "nvme.cmd.get_logpage.pred_lat.status.ws",
7729 FT_UINT8, BASE_HEX, VALS(plat_status_tbl), 0x7, NULL, HFILL}
7731 { &hf_nvme_get_logpage_pred_lat_status[2],
7732 { "Reserved", "nvme.cmd.get_logpage.pred_lat.status.rsvd",
7733 FT_UINT8, BASE_HEX, NULL, 0xf8, NULL, HFILL}
7735 { &hf_nvme_get_logpage_pred_lat_rsvd0,
7736 { "Reserved", "nvme.cmd.get_logpage.pred_lat.rsvd0",
7737 FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
7739 { &hf_nvme_get_logpage_pred_lat_etype[0],
7740 { "Event Type", "nvme.cmd.get_logpage.pred_lat.etype",
7741 FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
7743 { &hf_nvme_get_logpage_pred_lat_etype[1],
7744 { "DTWIN Reads Warning", "nvme.cmd.get_logpage.pred_lat.etype.rw",
7745 FT_BOOLEAN, 16, NULL, 0x1, NULL, HFILL}
7747 { &hf_nvme_get_logpage_pred_lat_etype[2],
7748 { "DTWIN Writes Warning", "nvme.cmd.get_logpage.pred_lat.etype.ww",
7749 FT_BOOLEAN, 16, NULL, 0x2, NULL, HFILL}
7751 { &hf_nvme_get_logpage_pred_lat_etype[3],
7752 { "DTWIN Time Warning", "nvme.cmd.get_logpage.pred_lat.etype.tw",
7753 FT_BOOLEAN, 16, NULL, 0x4, NULL, HFILL}
7755 { &hf_nvme_get_logpage_pred_lat_etype[4],
7756 { "Reserved", "nvme.cmd.get_logpage.pred_lat.etype.rsvd",
7757 FT_UINT16, BASE_HEX, NULL, 0x3ff8, NULL, HFILL}
7759 { &hf_nvme_get_logpage_pred_lat_etype[5],
7760 { "Autonomous transition from DTWIN to NDWIN due to typical or maximum value exceeded", "nvme.cmd.get_logpage.pred_lat.etype.atve",
7761 FT_BOOLEAN, 16, NULL, 0x4000, NULL, HFILL}
7763 { &hf_nvme_get_logpage_pred_lat_etype[6],
7764 { "Autonomous transition from DTWIN to NDWIN due to Deterministic Excursion", "nvme.cmd.get_logpage.pred_lat.etype.atde",
7765 FT_BOOLEAN, 16, NULL, 0x8000, NULL, HFILL}
7767 { &hf_nvme_get_logpage_pred_lat_rsvd1,
7768 { "Reserved", "nvme.cmd.get_logpage.pred_lat.rsvd1",
7769 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
7771 { &hf_nvme_get_logpage_pred_lat_dtwin_rt,
7772 { "DTWIN Reads Typical (4 KiB blocks)", "nvme.cmd.get_logpage.pred_lat.dtwin_rt",
7773 FT_UINT64, BASE_DEC, NULL, 0x0, NULL, HFILL}
7775 { &hf_nvme_get_logpage_pred_lat_dtwin_wt,
7776 { "DTWIN Writes Typical (optimal block size)", "nvme.cmd.get_logpage.pred_lat.dtwin_wt",
7777 FT_UINT64, BASE_DEC, NULL, 0x0, NULL, HFILL}
7779 { &hf_nvme_get_logpage_pred_lat_dtwin_tm,
7780 { "DTWIN Time Maximum (ms)", "nvme.cmd.get_logpage.pred_lat.dtwin_tm",
7781 FT_UINT64, BASE_DEC, NULL, 0x0, NULL, HFILL}
7783 { &hf_nvme_get_logpage_pred_lat_ndwin_tmh,
7784 { "NDWIN Time Minimum High (ms)", "nvme.cmd.get_logpage.pred_lat.ndwin_tmh",
7785 FT_UINT64, BASE_DEC, NULL, 0x0, NULL, HFILL}
7787 { &hf_nvme_get_logpage_pred_lat_ndwin_tml,
7788 { "NDWIN Time Minimum Low (ms)", "nvme.cmd.get_logpage.pred_lat.ndwin_tml",
7789 FT_UINT64, BASE_DEC, NULL, 0x0, NULL, HFILL}
7791 { &hf_nvme_get_logpage_pred_lat_rsvd2,
7792 { "Reserved", "nvme.cmd.get_logpage.pred_lat.rsvd2",
7793 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
7795 { &hf_nvme_get_logpage_pred_lat_dtwin_re,
7796 { "DTWIN Reads Estimate (4 KiB blocks)", "nvme.cmd.get_logpage.pred_lat.dtwin_re",
7797 FT_UINT64, BASE_DEC, NULL, 0x0, NULL, HFILL}
7799 { &hf_nvme_get_logpage_pred_lat_dtwin_we,
7800 { "DTWIN Writes Estimate (optimal block size)", "nvme.cmd.get_logpage.pred_lat.dtwin_we",
7801 FT_UINT64, BASE_DEC, NULL, 0x0, NULL, HFILL}
7803 { &hf_nvme_get_logpage_pred_lat_dtwin_te,
7804 { "DTWIN Time Estimate (ms)", "nvme.cmd.get_logpage.pred_lat.dtwin_te",
7805 FT_UINT64, BASE_DEC, NULL, 0x0, NULL, HFILL}
7807 { &hf_nvme_get_logpage_pred_lat_rsvd3,
7808 { "Reserved", "nvme.cmd.get_logpage.pred_lat.rsvd3",
7809 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
7811 /* Predictable Latency NVMSet Aggregate Response */
7812 { &hf_nvme_get_logpage_pred_lat_aggreg_ne,
7813 { "Number of Entries", "nvme.cmd.get_logpage.pred_lat_aggreg.ne",
7814 FT_UINT64, BASE_DEC, NULL, 0x0, NULL, HFILL}
7816 { &hf_nvme_get_logpage_pred_lat_aggreg_nset,
7817 { "NVM Set with Pending Predictable Latency Event", "nvme.cmd.get_logpage.pred_lat_aggreg.nset",
7818 FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
7820 /* ANA Response */
7821 { &hf_nvme_get_logpage_ana_chcnt,
7822 { "Change Count", "nvme.cmd.get_logpage.ana.chcnt",
7823 FT_UINT64, BASE_DEC, NULL, 0x0, NULL, HFILL}
7825 { &hf_nvme_get_logpage_ana_ngd,
7826 { "Number of ANA Group Descriptors", "nvme.cmd.get_logpage.ana.ngd",
7827 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL}
7829 { &hf_nvme_get_logpage_ana_rsvd,
7830 { "Reserved", "nvme.cmd.get_logpage.ana.rsvd",
7831 FT_UINT64, BASE_HEX, NULL, 0x0, NULL, HFILL}
7833 { &hf_nvme_get_logpage_ana_grp,
7834 { "ANA Group Descriptor", "nvme.cmd.get_logpage.ana.grp",
7835 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
7837 { &hf_nvme_get_logpage_ana_grp_id,
7838 { "ANA Group ID", "nvme.cmd.get_logpage.ana.grp.id",
7839 FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
7841 { &hf_nvme_get_logpage_ana_grp_nns,
7842 { "Number of NSID Values", "nvme.cmd.get_logpage.ana.grp.nns",
7843 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL}
7845 { &hf_nvme_get_logpage_ana_grp_chcnt,
7846 { "Change Count", "nvme.cmd.get_logpage.ana.grp.chcnt",
7847 FT_UINT64, BASE_DEC, NULL, 0x0, NULL, HFILL}
7849 { &hf_nvme_get_logpage_ana_grp_anas[0],
7850 { "ANA State", "nvme.cmd.get_logpage.ana.grp.anas",
7851 FT_UINT8, BASE_HEX, NULL, 0xf, NULL, HFILL}
7853 { &hf_nvme_get_logpage_ana_grp_anas[1],
7854 { "Asymmetric Namespace Access State", "nvme.cmd.get_logpage.ana.grp.anas.state",
7855 FT_UINT8, BASE_HEX, VALS(ana_state_tbl), 0xf, NULL, HFILL}
7857 { &hf_nvme_get_logpage_ana_grp_anas[2],
7858 { "Reserved", "nvme.cmd.get_logpage.ana.grp.anas.rsvd",
7859 FT_UINT8, BASE_HEX, NULL, 0xf0, NULL, HFILL}
7861 { &hf_nvme_get_logpage_ana_grp_rsvd,
7862 { "Reserved", "nvme.cmd.get_logpage.ana.grp.rsvd",
7863 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
7865 { &hf_nvme_get_logpage_ana_grp_nsid,
7866 { "Namespace Identifier", "nvme.cmd.get_logpage.ana.grp.nsid",
7867 FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
7869 /* LBA Status Information Response */
7870 { &hf_nvme_get_logpage_lba_status_lslplen,
7871 { "LBA Status Log Page Length (LSLPLEN)", "nvme.cmd.get_logpage.lba_status.lslplen",
7872 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL}
7874 { &hf_nvme_get_logpage_lba_status_nlslne,
7875 { "Number of LBA Status Log Namespace Elements (NLSLNE)", "nvme.cmd.get_logpage.lba_status.nlslne",
7876 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL}
7878 { &hf_nvme_get_logpage_lba_status_estulb,
7879 { "Estimate of Unrecoverable Logical Blocks (ESTULB)", "nvme.cmd.get_logpage.lba_status.estulb",
7880 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL}
7882 { &hf_nvme_get_logpage_lba_status_rsvd,
7883 { "Reserved", "nvme.cmd.get_logpage.lba_status.rsvd",
7884 FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
7886 { &hf_nvme_get_logpage_lba_status_lsgc,
7887 { "LBA Status Generation Counter (LSGC)", "nvme.cmd.get_logpage.lba_status.lsgc",
7888 FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
7890 { &hf_nvme_get_logpage_lba_status_nel,
7891 { "LBA Status Log Namespace Element List", "nvme.cmd.get_logpage.lba_status.nel",
7892 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
7894 { &hf_nvme_get_logpage_lba_status_nel_ne,
7895 { "LBA Status Log Namespace Element", "nvme.cmd.get_logpage.lba_status.nel.ne",
7896 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
7898 { &hf_nvme_get_logpage_lba_status_nel_ne_neid,
7899 { "Namespace Element Identifier (NEID)", "nvme.cmd.get_logpage.lba_status.nel.ne.neid",
7900 FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
7902 { &hf_nvme_get_logpage_lba_status_nel_ne_nlrd,
7903 { "Number of LBA Range Descriptors (NLRD)", "nvme.cmd.get_logpage.lba_status.nel.ne.nlrd",
7904 FT_UINT32, BASE_DEC_HEX, NULL, 0x0, NULL, HFILL}
7906 { &hf_nvme_get_logpage_lba_status_nel_ne_ratype,
7907 { "Number of LBA Range Descriptors (NLRD)", "nvme.cmd.get_logpage.lba_status.nel.ne.ratype",
7908 FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL}
7910 { &hf_nvme_get_logpage_lba_status_nel_ne_rsvd,
7911 { "Reserved", "nvme.cmd.get_logpage.lba_status.nel.ne.rsvd",
7912 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
7914 { &hf_nvme_get_logpage_lba_status_nel_ne_rd,
7915 { "LBA Range Descriptor", "nvme.cmd.get_logpage.lba_status.nel.ne.rd",
7916 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
7918 { &hf_nvme_get_logpage_lba_status_nel_ne_rd_rslba,
7919 { "LBA Range Descriptor", "nvme.cmd.get_logpage.lba_status.nel.ne.rd.rslba",
7920 FT_UINT64, BASE_HEX, NULL, 0x0, NULL, HFILL}
7922 { &hf_nvme_get_logpage_lba_status_nel_ne_rd_rnlb,
7923 { "Range Number of Logical Blocks (RNLB)", "nvme.cmd.get_logpage.lba_status.nel.ne.rd.rnlb",
7924 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL}
7926 { &hf_nvme_get_logpage_lba_status_nel_ne_rd_rsvd,
7927 { "Reserved", "nvme.cmd.get_logpage.lba_status.nel.ne.rd.rsvd",
7928 FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
7930 /* Get LogPage Endurance Group Aggregate Response */
7931 { &hf_nvme_get_logpage_egroup_aggreg_ne,
7932 { "Number of Entries", "nvme.cmd.get_logpage.egroup_agreg.ne",
7933 FT_UINT64, BASE_DEC, NULL, 0x0, NULL, HFILL}
7935 { &hf_nvme_get_logpage_egroup_aggreg_eg,
7936 { "Endurance Group", "nvme.cmd.get_logpage.egroup_agreg.eg",
7937 FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
7939 /* Get LogPage Reservation Notification Response */
7940 { &hf_nvme_get_logpage_reserv_notif_lpc,
7941 { "Log Page Count", "nvme.cmd.get_logpage.reserv_notif.lpc",
7942 FT_UINT64, BASE_HEX, NULL, 0x0, NULL, HFILL}
7944 { &hf_nvme_get_logpage_reserv_notif_lpt,
7945 { "Reservation Notification Log Page Type", "nvme.cmd.get_logpage.reserv_notif.lpt",
7946 FT_UINT8, BASE_HEX, VALS(rnlpt_tbl), 0x0, NULL, HFILL}
7948 { &hf_nvme_get_logpage_reserv_notif_nalp,
7949 { "Number of Available Log Pages", "nvme.cmd.get_logpage.reserv_notif.nalp",
7950 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL}
7952 { &hf_nvme_get_logpage_reserv_notif_rsvd0,
7953 { "Reserved", "nvme.cmd.get_logpage.reserv_notif.rsvd0",
7954 FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
7956 { &hf_nvme_get_logpage_reserv_notif_nsid,
7957 { "Namespace ID", "nvme.cmd.get_logpage.reserv_notif.nsid",
7958 FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
7960 { &hf_nvme_get_logpage_reserv_notif_rsvd1,
7961 { "Reserved", "nvme.cmd.get_logpage.reserv_notif.rsvd1",
7962 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
7964 /* Get LogPage Sanitize Response */
7965 { &hf_nvme_get_logpage_sanitize_sprog,
7966 { "Sanitize Progress (SPROG)", "nvme.cmd.get_logpage.sanitize.sprog",
7967 FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
7969 { &hf_nvme_get_logpage_sanitize_sstat[0],
7970 { "Sanitize Status (SSTAT)", "nvme.cmd.get_logpage.sanitize.sstat",
7971 FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
7973 { &hf_nvme_get_logpage_sanitize_sstat[1],
7974 { "Status of the most resent Sanitize Operation", "nvme.cmd.get_logpage.sanitize.sstat.mrst",
7975 FT_UINT16, BASE_HEX, VALS(san_mrst_tbl), 0x7, NULL, HFILL}
7977 { &hf_nvme_get_logpage_sanitize_sstat[2],
7978 { "Number of Completed Overwrite Passes", "nvme.cmd.get_logpage.sanitize.sstat.cop",
7979 FT_UINT16, BASE_HEX, NULL, 0xf8, NULL, HFILL}
7981 { &hf_nvme_get_logpage_sanitize_sstat[3],
7982 { "Global Data Erased", "nvme.cmd.get_logpage.sanitize.sstat.gde",
7983 FT_BOOLEAN, 16, NULL, 0x100, NULL, HFILL}
7985 { &hf_nvme_get_logpage_sanitize_sstat[4],
7986 { "Reserved", "nvme.cmd.get_logpage.sanitize.sstat.rsvd",
7987 FT_UINT16, BASE_HEX, NULL, 0xfe00, NULL, HFILL}
7989 { &hf_nvme_get_logpage_sanitize_scdw10,
7990 { "Sanitize Command Dword 10 Information (SCDW10)", "nvme.cmd.get_logpage.sanitize.scdw10",
7991 FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
7993 { &hf_nvme_get_logpage_sanitize_eto,
7994 { "Estimated Time For Overwrite (seconds)", "nvme.cmd.get_logpage.sanitize.eto",
7995 FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
7997 { &hf_nvme_get_logpage_sanitize_etbe,
7998 { "Estimated Time For Block Erase (seconds)", "nvme.cmd.get_logpage.sanitize.etbe",
7999 FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
8001 { &hf_nvme_get_logpage_sanitize_etce,
8002 { "Estimated Time For Crypto Erase (seconds)", "nvme.cmd.get_logpage.sanitize.etce",
8003 FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
8005 { &hf_nvme_get_logpage_sanitize_etond,
8006 { "Estimated Time For Overwrite (seconds) with No-Deallocate", "nvme.cmd.get_logpage.sanitize.etond",
8007 FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
8009 { &hf_nvme_get_logpage_sanitize_etbend,
8010 { "Estimated Time For Block Erase (seconds) with No-Deallocate", "nvme.cmd.get_logpage.sanitize.etbend",
8011 FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
8013 { &hf_nvme_get_logpage_sanitize_etcend,
8014 { "Estimated Time For Crypto Erase (seconds) with No-Deallocate", "nvme.cmd.get_logpage.sanitize.etcend",
8015 FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
8017 { &hf_nvme_get_logpage_sanitize_rsvd,
8018 { "Reserved", "nvme.cmd.get_logpage.sanitize.rsvd",
8019 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
8021 /* NVMe Response fields */
8022 { &hf_nvme_cqe_dword0,
8023 { "DWORD0", "nvme.cqe.dword0",
8024 FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
8026 { &hf_nvme_cqe_dword0_sf_err,
8027 { "Set Features Error Specific Code", "nvme.cqe.dword0.set_features.err",
8028 FT_UINT32, BASE_HEX, VALS(nvme_cqe_sc_sf_err_dword0_tbl), 0x0, NULL, HFILL}
8030 { &hf_nvme_cqe_aev_dword0[0],
8031 { "DWORD0", "nvme.cqe.dword0.aev",
8032 FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
8034 { &hf_nvme_cqe_aev_dword0[1],
8035 { "Asynchronous Event Type", "nvme.cqe.dword0.aev.aet",
8036 FT_UINT32, BASE_HEX, VALS(nvme_cqe_aev_aet_dword0_tbl), 0x7, NULL, HFILL}
8038 { &hf_nvme_cqe_aev_dword0[2],
8039 { "Reserved", "nvme.cqe.dword0.aev.rsvd0",
8040 FT_UINT32, BASE_HEX, NULL, 0xf8, NULL, HFILL}
8042 { &hf_nvme_cqe_aev_dword0[3],
8043 { "Asynchronous Event Information", "nvme.cqe.dword0.aev.aei",
8044 FT_UINT32, BASE_HEX, NULL, 0xff00, NULL, HFILL}
8046 { &hf_nvme_cqe_aev_dword0[4],
8047 { "Log Page Identifier", "nvme.cqe.dword0.aev.lpi",
8048 FT_UINT32, BASE_CUSTOM, CF_FUNC(add_logpage_lid), 0xff0000, NULL, HFILL}
8050 { &hf_nvme_cqe_aev_dword0[5],
8051 { "Reserved", "nvme.cqe.dword0.aev.rsvd1",
8052 FT_UINT32, BASE_HEX, NULL, 0xff000000, NULL, HFILL}
8054 /* Set Feature Responses */
8055 { &hf_nvme_cqe_dword0_sf_nq[0],
8056 { "DWORD0: Set Feature Number of Queues Result", "nvme.cqe.dword0.set_features.nq",
8057 FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
8059 { &hf_nvme_cqe_dword0_sf_nq[1],
8060 { "Number of IO Submission Queues Allocated", "nvme.cqe.dword0.set_features.nq.nsqa",
8061 FT_UINT32, BASE_CUSTOM, CF_FUNC(add_nvme_queues), 0xffff, NULL, HFILL}
8063 { &hf_nvme_cqe_dword0_sf_nq[2],
8064 { "Number of IO Completion Queues Allocated", "nvme.cqe.dword0.set_features.ncqa",
8065 FT_UINT32, BASE_CUSTOM, CF_FUNC(add_nvme_queues), 0xffff0000, NULL, HFILL}
8067 /* Get Feature Responses */
8068 { &hf_nvme_cqe_get_features_dword0_arb[0],
8069 { "DWORD0", "nvme.cqe.dword0.get_features.arb",
8070 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
8072 { &hf_nvme_cqe_get_features_dword0_arb[1],
8073 { "Arbitration Burst", "nvme.cqe.dword0.get_features.arb.ab",
8074 FT_UINT32, BASE_HEX, NULL, 0x7, NULL, HFILL}
8076 { &hf_nvme_cqe_get_features_dword0_arb[3],
8077 { "Low Priority Weight", "nvme.cqe.dword0.get_features.arb.lpw",
8078 FT_UINT32, BASE_HEX, NULL, 0xff00, NULL, HFILL}
8080 { &hf_nvme_cqe_get_features_dword0_arb[4],
8081 { "Medium Priority Weight", "nvme.cqe.dword0.get_features.arb.mpw",
8082 FT_UINT32, BASE_HEX, NULL, 0xff0000, NULL, HFILL}
8084 { &hf_nvme_cqe_get_features_dword0_arb[5],
8085 { "High Priority Weight", "nvme.cqe.dword0.get_features.arb.hpw",
8086 FT_UINT32, BASE_HEX, NULL, 0xff000000, NULL, HFILL}
8088 { &hf_nvme_cqe_get_features_dword0_pm[0],
8089 { "DWORD0", "nvme.cqe.dword0.get_features.pm",
8090 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
8092 { &hf_nvme_cqe_get_features_dword0_pm[1],
8093 { "Power State", "nvme.cqe.dword0.get_features.pm.ps",
8094 FT_UINT32, BASE_HEX, NULL, 0x1f, NULL, HFILL}
8096 { &hf_nvme_cqe_get_features_dword0_pm[2],
8097 { "Work Hint", "nvme.cqe.dword0.get_features.pm.wh",
8098 FT_UINT32, BASE_HEX, NULL, 0xe0, NULL, HFILL}
8100 { &hf_nvme_cqe_get_features_dword0_pm[3],
8101 { "Work Hint", "nvme.cqe.dword0.get_features.pm.rsvd",
8102 FT_UINT32, BASE_HEX, NULL, 0xff000000, NULL, HFILL}
8104 { &hf_nvme_cqe_get_features_dword0_lbart[0],
8105 { "DWORD0", "nvme.cqe.dword0.get_features.lbart",
8106 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
8108 { &hf_nvme_cqe_get_features_dword0_lbart[1],
8109 { "DWORD0", "nvme.cqe.dword0.get_features.lbart.lbarn",
8110 FT_UINT32, BASE_HEX, NULL, 0x3f, NULL, HFILL}
8112 { &hf_nvme_cqe_get_features_dword0_lbart[2],
8113 { "DWORD0", "nvme.cqe.dword0.get_features.lbart.rsvd",
8114 FT_UINT32, BASE_HEX, NULL, 0xffffffc0, NULL, HFILL}
8116 { &hf_nvme_cqe_get_features_dword0_tt[0],
8117 { "DWORD0", "nvme.cqe.dword0.get_features.tt",
8118 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
8120 { &hf_nvme_cqe_get_features_dword0_tt[1],
8121 { "Temperature Threshold", "nvme.cqe.dword0.get_features.tt.tmpth",
8122 FT_UINT32, BASE_HEX, NULL, 0xffff, NULL, HFILL}
8124 { &hf_nvme_cqe_get_features_dword0_tt[2],
8125 { "Threshold Temperature Select", "nvme.cqe.dword0.get_features.tt.tmpsel",
8126 FT_UINT32, BASE_HEX, VALS(sf_tmpsel_table), 0xf0000, NULL, HFILL}
8128 { &hf_nvme_cqe_get_features_dword0_tt[3],
8129 { "Threshold Type Select", "nvme.cqe.dword0.get_features.tt.thpsel",
8130 FT_UINT32, BASE_HEX, VALS(sf_thpsel_table), 0x300000, NULL, HFILL}
8132 { &hf_nvme_cqe_get_features_dword0_tt[4],
8133 { "Reserved", "nvme.cqe.dword0.get_features.tt.rsvd",
8134 FT_UINT32, BASE_HEX, NULL, 0xc00000, NULL, HFILL}
8136 { &hf_nvme_cqe_get_features_dword0_erec[0],
8137 { "DWORD0", "nvme.cqe.dword0.get_features.erec",
8138 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
8140 { &hf_nvme_cqe_get_features_dword0_erec[1],
8141 { "Time Limited Error Recovery (100 ms units)", "nvme.cqe.dword0.get_features.erec.tler",
8142 FT_UINT32, BASE_HEX, NULL, 0xffff, NULL, HFILL}
8144 { &hf_nvme_cqe_get_features_dword0_erec[2],
8145 { "Deallocated or Unwritten Logical Block Error Enable", "nvme.cqe.dword0.get_features.erec.dulbe",
8146 FT_BOOLEAN, 32, NULL, 0x10000, NULL, HFILL}
8148 { &hf_nvme_cqe_get_features_dword0_erec[3],
8149 { "Reserved", "nvme.cqe.dword0.get_features.erec.rsvd",
8150 FT_UINT32, BASE_HEX, NULL, 0xfe0000, NULL, HFILL}
8152 { &hf_nvme_cqe_get_features_dword0_vwce[0],
8153 { "DWORD0", "nvme.cqe.dword0.get_features.vwce",
8154 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
8156 { &hf_nvme_cqe_get_features_dword0_vwce[1],
8157 { "Volatile Write Cache Enable", "nvme.cqe.dword0.get_features.vwce.wce",
8158 FT_BOOLEAN, 32, NULL, 0x1, NULL, HFILL}
8160 { &hf_nvme_cqe_get_features_dword0_vwce[2],
8161 { "Volatile Write Cache Enable", "nvme.cqe.dword0.get_features.vwce.rsvd",
8162 FT_UINT32, BASE_HEX, NULL, 0xfffffffe, NULL, HFILL}
8164 { &hf_nvme_cqe_get_features_dword0_nq[0],
8165 { "DWORD0", "nvme.cqe.dword0.get_features.nq",
8166 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
8168 { &hf_nvme_cqe_get_features_dword0_nq[1],
8169 { "Number of IO Submission Queues Allocated", "nvme.cqe.dword0.get_features.nq.nsqa",
8170 FT_UINT32, BASE_CUSTOM, CF_FUNC(add_nvme_queues), 0xffff, NULL, HFILL}
8172 { &hf_nvme_cqe_get_features_dword0_nq[2],
8173 { "Number of IO Completion Queues Allocated", "nvme.cqe.dword0.get_features.nq.ncqa",
8174 FT_UINT32, BASE_CUSTOM, CF_FUNC(add_nvme_queues), 0xffff0000, NULL, HFILL}
8176 { &hf_nvme_cqe_get_features_dword0_irqc[0],
8177 { "DWORD0", "nvme.cqe.dword0.get_features.irqc",
8178 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
8180 { &hf_nvme_cqe_get_features_dword0_irqc[1],
8181 { "Aggregation Threshold", "nvme.cqe.dword0.get_features.irqc.thr",
8182 FT_UINT32, BASE_HEX, NULL, 0xffff, NULL, HFILL}
8184 { &hf_nvme_cqe_get_features_dword0_irqc[2],
8185 { "Aggregation Time (100 us units)", "nvme.cqe.dword0.get_features.irqc.time",
8186 FT_UINT32, BASE_HEX, NULL, 0xffff0000, NULL, HFILL}
8188 { &hf_nvme_cqe_get_features_dword0_irqv[0],
8189 { "DWORD0", "nvme.cqe.dword0.get_features.irqv",
8190 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
8192 { &hf_nvme_cqe_get_features_dword0_irqv[1],
8193 { "IRQ Vector", "nvme.cqe.dword0.get_features.irqv.iv",
8194 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
8196 { &hf_nvme_cqe_get_features_dword0_irqv[2],
8197 { "Coalescing Disable", "nvme.cqe.dword0.get_features.irqv.cd",
8198 FT_BOOLEAN, 32, NULL, 0x1ffff, NULL, HFILL}
8200 { &hf_nvme_cqe_get_features_dword0_irqv[3],
8201 { "Reserved", "nvme.cqe.dword0.get_features.irqv.rsvd",
8202 FT_UINT32, BASE_HEX, NULL, 0xfffe0000, NULL, HFILL}
8204 { &hf_nvme_cqe_get_features_dword0_wan[0],
8205 { "DWORD0", "nvme.cqe.dword0.get_features.wan",
8206 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
8208 { &hf_nvme_cqe_get_features_dword0_wan[1],
8209 { "Disable Normal", "nvme.cqe.dword0.get_features.wan.dn",
8210 FT_BOOLEAN, 32, NULL, 0x1, NULL, HFILL}
8212 { &hf_nvme_cqe_get_features_dword0_wan[2],
8213 { "Reserved", "nvme.cqe.dword0.get_features.wan.rsvd",
8214 FT_UINT32, BASE_HEX, NULL, 0xfffffffe, NULL, HFILL}
8216 { &hf_nvme_cqe_get_features_dword0_aec[0],
8217 { "DWORD0", "nvme.cqe.dword0.get_features.aec",
8218 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
8220 { &hf_nvme_cqe_get_features_dword0_aec[1],
8221 { "SMART and Health Critical Warnings Bitmask", "nvme.cqe.dword0.get_features.aec.smart",
8222 FT_UINT32, BASE_HEX, NULL, 0xff, NULL, HFILL}
8224 { &hf_nvme_cqe_get_features_dword0_aec[2],
8225 { "Namespace Attribute Notices", "nvme.cqe.dword0.get_features.aec.ns",
8226 FT_BOOLEAN, 32, NULL, 0x100, NULL, HFILL}
8228 { &hf_nvme_cqe_get_features_dword0_aec[3],
8229 { "Firmware Activation Notices", "nvme.cqe.dword0.get_features.aec.fwa",
8230 FT_BOOLEAN, 32, NULL, 0x200, NULL, HFILL}
8232 { &hf_nvme_cqe_get_features_dword0_aec[4],
8233 { "Telemetry Log Notices", "nvme.cqe.dword0.get_features.aec.tel",
8234 FT_BOOLEAN, 32, NULL, 0x400, NULL, HFILL}
8236 { &hf_nvme_cqe_get_features_dword0_aec[5],
8237 { "ANA Change Notices", "nvme.cqe.dword0.get_features.aec.ana",
8238 FT_BOOLEAN, 32, NULL, 0x800, NULL, HFILL}
8240 { &hf_nvme_cqe_get_features_dword0_aec[6],
8241 { "Predictable Latency Event Aggregate Log Change Notices", "nvme.cqe.dword0.get_features.aec.plat",
8242 FT_BOOLEAN, 32, NULL, 0x1000, NULL, HFILL}
8244 { &hf_nvme_cqe_get_features_dword0_aec[7],
8245 { "LBA Status Information Notices", "nvme.cqe.dword0.get_features.aec.lba",
8246 FT_BOOLEAN, 32, NULL, 0x2000, NULL, HFILL}
8248 { &hf_nvme_cqe_get_features_dword0_aec[8],
8249 { "Endurance Group Event Aggregate Log Change Notices", "nvme.cqe.dword0.get_features.aec.eg",
8250 FT_BOOLEAN, 32, NULL, 0x4000, NULL, HFILL}
8252 { &hf_nvme_cqe_get_features_dword0_aec[9],
8253 { "Reserved", "nvme.cqe.dword0.get_features.aec.rsvd",
8254 FT_UINT32, BASE_HEX, NULL, 0x7fff8000, NULL, HFILL}
8256 { &hf_nvme_cqe_get_features_dword0_aec[10],
8257 { "Discovery Log Page Change Notification", "nvme.cqe.dword0.get_features.aec.disc",
8258 FT_BOOLEAN, 32, NULL, 0x80000000, NULL, HFILL}
8260 { &hf_nvme_cqe_get_features_dword0_apst[0],
8261 { "DWORD0", "nvme.cqe.dword0.get_features.apst",
8262 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
8264 { &hf_nvme_cqe_get_features_dword0_apst[1],
8265 { "Autonomous Power State Transition Enable", "nvme.cqe.dword0.get_features.apst.apste",
8266 FT_BOOLEAN, 32, NULL, 0x1, NULL, HFILL}
8268 { &hf_nvme_cqe_get_features_dword0_apst[2],
8269 { "Reserved", "nvme.cqe.dword0.get_features.apst.rsvd",
8270 FT_UINT32, BASE_HEX, NULL, 0xfffffffe, NULL, HFILL}
8272 { &hf_nvme_cqe_get_features_dword0_kat[0],
8273 { "DWORD0", "nvme.cqe.dword0.get_features.kat",
8274 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
8276 { &hf_nvme_cqe_get_features_dword0_kat[1],
8277 { "Keep Alive Timeout", "nvme.cqe.dword0.get_features.kat.kato",
8278 FT_UINT32, BASE_DEC|BASE_UNIT_STRING, UNS(&units_milliseconds), 0, NULL, HFILL}
8280 { &hf_nvme_cqe_get_features_dword0_hctm[0],
8281 { "DWORD0", "nvme.cqe.dword0.get_features.hctm",
8282 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
8284 { &hf_nvme_cqe_get_features_dword0_hctm[1],
8285 { "Thermal Management Temperature 2 (K)", "nvme.cqe.dword0.get_features.hctm.tmt2",
8286 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
8288 { &hf_nvme_cqe_get_features_dword0_hctm[2],
8289 { "Thermal Management Temperature 1 (K)", "nvme.cqe.dword0.get_features.hctm.tmt1",
8290 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
8292 { &hf_nvme_cqe_get_features_dword0_nops[0],
8293 { "DWORD0", "nvme.cqe.dword0.get_features.nops",
8294 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
8296 { &hf_nvme_cqe_get_features_dword0_nops[1],
8297 { "Non-Operational Power State Permissive Mode Enable", "nvme.cqe.dword0.get_features.nops.noppme",
8298 FT_UINT32, BASE_HEX, NULL, 0x1, NULL, HFILL}
8300 { &hf_nvme_cqe_get_features_dword0_nops[2],
8301 { "Reserved", "nvme.cqe.dword0.get_features.nops.rsvd",
8302 FT_UINT32, BASE_HEX, NULL, 0xfffffffe, NULL, HFILL}
8304 { &hf_nvme_cqe_get_features_dword0_rrl[0],
8305 { "DWORD0", "nvme.cqe.dword0.get_features.rrl",
8306 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
8308 { &hf_nvme_cqe_get_features_dword0_rrl[1],
8309 { "Read Recovery Level", "nvme.cqe.dword0.get_features.rrl.rrl",
8310 FT_UINT32, BASE_HEX, NULL, 0xf, NULL, HFILL}
8312 { &hf_nvme_cqe_get_features_dword0_rrl[2],
8313 { "Reserved", "nvme.cqe.dword0.get_features.rrl.rsvd",
8314 FT_UINT32, BASE_HEX, NULL, 0xfffffff0, NULL, HFILL}
8316 { &hf_nvme_cqe_get_features_dword0_plmc[0],
8317 { "DWORD0", "nvme.cqe.dword0.get_features.plmc",
8318 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
8320 { &hf_nvme_cqe_get_features_dword0_plmc[1],
8321 { "Predictable Latency Enable", "nvme.cqe.dword0.get_features.plmc.ple",
8322 FT_UINT32, BASE_HEX, NULL, 0x1, NULL, HFILL}
8324 { &hf_nvme_cqe_get_features_dword0_plmc[2],
8325 { "Reserved", "nvme.cqe.dword0.get_features.plmc.rsvd",
8326 FT_UINT32, BASE_HEX, NULL, 0xfffffffe, NULL, HFILL}
8328 { &hf_nvme_cqe_get_features_dword0_plmw[0],
8329 { "DWORD0", "nvme.cqe.dword0.get_features.plmw",
8330 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
8332 { &hf_nvme_cqe_get_features_dword0_plmw[1],
8333 { "NVM Set Identifier", "nvme.cqe.dword0.get_features.plmw.nvmsetid",
8334 FT_UINT32, BASE_HEX, NULL, 0xffff, NULL, HFILL}
8336 { &hf_nvme_cqe_get_features_dword0_plmw[2],
8337 { "Reserved", "nvme.cqe.dword0.get_features.plmw.rsvd",
8338 FT_UINT32, BASE_HEX, NULL, 0xffff0000, NULL, HFILL}
8340 { &hf_nvme_cqe_get_features_dword0_lbasi[0],
8341 { "DWORD0", "nvme.cqe.dword0.get_features.lbasi",
8342 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
8344 { &hf_nvme_cqe_get_features_dword0_lbasi[1],
8345 { "LBA Status Information Report Interval (100 ms)", "nvme.cqe.dword0.get_features.lbasi.lsiri",
8346 FT_UINT32, BASE_HEX, NULL, 0xffff, NULL, HFILL}
8348 { &hf_nvme_cqe_get_features_dword0_lbasi[2],
8349 { "LBA Status Information Poll Interval (100 ms)", "nvme.cqe.dword0.get_features.lbasi.lsipi",
8350 FT_UINT32, BASE_HEX, NULL, 0xffff0000, NULL, HFILL}
8352 { &hf_nvme_cqe_get_features_dword0_san[0],
8353 { "DWORD0", "nvme.cqe.dword0.get_features.san",
8354 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
8356 { &hf_nvme_cqe_get_features_dword0_san[1],
8357 { "No-Deallocate Response Mode", "nvme.cqe.dword0.get_features.san.nodrm",
8358 FT_BOOLEAN, 32, NULL, 0x1, NULL, HFILL}
8360 { &hf_nvme_cqe_get_features_dword0_san[2],
8361 { "Reserved", "nvme.cqe.dword0.get_features.san.rsvd",
8362 FT_UINT32, BASE_HEX, NULL, 0xfffffffe, NULL, HFILL}
8364 { &hf_nvme_cqe_get_features_dword0_eg[0],
8365 { "DWORD0", "nvme.cqe.dword0.get_features.eg",
8366 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
8368 { &hf_nvme_cqe_get_features_dword0_eg[1],
8369 { "Endurance Group Identifier", "nvme.cqe.dword0.get_features.eg.endgid",
8370 FT_UINT32, BASE_HEX, NULL, 0xffff, NULL, HFILL}
8372 { &hf_nvme_cqe_get_features_dword0_eg[2],
8373 { "Endurance Group Critical Warnings Bitmask", "nvme.cqe.dword0.get_features.eg.egcw",
8374 FT_UINT32, BASE_HEX, NULL, 0xff0000, NULL, HFILL}
8376 { &hf_nvme_cqe_get_features_dword0_eg[3],
8377 { "Reserved", "nvme.cqe.dword0.get_features.eg.rsvd",
8378 FT_UINT32, BASE_HEX, NULL, 0xff000000, NULL, HFILL}
8380 { &hf_nvme_cqe_get_features_dword0_swp[0],
8381 { "DWORD0", "nvme.cqe.dword0.get_features.swp",
8382 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
8384 { &hf_nvme_cqe_get_features_dword0_swp[1],
8385 { "Pre-boot Software Load Count", "nvme.cqe.dword0.get_features.swp.pbslc",
8386 FT_UINT32, BASE_HEX, NULL, 0xff, NULL, HFILL}
8388 { &hf_nvme_cqe_get_features_dword0_swp[2],
8389 { "Reserved", "nvme.cqe.dword0.get_features.swp.rsvd",
8390 FT_UINT32, BASE_HEX, NULL, 0xffffff00, NULL, HFILL}
8392 { &hf_nvme_cqe_get_features_dword0_hid[0],
8393 { "DWORD0", "nvme.cqe.dword0.get_features.hid",
8394 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
8396 { &hf_nvme_cqe_get_features_dword0_hid[1],
8397 { "Enable Extended Host Identifier", "nvme.cqe.dword0.get_features.hid.exhid",
8398 FT_BOOLEAN, 32, NULL, 0x1, NULL, HFILL}
8400 { &hf_nvme_cqe_get_features_dword0_hid[2],
8401 { "Reserved", "nvme.cqe.dword0.get_features.hid.rsvd",
8402 FT_UINT32, BASE_HEX, NULL, 0xfffffffe, NULL, HFILL}
8404 { &hf_nvme_cqe_get_features_dword0_rsrvn[0],
8405 { "DWORD0", "nvme.cqe.dword0.get_features.rsrvn",
8406 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
8408 { &hf_nvme_cqe_get_features_dword0_rsrvn[1],
8409 { "Reserved", "nvme.cqe.dword0.get_features.rsrvn.rsvd0",
8410 FT_UINT32, BASE_HEX, NULL, 0x1, NULL, HFILL}
8412 { &hf_nvme_cqe_get_features_dword0_rsrvn[2],
8413 { "Mask Registration Preempted Notification" , "nvme.cqe.dword0.get_features.rsrvn.regpre",
8414 FT_BOOLEAN, 32, NULL, 0x2, NULL, HFILL}
8416 { &hf_nvme_cqe_get_features_dword0_rsrvn[3],
8417 { "Mask Reservation Released Notification", "nvme.cqe.dword0.get_features.rsrvn.resrel",
8418 FT_BOOLEAN, 32, NULL, 0x4, NULL, HFILL}
8420 { &hf_nvme_cqe_get_features_dword0_rsrvn[4],
8421 { "Mask Reservation Preempted Notification", "nvme.cqe.dword0.get_features.rsrvn.resrpe",
8422 FT_BOOLEAN, 32, NULL, 0x8, NULL, HFILL}
8424 { &hf_nvme_cqe_get_features_dword0_rsrvn[5],
8425 { "Reserved", "nvme.cqe.dword0.get_features.rsrvn.rsvd1",
8426 FT_UINT32, BASE_HEX, NULL, 0xfffff0, NULL, HFILL}
8428 { &hf_nvme_cqe_get_features_dword0_rsrvp[0],
8429 { "DWORD0", "nvme.cqe.dword0.get_features.rsrvp",
8430 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
8432 { &hf_nvme_cqe_get_features_dword0_rsrvp[1],
8433 { "Persist Through Power Loss", "nvme.cqe.dword0.get_features.rsrvp.ptpl",
8434 FT_BOOLEAN, 32, NULL, 0x1, NULL, HFILL}
8436 { &hf_nvme_cqe_get_features_dword0_rsrvp[2],
8437 { "Reserved", "nvme.cqe.dword0.get_features.rsrvp.rsvd",
8438 FT_UINT32, BASE_HEX, NULL, 0xfffffffe, NULL, HFILL}
8440 { &hf_nvme_cqe_get_features_dword0_nswp[0],
8441 { "DWORD0", "nvme.cqe.dword0.get_features.nswp",
8442 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL}
8444 { &hf_nvme_cqe_get_features_dword0_nswp[1],
8445 { "DWORD0", "nvme.cqe.dword0.get_features.nswp.wps",
8446 FT_UINT32, BASE_HEX, VALS(sf_wps), 0x7, NULL, HFILL}
8448 { &hf_nvme_cqe_get_features_dword0_nswp[2],
8449 { "DWORD0", "nvme.cqe.dword0.get_features.nswp.rsvd",
8450 FT_UINT32, BASE_HEX, NULL, 0xfffffff8, NULL, HFILL}
8452 /* Generic Response Fields */
8453 { &hf_nvme_cqe_dword1,
8454 { "DWORD1", "nvme.cqe.dword1",
8455 FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL}
8457 { &hf_nvme_cqe_sqhd,
8458 { "SQ Head Pointer", "nvme.cqe.sqhd",
8459 FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
8461 { &hf_nvme_cqe_sqid,
8462 { "SQ Identifier", "nvme.cqe.sqid",
8463 FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
8465 { &hf_nvme_cqe_cid,
8466 { "Command Identifier", "nvme.cqe.cid",
8467 FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
8469 { &hf_nvme_cqe_status[0],
8470 { "Status Field", "nvme.cqe.status",
8471 FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL}
8473 { &hf_nvme_cqe_status[1],
8474 { "Phase Tag", "nvme.cqe.status.p",
8475 FT_UINT16, BASE_HEX, NULL, 0x1, NULL, HFILL}
8477 { &hf_nvme_cqe_status_rsvd,
8478 { "Reserved", "nvme.cqe.status.rsvd",
8479 FT_UINT16, BASE_HEX, NULL, 0x1, NULL, HFILL}
8481 { &hf_nvme_cqe_status[2],
8482 { "Status Code", "nvme.cqe.status.sc",
8483 FT_UINT16, BASE_HEX, NULL, 0x1fe, NULL, HFILL}
8485 { &hf_nvme_cqe_status[3],
8486 { "Status Code Type", "nvme.cqe.status.sct",
8487 FT_UINT16, BASE_HEX, VALS(nvme_cqe_sct_tbl), 0xE00, NULL, HFILL}
8489 { &hf_nvme_cqe_status[4],
8490 { "Command Retry Delay", "nvme.cqe.status.crd",
8491 FT_UINT16, BASE_HEX, NULL, 0x3000, NULL, HFILL}
8493 { &hf_nvme_cqe_status[5],
8494 { "More Information in Log Page", "nvme.cqe.status.m",
8495 FT_BOOLEAN, 16, NULL, 0x4000, NULL, HFILL}
8497 { &hf_nvme_cqe_status[6],
8498 { "Do not Retry", "nvme.cqe.status.dnr",
8499 FT_BOOLEAN, 16, NULL, 0x8000, NULL, HFILL}
8501 { &hf_nvme_cmd_pkt,
8502 { "Cmd in", "nvme.cmd_pkt",
8503 FT_FRAMENUM, BASE_NONE, NULL, 0,
8504 "The Cmd for this transaction is in this frame", HFILL }
8506 { &hf_nvme_data_req,
8507 { "DATA Transfer Request", "nvme.data_req",
8508 FT_FRAMENUM, BASE_NONE, NULL, 0,
8509 "DATA transfer request for this transaction is in this frame", HFILL }
8511 { &hf_nvme_data_tr[0],
8512 { "DATA Transfer 0", "nvme.data.tr0",
8513 FT_FRAMENUM, BASE_NONE, NULL, 0,
8514 "DATA transfer 0 for this transaction is in this frame", HFILL }
8516 { &hf_nvme_data_tr[1],
8517 { "DATA Transfer 1", "nvme.data_tr1",
8518 FT_FRAMENUM, BASE_NONE, NULL, 0,
8519 "DATA transfer 1 for this transaction is in this frame", HFILL }
8521 { &hf_nvme_data_tr[2],
8522 { "DATA Transfer 2", "nvme.data_tr2",
8523 FT_FRAMENUM, BASE_NONE, NULL, 0,
8524 "DATA transfer 2 for this transaction is in this frame", HFILL }
8526 { &hf_nvme_data_tr[3],
8527 { "DATA Transfer 3", "nvme.data_tr3",
8528 FT_FRAMENUM, BASE_NONE, NULL, 0,
8529 "DATA transfer 3 for this transaction is in this frame", HFILL }
8531 { &hf_nvme_data_tr[4],
8532 { "DATA Transfer 4", "nvme.data_tr4",
8533 FT_FRAMENUM, BASE_NONE, NULL, 0,
8534 "DATA transfer 4 for this transaction is in this frame", HFILL }
8536 { &hf_nvme_data_tr[5],
8537 { "DATA Transfer 5", "nvme.data_tr5",
8538 FT_FRAMENUM, BASE_NONE, NULL, 0,
8539 "DATA transfer 5 for this transaction is in this frame", HFILL }
8541 { &hf_nvme_data_tr[6],
8542 { "DATA Transfer 6", "nvme.data_tr6",
8543 FT_FRAMENUM, BASE_NONE, NULL, 0,
8544 "DATA transfer 6 for this transaction is in this frame", HFILL }
8546 { &hf_nvme_data_tr[7],
8547 { "DATA Transfer 7", "nvme.data_tr7",
8548 FT_FRAMENUM, BASE_NONE, NULL, 0,
8549 "DATA transfer 7 for this transaction is in this frame", HFILL }
8551 { &hf_nvme_data_tr[8],
8552 { "DATA Transfer 8", "nvme.data_tr8",
8553 FT_FRAMENUM, BASE_NONE, NULL, 0,
8554 "DATA transfer 8 for this transaction is in this frame", HFILL }
8556 { &hf_nvme_data_tr[9],
8557 { "DATA Transfer 9", "nvme.data_tr9",
8558 FT_FRAMENUM, BASE_NONE, NULL, 0,
8559 "DATA transfer 9 for this transaction is in this frame", HFILL }
8561 { &hf_nvme_data_tr[10],
8562 { "DATA Transfer 10", "nvme.data_tr10",
8563 FT_FRAMENUM, BASE_NONE, NULL, 0,
8564 "DATA transfer 10 for this transaction is in this frame", HFILL }
8566 { &hf_nvme_data_tr[11],
8567 { "DATA Transfer 11", "nvme.data_tr11",
8568 FT_FRAMENUM, BASE_NONE, NULL, 0,
8569 "DATA transfer 11 for this transaction is in this frame", HFILL }
8571 { &hf_nvme_data_tr[12],
8572 { "DATA Transfer 12", "nvme.data_tr12",
8573 FT_FRAMENUM, BASE_NONE, NULL, 0,
8574 "DATA transfer 12 for this transaction is in this frame", HFILL }
8576 { &hf_nvme_data_tr[13],
8577 { "DATA Transfer 13", "nvme.data_tr13",
8578 FT_FRAMENUM, BASE_NONE, NULL, 0,
8579 "DATA transfer 13 for this transaction is in this frame", HFILL }
8581 { &hf_nvme_data_tr[14],
8582 { "DATA Transfer 14", "nvme.data_tr14",
8583 FT_FRAMENUM, BASE_NONE, NULL, 0,
8584 "DATA transfer 14 for this transaction is in this frame", HFILL }
8586 { &hf_nvme_data_tr[15],
8587 { "DATA Transfer 15", "nvme.data_tr15",
8588 FT_FRAMENUM, BASE_NONE, NULL, 0,
8589 "DATA transfer 15 for this transaction is in this frame", HFILL }
8591 { &hf_nvme_cqe_pkt,
8592 { "Cqe in", "nvme.cqe_pkt",
8593 FT_FRAMENUM, BASE_NONE, NULL, 0,
8594 "The Cqe for this transaction is in this frame", HFILL }
8596 { &hf_nvme_cmd_latency,
8597 { "Cmd Latency", "nvme.cmd_latency",
8598 FT_DOUBLE, BASE_NONE, NULL, 0x0,
8599 "The time between the command and completion, in usec", HFILL }
8601 { &hf_nvme_gen_data,
8602 { "Nvme Data", "nvme.data",
8603 FT_BYTES, BASE_NONE, NULL, 0, NULL, HFILL}
8606 static int *ett[] = {
8607 &ett_data,
8610 proto_nvme = proto_register_protocol("NVM Express", "nvme", "nvme");
8612 proto_register_field_array(proto_nvme, hf, array_length(hf));
8613 proto_register_subtree_array(ett, array_length(ett));
8617 * Editor modelines - https://www.wireshark.org/tools/modelines.html
8619 * Local variables:
8620 * c-basic-offset: 4
8621 * tab-width: 8
8622 * indent-tabs-mode: nil
8623 * End:
8625 * vi: set shiftwidth=4 tabstop=8 expandtab:
8626 * :indentSize=4:tabSize=8:noTabs=true: