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epan/dissectors/pidl/ C99 drsuapi
[wireshark-sm.git] / plugins / epan / ethercat / packet-ethercat-datagram.c
blob002871be78456011c9301bfe4420820aeb9cd55b
1 /* packet-ethercat-datagram.c
2 * Routines for ethercat packet disassembly
3 *
4 * Copyright (c) 2007 by Beckhoff Automation GmbH
5 *
6 * Wireshark - Network traffic analyzer
7 * By Gerald Combs <gerald@wireshark.org>
8 * Copyright 1998 Gerald Combs
9 *
10 * SPDX-License-Identifier: GPL-2.0-or-later
11 *
12 * https://download.beckhoff.com/download/document/io/ethercat-development-products/ethercat_esc_datasheet_sec1_technology_2i3.pdf
13 */
14
15 /* Include files */
16
17 #include "config.h"
18
19 #include <epan/packet.h>
20 #include <epan/tfs.h>
21 #include <wsutil/array.h>
22
23 #include "packet-ethercat-datagram.h"
24 #include "packet-ecatmb.h"
25
26 void proto_register_ecat(void);
27 void proto_reg_handoff_ecat(void);
28
29 static heur_dissector_list_t heur_subdissector_list;
30 static dissector_handle_t ecat_handle;
31 static dissector_handle_t ecat_mailbox_handle;
32
33 /* Define the EtherCAT proto */
34 static int proto_ecat_datagram;
35
36 /* Define the tree for EtherCAT */
37 static int ett_ecat;
38 static int ett_ecat_header;
39 static int ett_ecat_dc;
40 static int ett_ecat_length;
41 static int ett_ecat_padding;
42 static int ett_ecat_datagram_subtree;
43 static int ett_ecat_reg_esc_features;
44 static int ett_ecat_reg_dlctrl1;
45 static int ett_ecat_reg_dlctrl2;
46 static int ett_ecat_reg_dlctrl3;
47 static int ett_ecat_reg_dlctrl4;
48 static int ett_ecat_reg_dlstatus1;
49 static int ett_ecat_reg_dlstatus2;
50 static int ett_ecat_reg_alctrl;
51 static int ett_ecat_reg_alstatus;
52 static int ett_ecat_reg_pdictrl1;
53 static int ett_ecat_reg_pdictrl2;
54 static int ett_ecat_reg_ecat_mask;
55 static int ett_ecat_reg_pdiL;
56 static int ett_ecat_reg_ecat;
57 static int ett_ecat_reg_pdi1;
58 static int ett_ecat_reg_crc0;
59 static int ett_ecat_reg_crc1;
60 static int ett_ecat_reg_crc2;
61 static int ett_ecat_reg_crc3;
62 static int ett_ecat_reg_wd_status;
63 static int ett_ecat_reg_eeprom_assign;
64 static int ett_ecat_reg_ctrlstat;
65 static int ett_ecat_reg_mio_ctrlstat;
66 static int ett_ecat_mio_addr;
67 static int ett_ecat_mio_access;
68 static int ett_ecat_mio_status0;
69 static int ett_ecat_mio_status1;
70 static int ett_ecat_mio_status2;
71 static int ett_ecat_mio_status3;
72 static int ett_ecat_reg_fmmu;
73 static int ett_ecat_reg_syncman;
74 static int ett_ecat_reg_syncman_ctrlstatus;
75 static int ett_ecat_reg_syncman_sm_enable;
76 static int ett_ecat_reg_dc_cycunitctrl;
77 static int ett_ecat_dc_activation;
78 static int ett_ecat_dc_activationstat;
79 static int ett_ecat_dc_sync0_status;
80 static int ett_ecat_dc_sync1_status;
81 static int ett_ecat_dc_latch0_ctrl;
82 static int ett_ecat_dc_latch1_ctrl;
83 static int ett_ecat_dc_latch0_status;
84 static int ett_ecat_dc_latch1_status;
85
86 static int hf_ecat_sub;
87 static int hf_ecat_sub_data[10];
88 static int hf_ecat_sub_cmd[10];
89 static int hf_ecat_sub_idx[10];
90 static int hf_ecat_sub_cnt[10];
91 static int hf_ecat_sub_ado[10];
92 static int hf_ecat_sub_adp[10];
93 static int hf_ecat_sub_lad[10];
94
95 /* static int hf_ecat_header; */
96 static int hf_ecat_data;
97 static int hf_ecat_cnt;
98 static int hf_ecat_cmd;
99 static int hf_ecat_idx;
100 static int hf_ecat_adp;
101 static int hf_ecat_ado;
102 static int hf_ecat_lad;
103 /* static int hf_ecat_len; */
104 static int hf_ecat_int;
105
106 static int hf_ecat_sub_dc_diff_da[10];
107 static int hf_ecat_sub_dc_diff_bd[10];
108 static int hf_ecat_sub_dc_diff_cb[10];
109 static int hf_ecat_sub_dc_diff_cd[10];
110 static int hf_ecat_sub_dc_diff_ba[10];
111 static int hf_ecat_sub_dc_diff_ca[10];
112
113 static int hf_ecat_dc_diff_da;
114 static int hf_ecat_dc_diff_bd;
115 static int hf_ecat_dc_diff_cb;
116 static int hf_ecat_dc_diff_cd;
117 static int hf_ecat_dc_diff_ba;
118 static int hf_ecat_dc_diff_ca;
119
120 static int hf_ecat_length_len;
121 static int hf_ecat_length_r;
122 static int hf_ecat_length_c;
123 static int hf_ecat_length_m;
124
125 static int hf_ecat_padding;
126
127 static int hf_ecat_reg_revision;
128 static int hf_ecat_reg_esc_type;
129 static int hf_ecat_reg_esc_build;
130 static int hf_ecat_reg_esc_fmmucnt;
131 static int hf_ecat_reg_esc_smcnt;
132 static int hf_ecat_reg_esc_ports;
133 static int hf_ecat_reg_esc_dpram;
134 static int hf_ecat_reg_esc_features;
135 static int hf_ecat_reg_esc_features_fmmurestrict;
136 static int hf_ecat_reg_esc_features_smaddrrestrict;
137 static int hf_ecat_reg_esc_features_dcsupport;
138 static int hf_ecat_reg_esc_features_dc64support;
139 static int hf_ecat_reg_esc_features_ebuslowjitter;
140 static int hf_ecat_reg_esc_features_ebusextlinkdetect;
141 static int hf_ecat_reg_esc_features_miiextlinkdetect;
142 static int hf_ecat_reg_esc_features_crcext;
143 static int hf_ecat_reg_physaddr;
144 static int hf_ecat_reg_physaddr2;
145 static int hf_ecat_reg_dlctrl1;
146 static int hf_ecat_reg_dlctrl1_killnonecat;
147 static int hf_ecat_reg_dlctrl1_port0extlinkdetect;
148 static int hf_ecat_reg_dlctrl1_port1extlinkdetect;
149 static int hf_ecat_reg_dlctrl1_port2extlinkdetect;
150 static int hf_ecat_reg_dlctrl1_port3extlinkdetect;
151 static int hf_ecat_reg_dlctrl2;
152 static int hf_ecat_reg_dlctrl2_port0;
153 static int hf_ecat_reg_dlctrl2_port1;
154 static int hf_ecat_reg_dlctrl2_port2;
155 static int hf_ecat_reg_dlctrl2_port3;
156 static int hf_ecat_reg_dlctrl3;
157 static int hf_ecat_reg_dlctrl3_fifosize;
158 static int hf_ecat_reg_dlctrl3_lowebusjit;
159 static int hf_ecat_reg_dlctrl4;
160 static int hf_ecat_reg_dlctrl4_2ndaddress;
161 static int hf_ecat_reg_dlstatus1;
162 static int hf_ecat_reg_dlstatus1_operation;
163 static int hf_ecat_reg_dlstatus1_pdiwatchdog;
164 static int hf_ecat_reg_dlstatus1_enhlinkdetect;
165 static int hf_ecat_reg_dlstatus1_physlink_port0;
166 static int hf_ecat_reg_dlstatus1_physlink_port1;
167 static int hf_ecat_reg_dlstatus1_physlink_port2;
168 static int hf_ecat_reg_dlstatus1_physlink_port3;
169 static int hf_ecat_reg_dlstatus2;
170 static int hf_ecat_reg_dlstatus2_port0;
171 static int hf_ecat_reg_dlstatus2_port1;
172 static int hf_ecat_reg_dlstatus2_port2;
173 static int hf_ecat_reg_dlstatus2_port3;
174 static int hf_ecat_reg_regprotect;
175 static int hf_ecat_reg_accessprotect;
176 static int hf_ecat_reg_resetecat;
177 static int hf_ecat_reg_resetpdi;
178 static int hf_ecat_reg_regphysrwoffs;
179 static int hf_ecat_reg_alctrl;
180 static int hf_ecat_reg_alctrl_ctrl;
181 static int hf_ecat_reg_alctrl_errack;
182 static int hf_ecat_reg_alctrl_id;
183 static int hf_ecat_reg_alstatus;
184 static int hf_ecat_reg_alstatus_status;
185 static int hf_ecat_reg_alstatus_err;
186 static int hf_ecat_reg_alstatus_id;
187 static int hf_ecat_reg_pdictrl1;
188 static int hf_ecat_reg_pdictrl1_pdi;
189 static int hf_ecat_reg_pdictrl2;
190 static int hf_ecat_reg_pdictrl2_devemul;
191 static int hf_ecat_reg_pdictrl2_enhlnkdetect;
192 static int hf_ecat_reg_pdictrl2_dcsyncout;
193 static int hf_ecat_reg_pdictrl2_dcsyncin;
194 static int hf_ecat_reg_pdictrl2_enhlnkdetect0;
195 static int hf_ecat_reg_pdictrl2_enhlnkdetect1;
196 static int hf_ecat_reg_pdictrl2_enhlnkdetect2;
197 static int hf_ecat_reg_pdictrl2_enhlnkdetect3;
198 static int hf_ecat_reg_alstatuscode;
199 static int hf_ecat_reg_ecat_mask;
200 static int hf_ecat_reg_ecat_mask_latchevt;
201 static int hf_ecat_reg_ecat_mask_escstatevt;
202 static int hf_ecat_reg_ecat_mask_alstatevt;
203 static int hf_ecat_reg_ecat_mask_sm0irq;
204 static int hf_ecat_reg_ecat_mask_sm1irq;
205 static int hf_ecat_reg_ecat_mask_sm2irq;
206 static int hf_ecat_reg_ecat_mask_sm3irq;
207 static int hf_ecat_reg_ecat_mask_sm4irq;
208 static int hf_ecat_reg_ecat_mask_sm5irq;
209 static int hf_ecat_reg_ecat_mask_sm6irq;
210 static int hf_ecat_reg_ecat_mask_sm7irq;
211 static int hf_ecat_reg_pdiL;
212 static int hf_ecat_reg_pdiL_alctrl;
213 static int hf_ecat_reg_pdiL_latchin;
214 static int hf_ecat_reg_pdiL_sync0;
215 static int hf_ecat_reg_pdiL_sync1;
216 static int hf_ecat_reg_pdiL_smchg;
217 static int hf_ecat_reg_pdiL_eepromcmdpen;
218 static int hf_ecat_reg_pdiL_sm0;
219 static int hf_ecat_reg_pdiL_sm1;
220 static int hf_ecat_reg_pdiL_sm2;
221 static int hf_ecat_reg_pdiL_sm3;
222 static int hf_ecat_reg_pdiL_sm4;
223 static int hf_ecat_reg_pdiL_sm5;
224 static int hf_ecat_reg_pdiL_sm6;
225 static int hf_ecat_reg_pdiL_sm7;
226 static int hf_ecat_reg_pdiH;
227 static int hf_ecat_reg_ecat;
228 static int hf_ecat_reg_ecat_latchevt;
229 static int hf_ecat_reg_ecat_escstatevt;
230 static int hf_ecat_reg_ecat_alstatevt;
231 static int hf_ecat_reg_ecat_sm0irq;
232 static int hf_ecat_reg_ecat_sm1irq;
233 static int hf_ecat_reg_ecat_sm2irq;
234 static int hf_ecat_reg_ecat_sm3irq;
235 static int hf_ecat_reg_ecat_sm4irq;
236 static int hf_ecat_reg_ecat_sm5irq;
237 static int hf_ecat_reg_ecat_sm6irq;
238 static int hf_ecat_reg_ecat_sm7irq;
239 static int hf_ecat_reg_pdi1;
240 static int hf_ecat_reg_pdi1_alctrl;
241 static int hf_ecat_reg_pdi1_latchin;
242 static int hf_ecat_reg_pdi1_sync0;
243 static int hf_ecat_reg_pdi1_sync1;
244 static int hf_ecat_reg_pdi1_smchg;
245 static int hf_ecat_reg_pdi1_eepromcmdpen;
246 static int hf_ecat_reg_pdi1_sm0;
247 static int hf_ecat_reg_pdi1_sm1;
248 static int hf_ecat_reg_pdi1_sm2;
249 static int hf_ecat_reg_pdi1_sm3;
250 static int hf_ecat_reg_pdi1_sm4;
251 static int hf_ecat_reg_pdi1_sm5;
252 static int hf_ecat_reg_pdi1_sm6;
253 static int hf_ecat_reg_pdi1_sm7;
254 static int hf_ecat_reg_pdi2;
255 static int hf_ecat_reg_crc0;
256 static int hf_ecat_reg_crc0_frame;
257 static int hf_ecat_reg_crc0_rx;
258 static int hf_ecat_reg_crc1;
259 static int hf_ecat_reg_crc1_frame;
260 static int hf_ecat_reg_crc1_rx;
261 static int hf_ecat_reg_crc2;
262 static int hf_ecat_reg_crc2_frame;
263 static int hf_ecat_reg_crc2_rx;
264 static int hf_ecat_reg_crc3;
265 static int hf_ecat_reg_crc3_frame;
266 static int hf_ecat_reg_crc3_rx;
267 static int hf_ecat_reg_crc_fwd0;
268 static int hf_ecat_reg_crc_fwd1;
269 static int hf_ecat_reg_crc_fwd2;
270 static int hf_ecat_reg_crc_fwd3;
271 static int hf_ecat_reg_processuniterr;
272 static int hf_ecat_reg_pdierr;
273 static int hf_ecat_reg_linklost0;
274 static int hf_ecat_reg_linklost1;
275 static int hf_ecat_reg_linklost2;
276 static int hf_ecat_reg_linklost3;
277 static int hf_ecat_reg_wd_divisor;
278 static int hf_ecat_reg_wd_timepdi;
279 static int hf_ecat_reg_wd_timesm;
280 static int hf_ecat_reg_wd_status;
281 static int hf_ecat_reg_wd_status_pdwatchdog;
282 static int hf_ecat_reg_wd_cntsm;
283 static int hf_ecat_reg_wd_cntpdi;
284 static int hf_ecat_reg_eeprom_assign;
285 static int hf_ecat_reg_eeprom_assign_ctrl;
286 static int hf_ecat_reg_eeprom_assign_pdiaccess;
287 static int hf_ecat_reg_eeprom_assign_status;
288 static int hf_ecat_reg_ctrlstat;
289 static int hf_ecat_reg_ctrlstat_wraccess;
290 static int hf_ecat_reg_ctrlstat_eepromemul;
291 static int hf_ecat_reg_ctrlstat_8bacc;
292 static int hf_ecat_reg_ctrlstat_2bacc;
293 static int hf_ecat_reg_ctrlstat_rdacc;
294 static int hf_ecat_reg_ctrlstat_wracc;
295 static int hf_ecat_reg_ctrlstat_reloadacc;
296 static int hf_ecat_reg_ctrlstat_crcerr;
297 static int hf_ecat_reg_ctrlstat_lderr;
298 static int hf_ecat_reg_ctrlstat_cmderr;
299 static int hf_ecat_reg_ctrlstat_wrerr;
300 static int hf_ecat_reg_ctrlstat_busy;
301 static int hf_ecat_reg_addrl;
302 static int hf_ecat_reg_addrh;
303 static int hf_ecat_reg_data0;
304 static int hf_ecat_reg_data1;
305 static int hf_ecat_reg_data2;
306 static int hf_ecat_reg_data3;
307 static int hf_ecat_reg_mio_ctrlstat;
308 static int hf_ecat_reg_mio_ctrlstat_wracc1;
309 static int hf_ecat_reg_mio_ctrlstat_offsphy;
310 static int hf_ecat_reg_mio_ctrlstat_rdacc;
311 static int hf_ecat_reg_mio_ctrlstat_wracc2;
312 static int hf_ecat_reg_mio_ctrlstat_wrerr;
313 static int hf_ecat_reg_mio_ctrlstat_busy;
314 static int hf_ecat_reg_mio_addr;
315 static int hf_ecat_reg_mio_addr_phyaddr;
316 static int hf_ecat_reg_mio_addr_mioaddr;
317 static int hf_ecat_reg_mio_data;
318 static int hf_ecat_reg_mio_access;
319 static int hf_ecat_reg_mio_access_ecatacc;
320 static int hf_ecat_reg_mio_access_pdiacc;
321 static int hf_ecat_reg_mio_access_forcereset;
322 static int hf_ecat_reg_mio_status0;
323 static int hf_ecat_reg_mio_status0_physlink;
324 static int hf_ecat_reg_mio_status0_link;
325 static int hf_ecat_reg_mio_status0_linkstatuserr;
326 static int hf_ecat_reg_mio_status0_readerr;
327 static int hf_ecat_reg_mio_status0_linkpartnererr;
328 static int hf_ecat_reg_mio_status0_phycfgupdated;
329 static int hf_ecat_reg_mio_status1;
330 static int hf_ecat_reg_mio_status1_physlink;
331 static int hf_ecat_reg_mio_status1_link;
332 static int hf_ecat_reg_mio_status1_linkstatuserr;
333 static int hf_ecat_reg_mio_status1_readerr;
334 static int hf_ecat_reg_mio_status1_linkpartnererr;
335 static int hf_ecat_reg_mio_status1_phycfgupdated;
336 static int hf_ecat_reg_mio_status2;
337 static int hf_ecat_reg_mio_status2_physlink;
338 static int hf_ecat_reg_mio_status2_link;
339 static int hf_ecat_reg_mio_status2_linkstatuserr;
340 static int hf_ecat_reg_mio_status2_readerr;
341 static int hf_ecat_reg_mio_status2_linkpartnererr;
342 static int hf_ecat_reg_mio_status2_phycfgupdated;
343 static int hf_ecat_reg_mio_status3;
344 static int hf_ecat_reg_mio_status3_physlink;
345 static int hf_ecat_reg_mio_status3_link;
346 static int hf_ecat_reg_mio_status3_linkstatuserr;
347 static int hf_ecat_reg_mio_status3_readerr;
348 static int hf_ecat_reg_mio_status3_linkpartnererr;
349 static int hf_ecat_reg_mio_status3_phycfgupdated;
350 static int hf_ecat_reg_fmmu;
351 static int hf_ecat_reg_fmmu_lstart;
352 static int hf_ecat_reg_fmmu_llen;
353 static int hf_ecat_reg_fmmu_lstartbit;
354 static int hf_ecat_reg_fmmu_lendbit;
355 static int hf_ecat_reg_fmmu_pstart;
356 static int hf_ecat_reg_fmmu_pstartbit;
357 static int hf_ecat_reg_fmmu_type;
358 static int hf_ecat_reg_fmmu_typeread;
359 static int hf_ecat_reg_fmmu_typewrite;
360 static int hf_ecat_reg_fmmu_activate;
361 static int hf_ecat_reg_fmmu_activate0;
362 static int hf_ecat_reg_syncman_ctrlstatus;
363 static int hf_ecat_reg_syncman_pmode;
364 static int hf_ecat_reg_syncman_access;
365 static int hf_ecat_reg_syncman_irq_ecat;
366 static int hf_ecat_reg_syncman_irq_pdi;
367 static int hf_ecat_reg_syncman_wdt;
368 static int hf_ecat_reg_syncman_irq_write;
369 static int hf_ecat_reg_syncman_irq_read;
370 static int hf_ecat_reg_syncman_1bufstate;
371 static int hf_ecat_reg_syncman_3bufstate;
372 static int hf_ecat_reg_syncman_sm_enable;
373 static int hf_ecat_reg_syncman_enable;
374 static int hf_ecat_reg_syncman_repeatreq;
375 static int hf_ecat_reg_syncman_latchsmchg_ecat;
376 static int hf_ecat_reg_syncman_latchsmchg_pdi;
377 static int hf_ecat_reg_syncman_deactivate;
378 static int hf_ecat_reg_syncman_repeatack;
379 static int hf_ecat_reg_syncman;
380 static int hf_ecat_reg_syncman_start;
381 static int hf_ecat_reg_syncman_len;
382 static int hf_ecat_reg_dc_recv0;
383 static int hf_ecat_reg_dc_recv1;
384 static int hf_ecat_reg_dc_recv2;
385 static int hf_ecat_reg_dc_recv3;
386 static int hf_ecat_reg_dc_systime;
387 static int hf_ecat_reg_dc_systimeL;
388 static int hf_ecat_reg_dc_systimeH;
389 static int hf_ecat_reg_dc_recvtime64;
390 static int hf_ecat_reg_dc_systimeoffs;
391 static int hf_ecat_reg_dc_systimeoffsl;
392 static int hf_ecat_reg_dc_systimeoffsh;
393 static int hf_ecat_reg_dc_systimedelay;
394 static int hf_ecat_reg_dc_ctrlerr;
395 static int hf_ecat_reg_dc_speedstart;
396 static int hf_ecat_reg_dc_speeddiff;
397 static int hf_ecat_reg_dc_fltdepth_systimediff;
398 static int hf_ecat_reg_dc_fltdepth_speedcnt;
399 static int hf_ecat_reg_dc_cycunitctrl;
400 static int hf_ecat_reg_dc_cycunitctrl_access_cyclic;
401 static int hf_ecat_reg_dc_cycunitctrl_access_latch0;
402 static int hf_ecat_reg_dc_cycunitctrl_access_latch1;
403 static int hf_ecat_reg_dc_activation;
404 static int hf_ecat_reg_dc_activation_enablecyclic;
405 static int hf_ecat_reg_dc_activation_gen_sync0;
406 static int hf_ecat_reg_dc_activation_gen_sync1;
407 static int hf_ecat_reg_dc_activation_autoactivation;
408 static int hf_ecat_reg_dc_activation_stimeext;
409 static int hf_ecat_reg_dc_activation_stimecheck;
410 static int hf_ecat_reg_dc_activation_hlfrange;
411 static int hf_ecat_reg_dc_activation_dblrange;
412 static int hf_ecat_reg_dc_cycimpuls;
413 static int hf_ecat_reg_dc_activationstat;
414 static int hf_ecat_reg_dc_activationstat_sync0pend;
415 static int hf_ecat_reg_dc_activationstat_sync1pend;
416 static int hf_ecat_reg_dc_activationstat_stimeoutofrange;
417 static int hf_ecat_reg_dc_sync0_status;
418 static int hf_ecat_reg_dc_sync0_status_triggered;
419 static int hf_ecat_reg_dc_sync1_status;
420 static int hf_ecat_reg_dc_sync1_status_triggered;
421 static int hf_ecat_reg_dc_starttime0;
422 static int hf_ecat_reg_dc_starttime1;
423 static int hf_ecat_reg_dc_cyctime0;
424 static int hf_ecat_reg_dc_cyctime1;
425 static int hf_ecat_reg_dc_latch0_ctrl_pos;
426 static int hf_ecat_reg_dc_latch0_ctrl_neg;
427 static int hf_ecat_reg_dc_latch1_ctrl_pos;
428 static int hf_ecat_reg_dc_latch1_ctrl_neg;
429 static int hf_ecat_reg_dc_latch0_status_eventpos;
430 static int hf_ecat_reg_dc_latch0_status_eventneg;
431 static int hf_ecat_reg_dc_latch0_status_pinstate;
432 static int hf_ecat_reg_dc_latch1_status_eventpos;
433 static int hf_ecat_reg_dc_latch1_status_eventneg;
434 static int hf_ecat_reg_dc_latch1_status_pinstate;
435 static int hf_ecat_reg_dc_latch0_ctrl;
436 static int hf_ecat_reg_dc_latch1_ctrl;
437 static int hf_ecat_reg_dc_latch0_status;
438 static int hf_ecat_reg_dc_latch1_status;
439 static int hf_ecat_reg_dc_latch0_pos;
440 static int hf_ecat_reg_dc_latch0_neg;
441 static int hf_ecat_reg_dc_latch1_pos;
442 static int hf_ecat_reg_dc_latch1_neg;
443 static int hf_ecat_reg_dc_rcvsyncmanchg;
444 static int hf_ecat_reg_dc_pdismstart;
445 static int hf_ecat_reg_dc_pdismchg;
446
447
448 static const value_string EcCmdShort[] =
449 {
450 { 0, "NOP" },
451 { 1, "APRD" },
452 { 2, "APWR" },
453 { 3, "APRW" },
454 { 4, "FPRD" },
455 { 5, "FPWR" },
456 { 6, "FPRW" },
457 { 7, "BRD" },
458 { 8, "BWR" },
459 { 9, "BRW" },
460 { 10, "LRD" },
461 { 11, "LWR" },
462 { 12, "LRW" },
463 { 13, "ARMW" },
464 { 14, "FRMW" },
465 { 255, "EXT" },
466 { 0, NULL }
467 };
468
469 static const value_string EcCmdLong[] =
470 {
471 { 0, "No operation" },
472 { 1, "Auto Increment Physical Read" },
473 { 2, "Auto Increment Physical Write" },
474 { 3, "Auto Increment Physical ReadWrite" },
475 { 4, "Configured address Physical Read" },
476 { 5, "Configured address Physical Write" },
477 { 6, "Configured address Physical ReadWrite" },
478 { 7, "Broadcast Read" },
479 { 8, "Broadcast Write" },
480 { 9, "Broadcast ReadWrite" },
481 { 10, "Logical Read" },
482 { 11, "Logical Write" },
483 { 12, "Logical ReadWrite" },
484 { 13, "Auto Increment Physical Read Multiple Write" },
485 { 14, "Configured Address Physical Read Multiple Write" },
486 { 255, "EXT" },
487 { 0, NULL }
488 };
489
490 static const value_string ecat_subframe_reserved_vals[] =
491 {
492 { 0, "Valid"},
493 { 0, NULL}
494 };
495
496 static const true_false_string tfs_ecat_subframe_circulating_vals =
497 {
498 "Frame has circulated once", "Frame is not circulating"
499 };
500
501 static const true_false_string tfs_ecat_subframe_more_vals =
502 {
503 "More EtherCAT datagrams will follow", "Last EtherCAT datagram"
504 };
505
506 static const true_false_string tfs_ecat_fmmu_typeread =
507 {
508 "Read in use", "Read ignore"
509 };
510
511 static const true_false_string tfs_ecat_fmmu_typewrite =
512 {
513 "Write in use", "Write ignore"
514 };
515
516 static const true_false_string tfs_local_true_false =
517 {
518 "True", "False",
519 };
520
521 static const true_false_string tfs_local_disabled_enabled =
522 {
523 "Enabled", "Disabled",
524 };
525
526 static const true_false_string tfs_local_disable_enable =
527 {
528 "Enable", "Disable",
529 };
530
531 static const true_false_string tfs_esc_reg_watchdog =
532 {
533 "Okay", "Run out",
534 };
535
536
537 static const char* convertEcCmdToText(int cmd, const value_string ec_cmd[])
538 {
539 return val_to_str(cmd, ec_cmd, "<UNKNOWN: %d>");
540 }
541
542 #define ENDOF(p) ((p)+1) /* pointer to end of *p*/
543
544 typedef enum
545 {
546 EC_CMD_TYPE_NOP = 0,
547 EC_CMD_TYPE_APRD = 1,
548 EC_CMD_TYPE_APWR = 2,
549 EC_CMD_TYPE_APRW = 3,
550 EC_CMD_TYPE_FPRD = 4,
551 EC_CMD_TYPE_FPWR = 5,
552 EC_CMD_TYPE_FPRW = 6,
553 EC_CMD_TYPE_BRD = 7,
554 EC_CMD_TYPE_BWR = 8,
555 EC_CMD_TYPE_BRW = 9,
556 EC_CMD_TYPE_LRD = 10,
557 EC_CMD_TYPE_LWR = 11,
558 EC_CMD_TYPE_LRW = 12,
559 EC_CMD_TYPE_ARMW = 13,
560 EC_CMD_TYPE_FRMW = 14,
561 EC_CMD_TYPE_EXT = 255
562 } EC_CMD_TYPE;
563
564 /* Esc Feature Reg 8 */
565 static int * const ecat_esc_reg_8[] = {
566 &hf_ecat_reg_esc_features_fmmurestrict,
567 &hf_ecat_reg_esc_features_smaddrrestrict,
568 &hf_ecat_reg_esc_features_dcsupport,
569 &hf_ecat_reg_esc_features_dc64support,
570 &hf_ecat_reg_esc_features_ebuslowjitter,
571 &hf_ecat_reg_esc_features_ebusextlinkdetect,
572 &hf_ecat_reg_esc_features_miiextlinkdetect,
573 &hf_ecat_reg_esc_features_crcext,
574 NULL
575 };
576
577 /* Esc Status Reg 100 */
578 static int * const ecat_esc_reg_100[] =
579 {
580 &hf_ecat_reg_dlctrl1_killnonecat,
581 &hf_ecat_reg_dlctrl1_port0extlinkdetect,
582 &hf_ecat_reg_dlctrl1_port1extlinkdetect,
583 &hf_ecat_reg_dlctrl1_port2extlinkdetect,
584 &hf_ecat_reg_dlctrl1_port3extlinkdetect,
585 NULL
586 };
587
588 /* Esc Status Reg 101 */
589 static const value_string vals_esc_reg_101[] = {
590 { 0, "Auto loop" },
591 { 1, "Auto close only" },
592 { 2, "Loop open" },
593 { 3, "Loop closed" },
594 { 0, NULL },
595 };
596
597 static int * const ecat_esc_reg_101[] =
598 {
599 &hf_ecat_reg_dlctrl2_port0,
600 &hf_ecat_reg_dlctrl2_port1,
601 &hf_ecat_reg_dlctrl2_port2,
602 &hf_ecat_reg_dlctrl2_port3,
603 NULL
604 };
605
606 static int * const ecat_esc_reg_102[] = {
607 &hf_ecat_reg_dlctrl3_fifosize,
608 &hf_ecat_reg_dlctrl3_lowebusjit,
609 NULL
610 };
611
612 static int * const ecat_esc_reg_103[] = {
613 &hf_ecat_reg_dlctrl4_2ndaddress,
614 NULL
615 };
616
617 /* Esc Status Reg 110 */
618 static int * const ecat_esc_reg_110[] =
619 {
620 &hf_ecat_reg_dlstatus1_operation,
621 &hf_ecat_reg_dlstatus1_pdiwatchdog,
622 &hf_ecat_reg_dlstatus1_enhlinkdetect,
623 &hf_ecat_reg_dlstatus1_physlink_port0,
624 &hf_ecat_reg_dlstatus1_physlink_port1,
625 &hf_ecat_reg_dlstatus1_physlink_port2,
626 &hf_ecat_reg_dlstatus1_physlink_port3,
627 NULL
628 };
629
630 /* Esc Status Reg 111 */
631 static const value_string vals_esc_reg_111[] = {
632 { 0, "Loop open, no link" },
633 { 1, "Loop closed, no link" },
634 { 2, "Loop open, with link" },
635 { 3, "Loop closed, with link" },
636 { 0, NULL},
637 };
638
639 static int * const ecat_esc_reg_111[] =
640 {
641 &hf_ecat_reg_dlstatus2_port0,
642 &hf_ecat_reg_dlstatus2_port1,
643 &hf_ecat_reg_dlstatus2_port2,
644 &hf_ecat_reg_dlstatus2_port3,
645 NULL
646 };
647
648 static const value_string vals_esc_reg_120[] = {
649 { 1, "INIT" },
650 { 2, "PREOP" },
651 { 3, "BOOTSTRAP" },
652 { 4, "SAFEOP" },
653 { 8, "OP" },
654 { 0, NULL},
655 };
656
657 static int * const ecat_esc_reg_120[] = {
658 &hf_ecat_reg_alctrl_ctrl,
659 &hf_ecat_reg_alctrl_errack,
660 &hf_ecat_reg_alctrl_id,
661 NULL
662 };
663
664 static int * const ecat_esc_reg_130[] = {
665 &hf_ecat_reg_alstatus_status,
666 &hf_ecat_reg_alstatus_err,
667 &hf_ecat_reg_alstatus_id,
668 NULL
669 };
670
671 static const value_string vals_esc_reg_140[] = {
672 { 0, "None" },
673 { 1, "4 bit dig. input" },
674 { 2, "4 bit dig. output" },
675 { 3, "2 bit dig. in/output" },
676 { 4, "dig. in/output" },
677 { 5, "SPI slave" },
678 { 7, "EtherCAT bridge" },
679 { 8, "16 bit uC (async)" },
680 { 9, "8 bit uC (async)" },
681 { 10, "16 bit uC (sync)" },
682 { 11, "8 bit uC (sync)" },
683 { 16, "32/0 bit dig. in/output" },
684 { 17, "24/8 bit dig. in/output" },
685 { 18, "16/16 bit dig. in/output" },
686 { 19, "8/24 bit dig. in/output" },
687 { 20, "0/32 bit dig. in/output" },
688 { 128, "On chip bus" },
689 { 0, NULL},
690 };
691
692 static int * const ecat_esc_reg_140[] = {
693 &hf_ecat_reg_pdictrl1_pdi,
694 NULL
695 };
696
697 static int * const ecat_esc_reg_141[] = {
698 &hf_ecat_reg_pdictrl2_devemul,
699 &hf_ecat_reg_pdictrl2_enhlnkdetect,
700 &hf_ecat_reg_pdictrl2_dcsyncout,
701 &hf_ecat_reg_pdictrl2_dcsyncin,
702 &hf_ecat_reg_pdictrl2_enhlnkdetect0,
703 &hf_ecat_reg_pdictrl2_enhlnkdetect1,
704 &hf_ecat_reg_pdictrl2_enhlnkdetect2,
705 &hf_ecat_reg_pdictrl2_enhlnkdetect3,
706 NULL
707 };
708
709 static int * const ecat_esc_reg_200[] = {
710 &hf_ecat_reg_ecat_mask_latchevt,
711 &hf_ecat_reg_ecat_mask_escstatevt,
712 &hf_ecat_reg_ecat_mask_alstatevt,
713 &hf_ecat_reg_ecat_mask_sm0irq,
714 &hf_ecat_reg_ecat_mask_sm1irq,
715 &hf_ecat_reg_ecat_mask_sm2irq,
716 &hf_ecat_reg_ecat_mask_sm3irq,
717 &hf_ecat_reg_ecat_mask_sm4irq,
718 &hf_ecat_reg_ecat_mask_sm5irq,
719 &hf_ecat_reg_ecat_mask_sm6irq,
720 &hf_ecat_reg_ecat_mask_sm7irq,
721 NULL
722 };
723
724 static int * const ecat_esc_reg_204[] = {
725 &hf_ecat_reg_pdiL_alctrl,
726 &hf_ecat_reg_pdiL_latchin,
727 &hf_ecat_reg_pdiL_sync0,
728 &hf_ecat_reg_pdiL_sync1,
729 &hf_ecat_reg_pdiL_smchg,
730 &hf_ecat_reg_pdiL_eepromcmdpen,
731 &hf_ecat_reg_pdiL_sm0,
732 &hf_ecat_reg_pdiL_sm1,
733 &hf_ecat_reg_pdiL_sm2,
734 &hf_ecat_reg_pdiL_sm3,
735 &hf_ecat_reg_pdiL_sm4,
736 &hf_ecat_reg_pdiL_sm5,
737 &hf_ecat_reg_pdiL_sm6,
738 &hf_ecat_reg_pdiL_sm7,
739 NULL
740 };
741
742 static int * const ecat_esc_reg_210[] = {
743 &hf_ecat_reg_ecat_latchevt,
744 &hf_ecat_reg_ecat_escstatevt,
745 &hf_ecat_reg_ecat_alstatevt,
746 &hf_ecat_reg_ecat_sm0irq,
747 &hf_ecat_reg_ecat_sm1irq,
748 &hf_ecat_reg_ecat_sm2irq,
749 &hf_ecat_reg_ecat_sm3irq,
750 &hf_ecat_reg_ecat_sm4irq,
751 &hf_ecat_reg_ecat_sm5irq,
752 &hf_ecat_reg_ecat_sm6irq,
753 &hf_ecat_reg_ecat_sm7irq,
754 NULL
755 };
756
757 static int * const ecat_esc_reg_220[] = {
758 &hf_ecat_reg_pdi1_alctrl,
759 &hf_ecat_reg_pdi1_latchin,
760 &hf_ecat_reg_pdi1_sync0,
761 &hf_ecat_reg_pdi1_sync1,
762 &hf_ecat_reg_pdi1_smchg,
763 &hf_ecat_reg_pdi1_eepromcmdpen,
764 &hf_ecat_reg_pdi1_sm0,
765 &hf_ecat_reg_pdi1_sm1,
766 &hf_ecat_reg_pdi1_sm2,
767 &hf_ecat_reg_pdi1_sm3,
768 &hf_ecat_reg_pdi1_sm4,
769 &hf_ecat_reg_pdi1_sm5,
770 &hf_ecat_reg_pdi1_sm6,
771 &hf_ecat_reg_pdi1_sm7,
772 NULL
773 };
774
775 static int * const ecat_esc_reg_300[] = {
776 &hf_ecat_reg_crc0_frame,
777 &hf_ecat_reg_crc0_rx,
778 NULL
779 };
780
781 static int * const ecat_esc_reg_302[] = {
782 &hf_ecat_reg_crc1_frame,
783 &hf_ecat_reg_crc1_rx,
784 NULL
785 };
786
787 static int * const ecat_esc_reg_304[] = {
788 &hf_ecat_reg_crc2_frame,
789 &hf_ecat_reg_crc2_rx,
790 NULL
791 };
792
793 static int * const ecat_esc_reg_306[] = {
794 &hf_ecat_reg_crc3_frame,
795 &hf_ecat_reg_crc3_rx,
796 NULL
797 };
798
799 static int * const ecat_esc_reg_440[] = {
800 &hf_ecat_reg_wd_status_pdwatchdog,
801 NULL
802 };
803
804 static const true_false_string tfs_esc_reg_500_0 = {
805 "Local uC", "ECAT"
806 };
807
808 static const true_false_string tfs_esc_reg_500_1 = {
809 "Reset Bit 501.0 to 0", "Do not change Bit 501.0"
810 };
811
812 static int * const ecat_esc_reg_500[] = {
813 &hf_ecat_reg_eeprom_assign_ctrl,
814 &hf_ecat_reg_eeprom_assign_pdiaccess,
815 &hf_ecat_reg_eeprom_assign_status,
816 NULL
817 };
818
819 static const true_false_string tfs_esc_reg_502_5 = {
820 "PDI emulates EEPROM", "Normal operation"
821 };
822
823 static int * const ecat_esc_reg_502[] = {
824 &hf_ecat_reg_ctrlstat_wraccess,
825 &hf_ecat_reg_ctrlstat_eepromemul,
826 &hf_ecat_reg_ctrlstat_8bacc,
827 &hf_ecat_reg_ctrlstat_2bacc,
828 &hf_ecat_reg_ctrlstat_rdacc,
829 &hf_ecat_reg_ctrlstat_wracc,
830 &hf_ecat_reg_ctrlstat_reloadacc,
831 &hf_ecat_reg_ctrlstat_crcerr,
832 &hf_ecat_reg_ctrlstat_lderr,
833 &hf_ecat_reg_ctrlstat_cmderr,
834 &hf_ecat_reg_ctrlstat_wrerr,
835 &hf_ecat_reg_ctrlstat_busy,
836 NULL
837 };
838
839 static int * const ecat_esc_reg_510[] = {
840 &hf_ecat_reg_mio_ctrlstat_wracc1,
841 &hf_ecat_reg_mio_ctrlstat_offsphy,
842 &hf_ecat_reg_mio_ctrlstat_rdacc,
843 &hf_ecat_reg_mio_ctrlstat_wracc2,
844 &hf_ecat_reg_mio_ctrlstat_wrerr,
845 &hf_ecat_reg_mio_ctrlstat_busy,
846 NULL
847 };
848
849 static int * const ecat_esc_reg_512[] = {
850 &hf_ecat_reg_mio_addr_phyaddr,
851 &hf_ecat_reg_mio_addr_mioaddr,
852 NULL
853 };
854
855 static int * const ecat_esc_reg_516[] = {
856 &hf_ecat_reg_mio_access_ecatacc,
857 &hf_ecat_reg_mio_access_pdiacc,
858 &hf_ecat_reg_mio_access_forcereset,
859 NULL
860 };
861
862 static int * const ecat_esc_reg_518[] = {
863 &hf_ecat_reg_mio_status0_physlink,
864 &hf_ecat_reg_mio_status0_link,
865 &hf_ecat_reg_mio_status0_linkstatuserr,
866 &hf_ecat_reg_mio_status0_readerr,
867 &hf_ecat_reg_mio_status0_linkpartnererr,
868 &hf_ecat_reg_mio_status0_phycfgupdated,
869 NULL
870 };
871
872 static int * const ecat_esc_reg_519[] = {
873 &hf_ecat_reg_mio_status1_physlink,
874 &hf_ecat_reg_mio_status1_link,
875 &hf_ecat_reg_mio_status1_linkstatuserr,
876 &hf_ecat_reg_mio_status1_readerr,
877 &hf_ecat_reg_mio_status1_linkpartnererr,
878 &hf_ecat_reg_mio_status1_phycfgupdated,
879 NULL
880 };
881
882 static int * const ecat_esc_reg_51A[] = {
883 &hf_ecat_reg_mio_status2_physlink,
884 &hf_ecat_reg_mio_status2_link,
885 &hf_ecat_reg_mio_status2_linkstatuserr,
886 &hf_ecat_reg_mio_status2_readerr,
887 &hf_ecat_reg_mio_status2_linkpartnererr,
888 &hf_ecat_reg_mio_status2_phycfgupdated,
889 NULL
890 };
891
892 static int * const ecat_esc_reg_51B[] = {
893 &hf_ecat_reg_mio_status3_physlink,
894 &hf_ecat_reg_mio_status3_link,
895 &hf_ecat_reg_mio_status3_linkstatuserr,
896 &hf_ecat_reg_mio_status3_readerr,
897 &hf_ecat_reg_mio_status3_linkpartnererr,
898 &hf_ecat_reg_mio_status3_phycfgupdated,
899 NULL
900 };
901
902 static const true_false_string tfs_ecat_fmmu_activate =
903 {
904 "activated", "deactivated"
905 };
906
907 static int ecat_reg_600(packet_info *pinfo _U_, proto_tree *tree, tvbuff_t *tvb, int offset)
908 {
909 proto_item* item;
910 proto_tree* subtree;
911
912 item = proto_tree_add_item(tree, hf_ecat_reg_fmmu, tvb, offset, 16, ENC_NA);
913 subtree = proto_item_add_subtree(item, ett_ecat_reg_fmmu);
914
915 proto_tree_add_item(subtree, hf_ecat_reg_fmmu_lstart, tvb, offset, 4, ENC_LITTLE_ENDIAN);
916 offset += 4;
917 proto_tree_add_item(subtree, hf_ecat_reg_fmmu_llen, tvb, offset, 2, ENC_LITTLE_ENDIAN);
918 offset += 2;
919 proto_tree_add_item(subtree, hf_ecat_reg_fmmu_lstartbit, tvb, offset, 1, ENC_NA);
920 offset += 1;
921 proto_tree_add_item(subtree, hf_ecat_reg_fmmu_lendbit, tvb, offset, 1, ENC_NA);
922 offset += 1;
923 proto_tree_add_item(subtree, hf_ecat_reg_fmmu_pstart, tvb, offset, 2, ENC_LITTLE_ENDIAN);
924 offset += 2;
925 proto_tree_add_item(subtree, hf_ecat_reg_fmmu_pstartbit, tvb, offset, 1, ENC_NA);
926 offset += 1;
927 proto_tree_add_item(subtree, hf_ecat_reg_fmmu_type, tvb, offset, 1, ENC_NA);
928 proto_tree_add_item(subtree, hf_ecat_reg_fmmu_typeread, tvb, offset, 1, ENC_NA);
929 proto_tree_add_item(subtree, hf_ecat_reg_fmmu_typewrite, tvb, offset, 1, ENC_NA);
930 offset += 1;
931 proto_tree_add_item(subtree, hf_ecat_reg_fmmu_activate, tvb, offset, 1, ENC_NA);
932 proto_tree_add_item(subtree, hf_ecat_reg_fmmu_activate0, tvb, offset, 1, ENC_NA);
933
934 return 16;
935 }
936
937 static int ecat_reg_800(packet_info *pinfo _U_, proto_tree *tree, tvbuff_t *tvb, int offset)
938 {
939 proto_item* item;
940 proto_tree* subtree;
941
942 static int * const reg4[] = {
943 &hf_ecat_reg_syncman_pmode,
944 &hf_ecat_reg_syncman_access,
945 &hf_ecat_reg_syncman_irq_ecat,
946 &hf_ecat_reg_syncman_irq_pdi,
947 &hf_ecat_reg_syncman_wdt,
948 &hf_ecat_reg_syncman_irq_write,
949 &hf_ecat_reg_syncman_irq_read,
950 &hf_ecat_reg_syncman_1bufstate,
951 &hf_ecat_reg_syncman_3bufstate,
952 NULL
953 };
954 static int * const reg6[] = {
955 &hf_ecat_reg_syncman_enable,
956 &hf_ecat_reg_syncman_repeatreq,
957 &hf_ecat_reg_syncman_latchsmchg_ecat,
958 &hf_ecat_reg_syncman_latchsmchg_pdi,
959 &hf_ecat_reg_syncman_deactivate,
960 &hf_ecat_reg_syncman_repeatack,
961 NULL
962 };
963
964 item = proto_tree_add_item(tree, hf_ecat_reg_syncman, tvb, offset, 8, ENC_NA);
965 subtree = proto_item_add_subtree(item, ett_ecat_reg_syncman);
966
967 proto_tree_add_item(subtree, hf_ecat_reg_syncman_start, tvb, offset, 2, ENC_LITTLE_ENDIAN);
968 offset += 2;
969 proto_tree_add_item(subtree, hf_ecat_reg_syncman_len, tvb, offset, 2, ENC_LITTLE_ENDIAN);
970 offset += 2;
971 proto_tree_add_bitmask(subtree, tvb, offset, hf_ecat_reg_syncman_ctrlstatus, ett_ecat_reg_syncman_ctrlstatus, reg4, ENC_LITTLE_ENDIAN);
972 offset += 2;
973 proto_tree_add_bitmask(subtree, tvb, offset, hf_ecat_reg_syncman_sm_enable, ett_ecat_reg_syncman_sm_enable, reg6, ENC_LITTLE_ENDIAN);
974
975 return 8;
976 }
977
978 static const value_string vals_esc_reg_8041[] = {
979 { 0, "3 buffer" },
980 { 2, "1 buffer" },
981 { 3, "1 buffer direct" },
982 { 0, NULL},
983 };
984
985 static const value_string vals_esc_reg_8042[] = {
986 { 0, "Read" },
987 { 1, "Write" },
988 { 0, NULL},
989 };
990
991 static const true_false_string tfs_esc_reg_8051 = {
992 "Written", "Read"
993 };
994
995 static const value_string vals_esc_reg_8052[] = {
996 { 0, "1. buffer" },
997 { 1, "2. buffer" },
998 { 2, "3. buffer" },
999 { 3, "blocked (start)" },
1000 { 0, NULL},
1001 };
1002
1003
1004 static const true_false_string tfs_esc_reg_9801 = {
1005 "PDI", "ECAT"
1006 };
1007
1008 static int * const ecat_esc_reg_980[] = {
1009 &hf_ecat_reg_dc_cycunitctrl_access_cyclic,
1010 &hf_ecat_reg_dc_cycunitctrl_access_latch0,
1011 &hf_ecat_reg_dc_cycunitctrl_access_latch1,
1012 NULL
1013 };
1014
1015 static int * const ecat_esc_reg_981[] = {
1016 &hf_ecat_reg_dc_activation_enablecyclic,
1017 &hf_ecat_reg_dc_activation_gen_sync0,
1018 &hf_ecat_reg_dc_activation_gen_sync1,
1019 &hf_ecat_reg_dc_activation_autoactivation,
1020 &hf_ecat_reg_dc_activation_stimeext,
1021 &hf_ecat_reg_dc_activation_stimecheck,
1022 &hf_ecat_reg_dc_activation_hlfrange,
1023 &hf_ecat_reg_dc_activation_dblrange,
1024 NULL
1025 };
1026
1027 static int * const ecat_esc_reg_984[] = {
1028 &hf_ecat_reg_dc_activationstat_sync0pend,
1029 &hf_ecat_reg_dc_activationstat_sync1pend,
1030 &hf_ecat_reg_dc_activationstat_stimeoutofrange,
1031 NULL
1032 };
1033
1034 static int * const ecat_esc_reg_98e[] = {
1035 &hf_ecat_reg_dc_sync0_status_triggered,
1036 NULL
1037 };
1038
1039 static int * const ecat_esc_reg_98f[] = {
1040 &hf_ecat_reg_dc_sync1_status_triggered,
1041 NULL
1042 };
1043
1044 static const true_false_string tfs_esc_reg_9A8E1 = {
1045 "Single event", "Continuous"
1046 };
1047
1048 static int * const ecat_esc_reg_9a8[] = {
1049 &hf_ecat_reg_dc_latch0_ctrl_pos,
1050 &hf_ecat_reg_dc_latch0_ctrl_neg,
1051 NULL
1052 };
1053 static int * const ecat_esc_reg_9a9[] = {
1054 &hf_ecat_reg_dc_latch1_ctrl_pos,
1055 &hf_ecat_reg_dc_latch1_ctrl_neg,
1056 NULL
1057 };
1058
1059 static int * const ecat_esc_reg_9ae[] = {
1060 &hf_ecat_reg_dc_latch0_status_eventpos,
1061 &hf_ecat_reg_dc_latch0_status_eventneg,
1062 &hf_ecat_reg_dc_latch0_status_pinstate,
1063 NULL
1064 };
1065 static int * const ecat_esc_reg_9af[] = {
1066 &hf_ecat_reg_dc_latch1_status_eventpos,
1067 &hf_ecat_reg_dc_latch1_status_eventneg,
1068 &hf_ecat_reg_dc_latch1_status_pinstate,
1069 NULL
1070 };
1071
1072 typedef int register_dissect_func(packet_info *pinfo, proto_tree *tree, tvbuff_t *tvb, int offset);
1073
1074 /* esc registers */
1075 typedef struct
1076 {
1077 uint16_t reg;
1078 uint16_t length;
1079 uint16_t repeat;
1080 int* phf;
1081 int* const *bitmask_info;
1082 int* pett;
1083 register_dissect_func *dissect;
1084 } ecat_esc_reg_info;
1085
1086
1087 #define NO_SUBTREE_FILL NULL, NULL, NULL
1088
1089 static ecat_esc_reg_info ecat_esc_registers [] =
1090 {
1091 { 0x0000, 1, 1, &hf_ecat_reg_revision, NO_SUBTREE_FILL},
1092 { 0x0001, 1, 1, &hf_ecat_reg_esc_type, NO_SUBTREE_FILL},
1093 { 0x0002, 2, 1, &hf_ecat_reg_esc_build, NO_SUBTREE_FILL},
1094 { 0x0004, 1, 1, &hf_ecat_reg_esc_fmmucnt, NO_SUBTREE_FILL},
1095 { 0x0005, 1, 1, &hf_ecat_reg_esc_smcnt, NO_SUBTREE_FILL},
1096 { 0x0006, 1, 1, &hf_ecat_reg_esc_ports, NO_SUBTREE_FILL},
1097 { 0x0007, 1, 1, &hf_ecat_reg_esc_dpram, NO_SUBTREE_FILL},
1098 { 0x0008, 2, 1, &hf_ecat_reg_esc_features, ecat_esc_reg_8, &ett_ecat_reg_esc_features, NULL},
1099 { 0x0010, 2, 1, &hf_ecat_reg_physaddr, NO_SUBTREE_FILL},
1100 { 0x0012, 2, 1, &hf_ecat_reg_physaddr2, NO_SUBTREE_FILL},
1101 { 0x0020, 2, 1, &hf_ecat_reg_regprotect, NO_SUBTREE_FILL},
1102 { 0x0030, 2, 1, &hf_ecat_reg_accessprotect, NO_SUBTREE_FILL},
1103 { 0x0040, 1, 1, &hf_ecat_reg_resetecat, NO_SUBTREE_FILL},
1104 { 0x0041, 1, 1, &hf_ecat_reg_resetpdi, NO_SUBTREE_FILL},
1105 { 0x0100, 1, 1, &hf_ecat_reg_dlctrl1, ecat_esc_reg_100, &ett_ecat_reg_dlctrl1, NULL},
1106 { 0x0101, 1, 1, &hf_ecat_reg_dlctrl2, ecat_esc_reg_101, &ett_ecat_reg_dlctrl2, NULL},
1107 { 0x0102, 1, 1, &hf_ecat_reg_dlctrl3, ecat_esc_reg_102, &ett_ecat_reg_dlctrl3, NULL},
1108 { 0x0103, 1, 1, &hf_ecat_reg_dlctrl4, ecat_esc_reg_103, &ett_ecat_reg_dlctrl4, NULL},
1109 { 0x0108, 2, 1, &hf_ecat_reg_regphysrwoffs, NO_SUBTREE_FILL},
1110 { 0x0110, 1, 1, &hf_ecat_reg_dlstatus1, ecat_esc_reg_110, &ett_ecat_reg_dlstatus1, NULL},
1111 { 0x0111, 1, 1, &hf_ecat_reg_dlstatus2, ecat_esc_reg_111, &ett_ecat_reg_dlstatus2, NULL},
1112 { 0x0120, 2, 1, &hf_ecat_reg_alctrl, ecat_esc_reg_120, &ett_ecat_reg_alctrl, NULL},
1113 { 0x0130, 2, 1, &hf_ecat_reg_alstatus, ecat_esc_reg_130, &ett_ecat_reg_alstatus, NULL},
1114 { 0x0134, 2, 1, &hf_ecat_reg_alstatuscode, NO_SUBTREE_FILL},
1115 { 0x0140, 1, 1, &hf_ecat_reg_pdictrl1, ecat_esc_reg_140, &ett_ecat_reg_pdictrl1, NULL},
1116 { 0x0141, 1, 1, &hf_ecat_reg_pdictrl2, ecat_esc_reg_141, &ett_ecat_reg_pdictrl2, NULL},
1117 { 0x0200, 2, 1, &hf_ecat_reg_ecat_mask, ecat_esc_reg_200, &ett_ecat_reg_ecat_mask, NULL},
1118 { 0x0204, 2, 1, &hf_ecat_reg_pdiL, ecat_esc_reg_204, &ett_ecat_reg_pdiL, NULL},
1119 { 0x0206, 2, 1, &hf_ecat_reg_pdiH, NO_SUBTREE_FILL},
1120 { 0x0210, 2, 1, &hf_ecat_reg_ecat, ecat_esc_reg_210, &ett_ecat_reg_ecat, NULL},
1121 { 0x0220, 2, 1, &hf_ecat_reg_pdi1, ecat_esc_reg_220, &ett_ecat_reg_pdi1, NULL},
1122 { 0x0222, 2, 1, &hf_ecat_reg_pdi2, NO_SUBTREE_FILL},
1123 { 0x0300, 2, 1, &hf_ecat_reg_crc0, ecat_esc_reg_300, &ett_ecat_reg_crc0, NULL},
1124 { 0x0302, 2, 1, &hf_ecat_reg_crc1, ecat_esc_reg_302, &ett_ecat_reg_crc1, NULL},
1125 { 0x0304, 2, 1, &hf_ecat_reg_crc2, ecat_esc_reg_304, &ett_ecat_reg_crc2, NULL},
1126 { 0x0306, 2, 1, &hf_ecat_reg_crc3, ecat_esc_reg_306, &ett_ecat_reg_crc3, NULL},
1127 { 0x0308, 1, 1, &hf_ecat_reg_crc_fwd0, NO_SUBTREE_FILL},
1128 { 0x0309, 1, 1, &hf_ecat_reg_crc_fwd1, NO_SUBTREE_FILL},
1129 { 0x030A, 1, 1, &hf_ecat_reg_crc_fwd2, NO_SUBTREE_FILL},
1130 { 0x030B, 1, 1, &hf_ecat_reg_crc_fwd3, NO_SUBTREE_FILL},
1131 { 0x030C, 1, 1, &hf_ecat_reg_processuniterr, NO_SUBTREE_FILL},
1132 { 0x030D, 1, 1, &hf_ecat_reg_pdierr, NO_SUBTREE_FILL},
1133 { 0x0310, 1, 1, &hf_ecat_reg_linklost0, NO_SUBTREE_FILL},
1134 { 0x0311, 1, 1, &hf_ecat_reg_linklost1, NO_SUBTREE_FILL},
1135 { 0x0312, 1, 1, &hf_ecat_reg_linklost2, NO_SUBTREE_FILL},
1136 { 0x0313, 1, 1, &hf_ecat_reg_linklost3, NO_SUBTREE_FILL},
1137 { 0x0400, 2, 1, &hf_ecat_reg_wd_divisor, NO_SUBTREE_FILL},
1138 { 0x0410, 2, 1, &hf_ecat_reg_wd_timepdi, NO_SUBTREE_FILL},
1139 { 0x0420, 2, 1, &hf_ecat_reg_wd_timesm, NO_SUBTREE_FILL},
1140 { 0x0440, 1, 1, &hf_ecat_reg_wd_status, ecat_esc_reg_440, &ett_ecat_reg_wd_status, NULL},
1141 { 0x0442, 1, 1, &hf_ecat_reg_wd_cntsm, NO_SUBTREE_FILL},
1142 { 0x0443, 1, 1, &hf_ecat_reg_wd_cntpdi, NO_SUBTREE_FILL},
1143 { 0x0500, 2, 1, &hf_ecat_reg_eeprom_assign, ecat_esc_reg_500, &ett_ecat_reg_eeprom_assign, NULL},
1144 { 0x0502, 2, 1, &hf_ecat_reg_ctrlstat, ecat_esc_reg_502, &ett_ecat_reg_ctrlstat, NULL},
1145 { 0x0504, 2, 1, &hf_ecat_reg_addrl, NO_SUBTREE_FILL},
1146 { 0x0506, 2, 1, &hf_ecat_reg_addrh, NO_SUBTREE_FILL},
1147 { 0x0508, 2, 1, &hf_ecat_reg_data0, NO_SUBTREE_FILL},
1148 { 0x050a, 2, 1, &hf_ecat_reg_data1, NO_SUBTREE_FILL},
1149 { 0x050c, 2, 1, &hf_ecat_reg_data2, NO_SUBTREE_FILL},
1150 { 0x050e, 2, 1, &hf_ecat_reg_data3, NO_SUBTREE_FILL},
1151 { 0x0510, 2, 1, &hf_ecat_reg_mio_ctrlstat, ecat_esc_reg_510, &ett_ecat_reg_mio_ctrlstat, NULL},
1152 { 0x0512, 2, 1, &hf_ecat_reg_mio_addr, ecat_esc_reg_512, &ett_ecat_mio_addr, NULL},
1153 { 0x0514, 2, 1, &hf_ecat_reg_mio_data, NO_SUBTREE_FILL},
1154 { 0x0516, 2, 1, &hf_ecat_reg_mio_access, ecat_esc_reg_516, &ett_ecat_mio_access, NULL},
1155 { 0x0518, 1, 1, &hf_ecat_reg_mio_status0, ecat_esc_reg_518, &ett_ecat_mio_status0, NULL},
1156 { 0x0519, 1, 1, &hf_ecat_reg_mio_status1, ecat_esc_reg_519, &ett_ecat_mio_status1, NULL},
1157 { 0x051A, 1, 1, &hf_ecat_reg_mio_status2, ecat_esc_reg_51A, &ett_ecat_mio_status2, NULL},
1158 { 0x051B, 1, 1, &hf_ecat_reg_mio_status3, ecat_esc_reg_51B, &ett_ecat_mio_status3, NULL},
1159 { 0x0600, 16, 16, &hf_ecat_reg_fmmu, NULL, NULL, ecat_reg_600},
1160 { 0x0800, 8, 8, &hf_ecat_reg_syncman, NULL, NULL, ecat_reg_800},
1161 { 0x0900, 4, 1, &hf_ecat_reg_dc_recv0, NO_SUBTREE_FILL},
1162 { 0x0904, 4, 1, &hf_ecat_reg_dc_recv1, NO_SUBTREE_FILL},
1163 { 0x0908, 4, 1, &hf_ecat_reg_dc_recv2, NO_SUBTREE_FILL},
1164 { 0x090c, 4, 1, &hf_ecat_reg_dc_recv3, NO_SUBTREE_FILL},
1165 { 0x0910, 8, 1, &hf_ecat_reg_dc_systime, NO_SUBTREE_FILL},
1166 { 0x0910, 4, 1, &hf_ecat_reg_dc_systimeL, NO_SUBTREE_FILL},
1167 { 0x0914, 4, 1, &hf_ecat_reg_dc_systimeH, NO_SUBTREE_FILL},
1168 { 0x0918, 8, 1, &hf_ecat_reg_dc_recvtime64, NO_SUBTREE_FILL},
1169 { 0x0920, 8, 1, &hf_ecat_reg_dc_systimeoffs, NO_SUBTREE_FILL},
1170 { 0x0920, 4, 1, &hf_ecat_reg_dc_systimeoffsl, NO_SUBTREE_FILL},
1171 { 0x0924, 4, 1, &hf_ecat_reg_dc_systimeoffsh, NO_SUBTREE_FILL},
1172 { 0x0928, 4, 1, &hf_ecat_reg_dc_systimedelay, NO_SUBTREE_FILL},
1173 { 0x092c, 4, 1, &hf_ecat_reg_dc_ctrlerr, NO_SUBTREE_FILL},
1174 { 0x0930, 2, 1, &hf_ecat_reg_dc_speedstart, NO_SUBTREE_FILL},
1175 { 0x0932, 2, 1, &hf_ecat_reg_dc_speeddiff, NO_SUBTREE_FILL},
1176 { 0x0934, 1, 1, &hf_ecat_reg_dc_fltdepth_systimediff, NO_SUBTREE_FILL},
1177 { 0x0935, 1, 1, &hf_ecat_reg_dc_fltdepth_speedcnt, NO_SUBTREE_FILL},
1178 { 0x0980, 1, 1, &hf_ecat_reg_dc_cycunitctrl, ecat_esc_reg_980, &ett_ecat_reg_dc_cycunitctrl, NULL},
1179 { 0x0981, 1, 1, &hf_ecat_reg_dc_activation, ecat_esc_reg_981, &ett_ecat_dc_activation, NULL},
1180 { 0x0982, 2, 1, &hf_ecat_reg_dc_cycimpuls, NO_SUBTREE_FILL},
1181 { 0x0984, 1, 1, &hf_ecat_reg_dc_activationstat, ecat_esc_reg_984, &ett_ecat_dc_activationstat, NULL},
1182 { 0x098e, 1, 1, &hf_ecat_reg_dc_sync0_status, ecat_esc_reg_98e, &ett_ecat_dc_sync0_status, NULL},
1183 { 0x098f, 1, 1, &hf_ecat_reg_dc_sync1_status, ecat_esc_reg_98f, &ett_ecat_dc_sync1_status, NULL},
1184 { 0x0990, 8, 1, &hf_ecat_reg_dc_starttime0, NO_SUBTREE_FILL},
1185 { 0x0998, 8, 1, &hf_ecat_reg_dc_starttime1, NO_SUBTREE_FILL},
1186 { 0x09a0, 4, 1, &hf_ecat_reg_dc_cyctime0, NO_SUBTREE_FILL},
1187 { 0x09a4, 4, 1, &hf_ecat_reg_dc_cyctime1, NO_SUBTREE_FILL},
1188 { 0x09a8, 1, 1, &hf_ecat_reg_dc_latch0_ctrl, ecat_esc_reg_9a8, &ett_ecat_dc_latch0_ctrl, NULL},
1189 { 0x09a9, 1, 1, &hf_ecat_reg_dc_latch1_ctrl, ecat_esc_reg_9a9, &ett_ecat_dc_latch1_ctrl, NULL},
1190 { 0x09ae, 1, 1, &hf_ecat_reg_dc_latch0_status, ecat_esc_reg_9ae, &ett_ecat_dc_latch0_status, NULL},
1191 { 0x09af, 1, 1, &hf_ecat_reg_dc_latch1_status, ecat_esc_reg_9af, &ett_ecat_dc_latch1_status, NULL},
1192 { 0x09b0, 8, 1, &hf_ecat_reg_dc_latch0_pos, NO_SUBTREE_FILL},
1193 { 0x09b8, 8, 1, &hf_ecat_reg_dc_latch0_neg, NO_SUBTREE_FILL},
1194 { 0x09c0, 8, 1, &hf_ecat_reg_dc_latch1_pos, NO_SUBTREE_FILL},
1195 { 0x09c8, 8, 1, &hf_ecat_reg_dc_latch1_neg, NO_SUBTREE_FILL},
1196 { 0x09f0, 4, 1, &hf_ecat_reg_dc_rcvsyncmanchg, NO_SUBTREE_FILL},
1197 { 0x09f8, 4, 1, &hf_ecat_reg_dc_pdismstart, NO_SUBTREE_FILL},
1198 { 0x09fc, 4, 1, &hf_ecat_reg_dc_pdismchg, NO_SUBTREE_FILL},
1199
1200 };
1201
1202 /* esc dissector */
1203 static int dissect_esc_register(packet_info* pinfo, proto_tree *tree, tvbuff_t *tvb, int offset, uint32_t len, EcParserHDR* hdr, uint16_t cnt)
1204 {
1205 unsigned i;
1206 int r;
1207 int res = -1;
1208 int regOffset;
1209 int read = 0;
1210
1211 if (len > 0 )
1212 {
1213 switch ( hdr->cmd )
1214 {
1215 case EC_CMD_TYPE_APRD:
1216 case EC_CMD_TYPE_BRD:
1217 case EC_CMD_TYPE_FPRD:
1218 read = 1;
1219 /* Fall through */
1220 case EC_CMD_TYPE_APWR:
1221 case EC_CMD_TYPE_APRW:
1222 case EC_CMD_TYPE_FPWR:
1223 case EC_CMD_TYPE_FPRW:
1224 case EC_CMD_TYPE_BWR:
1225 case EC_CMD_TYPE_BRW:
1226 case EC_CMD_TYPE_ARMW:
1227 case EC_CMD_TYPE_FRMW:
1228 for ( i=0; i<array_length(ecat_esc_registers); i++ )
1229 {
1230 if ( hdr->anAddrUnion.a.ado + len< ecat_esc_registers[i].reg )
1231 break;
1232
1233 regOffset = ecat_esc_registers[i].reg;
1234 for ( r=0; r<ecat_esc_registers[i].repeat; r++ )
1235 {
1236 if ( regOffset >= hdr->anAddrUnion.a.ado && regOffset+ecat_esc_registers[i].length <= (uint16_t)(hdr->anAddrUnion.a.ado + len) )
1237 {
1238 if ( cnt > 0 || !read )
1239 {
1240 if (ecat_esc_registers[i].dissect != NULL)
1241 {
1242 ecat_esc_registers[i].dissect(pinfo, tree, tvb, offset+(regOffset-hdr->anAddrUnion.a.ado));
1243 }
1244 else if (ecat_esc_registers[i].bitmask_info != NULL)
1245 {
1246 proto_tree_add_bitmask(tree, tvb, offset+(regOffset-hdr->anAddrUnion.a.ado), *ecat_esc_registers[i].phf,
1247 *ecat_esc_registers[i].pett, ecat_esc_registers[i].bitmask_info, ENC_LITTLE_ENDIAN);
1248 }
1249 else
1250 {
1251 proto_tree_add_item(tree, *ecat_esc_registers[i].phf, tvb, offset+(regOffset-hdr->anAddrUnion.a.ado), ecat_esc_registers[i].length, ENC_LITTLE_ENDIAN);
1252 }
1253 }
1254 res = 0;
1255 }
1256 regOffset+=ecat_esc_registers[i].length;
1257 }
1258 }
1259 break;
1260 }
1261 }
1262
1263 return res;
1264 }
1265 static void init_EcParserHDR(EcParserHDR* pHdr, tvbuff_t *tvb, int offset)
1266 {
1267 pHdr->cmd = tvb_get_uint8(tvb, offset++);
1268 pHdr->idx = tvb_get_uint8(tvb, offset++);
1269 pHdr->anAddrUnion.a.adp = tvb_get_letohs(tvb, offset); offset+=2;
1270 pHdr->anAddrUnion.a.ado = tvb_get_letohs(tvb, offset); offset+=2;
1271 pHdr->len = tvb_get_letohs(tvb, offset); offset+=2;
1272 pHdr->intr = tvb_get_letohs(tvb, offset);
1273 }
1274
1275 static void init_dc_measure(uint32_t* pDC, tvbuff_t *tvb, int offset)
1276 {
1277 int i;
1278 for ( i=0; i<4; i++ )
1279 {
1280 pDC[i] = tvb_get_letohl(tvb, offset);
1281 offset+=4;
1282 }
1283 }
1284
1285 static uint16_t get_wc(EcParserHDR* pHdr, tvbuff_t *tvb, int offset)
1286 {
1287 return tvb_get_letohs(tvb, offset+EcParserHDR_Len+(pHdr->len&0x07ff));
1288 }
1289
1290 static uint16_t get_cmd_len(EcParserHDR* pHdr)
1291 {
1292 return (EcParserHDR_Len+(pHdr->len&0x07ff)+2); /*Header + data + wc*/
1293 }
1294
1295
1296 static void EcSummaryFormater(uint32_t datalength, tvbuff_t *tvb, int offset, char *szText, int nMax)
1297 {
1298 unsigned nSub=0;
1299 unsigned nLen=0;
1300 uint8_t nCmds[4];
1301 unsigned nLens[4];
1302 EcParserHDR ecFirst;
1303 EcParserHDR ecParser;
1304
1305 unsigned suboffset=0;
1306
1307 init_EcParserHDR(&ecFirst, tvb, offset);
1308
1309 while ( suboffset < datalength )
1310 {
1311 PEcParserHDR pEcParser;
1312 if ( nSub > 0 )
1313 {
1314 init_EcParserHDR(&ecParser, tvb, offset+suboffset);
1315 pEcParser = &ecParser;
1316 }
1317 else
1318 pEcParser = &ecFirst;
1319
1320 if ( nSub < 4 )
1321 {
1322 nCmds[nSub] = pEcParser->cmd;
1323 nLens[nSub] = pEcParser->len&0x07ff;
1324 }
1325 nSub++;
1326 nLen += (pEcParser->len&0x07ff);
1327 /* bit 14 -- roundtrip */
1328
1329 if ( (pEcParser->len&0x8000) == 0 )
1330 break;
1331
1332 suboffset+=get_cmd_len(pEcParser);
1333 }
1334 if ( nSub == 1 )
1335 {
1336 uint16_t len = ecFirst.len&0x07ff;
1337 uint16_t cnt = get_wc(&ecFirst, tvb, offset);
1338 snprintf ( szText, nMax, "'%s': Len: %d, Adp 0x%x, Ado 0x%x, Wc %d ",
1339 convertEcCmdToText(ecFirst.cmd, EcCmdShort), len, ecFirst.anAddrUnion.a.adp, ecFirst.anAddrUnion.a.ado, cnt );
1340 }
1341 else if ( nSub == 2 )
1342 {
1343 snprintf ( szText, nMax, "%d Cmds, '%s': len %d, '%s': len %d ",
1344 nSub, convertEcCmdToText(nCmds[0], EcCmdShort), nLens[0], convertEcCmdToText(nCmds[1], EcCmdShort), nLens[1]);
1345 }
1346 else if ( nSub == 3 )
1347 {
1348 snprintf ( szText, nMax, "%d Cmds, '%s': len %d, '%s': len %d, '%s': len %d",
1349 nSub, convertEcCmdToText(nCmds[0], EcCmdShort), nLens[0], convertEcCmdToText(nCmds[1], EcCmdShort), nLens[1], convertEcCmdToText(nCmds[2], EcCmdShort), nLens[2]);
1350 }
1351 else if ( nSub == 4 )
1352 {
1353 snprintf ( szText, nMax, "%d Cmds, '%s': len %d, '%s': len %d, '%s': len %d, '%s': len %d",
1354 nSub, convertEcCmdToText(nCmds[0], EcCmdShort), nLens[0], convertEcCmdToText(nCmds[1], EcCmdShort), nLens[1], convertEcCmdToText(nCmds[2], EcCmdShort), nLens[2], convertEcCmdToText(nCmds[3], EcCmdShort), nLens[3]);
1355 }
1356 else
1357 snprintf ( szText, nMax, "%d Cmds, SumLen %d, '%s'... ",
1358 nSub, nLen, convertEcCmdToText(ecFirst.cmd, EcCmdShort));
1359 }
1360
1361 static void EcCmdFormatter(uint8_t cmd, char *szText, int nMax)
1362 {
1363 int idx=0;
1364 const char *szCmd = try_val_to_str_idx((uint32_t)cmd, EcCmdLong, &idx);
1365
1366 if ( idx != -1 )
1367 snprintf(szText, nMax, "Cmd : %d (%s)", cmd, szCmd);
1368 else
1369 snprintf(szText, nMax, "Cmd : %d (Unknown command)", cmd);
1370 }
1371
1372
1373 static void EcSubFormatter(tvbuff_t *tvb, int offset, char *szText, int nMax)
1374 {
1375 EcParserHDR ecParser;
1376 uint16_t len, cnt;
1377
1378 init_EcParserHDR(&ecParser, tvb, offset);
1379 len = ecParser.len&0x07ff;
1380 cnt = get_wc(&ecParser, tvb, offset);
1381
1382 switch ( ecParser.cmd )
1383 {
1384 case EC_CMD_TYPE_NOP:
1385 case EC_CMD_TYPE_APRD:
1386 case EC_CMD_TYPE_APWR:
1387 case EC_CMD_TYPE_APRW:
1388 case EC_CMD_TYPE_FPRD:
1389 case EC_CMD_TYPE_FPWR:
1390 case EC_CMD_TYPE_FPRW:
1391 case EC_CMD_TYPE_BRD:
1392 case EC_CMD_TYPE_BWR:
1393 case EC_CMD_TYPE_BRW:
1394 case EC_CMD_TYPE_ARMW:
1395 case EC_CMD_TYPE_FRMW:
1396 snprintf ( szText, nMax, "EtherCAT datagram: Cmd: '%s' (%d), Len: %d, Adp 0x%x, Ado 0x%x, Cnt %d",
1397 convertEcCmdToText(ecParser.cmd, EcCmdShort), ecParser.cmd, len, ecParser.anAddrUnion.a.adp, ecParser.anAddrUnion.a.ado, cnt);
1398 break;
1399 case EC_CMD_TYPE_LRD:
1400 case EC_CMD_TYPE_LWR:
1401 case EC_CMD_TYPE_LRW:
1402 snprintf ( szText, nMax, "EtherCAT datagram: Cmd: '%s' (%d), Len: %d, Addr 0x%x, Cnt %d",
1403 convertEcCmdToText(ecParser.cmd, EcCmdShort), ecParser.cmd, len, ecParser.anAddrUnion.addr, cnt);
1404 break;
1405 case EC_CMD_TYPE_EXT:
1406 snprintf ( szText, nMax, "EtherCAT datagram: Cmd: 'EXT' (%d), Len: %d", ecParser.cmd, len);
1407 break;
1408 default:
1409 snprintf ( szText, nMax, "EtherCAT datagram: Cmd: 'Unknown' (%d), Len: %d", ecParser.cmd, len);
1410 }
1411 }
1412
1413 /* Ethercat Datagram */
1414 static int dissect_ecat_datagram(tvbuff_t *tvb, packet_info *pinfo, proto_tree *tree, void* data _U_)
1415 {
1416 tvbuff_t *next_tvb;
1417 proto_item *ti, *aitem = NULL;
1418 proto_tree *ecat_datagrams_tree = NULL;
1419 unsigned offset = 0;
1420 char szText[200];
1421 int nMax = sizeof(szText)-1;
1422
1423 unsigned ecLength=0;
1424 unsigned subCount = 0;
1425 const unsigned datagram_length = tvb_captured_length(tvb);
1426 unsigned datagram_padding_bytes = 0;
1427 EcParserHDR ecHdr;
1428 heur_dtbl_entry_t *hdtbl_entry;
1429
1430 col_set_str(pinfo->cinfo, COL_PROTOCOL, "ECAT");
1431
1432 col_clear(pinfo->cinfo, COL_INFO);
1433
1434 /* If the data portion of an EtherCAT datagram is less than 44 bytes, then
1435 it must have been padded with an additional n number of bytes to reach a
1436 total Ethernet frame length of 64 bytes (Ethernet header + Ethernet Data +
1437 FCS). Hence at least 44 bytes data shall always be available in any
1438 EtherCAT datagram. */
1439 /* tvb_ensure_bytes_exist(tvb, offset, 44);
1440 this is not correct, because the frame might have been captured before the
1441 os added the padding bytes. E.g. in Windows the frames are captured on the
1442 protocol layer. When another protocol driver sends a frame this frame does
1443 not include the padding bytes.
1444 */
1445
1446 /* Count the length of the individual EtherCAT datagrams (sub datagrams)
1447 that are part of this EtherCAT frame. Stop counting when the current
1448 sub datagram header tells that there are no more sub datagrams or when
1449 there is no more data available in the PDU. */
1450 do
1451 {
1452 init_EcParserHDR(&ecHdr, tvb, ecLength);
1453 ecLength += get_cmd_len(&ecHdr);
1454 } while ((ecLength < datagram_length) &&
1455 (ecHdr.len & 0x8000));
1456
1457 /* Calculate the amount of padding data available in the PDU */
1458 datagram_padding_bytes = datagram_length - ecLength;
1459
1460 EcSummaryFormater(ecLength, tvb, offset, szText, nMax);
1461 col_append_str(pinfo->cinfo, COL_INFO, szText);
1462
1463 if( tree )
1464 {
1465 /* Create the EtherCAT datagram(s) subtree */
1466 ti = proto_tree_add_item(tree, proto_ecat_datagram, tvb, 0, -1, ENC_NA);
1467 ecat_datagrams_tree = proto_item_add_subtree(ti, ett_ecat);
1468
1469 proto_item_append_text(ti,": %s", szText);
1470 }
1471
1472 /* Dissect all sub frames of this EtherCAT PDU */
1473 do
1474 {
1475 proto_tree *ecat_datagram_tree = NULL, *ecat_header_tree = NULL, *ecat_dc_tree = NULL;
1476
1477 proto_item *hidden_item;
1478 uint32_t subsize;
1479 uint32_t suboffset;
1480 uint32_t len;
1481 uint16_t cnt;
1482 ETHERCAT_MBOX_HEADER mbox;
1483
1484 suboffset = offset;
1485 init_EcParserHDR(&ecHdr, tvb, suboffset);
1486
1487 subsize = get_cmd_len(&ecHdr);
1488 len = ecHdr.len & 0x07ff;
1489 cnt = get_wc(&ecHdr, tvb, suboffset);
1490
1491 if( tree )
1492 {
1493 /* Create the sub tree for the current datagram */
1494 EcSubFormatter(tvb, suboffset, szText, nMax);
1495 ecat_datagram_tree = proto_tree_add_subtree(ecat_datagrams_tree, tvb, suboffset, subsize, ett_ecat_datagram_subtree, NULL, szText);
1496
1497 /* Create a subtree placeholder for the Header */
1498 ecat_header_tree = proto_tree_add_subtree(ecat_datagram_tree, tvb, offset, EcParserHDR_Len, ett_ecat_header, NULL, "Header");
1499
1500 EcCmdFormatter(ecHdr.cmd, szText, nMax);
1501 aitem = proto_tree_add_item(ecat_header_tree, hf_ecat_cmd, tvb, suboffset, 1, ENC_LITTLE_ENDIAN);
1502 proto_item_set_text(aitem, "%s", szText);
1503 if( subCount < 10 ){
1504 aitem = proto_tree_add_item(ecat_header_tree, hf_ecat_sub_cmd[subCount], tvb, suboffset, 1, ENC_LITTLE_ENDIAN);
1505 proto_item_set_hidden(aitem);
1506 }
1507 suboffset+=1;
1508
1509 proto_tree_add_item(ecat_header_tree, hf_ecat_idx, tvb, suboffset, 1, ENC_LITTLE_ENDIAN);
1510 if( subCount < 10 ){
1511 aitem = proto_tree_add_item(ecat_header_tree, hf_ecat_sub_idx[subCount], tvb, suboffset, 1, ENC_LITTLE_ENDIAN);
1512 proto_item_set_hidden(aitem);
1513 }
1514 suboffset+=1;
1515
1516 switch ( ecHdr.cmd )
1517 {
1518 case 10:
1519 case 11:
1520 case 12:
1521 proto_tree_add_item(ecat_header_tree, hf_ecat_lad, tvb, suboffset, 4, ENC_LITTLE_ENDIAN);
1522 if( subCount < 10 ){
1523 aitem = proto_tree_add_item(ecat_header_tree, hf_ecat_sub_lad[subCount], tvb, suboffset, 4, ENC_LITTLE_ENDIAN);
1524 proto_item_set_hidden(aitem);
1525 }
1526
1527 suboffset+=4;
1528 break;
1529 default:
1530 proto_tree_add_item(ecat_header_tree, hf_ecat_adp, tvb, suboffset, 2, ENC_LITTLE_ENDIAN);
1531 if( subCount < 10 ){
1532 aitem = proto_tree_add_item(ecat_header_tree, hf_ecat_sub_adp[subCount], tvb, suboffset, 2, ENC_LITTLE_ENDIAN);
1533 proto_item_set_hidden(aitem);
1534 }
1535
1536 suboffset+=2;
1537 proto_tree_add_item(ecat_header_tree, hf_ecat_ado, tvb, suboffset, 2, ENC_LITTLE_ENDIAN);
1538 if( subCount < 10 ){
1539 aitem = proto_tree_add_item(ecat_header_tree, hf_ecat_sub_ado[subCount], tvb, suboffset, 2, ENC_LITTLE_ENDIAN);
1540 proto_item_set_hidden(aitem);
1541 }
1542
1543 suboffset+=2;
1544 }
1545
1546 {
1547 proto_tree *length_sub_tree;
1548
1549 /* Add information about the length field (11 bit length, 3 bits
1550 reserved, 1 bit circulating frame and 1 bit more in a sub tree */
1551 length_sub_tree = proto_tree_add_subtree_format(ecat_header_tree, tvb, suboffset, 2,
1552 ett_ecat_length, NULL, "Length : %d (0x%x) - %s - %s",
1553 len, len, ecHdr.len & 0x4000 ? "Roundtrip" : "No Roundtrip", ecHdr.len & 0x8000 ? "More Follows..." : "Last Sub Command");
1554
1555 proto_tree_add_item(length_sub_tree, hf_ecat_length_len, tvb, suboffset, 2, ENC_LITTLE_ENDIAN);
1556 proto_tree_add_item(length_sub_tree, hf_ecat_length_r, tvb, suboffset, 2, ENC_LITTLE_ENDIAN);
1557 proto_tree_add_item(length_sub_tree, hf_ecat_length_c, tvb, suboffset, 2, ENC_LITTLE_ENDIAN);
1558 proto_tree_add_item(length_sub_tree, hf_ecat_length_m, tvb, suboffset, 2, ENC_LITTLE_ENDIAN);
1559
1560 suboffset+=2;
1561 }
1562
1563 proto_tree_add_item(ecat_header_tree, hf_ecat_int, tvb, suboffset, 2, ENC_LITTLE_ENDIAN);
1564 suboffset+=2;
1565 }
1566 else
1567 {
1568 suboffset+=EcParserHDR_Len;
1569 }
1570
1571 if ( (ecHdr.cmd == 1 || ecHdr.cmd == 4) && ecHdr.anAddrUnion.a.ado == 0x900 && ecHdr.len >= 16 && cnt > 0 )
1572 {
1573 uint32_t pDC[4];
1574 init_dc_measure(pDC, tvb, suboffset);
1575
1576 ecat_dc_tree = proto_tree_add_subtree(ecat_datagram_tree, tvb, suboffset, len, ett_ecat_dc, NULL, "Dc");
1577 dissect_esc_register(pinfo, ecat_dc_tree, tvb, suboffset, len, &ecHdr, cnt);
1578
1579 if( subCount < 10 ){
1580 aitem = proto_tree_add_item(ecat_datagram_tree, hf_ecat_sub_data[subCount], tvb, offset + EcParserHDR_Len, len, ENC_NA);
1581 proto_item_set_hidden(aitem);
1582 }
1583
1584 if ( pDC[3] != 0 )
1585 {
1586 proto_tree_add_uint(ecat_dc_tree, hf_ecat_dc_diff_da, tvb, suboffset, 4, pDC[3] - pDC[0]);
1587 if( subCount < 10 ){
1588 hidden_item = proto_tree_add_uint(ecat_dc_tree, hf_ecat_sub_dc_diff_da[subCount], tvb, suboffset, 4, pDC[3] - pDC[0]);
1589 proto_item_set_hidden(hidden_item);
1590 }
1591
1592 if ( pDC[1] != 0 )
1593 {
1594 proto_tree_add_uint(ecat_dc_tree, hf_ecat_dc_diff_bd, tvb, suboffset, 4, pDC[1] - pDC[3]);
1595 if( subCount < 10 ){
1596 hidden_item = proto_tree_add_uint(ecat_dc_tree, hf_ecat_sub_dc_diff_bd[subCount], tvb, suboffset, 4, pDC[1] - pDC[3]);
1597 proto_item_set_hidden(hidden_item);
1598 }
1599 }
1600 else if ( pDC[2] != 0 )
1601 {
1602 proto_tree_add_uint(ecat_dc_tree, hf_ecat_dc_diff_cd, tvb, suboffset, 4, pDC[2] - pDC[3]);
1603 if( subCount < 10 ){
1604 hidden_item = proto_tree_add_uint(ecat_dc_tree, hf_ecat_sub_dc_diff_cd[subCount], tvb, suboffset, 4, pDC[2] - pDC[3]);
1605 proto_item_set_hidden(hidden_item);
1606 }
1607 }
1608 }
1609 if ( pDC[1] != 0 )
1610 {
1611 proto_tree_add_uint(ecat_dc_tree, hf_ecat_dc_diff_ba, tvb, suboffset, 4, pDC[1] - pDC[0]);
1612 if( subCount < 10 ){
1613 hidden_item = proto_tree_add_uint(ecat_dc_tree, hf_ecat_sub_dc_diff_ba[subCount], tvb, suboffset, 4, pDC[1] - pDC[0]);
1614 proto_item_set_hidden(hidden_item);
1615 }
1616 if ( pDC[2] != 0 )
1617 {
1618 proto_tree_add_uint(ecat_dc_tree, hf_ecat_dc_diff_cb, tvb, suboffset, 4, pDC[2] - pDC[1]);
1619 if( subCount < 10 ){
1620 hidden_item = proto_tree_add_uint(ecat_dc_tree, hf_ecat_sub_dc_diff_cb[subCount], tvb, suboffset, 4, pDC[2] - pDC[1]);
1621 proto_item_set_hidden(hidden_item);
1622 }
1623 }
1624 }
1625 else if ( pDC[2] != 0 )
1626 {
1627 proto_tree_add_uint(ecat_dc_tree, hf_ecat_dc_diff_ca, tvb, suboffset, 4, pDC[2] - pDC[0]);
1628 if( subCount < 10 ){
1629 hidden_item = proto_tree_add_uint(ecat_dc_tree, hf_ecat_sub_dc_diff_ca[subCount], tvb, suboffset, 4, pDC[2] - pDC[0]);
1630 proto_item_set_hidden(hidden_item);
1631 }
1632 }
1633 }
1634 else if (dissect_esc_register(pinfo, ecat_datagram_tree, tvb, suboffset, len, &ecHdr, cnt) != 0)
1635 {
1636 unsigned startOfData = offset + EcParserHDR_Len;
1637 unsigned dataLength = len;
1638
1639 if ( len >= ETHERCAT_MBOX_HEADER_LEN &&
1640 ((ecHdr.cmd==EC_CMD_TYPE_FPWR || ecHdr.cmd == EC_CMD_TYPE_APWR || ecHdr.cmd == EC_CMD_TYPE_APRW || ecHdr.cmd == EC_CMD_TYPE_FPRW) || ((ecHdr.cmd==EC_CMD_TYPE_FPRD || ecHdr.cmd==EC_CMD_TYPE_APRD) && cnt==1) ) &&
1641 ecHdr.anAddrUnion.a.ado>=0x1000
1642 )
1643 {
1644 init_mbx_header(&mbox, tvb, startOfData);
1645 switch ( mbox.aControlUnion.v.Type )
1646 {
1647 case ETHERCAT_MBOX_TYPE_EOE:
1648 case ETHERCAT_MBOX_TYPE_ADS:
1649 case ETHERCAT_MBOX_TYPE_FOE:
1650 case ETHERCAT_MBOX_TYPE_COE:
1651 case ETHERCAT_MBOX_TYPE_SOE:
1652 if ( mbox.Length <= 1500 )
1653 {
1654 unsigned MBoxLength = mbox.Length + ETHERCAT_MBOX_HEADER_LEN;
1655 if ( MBoxLength > len )
1656 MBoxLength = len;
1657
1658 next_tvb = tvb_new_subset_length(tvb, startOfData, MBoxLength);
1659 call_dissector_only(ecat_mailbox_handle, next_tvb, pinfo, ecat_datagram_tree, NULL);
1660
1661 startOfData += MBoxLength;
1662 dataLength -= MBoxLength;
1663 }
1664 break;
1665 }
1666 }
1667 if( dataLength > 0 )
1668 {
1669 /* Allow sub dissectors to have a chance with this data */
1670 if(!dissector_try_heuristic(heur_subdissector_list, tvb, pinfo, ecat_datagram_tree, &hdtbl_entry, NULL))
1671 {
1672 /* No sub dissector did recognize this data, dissect it as data only */
1673 proto_tree_add_item(ecat_datagram_tree, hf_ecat_data, tvb, startOfData, dataLength, ENC_NA);
1674 }
1675
1676 if( subCount < 10 ){
1677 aitem = proto_tree_add_item(ecat_datagram_tree, hf_ecat_sub_data[subCount], tvb, startOfData, dataLength, ENC_NA);
1678 proto_item_set_hidden(aitem);
1679 }
1680 }
1681 }
1682
1683 if( tree )
1684 {
1685 proto_tree_add_item(ecat_datagram_tree, hf_ecat_cnt, tvb, offset + EcParserHDR_Len + len , 2, ENC_LITTLE_ENDIAN);
1686 if( subCount < 10 ){
1687 aitem = proto_tree_add_item(ecat_datagram_tree, hf_ecat_sub_cnt[subCount], tvb, offset + EcParserHDR_Len + len , 2, ENC_LITTLE_ENDIAN);
1688 proto_item_set_hidden(aitem);
1689 }
1690 }
1691
1692 offset+=subsize;
1693 subCount++;
1694 } while((offset < datagram_length) &&
1695 (ecHdr.len & 0x8000));
1696
1697 /* Add information that states which portion of the PDU that is pad bytes.
1698 These are added just to get an Ethernet frame size of at least 64 bytes,
1699 which is required by the protocol specification */
1700 if(datagram_padding_bytes > 0)
1701 {
1702 proto_tree_add_item(tree, hf_ecat_padding, tvb, offset, tvb_captured_length_remaining(tvb, offset), ENC_NA);
1703 }
1704 return tvb_captured_length(tvb);
1705 }
1706
1707 void proto_register_ecat(void)
1708 {
1709 static hf_register_info hf[] =
1710 {
1711 { &hf_ecat_sub,
1712 { "EtherCAT Frame", "ecat.sub", FT_BYTES, BASE_NONE, NULL, 0x0,
1713 NULL, HFILL }
1714 },
1715 #if 0
1716 { &hf_ecat_header,
1717 { "header", "ecat.header",
1718 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL }
1719 },
1720 #endif
1721 { &hf_ecat_sub_data[0],
1722 { "Data", "ecat.sub1.data",
1723 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL }
1724 },
1725 { &hf_ecat_sub_data[1],
1726 { "Data", "ecat.sub2.data",
1727 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL }
1728 },
1729 { &hf_ecat_sub_data[2],
1730 { "Data", "ecat.sub3.data",
1731 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL }
1732 },
1733 { &hf_ecat_sub_data[3],
1734 { "Data", "ecat.sub4.data",
1735 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL }
1736 },
1737 { &hf_ecat_sub_data[4],
1738 { "Data", "ecat.sub5.data",
1739 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL }
1740 },
1741 { &hf_ecat_sub_data[5],
1742 { "Data", "ecat.sub6.data",
1743 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL }
1744 },
1745 { &hf_ecat_sub_data[6],
1746 { "Data", "ecat.sub7.data",
1747 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL }
1748 },
1749 { &hf_ecat_sub_data[7],
1750 { "Data", "ecat.sub8.data",
1751 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL }
1752 },
1753 { &hf_ecat_sub_data[8],
1754 { "Data", "ecat.sub9.data",
1755 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL }
1756 },
1757 { &hf_ecat_sub_data[9],
1758 { "Data", "ecat.sub10.data",
1759 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL }
1760 },
1761 { &hf_ecat_data,
1762 { "Data", "ecat.data",
1763 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL }
1764 },
1765 { &hf_ecat_cnt,
1766 { "Working Cnt", "ecat.cnt",
1767 FT_UINT16, BASE_DEC, NULL, 0x0, "The working counter is increased once for each addressed device if at least one byte/bit of the data was successfully read and/or written by that device, it is increased once for every operation made by that device - read/write/read and write", HFILL }
1768 },
1769 { &hf_ecat_sub_cnt[0],
1770 { "Working Cnt", "ecat.sub1.cnt",
1771 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL }
1772 },
1773 { &hf_ecat_sub_cnt[1],
1774 { "Working Cnt", "ecat.sub2.cnt",
1775 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL }
1776 },
1777 { &hf_ecat_sub_cnt[2],
1778 { "Working Cnt", "ecat.sub3.cnt",
1779 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL }
1780 },
1781 { &hf_ecat_sub_cnt[3],
1782 { "Working Cnt", "ecat.sub4.cnt",
1783 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL }
1784 },
1785 { &hf_ecat_sub_cnt[4],
1786 { "Working Cnt", "ecat.sub5.cnt",
1787 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL }
1788 },
1789 { &hf_ecat_sub_cnt[5],
1790 { "Working Cnt", "ecat.sub6.cnt",
1791 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL }
1792 },
1793 { &hf_ecat_sub_cnt[6],
1794 { "Working Cnt", "ecat.sub7.cnt",
1795 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL }
1796 },
1797 { &hf_ecat_sub_cnt[7],
1798 { "Working Cnt", "ecat.sub8.cnt",
1799 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL }
1800 },
1801 { &hf_ecat_sub_cnt[8],
1802 { "Working Cnt", "ecat.sub9.cnt",
1803 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL }
1804 },
1805 { &hf_ecat_sub_cnt[9],
1806 { "Working Cnt", "ecat.sub10.cnt",
1807 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL }
1808 },
1809 { &hf_ecat_cmd,
1810 { "Command", "ecat.cmd",
1811 FT_UINT8, BASE_HEX, VALS(EcCmdShort), 0x0, NULL, HFILL }
1812 },
1813 { &hf_ecat_sub_cmd[0],
1814 { "Command", "ecat.sub1.cmd",
1815 FT_UINT8, BASE_HEX, VALS(EcCmdShort), 0x0, NULL, HFILL }
1816 },
1817 { &hf_ecat_sub_cmd[1],
1818 { "Command", "ecat.sub2.cmd",
1819 FT_UINT8, BASE_HEX, VALS(EcCmdShort), 0x0, NULL, HFILL }
1820 },
1821 { &hf_ecat_sub_cmd[2],
1822 { "Command", "ecat.sub3.cmd",
1823 FT_UINT8, BASE_HEX, VALS(EcCmdShort), 0x0, NULL, HFILL }
1824 },
1825 { &hf_ecat_sub_cmd[3],
1826 { "Command", "ecat.sub4.cmd",
1827 FT_UINT8, BASE_HEX, VALS(EcCmdShort), 0x0, NULL, HFILL }
1828 },
1829 { &hf_ecat_sub_cmd[4],
1830 { "Command", "ecat.sub5.cmd",
1831 FT_UINT8, BASE_HEX, VALS(EcCmdShort), 0x0, NULL, HFILL }
1832 },
1833 { &hf_ecat_sub_cmd[5],
1834 { "Command", "ecat.sub6.cmd",
1835 FT_UINT8, BASE_HEX, VALS(EcCmdShort), 0x0, NULL, HFILL }
1836 },
1837 { &hf_ecat_sub_cmd[6],
1838 { "Command", "ecat.sub7.cmd",
1839 FT_UINT8, BASE_HEX, VALS(EcCmdShort), 0x0, NULL, HFILL }
1840 },
1841 { &hf_ecat_sub_cmd[7],
1842 { "Command", "ecat.sub8.cmd",
1843 FT_UINT8, BASE_HEX, VALS(EcCmdShort), 0x0, NULL, HFILL }
1844 },
1845 { &hf_ecat_sub_cmd[8],
1846 { "Command", "ecat.sub9.cmd",
1847 FT_UINT8, BASE_HEX, VALS(EcCmdShort), 0x0, NULL, HFILL }
1848 },
1849 { &hf_ecat_sub_cmd[9],
1850 { "Command", "ecat.sub10.cmd",
1851 FT_UINT8, BASE_HEX, VALS(EcCmdShort), 0x0, NULL, HFILL }
1852 },
1853 { &hf_ecat_idx,
1854 { "Index", "ecat.idx",
1855 FT_UINT8, BASE_HEX, NULL, 0x0,
1856 NULL, HFILL }
1857 },
1858 { &hf_ecat_sub_idx[0],
1859 { "Index", "ecat.sub1.idx",
1860 FT_UINT8, BASE_HEX, NULL, 0x0,
1861 NULL, HFILL }
1862 },
1863 { &hf_ecat_sub_idx[1],
1864 { "Index", "ecat.sub2.idx",
1865 FT_UINT8, BASE_HEX, NULL, 0x0,
1866 NULL, HFILL }
1867 },
1868 { &hf_ecat_sub_idx[2],
1869 { "Index", "ecat.sub3.idx",
1870 FT_UINT8, BASE_HEX, NULL, 0x0,
1871 NULL, HFILL }
1872 },
1873 { &hf_ecat_sub_idx[3],
1874 { "Index", "ecat.sub4.idx",
1875 FT_UINT8, BASE_HEX, NULL, 0x0,
1876 NULL, HFILL }
1877 },
1878 { &hf_ecat_sub_idx[4],
1879 { "Index", "ecat.sub5.idx",
1880 FT_UINT8, BASE_HEX, NULL, 0x0,
1881 NULL, HFILL }
1882 },
1883 { &hf_ecat_sub_idx[5],
1884 { "Index", "ecat.sub6.idx",
1885 FT_UINT8, BASE_HEX, NULL, 0x0,
1886 NULL, HFILL }
1887 },
1888 { &hf_ecat_sub_idx[6],
1889 { "Index", "ecat.sub7.idx",
1890 FT_UINT8, BASE_HEX, NULL, 0x0,
1891 NULL, HFILL }
1892 },
1893 { &hf_ecat_sub_idx[7],
1894 { "Index", "ecat.sub8.idx",
1895 FT_UINT8, BASE_HEX, NULL, 0x0,
1896 NULL, HFILL }
1897 },
1898 { &hf_ecat_sub_idx[8],
1899 { "Index", "ecat.sub9.idx",
1900 FT_UINT8, BASE_HEX, NULL, 0x0,
1901 NULL, HFILL }
1902 },
1903 { &hf_ecat_sub_idx[9],
1904 { "Index", "ecat.sub10.idx",
1905 FT_UINT8, BASE_HEX, NULL, 0x0,
1906 NULL, HFILL }
1907 },
1908 { &hf_ecat_adp,
1909 { "Slave Addr", "ecat.adp",
1910 FT_UINT16, BASE_HEX, NULL, 0x0,
1911 NULL, HFILL }
1912 },
1913 { &hf_ecat_sub_adp[0],
1914 { "Slave Addr", "ecat.sub1.adp",
1915 FT_UINT16, BASE_HEX, NULL, 0x0,
1916 NULL, HFILL }
1917 },
1918 { &hf_ecat_sub_adp[1],
1919 { "Slave Addr", "ecat.sub2.adp",
1920 FT_UINT16, BASE_HEX, NULL, 0x0,
1921 NULL, HFILL }
1922 },
1923 { &hf_ecat_sub_adp[2],
1924 { "Slave Addr", "ecat.sub3.adp",
1925 FT_UINT16, BASE_HEX, NULL, 0x0,
1926 NULL, HFILL }
1927 },
1928 { &hf_ecat_sub_adp[3],
1929 { "Slave Addr", "ecat.sub4.adp",
1930 FT_UINT16, BASE_HEX, NULL, 0x0,
1931 NULL, HFILL }
1932 },
1933 { &hf_ecat_sub_adp[4],
1934 { "Slave Addr", "ecat.sub5.adp",
1935 FT_UINT16, BASE_HEX, NULL, 0x0,
1936 NULL, HFILL }
1937 },
1938 { &hf_ecat_sub_adp[5],
1939 { "Slave Addr", "ecat.sub6.adp",
1940 FT_UINT16, BASE_HEX, NULL, 0x0,
1941 NULL, HFILL }
1942 },
1943 { &hf_ecat_sub_adp[6],
1944 { "Slave Addr", "ecat.sub7.adp",
1945 FT_UINT16, BASE_HEX, NULL, 0x0,
1946 NULL, HFILL }
1947 },
1948 { &hf_ecat_sub_adp[7],
1949 { "Slave Addr", "ecat.sub8.adp",
1950 FT_UINT16, BASE_HEX, NULL, 0x0,
1951 NULL, HFILL }
1952 },
1953 { &hf_ecat_sub_adp[8],
1954 { "Slave Addr", "ecat.sub9.adp",
1955 FT_UINT16, BASE_HEX, NULL, 0x0,
1956 NULL, HFILL }
1957 },
1958 { &hf_ecat_sub_adp[9],
1959 { "Slave Addr", "ecat.sub10.adp",
1960 FT_UINT16, BASE_HEX, NULL, 0x0,
1961 NULL, HFILL }
1962 },
1963 { &hf_ecat_ado,
1964 { "Offset Addr", "ecat.ado",
1965 FT_UINT16, BASE_HEX, NULL, 0x0,
1966 NULL, HFILL }
1967 },
1968 { &hf_ecat_sub_ado[0],
1969 { "Offset Addr", "ecat.sub1.ado",
1970 FT_UINT16, BASE_HEX, NULL, 0x0,
1971 NULL, HFILL }
1972 },
1973 { &hf_ecat_sub_ado[1],
1974 { "Offset Addr", "ecat.sub2.ado",
1975 FT_UINT16, BASE_HEX, NULL, 0x0,
1976 NULL, HFILL }
1977 },
1978 { &hf_ecat_sub_ado[2],
1979 { "Offset Addr", "ecat.sub3.ado",
1980 FT_UINT16, BASE_HEX, NULL, 0x0,
1981 NULL, HFILL }
1982 },
1983 { &hf_ecat_sub_ado[3],
1984 { "Offset Addr", "ecat.sub4.ado",
1985 FT_UINT16, BASE_HEX, NULL, 0x0,
1986 NULL, HFILL }
1987 },
1988 { &hf_ecat_sub_ado[4],
1989 { "Offset Addr", "ecat.sub5.ado",
1990 FT_UINT16, BASE_HEX, NULL, 0x0,
1991 NULL, HFILL }
1992 },
1993 { &hf_ecat_sub_ado[5],
1994 { "Offset Addr", "ecat.sub6.ado",
1995 FT_UINT16, BASE_HEX, NULL, 0x0,
1996 NULL, HFILL }
1997 },
1998 { &hf_ecat_sub_ado[6],
1999 { "Offset Addr", "ecat.sub7.ado",
2000 FT_UINT16, BASE_HEX, NULL, 0x0,
2001 NULL, HFILL }
2002 },
2003 { &hf_ecat_sub_ado[7],
2004 { "Offset Addr", "ecat.sub8.ado",
2005 FT_UINT16, BASE_HEX, NULL, 0x0,
2006 NULL, HFILL }
2007 },
2008 { &hf_ecat_sub_ado[8],
2009 { "Offset Addr", "ecat.sub9.ado",
2010 FT_UINT16, BASE_HEX, NULL, 0x0,
2011 NULL, HFILL }
2012 },
2013 { &hf_ecat_sub_ado[9],
2014 { "Offset Addr", "ecat.sub10.ado",
2015 FT_UINT16, BASE_HEX, NULL, 0x0,
2016 NULL, HFILL }
2017 },
2018 { &hf_ecat_lad,
2019 { "Log Addr", "ecat.lad",
2020 FT_UINT32, BASE_HEX, NULL, 0x0,
2021 NULL, HFILL }
2022 },
2023 { &hf_ecat_sub_lad[0],
2024 { "Log Addr", "ecat.sub1.lad",
2025 FT_UINT32, BASE_HEX, NULL, 0x0,
2026 NULL, HFILL }
2027 },
2028 { &hf_ecat_sub_lad[1],
2029 { "Log Addr", "ecat.sub2.lad",
2030 FT_UINT32, BASE_HEX, NULL, 0x0,
2031 NULL, HFILL }
2032 },
2033 { &hf_ecat_sub_lad[2],
2034 { "Log Addr", "ecat.sub3.lad",
2035 FT_UINT32, BASE_HEX, NULL, 0x0,
2036 NULL, HFILL }
2037 },
2038 { &hf_ecat_sub_lad[3],
2039 { "Log Addr", "ecat.sub4.lad",
2040 FT_UINT32, BASE_HEX, NULL, 0x0,
2041 NULL, HFILL }
2042 },
2043 { &hf_ecat_sub_lad[4],
2044 { "Log Addr", "ecat.sub5.lad",
2045 FT_UINT32, BASE_HEX, NULL, 0x0,
2046 NULL, HFILL }
2047 },
2048 { &hf_ecat_sub_lad[5],
2049 { "Log Addr", "ecat.sub6.lad",
2050 FT_UINT32, BASE_HEX, NULL, 0x0,
2051 NULL, HFILL }
2052 },
2053 { &hf_ecat_sub_lad[6],
2054 { "Log Addr", "ecat.sub7.lad",
2055 FT_UINT32, BASE_HEX, NULL, 0x0,
2056 NULL, HFILL }
2057 },
2058 { &hf_ecat_sub_lad[7],
2059 { "Log Addr", "ecat.sub8.lad",
2060 FT_UINT32, BASE_HEX, NULL, 0x0,
2061 NULL, HFILL }
2062 },
2063 { &hf_ecat_sub_lad[8],
2064 { "Log Addr", "ecat.sub9.lad",
2065 FT_UINT32, BASE_HEX, NULL, 0x0,
2066 NULL, HFILL }
2067 },
2068 { &hf_ecat_sub_lad[9],
2069 { "Log Addr", "ecat.sub10.lad",
2070 FT_UINT32, BASE_HEX, NULL, 0x0,
2071 NULL, HFILL }
2072 },
2073 #if 0
2074 { &hf_ecat_len,
2075 { "Length", "ecat.len",
2076 FT_UINT16, BASE_DEC, NULL, 0x0,
2077 NULL, HFILL }
2078 },
2079 #endif
2080 { &hf_ecat_int,
2081 { "Interrupt", "ecat.int",
2082 FT_UINT16, BASE_HEX, NULL, 0x0,
2083 NULL, HFILL }
2084 },
2085 { &hf_ecat_dc_diff_da,
2086 { "DC D-A", "ecat.dc.dif.da",
2087 FT_UINT32, BASE_DEC, NULL, 0x0,
2088 NULL, HFILL }
2089 },
2090 { &hf_ecat_dc_diff_bd,
2091 { "DC B-D", "ecat.dc.dif.bd",
2092 FT_UINT32, BASE_DEC, NULL, 0x0,
2093 NULL, HFILL }
2094 },
2095 { &hf_ecat_dc_diff_cb,
2096 { "DC C-B", "ecat.dc.dif.cb",
2097 FT_UINT32, BASE_DEC, NULL, 0x0,
2098 NULL, HFILL }
2099 },
2100 { &hf_ecat_dc_diff_cd,
2101 { "DC C-D", "ecat.dc.dif.cd",
2102 FT_UINT32, BASE_DEC, NULL, 0x0,
2103 NULL, HFILL }
2104 },
2105 { &hf_ecat_dc_diff_ba,
2106 { "DC B-A", "ecat.dc.dif.ba",
2107 FT_UINT32, BASE_DEC, NULL, 0x0,
2108 NULL, HFILL }
2109 },
2110 { &hf_ecat_dc_diff_ca,
2111 { "DC C-A", "ecat.dc.dif.ca",
2112 FT_UINT32, BASE_DEC, NULL, 0x0,
2113 NULL, HFILL }
2114 },
2115 { &hf_ecat_sub_dc_diff_da[0],
2116 { "DC D-A", "ecat.sub1.dc.dif.da",
2117 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL }
2118 },
2119 { &hf_ecat_sub_dc_diff_da[1],
2120 { "DC D-A", "ecat.sub2.dc.dif.da",
2121 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL }
2122 },
2123 { &hf_ecat_sub_dc_diff_da[2],
2124 { "DC D-A", "ecat.sub3.dc.dif.da",
2125 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL }
2126 },
2127 { &hf_ecat_sub_dc_diff_da[3],
2128 { "DC D-A", "ecat.sub4.dc.dif.da",
2129 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL }
2130 },
2131 { &hf_ecat_sub_dc_diff_da[4],
2132 { "DC D-A", "ecat.sub5.dc.dif.da",
2133 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL }
2134 },
2135 { &hf_ecat_sub_dc_diff_da[5],
2136 { "DC D-A", "ecat.sub6.dc.dif.da",
2137 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL }
2138 },
2139 { &hf_ecat_sub_dc_diff_da[6],
2140 { "DC D-A", "ecat.sub7.dc.dif.da",
2141 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL }
2142 },
2143 { &hf_ecat_sub_dc_diff_da[7],
2144 { "DC D-A", "ecat.sub8.dc.dif.da",
2145 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL }
2146 },
2147 { &hf_ecat_sub_dc_diff_da[8],
2148 { "DC D-A", "ecat.sub9.dc.dif.da",
2149 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL }
2150 },
2151 { &hf_ecat_sub_dc_diff_da[9],
2152 { "DC D-A", "ecat.sub10.dc.dif.da",
2153 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL }
2154 },
2155
2156 { &hf_ecat_sub_dc_diff_bd[0],
2157 { "DC B-C", "ecat.sub1.dc.dif.bd",
2158 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL }
2159 },
2160 { &hf_ecat_sub_dc_diff_bd[1],
2161 { "DC B-C", "ecat.sub2.dc.dif.bd",
2162 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL }
2163 },
2164 { &hf_ecat_sub_dc_diff_bd[2],
2165 { "DC B-C", "ecat.sub3.dc.dif.bd",
2166 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL }
2167 },
2168 { &hf_ecat_sub_dc_diff_bd[3],
2169 { "DC B-C", "ecat.sub4.dc.dif.bd",
2170 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL }
2171 },
2172 { &hf_ecat_sub_dc_diff_bd[4],
2173 { "DC B-C", "ecat.sub5.dc.dif.bd",
2174 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL }
2175 },
2176 { &hf_ecat_sub_dc_diff_bd[5],
2177 { "DC B-C", "ecat.sub6.dc.dif.bd",
2178 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL }
2179 },
2180 { &hf_ecat_sub_dc_diff_bd[6],
2181 { "DC B-C", "ecat.sub7.dc.dif.bd",
2182 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL }
2183 },
2184 { &hf_ecat_sub_dc_diff_bd[7],
2185 { "DC B-C", "ecat.sub8.dc.dif.bd",
2186 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL }
2187 },
2188 { &hf_ecat_sub_dc_diff_bd[8],
2189 { "DC B-C", "ecat.sub9.dc.dif.bd",
2190 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL }
2191 },
2192 { &hf_ecat_sub_dc_diff_bd[9],
2193 { "DC B-D", "ecat.sub10.dc.dif.bd",
2194 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL }
2195 },
2196
2197 { &hf_ecat_sub_dc_diff_cb[0],
2198 { "DC C-B", "ecat.sub1.dc.dif.cb",
2199 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL }
2200 },
2201 { &hf_ecat_sub_dc_diff_cb[1],
2202 { "DC C-B", "ecat.sub2.dc.dif.cb",
2203 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL }
2204 },
2205 { &hf_ecat_sub_dc_diff_cb[2],
2206 { "DC C-B", "ecat.sub3.dc.dif.cb",
2207 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL }
2208 },
2209 { &hf_ecat_sub_dc_diff_cb[3],
2210 { "DC C-B", "ecat.sub4.dc.dif.cb",
2211 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL }
2212 },
2213 { &hf_ecat_sub_dc_diff_cb[4],
2214 { "DC C-B", "ecat.sub5.dc.dif.cb",
2215 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL }
2216 },
2217 { &hf_ecat_sub_dc_diff_cb[5],
2218 { "DC C-B", "ecat.sub6.dc.dif.cb",
2219 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL }
2220 },
2221 { &hf_ecat_sub_dc_diff_cb[6],
2222 { "DC C-B", "ecat.sub7.dc.dif.cb",
2223 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL }
2224 },
2225 { &hf_ecat_sub_dc_diff_cb[7],
2226 { "DC C-B", "ecat.sub8.dc.dif.cb",
2227 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL }
2228 },
2229 { &hf_ecat_sub_dc_diff_cb[8],
2230 { "DC C-B", "ecat.sub9.dc.dif.cb",
2231 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL }
2232 },
2233 { &hf_ecat_sub_dc_diff_cb[9],
2234 { "DC C-B", "ecat.sub10.dc.dif.cb",
2235 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL }
2236 },
2237
2238 { &hf_ecat_sub_dc_diff_cd[0],
2239 { "DC C-D", "ecat.sub1.dc.dif.cd",
2240 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL }
2241 },
2242 { &hf_ecat_sub_dc_diff_cd[1],
2243 { "DC C-D", "ecat.sub2.dc.dif.cd",
2244 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL }
2245 },
2246 { &hf_ecat_sub_dc_diff_cd[2],
2247 { "DC C-D", "ecat.sub3.dc.dif.cd",
2248 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL }
2249 },
2250 { &hf_ecat_sub_dc_diff_cd[3],
2251 { "DC C-D", "ecat.sub4.dc.dif.cd",
2252 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL }
2253 },
2254 { &hf_ecat_sub_dc_diff_cd[4],
2255 { "DC C-D", "ecat.sub5.dc.dif.cd",
2256 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL }
2257 },
2258 { &hf_ecat_sub_dc_diff_cd[5],
2259 { "DC C-D", "ecat.sub6.dc.dif.cd",
2260 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL }
2261 },
2262 { &hf_ecat_sub_dc_diff_cd[6],
2263 { "DC C-D", "ecat.sub7.dc.dif.cd",
2264 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL }
2265 },
2266 { &hf_ecat_sub_dc_diff_cd[7],
2267 { "DC C-D", "ecat.sub8.dc.dif.cd",
2268 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL }
2269 },
2270 { &hf_ecat_sub_dc_diff_cd[8],
2271 { "DC C-D", "ecat.sub9.dc.dif.cd",
2272 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL }
2273 },
2274 { &hf_ecat_sub_dc_diff_cd[9],
2275 { "DC C-D", "ecat.sub10.dc.dif.cd",
2276 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL }
2277 },
2278
2279 { &hf_ecat_sub_dc_diff_ba[0],
2280 { "DC B-A", "ecat.sub1.dc.dif.ba",
2281 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL }
2282 },
2283 { &hf_ecat_sub_dc_diff_ba[1],
2284 { "DC B-A", "ecat.sub2.dc.dif.ba",
2285 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL }
2286 },
2287 { &hf_ecat_sub_dc_diff_ba[2],
2288 { "DC B-A", "ecat.sub3.dc.dif.ba",
2289 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL }
2290 },
2291 { &hf_ecat_sub_dc_diff_ba[3],
2292 { "DC B-A", "ecat.sub4.dc.dif.ba",
2293 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL }
2294 },
2295 { &hf_ecat_sub_dc_diff_ba[4],
2296 { "DC B-A", "ecat.sub5.dc.dif.ba",
2297 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL }
2298 },
2299 { &hf_ecat_sub_dc_diff_ba[5],
2300 { "DC B-A", "ecat.sub6.dc.dif.ba",
2301 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL }
2302 },
2303 { &hf_ecat_sub_dc_diff_ba[6],
2304 { "DC B-A", "ecat.sub7.dc.dif.ba",
2305 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL }
2306 },
2307 { &hf_ecat_sub_dc_diff_ba[7],
2308 { "DC B-A", "ecat.sub8.dc.dif.ba",
2309 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL }
2310 },
2311 { &hf_ecat_sub_dc_diff_ba[8],
2312 { "DC B-A", "ecat.sub9.dc.dif.ba",
2313 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL }
2314 },
2315 { &hf_ecat_sub_dc_diff_ba[9],
2316 { "DC B-A", "ecat.sub10.dc.dif.ba",
2317 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL }
2318 },
2319
2320 { &hf_ecat_sub_dc_diff_ca[0],
2321 { "DC C-A", "ecat.sub1.dc.dif.ca",
2322 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL }
2323 },
2324 { &hf_ecat_sub_dc_diff_ca[1],
2325 { "DC C-A", "ecat.sub2.dc.dif.ca",
2326 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL }
2327 },
2328 { &hf_ecat_sub_dc_diff_ca[2],
2329 { "DC C-A", "ecat.sub3.dc.dif.ca",
2330 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL }
2331 },
2332 { &hf_ecat_sub_dc_diff_ca[3],
2333 { "DC C-A", "ecat.sub4.dc.dif.ca",
2334 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL }
2335 },
2336 { &hf_ecat_sub_dc_diff_ca[4],
2337 { "DC C-A", "ecat.sub5.dc.dif.ca",
2338 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL }
2339 },
2340 { &hf_ecat_sub_dc_diff_ca[5],
2341 { "DC C-A", "ecat.sub6.dc.dif.ca",
2342 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL }
2343 },
2344 { &hf_ecat_sub_dc_diff_ca[6],
2345 { "DC C-A", "ecat.sub7.dc.dif.ca",
2346 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL }
2347 },
2348 { &hf_ecat_sub_dc_diff_ca[7],
2349 { "DC C-A", "ecat.sub8.dc.dif.ca",
2350 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL }
2351 },
2352 { &hf_ecat_sub_dc_diff_ca[8],
2353 { "DC C-A", "ecat.sub9.dc.dif.ca",
2354 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL }
2355 },
2356 { &hf_ecat_sub_dc_diff_ca[9],
2357 { "DC C-A", "ecat.sub10.dc.dif.ca",
2358 FT_UINT32, BASE_DEC, NULL, 0x0, NULL, HFILL }
2359 },
2360 { &hf_ecat_length_len,
2361 { "Length", "ecat.subframe.length",
2362 FT_UINT16, BASE_DEC, NULL, 0x07ff, NULL, HFILL}
2363 },
2364 { &hf_ecat_length_r,
2365 { "Reserved", "ecat.subframe.reserved",
2366 FT_UINT16, BASE_DEC, VALS(ecat_subframe_reserved_vals), 0x3800, NULL, HFILL}
2367 },
2368 { &hf_ecat_length_c,
2369 { "Round trip", "ecat.subframe.circulating",
2370 FT_BOOLEAN, 16, TFS(&tfs_ecat_subframe_circulating_vals), 0x4000, NULL, HFILL}
2371 },
2372 { &hf_ecat_length_m,
2373 { "Last indicator", "ecat.subframe.more",
2374 FT_BOOLEAN, 16, TFS(&tfs_ecat_subframe_more_vals), 0x8000, NULL, HFILL}
2375 },
2376 { &hf_ecat_padding,
2377 { "Pad bytes", "ecat.subframe.pad_bytes",
2378 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL}
2379 },
2380
2381 /* Registers */
2382 { &hf_ecat_reg_revision,
2383 {"ESC Revision (0x0)", "ecat.reg.revision",
2384 FT_UINT8, BASE_HEX, NULL, 0, NULL, HFILL }
2385 },
2386 { &hf_ecat_reg_esc_type,
2387 {"ESC Type (0x1)", "ecat.reg.type",
2388 FT_UINT8, BASE_HEX, NULL, 0, NULL, HFILL }
2389 },
2390 { &hf_ecat_reg_esc_build,
2391 {"ESC Build (0x2)", "ecat.reg.build",
2392 FT_UINT16, BASE_HEX, NULL, 0, NULL, HFILL }
2393 },
2394 { &hf_ecat_reg_esc_fmmucnt,
2395 {"ESC FMMU Cnt (0x4)", "ecat.reg.fmmucnt",
2396 FT_UINT8, BASE_HEX, NULL, 0, NULL, HFILL }
2397 },
2398 { &hf_ecat_reg_esc_smcnt,
2399 {"ESC SM Cnt (0x5)", "ecat.reg.smcnt",
2400 FT_UINT8, BASE_HEX, NULL, 0, NULL, HFILL }
2401 },
2402 { &hf_ecat_reg_esc_ports,
2403 {"ESC Ports (0x6)", "ecat.reg.ports",
2404 FT_UINT8, BASE_HEX, NULL, 0, NULL, HFILL }
2405 },
2406 { &hf_ecat_reg_esc_dpram,
2407 {"ESC DPRAM (0x7)", "ecat.reg.dpram",
2408 FT_UINT8, BASE_HEX, NULL, 0, NULL, HFILL }
2409 },
2410 { &hf_ecat_reg_esc_features,
2411 {"ESC Features (0x8)", "ecat.reg.features",
2412 FT_UINT16, BASE_HEX, NULL, 0, NULL, HFILL }
2413 },
2414 { &hf_ecat_reg_esc_features_fmmurestrict,
2415 {"FMMU bytewise restriction", "ecat.reg.features.fmmurestrict",
2416 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0001, NULL, HFILL }
2417 },
2418 { &hf_ecat_reg_esc_features_smaddrrestrict,
2419 {"SM addressing restriction", "ecat.reg.features.smaddrrestrict",
2420 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0002, NULL, HFILL }
2421 },
2422 { &hf_ecat_reg_esc_features_dcsupport,
2423 {"DC support", "ecat.reg.features.dcsupport",
2424 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0004, NULL, HFILL }
2425 },
2426 { &hf_ecat_reg_esc_features_dc64support,
2427 {"DC 64 bit support", "ecat.reg.features.dc64support",
2428 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0008, NULL, HFILL }
2429 },
2430 { &hf_ecat_reg_esc_features_ebuslowjitter,
2431 {"E-Bus low jitter", "ecat.reg.features.ebuslowjitter",
2432 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0010, NULL, HFILL }
2433 },
2434 { &hf_ecat_reg_esc_features_ebusextlinkdetect,
2435 {"E-Bus ext. link detection", "ecat.reg.features.ebusextlinkdetect",
2436 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0020, NULL, HFILL }
2437 },
2438 { &hf_ecat_reg_esc_features_miiextlinkdetect,
2439 {"MII ext. link detection", "ecat.reg.features.miiextlinkdetect",
2440 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0040, NULL, HFILL }
2441 },
2442 { &hf_ecat_reg_esc_features_crcext,
2443 {"CRC ext. detection", "ecat.reg.features.crcext",
2444 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0080, NULL, HFILL }
2445 },
2446 { &hf_ecat_reg_physaddr,
2447 {"Phys Addr (0x10)", "ecat.reg.physaddr",
2448 FT_UINT16, BASE_HEX, NULL, 0, NULL, HFILL }
2449 },
2450 { &hf_ecat_reg_physaddr2,
2451 {"Phys Addr 2nd (0x12)", "ecat.reg.physaddr2",
2452 FT_UINT16, BASE_HEX, NULL, 0, NULL, HFILL }
2453 },
2454 { &hf_ecat_reg_dlctrl1,
2455 {"ESC Ctrl (0x100)", "ecat.reg.dlctrl1",
2456 FT_UINT8, BASE_HEX, NULL, 0, NULL, HFILL }
2457 },
2458 { &hf_ecat_reg_dlctrl1_killnonecat,
2459 {"Kill non EtherCAT frames", "ecat.reg.dlctrl1.killnonecat",
2460 FT_BOOLEAN, 8, TFS(&tfs_local_true_false), 0x01, NULL, HFILL }
2461 },
2462 { &hf_ecat_reg_dlctrl1_port0extlinkdetect,
2463 {"Port 0 ext. link detection", "ecat.reg.dlctrl1.port0extlinkdetect",
2464 FT_BOOLEAN, 8, TFS(&tfs_local_disabled_enabled), 0x10, NULL, HFILL }
2465 },
2466 { &hf_ecat_reg_dlctrl1_port1extlinkdetect,
2467 {"Port 1 ext. link detection", "ecat.reg.dlctrl1.port1extlinkdetect",
2468 FT_BOOLEAN, 8, TFS(&tfs_local_disabled_enabled), 0x20, NULL, HFILL }
2469 },
2470 { &hf_ecat_reg_dlctrl1_port2extlinkdetect,
2471 {"Port 2 ext. link detection", "ecat.reg.dlctrl1.port2extlinkdetect",
2472 FT_BOOLEAN, 8, TFS(&tfs_local_disabled_enabled), 0x40, NULL, HFILL }
2473 },
2474 { &hf_ecat_reg_dlctrl1_port3extlinkdetect,
2475 {"Port 3 ext. link detection", "ecat.reg.dlctrl1.port3extlinkdetect",
2476 FT_BOOLEAN, 8, TFS(&tfs_local_disabled_enabled), 0x80, NULL, HFILL }
2477 },
2478 { &hf_ecat_reg_dlctrl2,
2479 {"ESC Ctrl (0x101)", "ecat.reg.dlcrtl2",
2480 FT_UINT8, BASE_HEX, NULL, 0, NULL, HFILL }
2481 },
2482 { &hf_ecat_reg_dlctrl2_port0,
2483 {"Port 0", "ecat.reg.dlcrtl2.port0",
2484 FT_UINT8, BASE_HEX, VALS(vals_esc_reg_101), 0x03, NULL, HFILL }
2485 },
2486 { &hf_ecat_reg_dlctrl2_port1,
2487 {"Port 1", "ecat.reg.dlcrtl2.port1",
2488 FT_UINT8, BASE_HEX, VALS(vals_esc_reg_101), 0x0C, NULL, HFILL }
2489 },
2490 { &hf_ecat_reg_dlctrl2_port2,
2491 {"Port 2", "ecat.reg.dlcrtl2.port2",
2492 FT_UINT8, BASE_HEX, VALS(vals_esc_reg_101), 0x30, NULL, HFILL }
2493 },
2494 { &hf_ecat_reg_dlctrl2_port3,
2495 {"Port 3", "ecat.reg.dlcrtl2.port3",
2496 FT_UINT8, BASE_HEX, VALS(vals_esc_reg_101), 0xC0, NULL, HFILL }
2497 },
2498 { &hf_ecat_reg_dlctrl3,
2499 {"ESC Ctrl (0x102)", "ecat.reg.dlctrl3",
2500 FT_UINT8, BASE_HEX, NULL, 0, NULL, HFILL }
2501 },
2502 { &hf_ecat_reg_dlctrl3_fifosize,
2503 {"Fifo size", "ecat.reg.dlctrl3.fifosize",
2504 FT_UINT8, BASE_HEX, NULL, 0x07, NULL, HFILL }
2505 },
2506 { &hf_ecat_reg_dlctrl3_lowebusjit,
2507 {"Low E-Bus jitter", "ecat.reg.dlctrl3.lowebusjit",
2508 FT_BOOLEAN, 8, TFS(&tfs_local_disabled_enabled), 0x08, NULL, HFILL }
2509 },
2510 { &hf_ecat_reg_dlctrl4,
2511 {"ESC Ctrl (0x103)", "ecat.reg.dlctrl4",
2512 FT_UINT8, BASE_HEX, NULL, 0, NULL, HFILL }
2513 },
2514 { &hf_ecat_reg_dlctrl4_2ndaddress,
2515 {"Second address", "ecat.reg.dlctrl4.2ndaddress",
2516 FT_BOOLEAN, 8, TFS(&tfs_local_disabled_enabled), 0x01, NULL, HFILL }
2517 },
2518 { &hf_ecat_reg_dlstatus1,
2519 {"ESC Status (0x110)", "ecat.reg.dlstatus1",
2520 FT_UINT8, BASE_HEX, NULL, 0, NULL, HFILL }
2521 },
2522 { &hf_ecat_reg_dlstatus1_operation,
2523 {"Operation", "ecat.reg.dlstatus1.operation",
2524 FT_BOOLEAN, 8, TFS(&tfs_local_true_false), 0x01, NULL, HFILL }
2525 },
2526 { &hf_ecat_reg_dlstatus1_pdiwatchdog,
2527 {"PDI watchdog", "ecat.reg.dlstatus1.pdiwatchdog",
2528 FT_BOOLEAN, 8, TFS(&tfs_esc_reg_watchdog), 0x02, NULL, HFILL }
2529 },
2530 { &hf_ecat_reg_dlstatus1_enhlinkdetect,
2531 {"Enh. Link Detection", "ecat.reg.dlstatus1.enhlinkdetect",
2532 FT_BOOLEAN, 8, TFS(&tfs_local_disabled_enabled), 0x04, NULL, HFILL }
2533 },
2534 { &hf_ecat_reg_dlstatus1_physlink_port0,
2535 {"Physical link Port 0", "ecat.reg.dlstatus1.physlink.port0",
2536 FT_BOOLEAN, 8, TFS(&tfs_local_true_false), 0x10, NULL, HFILL }
2537 },
2538 { &hf_ecat_reg_dlstatus1_physlink_port1,
2539 {"Physical link Port 1", "ecat.reg.dlstatus1.physlink.port1",
2540 FT_BOOLEAN, 8, TFS(&tfs_local_true_false), 0x20, NULL, HFILL }
2541 },
2542 { &hf_ecat_reg_dlstatus1_physlink_port2,
2543 {"Physical link Port 2", "ecat.reg.dlstatus1.physlink.port2",
2544 FT_BOOLEAN, 8, TFS(&tfs_local_true_false), 0x40, NULL, HFILL }
2545 },
2546 { &hf_ecat_reg_dlstatus1_physlink_port3,
2547 {"Physical link Port 3", "ecat.reg.dlstatus1.physlink.port3",
2548 FT_BOOLEAN, 8, TFS(&tfs_local_true_false), 0x80, NULL, HFILL }
2549 },
2550 { &hf_ecat_reg_dlstatus2,
2551 {"ESC Status (0x111)", "ecat.reg.dlstatus2",
2552 FT_UINT8, BASE_HEX, NULL, 0, NULL, HFILL }
2553 },
2554 { &hf_ecat_reg_dlstatus2_port0,
2555 {"Port 0", "ecat.reg.dlstatus2.port0",
2556 FT_UINT8, BASE_HEX, VALS(vals_esc_reg_111), 0x03, NULL, HFILL }
2557 },
2558 { &hf_ecat_reg_dlstatus2_port1,
2559 {"Port 1", "ecat.reg.dlstatus2.port1",
2560 FT_UINT8, BASE_HEX, VALS(vals_esc_reg_111), 0x0C, NULL, HFILL }
2561 },
2562 { &hf_ecat_reg_dlstatus2_port2,
2563 {"Port 2", "ecat.reg.dlstatus2.port2",
2564 FT_UINT8, BASE_HEX, VALS(vals_esc_reg_111), 0x30, NULL, HFILL }
2565 },
2566 { &hf_ecat_reg_dlstatus2_port3,
2567 {"Port 3", "ecat.reg.dlstatus2.port3",
2568 FT_UINT8, BASE_HEX, VALS(vals_esc_reg_111), 0xC0, NULL, HFILL }
2569 },
2570 { &hf_ecat_reg_regprotect,
2571 {"Write Register Protect (0x20)", "ecat.reg.regprotect",
2572 FT_UINT16, BASE_HEX, NULL, 0, NULL, HFILL }
2573 },
2574 { &hf_ecat_reg_accessprotect,
2575 {"Access Protect (0x30)", "ecat.reg.accessprotect",
2576 FT_UINT16, BASE_HEX, NULL, 0, NULL, HFILL }
2577 },
2578 { &hf_ecat_reg_resetecat,
2579 {"ESC reset Ecat (0x40)", "ecat.reg.resetecat",
2580 FT_UINT8, BASE_HEX, NULL, 0, NULL, HFILL }
2581 },
2582 { &hf_ecat_reg_resetpdi,
2583 {"ESC reset Pdi (0x41)", "ecat.reg.resetpdi",
2584 FT_UINT8, BASE_HEX, NULL, 0, NULL, HFILL }
2585 },
2586 { &hf_ecat_reg_regphysrwoffs,
2587 {"Phys. RW Offset (0x108)", "ecat.regphysrwoffs",
2588 FT_UINT16, BASE_HEX, NULL, 0, NULL, HFILL }
2589 },
2590 { &hf_ecat_reg_alctrl,
2591 {"AL Ctrl (0x120)", "ecat.reg.alctrl",
2592 FT_UINT16, BASE_HEX, NULL, 0, NULL, HFILL }
2593 },
2594 { &hf_ecat_reg_alctrl_ctrl,
2595 {"Al Ctrl", "ecat.reg.alctrl.ctrl",
2596 FT_UINT16, BASE_HEX, VALS(vals_esc_reg_120), 0x0f, NULL, HFILL }
2597 },
2598 { &hf_ecat_reg_alctrl_errack,
2599 {"Error Ack", "ecat.reg.alctrl.errack",
2600 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0010, NULL, HFILL }
2601 },
2602 { &hf_ecat_reg_alctrl_id,
2603 {"Id", "ecat.reg.alctrl.id",
2604 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0020, NULL, HFILL }
2605 },
2606 { &hf_ecat_reg_alstatus,
2607 {"AL Status (0x130)", "ecat.reg.alstatus",
2608 FT_UINT16, BASE_HEX, NULL, 0, NULL, HFILL }
2609 },
2610 { &hf_ecat_reg_alstatus_status,
2611 {"Al Status", "ecat.reg.alstatus.status",
2612 FT_UINT16, BASE_HEX, VALS(vals_esc_reg_120), 0x000f, NULL, HFILL }
2613 },
2614 { &hf_ecat_reg_alstatus_err,
2615 {"Error", "ecat.reg.alstatus.err",
2616 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0010, NULL, HFILL }
2617 },
2618 { &hf_ecat_reg_alstatus_id,
2619 {"Id", "ecat.reg.alstatus.id",
2620 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0020, NULL, HFILL }
2621 },
2622 { &hf_ecat_reg_alstatuscode,
2623 {"AL Status Code (0x134)", "ecat.reg.alstatuscode",
2624 FT_UINT16, BASE_HEX, NULL, 0, NULL, HFILL }
2625 },
2626 { &hf_ecat_reg_pdictrl1,
2627 {"PDI Ctrl (0x140)", "ecat.reg.pdictrl1",
2628 FT_UINT8, BASE_HEX, NULL, 0, NULL, HFILL }
2629 },
2630 { &hf_ecat_reg_pdictrl1_pdi,
2631 {"PDI", "ecat.reg.pdictrl1.pdi",
2632 FT_UINT8, BASE_HEX, VALS(vals_esc_reg_140), 0xff, NULL, HFILL }
2633 },
2634 { &hf_ecat_reg_pdictrl2,
2635 {"PDI Ctrl (0x141)", "ecat.reg.pdictrl2",
2636 FT_UINT8, BASE_HEX, NULL, 0, NULL, HFILL }
2637 },
2638 { &hf_ecat_reg_pdictrl2_devemul,
2639 {"Device emulation", "ecat.reg.pdictrl2.devemul",
2640 FT_BOOLEAN, 8, TFS(&tfs_local_true_false), 0x01, NULL, HFILL }
2641 },
2642 { &hf_ecat_reg_pdictrl2_enhlnkdetect,
2643 {"Enhanced link detection", "ecat.reg.pdictrl2.enhlnkdetect",
2644 FT_BOOLEAN, 8, TFS(&tfs_local_disable_enable), 0x02, NULL, HFILL }
2645 },
2646 { &hf_ecat_reg_pdictrl2_dcsyncout,
2647 {"Enable DC sync out", "ecat.reg.pdictrl2.dcsyncout",
2648 FT_BOOLEAN, 8, TFS(&tfs_local_disable_enable), 0x04, NULL, HFILL }
2649 },
2650 { &hf_ecat_reg_pdictrl2_dcsyncin,
2651 {"Enable DC latch in", "ecat.reg.pdictrl2.dcsyncin",
2652 FT_BOOLEAN, 8, TFS(&tfs_local_disable_enable), 0x08, NULL, HFILL }
2653 },
2654 { &hf_ecat_reg_pdictrl2_enhlnkdetect0,
2655 {"Enhanced link detection port 0", "ecat.reg.pdictrl2.enhlnkdetect0",
2656 FT_BOOLEAN, 8, TFS(&tfs_local_disable_enable), 0x10, NULL, HFILL }
2657 },
2658 { &hf_ecat_reg_pdictrl2_enhlnkdetect1,
2659 {"Enhanced link detection port 1", "ecat.reg.pdictrl2.enhlnkdetect1",
2660 FT_BOOLEAN, 8, TFS(&tfs_local_disable_enable), 0x20, NULL, HFILL }
2661 },
2662 { &hf_ecat_reg_pdictrl2_enhlnkdetect2,
2663 {"Enhanced link detection port 2", "ecat.reg.pdictrl2.enhlnkdetect2",
2664 FT_BOOLEAN, 8, TFS(&tfs_local_disable_enable), 0x40, NULL, HFILL }
2665 },
2666 { &hf_ecat_reg_pdictrl2_enhlnkdetect3,
2667 {"Enhanced link detection port 3", "ecat.reg.pdictrl2.enhlnkdetect3",
2668 FT_BOOLEAN, 8, TFS(&tfs_local_disable_enable), 0x80, NULL, HFILL }
2669 },
2670 { &hf_ecat_reg_ecat_mask,
2671 {"ECAT IRQ Mask (0x200)", "ecat.reg.irqmask.ecat_mask",
2672 FT_UINT16, BASE_HEX, NULL, 0, NULL, HFILL }
2673 },
2674 { &hf_ecat_reg_ecat_mask_latchevt,
2675 {"Latch event", "ecat.reg.irqmask.ecat_mask.latchevt",
2676 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0001, NULL, HFILL }
2677 },
2678 { &hf_ecat_reg_ecat_mask_escstatevt,
2679 {"ESC Status event", "ecat.reg.irqmask.ecat_mask.escstatevt",
2680 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0004, NULL, HFILL }
2681 },
2682 { &hf_ecat_reg_ecat_mask_alstatevt,
2683 {"AL Status event", "ecat.reg.irqmask.ecat_mask.alstatevt",
2684 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0008, NULL, HFILL }
2685 },
2686 { &hf_ecat_reg_ecat_mask_sm0irq,
2687 {"SM 0 IRQ", "ecat.reg.irqmask.ecat_mask.sm0irq",
2688 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0100, NULL, HFILL }
2689 },
2690 { &hf_ecat_reg_ecat_mask_sm1irq,
2691 {"SM 1 IRQ", "ecat.reg.irqmask.ecat_mask.sm1irq",
2692 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0200, NULL, HFILL }
2693 },
2694 { &hf_ecat_reg_ecat_mask_sm2irq,
2695 {"SM 2 IRQ", "ecat.reg.irqmask.ecat_mask.sm2irq",
2696 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0400, NULL, HFILL }
2697 },
2698 { &hf_ecat_reg_ecat_mask_sm3irq,
2699 {"SM 3 IRQ", "ecat.reg.irqmask.ecat_mask.sm3irq",
2700 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0800, NULL, HFILL }
2701 },
2702 { &hf_ecat_reg_ecat_mask_sm4irq,
2703 {"SM 4 IRQ", "ecat.reg.irqmask.ecat_mask.sm4irq",
2704 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x1000, NULL, HFILL }
2705 },
2706 { &hf_ecat_reg_ecat_mask_sm5irq,
2707 {"SM 5 IRQ", "ecat.reg.irqmask.ecat_mask.sm5irq",
2708 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x2000, NULL, HFILL }
2709 },
2710 { &hf_ecat_reg_ecat_mask_sm6irq,
2711 {"SM 6 IRQ", "ecat.reg.irqmask.ecat_mask.sm6irq",
2712 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x4000, NULL, HFILL }
2713 },
2714 { &hf_ecat_reg_ecat_mask_sm7irq,
2715 {"SM 7 IRQ", "ecat.reg.irqmask.ecat_mask.sm7irq",
2716 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x8000, NULL, HFILL }
2717 },
2718 { &hf_ecat_reg_pdiL,
2719 {"PDI IRQ Mask L (0x204)", "ecat.reg.irqmask.pdiL",
2720 FT_UINT16, BASE_HEX, NULL, 0, NULL, HFILL }
2721 },
2722 { &hf_ecat_reg_pdiL_alctrl,
2723 {"AL Ctrl", "ecat.reg.irqmask.pdiL.alctrl",
2724 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x1, NULL, HFILL }
2725 },
2726 { &hf_ecat_reg_pdiL_latchin,
2727 {"Latch input", "ecat.reg.irqmask.pdiL.latchin",
2728 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0002, NULL, HFILL }
2729 },
2730 { &hf_ecat_reg_pdiL_sync0,
2731 {"SYNC 0", "ecat.reg.irqmask.pdiL.sync0",
2732 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0004, NULL, HFILL }
2733 },
2734 { &hf_ecat_reg_pdiL_sync1,
2735 {"SYNC 1", "ecat.reg.irqmask.pdiL.sync1",
2736 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0008, NULL, HFILL }
2737 },
2738 { &hf_ecat_reg_pdiL_smchg,
2739 {"SM changed", "ecat.reg.irqmask.pdiL.smchg",
2740 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0010, NULL, HFILL }
2741 },
2742 { &hf_ecat_reg_pdiL_eepromcmdpen,
2743 {"EEPROM command pending", "ecat.reg.irqmask.pdiL.eepromcmdpen",
2744 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0020, NULL, HFILL }
2745 },
2746 { &hf_ecat_reg_pdiL_sm0,
2747 {"SM 0", "ecat.reg.irqmask.pdiL.sm0",
2748 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0100, NULL, HFILL }
2749 },
2750 { &hf_ecat_reg_pdiL_sm1,
2751 {"SM 1", "ecat.reg.irqmask.pdiL.sm1",
2752 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0200, NULL, HFILL }
2753 },
2754 { &hf_ecat_reg_pdiL_sm2,
2755 {"SM 2", "ecat.reg.irqmask.pdiL.sm2",
2756 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0400, NULL, HFILL }
2757 },
2758 { &hf_ecat_reg_pdiL_sm3,
2759 {"SM 3", "ecat.reg.irqmask.pdiL.sm3",
2760 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0800, NULL, HFILL }
2761 },
2762 { &hf_ecat_reg_pdiL_sm4,
2763 {"SM 4", "ecat.reg.irqmask.pdiL.sm4",
2764 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x1000, NULL, HFILL }
2765 },
2766 { &hf_ecat_reg_pdiL_sm5,
2767 {"SM 5", "ecat.reg.irqmask.pdiL.sm5",
2768 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x2000, NULL, HFILL }
2769 },
2770 { &hf_ecat_reg_pdiL_sm6,
2771 {"SM 6", "ecat.reg.irqmask.pdiL.sm6",
2772 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x4000, NULL, HFILL }
2773 },
2774 { &hf_ecat_reg_pdiL_sm7,
2775 {"SM 7", "ecat.reg.irqmask.pdiL.sm7",
2776 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x8000, NULL, HFILL }
2777 },
2778 { &hf_ecat_reg_pdiH,
2779 {"PDI IRQ Mask H (0x206)", "ecat.reg.irqmask.pdiH",
2780 FT_UINT16, BASE_HEX, NULL, 0, NULL, HFILL }
2781 },
2782 { &hf_ecat_reg_ecat,
2783 {"ECAT IRQ (0x210)", "ecat.reg.irq.ecat",
2784 FT_UINT16, BASE_HEX, NULL, 0, NULL, HFILL }
2785 },
2786 { &hf_ecat_reg_ecat_latchevt,
2787 {"Latch event", "ecat.reg.irq.ecat.latchevt",
2788 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0001, NULL, HFILL }
2789 },
2790 { &hf_ecat_reg_ecat_escstatevt,
2791 {"ESC Status event", "ecat.reg.irq.ecat.escstatevt",
2792 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0004, NULL, HFILL }
2793 },
2794 { &hf_ecat_reg_ecat_alstatevt,
2795 {"AL Status event", "ecat.reg.irq.ecat.alstatevt",
2796 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0008, NULL, HFILL }
2797 },
2798 { &hf_ecat_reg_ecat_sm0irq,
2799 {"SM 0 IRQ", "ecat.reg.irq.ecat.sm0irq",
2800 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0100, NULL, HFILL }
2801 },
2802 { &hf_ecat_reg_ecat_sm1irq,
2803 {"SM 1 IRQ", "ecat.reg.irq.ecat.sm1irq",
2804 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0200, NULL, HFILL }
2805 },
2806 { &hf_ecat_reg_ecat_sm2irq,
2807 {"SM 2 IRQ", "ecat.reg.irq.ecat.sm2irq",
2808 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0400, NULL, HFILL }
2809 },
2810 { &hf_ecat_reg_ecat_sm3irq,
2811 {"SM 3 IRQ", "ecat.reg.irq.ecat.sm3irq",
2812 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0800, NULL, HFILL }
2813 },
2814 { &hf_ecat_reg_ecat_sm4irq,
2815 {"SM 4 IRQ", "ecat.reg.irq.ecat.sm4irq",
2816 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x1000, NULL, HFILL }
2817 },
2818 { &hf_ecat_reg_ecat_sm5irq,
2819 {"SM 5 IRQ", "ecat.reg.irq.ecat.sm5irq",
2820 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x2000, NULL, HFILL }
2821 },
2822 { &hf_ecat_reg_ecat_sm6irq,
2823 {"SM 6 IRQ", "ecat.reg.irq.ecat.sm6irq",
2824 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x4000, NULL, HFILL }
2825 },
2826 { &hf_ecat_reg_ecat_sm7irq,
2827 {"SM 7 IRQ", "ecat.reg.irq.ecat.sm7irq",
2828 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x8000, NULL, HFILL }
2829 },
2830 { &hf_ecat_reg_pdi1,
2831 {"PDI IRQ 1 (0x220)", "ecat.reg.irq.pdi1",
2832 FT_UINT16, BASE_HEX, NULL, 0, NULL, HFILL }
2833 },
2834 { &hf_ecat_reg_pdi1_alctrl,
2835 {"AL Ctrl", "ecat.reg.irq.pdi1.alctrl",
2836 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0001, NULL, HFILL }
2837 },
2838 { &hf_ecat_reg_pdi1_latchin,
2839 {"Latch input", "ecat.reg.irq.pdi1.latchin",
2840 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0002, NULL, HFILL }
2841 },
2842 { &hf_ecat_reg_pdi1_sync0,
2843 {"SYNC 0", "ecat.reg.irq.pdi1.sync0",
2844 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0004, NULL, HFILL }
2845 },
2846 { &hf_ecat_reg_pdi1_sync1,
2847 {"SYNC 1", "ecat.reg.irq.pdi1.sync1",
2848 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0008, NULL, HFILL }
2849 },
2850 { &hf_ecat_reg_pdi1_smchg,
2851 {"SM changed", "ecat.reg.irq.pdi1.smchg",
2852 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0010, NULL, HFILL }
2853 },
2854 { &hf_ecat_reg_pdi1_eepromcmdpen,
2855 {"EEPROM command pending", "ecat.reg.irq.pdi1.eepromcmdpen",
2856 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0020, NULL, HFILL }
2857 },
2858 { &hf_ecat_reg_pdi1_sm0,
2859 {"SM 0", "ecat.reg.irq.pdi1.sm0",
2860 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0100, NULL, HFILL }
2861 },
2862 { &hf_ecat_reg_pdi1_sm1,
2863 {"SM 1", "ecat.reg.irq.pdi1.sm1",
2864 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0200, NULL, HFILL }
2865 },
2866 { &hf_ecat_reg_pdi1_sm2,
2867 {"SM 2", "ecat.reg.irq.pdi1.sm2",
2868 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0400, NULL, HFILL }
2869 },
2870 { &hf_ecat_reg_pdi1_sm3,
2871 {"SM 3", "ecat.reg.irq.pdi1.sm3",
2872 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0800, NULL, HFILL }
2873 },
2874 { &hf_ecat_reg_pdi1_sm4,
2875 {"SM 4", "ecat.reg.irq.pdi1.sm4",
2876 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x1000, NULL, HFILL }
2877 },
2878 { &hf_ecat_reg_pdi1_sm5,
2879 {"SM 5", "ecat.reg.irq.pdi1.sm5",
2880 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x2000, NULL, HFILL }
2881 },
2882 { &hf_ecat_reg_pdi1_sm6,
2883 {"SM 6", "ecat.reg.irq.pdi1.sm6",
2884 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x4000, NULL, HFILL }
2885 },
2886 { &hf_ecat_reg_pdi1_sm7,
2887 {"SM 7", "ecat.reg.irq.pdi1.sm7",
2888 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x8000, NULL, HFILL }
2889 },
2890 { &hf_ecat_reg_pdi2,
2891 {"PDI IRQ 2 (0x222)", "ecat.reg.irq.pdi2",
2892 FT_UINT16, BASE_HEX, NULL, 0, NULL, HFILL }
2893 },
2894 { &hf_ecat_reg_crc0,
2895 {"CRC 0 (0x300)", "ecat.reg.crc0",
2896 FT_UINT16, BASE_HEX, NULL, 0, NULL, HFILL }
2897 },
2898 { &hf_ecat_reg_crc1,
2899 {"CRC 1 (0x302)", "ecat.reg.crc1",
2900 FT_UINT16, BASE_HEX, NULL, 0, NULL, HFILL }
2901 },
2902 { &hf_ecat_reg_crc2,
2903 {"CRC 2 (0x304)", "ecat.reg.crc2",
2904 FT_UINT16, BASE_HEX, NULL, 0, NULL, HFILL }
2905 },
2906 { &hf_ecat_reg_crc3,
2907 {"CRC 3 (0x306)", "ecat.reg.crc3",
2908 FT_UINT16, BASE_HEX, NULL, 0, NULL, HFILL }
2909 },
2910 { &hf_ecat_reg_crc0_frame,
2911 {"Invalid frame", "ecat.reg.crc0.frame",
2912 FT_UINT16, BASE_HEX, NULL, 0x00ff, NULL, HFILL }
2913 },
2914 { &hf_ecat_reg_crc0_rx,
2915 {"RX error", "ecat.reg.crc0.rx",
2916 FT_UINT16, BASE_HEX, NULL, 0xff00, NULL, HFILL }
2917 },
2918 { &hf_ecat_reg_crc1_frame,
2919 {"Invalid frame", "ecat.reg.crc1.frame",
2920 FT_UINT16, BASE_HEX, NULL, 0x00ff, NULL, HFILL }
2921 },
2922 { &hf_ecat_reg_crc1_rx,
2923 {"RX error", "ecat.reg.crc1.rx",
2924 FT_UINT16, BASE_HEX, NULL, 0xff00, NULL, HFILL }
2925 },
2926 { &hf_ecat_reg_crc2_frame,
2927 {"Invalid frame", "ecat.reg.crc2.frame",
2928 FT_UINT16, BASE_HEX, NULL, 0x00ff, NULL, HFILL }
2929 },
2930 { &hf_ecat_reg_crc2_rx,
2931 {"RX error", "ecat.reg.crc2.rx",
2932 FT_UINT16, BASE_HEX, NULL, 0xff00, NULL, HFILL }
2933 },
2934 { &hf_ecat_reg_crc3_frame,
2935 {"Invalid frame", "ecat.reg.crc3.frame",
2936 FT_UINT16, BASE_HEX, NULL, 0x00ff, NULL, HFILL }
2937 },
2938 { &hf_ecat_reg_crc3_rx,
2939 {"RX error", "ecat.reg.crc3.rx",
2940 FT_UINT16, BASE_HEX, NULL, 0xff00, NULL, HFILL }
2941 },
2942 { &hf_ecat_reg_crc_fwd0,
2943 {"Forw. CRC 0 (0x308)", "ecat.reg.crc.fwd0",
2944 FT_UINT8, BASE_HEX, NULL, 0, NULL, HFILL }
2945 },
2946 { &hf_ecat_reg_crc_fwd1,
2947 {"Forw. CRC 1 (0x309)", "ecat.reg.crc.fwd1",
2948 FT_UINT8, BASE_HEX, NULL, 0, NULL, HFILL }
2949 },
2950 { &hf_ecat_reg_crc_fwd2,
2951 {"Forw. CRC 2 (0x30A)", "ecat.reg.crc.fwd2",
2952 FT_UINT8, BASE_HEX, NULL, 0, NULL, HFILL }
2953 },
2954 { &hf_ecat_reg_crc_fwd3,
2955 {"Forw. CRC 3 (0x30B)", "ecat.reg.crc.fwd3",
2956 FT_UINT8, BASE_HEX, NULL, 0, NULL, HFILL }
2957 },
2958 { &hf_ecat_reg_processuniterr,
2959 {"Process unit error (0x30C)", "ecat.reg.processuniterr",
2960 FT_UINT8, BASE_HEX, NULL, 0, NULL, HFILL }
2961 },
2962 { &hf_ecat_reg_pdierr,
2963 {"PDI error (0x30D)", "ecat.reg.pdierr",
2964 FT_UINT8, BASE_HEX, NULL, 0, NULL, HFILL }
2965 },
2966 { &hf_ecat_reg_linklost0,
2967 {"Link Lost 0 (0x310)", "ecat.reg.linklost0",
2968 FT_UINT8, BASE_HEX, NULL, 0, NULL, HFILL }
2969 },
2970 { &hf_ecat_reg_linklost1,
2971 {"Link Lost 1 (0x311)", "ecat.reg.linklost1",
2972 FT_UINT8, BASE_HEX, NULL, 0, NULL, HFILL }
2973 },
2974 { &hf_ecat_reg_linklost2,
2975 {"Link Lost 2 (0x312)", "ecat.reg.linklost2",
2976 FT_UINT8, BASE_HEX, NULL, 0, NULL, HFILL }
2977 },
2978 { &hf_ecat_reg_linklost3,
2979 {"Link Lost 3 (0x313)", "ecat.reg.linklost3",
2980 FT_UINT8, BASE_HEX, NULL, 0, NULL, HFILL }
2981 },
2982 { &hf_ecat_reg_wd_divisor,
2983 {"WD Divisor (0x400)", "ecat.reg.wd.divisor",
2984 FT_UINT16, BASE_HEX, NULL, 0, NULL, HFILL }
2985 },
2986 { &hf_ecat_reg_wd_timepdi,
2987 {"WD Time PDI (0x410)", "ecat.reg.wd.timepdi",
2988 FT_UINT16, BASE_HEX, NULL, 0, NULL, HFILL }
2989 },
2990 { &hf_ecat_reg_wd_timesm,
2991 {"WD Time SM (0x420)", "ecat.reg.wd.timesm",
2992 FT_UINT16, BASE_HEX, NULL, 0, NULL, HFILL }
2993 },
2994 { &hf_ecat_reg_wd_status,
2995 {"WD Status (0x440)", "ecat.reg.wd.status",
2996 FT_UINT8, BASE_HEX, NULL, 0, NULL, HFILL }
2997 },
2998 { &hf_ecat_reg_wd_status_pdwatchdog,
2999 {"PD watchdog", "ecat.reg.wd.status.pdwatchdog",
3000 FT_BOOLEAN, 8, TFS(&tfs_esc_reg_watchdog), 0x1, NULL, HFILL }
3001 },
3002 { &hf_ecat_reg_wd_cntsm,
3003 {"WD SM Counter (0x442)", "ecat.reg.wd.cntsm",
3004 FT_UINT8, BASE_HEX, NULL, 0, NULL, HFILL }
3005 },
3006 { &hf_ecat_reg_wd_cntpdi,
3007 {"WD PDI Counter (0x443)", "ecat.reg.wd.cntpdi",
3008 FT_UINT8, BASE_HEX, NULL, 0, NULL, HFILL }
3009 },
3010 { &hf_ecat_reg_eeprom_assign,
3011 {"EEPROM Assign (0x500)", "ecat.reg.eeprom.assign",
3012 FT_UINT16, BASE_HEX, NULL, 0, NULL, HFILL }
3013 },
3014 { &hf_ecat_reg_eeprom_assign_ctrl,
3015 {"EEPROM access ctrl", "ecat.reg.eeprom.assign.ctrl",
3016 FT_BOOLEAN, 8, TFS(&tfs_esc_reg_500_0), 0x1, NULL, HFILL }
3017 },
3018 { &hf_ecat_reg_eeprom_assign_pdiaccess,
3019 {"Reset PDI access", "ecat.reg.eeprom.assign.pdiaccess",
3020 FT_BOOLEAN, 8, TFS(&tfs_esc_reg_500_1), 0x02, NULL, HFILL }
3021 },
3022 { &hf_ecat_reg_eeprom_assign_status,
3023 {"EEPROM access status", "ecat.reg.eeprom.assign.status",
3024 FT_BOOLEAN, 8, TFS(&tfs_esc_reg_500_0), 0x10, NULL, HFILL }
3025 },
3026 { &hf_ecat_reg_ctrlstat,
3027 {"EEPROM Ctrl/Status (0x502)", "ecat.reg.ctrlstat",
3028 FT_UINT16, BASE_HEX, NULL, 0, NULL, HFILL }
3029 },
3030 { &hf_ecat_reg_ctrlstat_wraccess,
3031 {"Write access", "ecat.reg.ctrlstat.wraccess",
3032 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0001, NULL, HFILL }
3033 },
3034 /* Next 4 bits reserved */
3035 { &hf_ecat_reg_ctrlstat_eepromemul,
3036 {"EEPROM emulation", "ecat.reg.ctrlstat.eepromemul",
3037 FT_BOOLEAN, 16, TFS(&tfs_esc_reg_502_5), 0x0020, NULL, HFILL }
3038 },
3039 { &hf_ecat_reg_ctrlstat_8bacc,
3040 {"8 byte access", "ecat.reg.ctrlstat.8bacc",
3041 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0040, NULL, HFILL }
3042 },
3043 { &hf_ecat_reg_ctrlstat_2bacc,
3044 {"2 byte address", "ecat.reg.ctrlstat.2bacc",
3045 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0080, NULL, HFILL }
3046 },
3047 { &hf_ecat_reg_ctrlstat_rdacc,
3048 {"Read access", "ecat.reg.ctrlstat.rdacc",
3049 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0100, NULL, HFILL }
3050 },
3051 { &hf_ecat_reg_ctrlstat_wracc,
3052 {"Write access", "ecat.reg.ctrlstat.wracc",
3053 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0200, NULL, HFILL }
3054 },
3055 { &hf_ecat_reg_ctrlstat_reloadacc,
3056 {"Reload access", "ecat.reg.ctrlstat.reloadacc",
3057 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0400, NULL, HFILL }
3058 },
3059 { &hf_ecat_reg_ctrlstat_crcerr,
3060 {"CRC error", "ecat.reg.ctrlstat.crcerr",
3061 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0800, NULL, HFILL }
3062 },
3063 { &hf_ecat_reg_ctrlstat_lderr,
3064 {"Load error", "ecat.reg.ctrlstat.lderr",
3065 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x1000, NULL, HFILL }
3066 },
3067 { &hf_ecat_reg_ctrlstat_cmderr,
3068 {"Cmd error", "ecat.reg.ctrlstat.cmderr",
3069 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x2000, NULL, HFILL }
3070 },
3071 { &hf_ecat_reg_ctrlstat_wrerr,
3072 {"Write error", "ecat.reg.ctrlstat.wrerr",
3073 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x4000, NULL, HFILL }
3074 },
3075 { &hf_ecat_reg_ctrlstat_busy,
3076 {"Busy", "ecat.reg.ctrlstat.busy",
3077 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x8000, NULL, HFILL }
3078 },
3079 { &hf_ecat_reg_addrl,
3080 {"EEPROM Address Lo (0x504)", "ecat.reg.addrl",
3081 FT_UINT16, BASE_HEX, NULL, 0, NULL, HFILL }
3082 },
3083 { &hf_ecat_reg_addrh,
3084 {"EEPROM Address Hi (0x506)", "ecat.reg.addrh",
3085 FT_UINT16, BASE_HEX, NULL, 0, NULL, HFILL }
3086 },
3087 { &hf_ecat_reg_data0,
3088 {"EEPROM Data 0 (0x508)", "ecat.reg.data0",
3089 FT_UINT16, BASE_HEX, NULL, 0, NULL, HFILL }
3090 },
3091 { &hf_ecat_reg_data1,
3092 {"EEPROM Data 1 (0x50A)", "ecat.reg.data1",
3093 FT_UINT16, BASE_HEX, NULL, 0, NULL, HFILL }
3094 },
3095 { &hf_ecat_reg_data2,
3096 {"EEPROM Data 2 (0x50c)", "ecat.reg.data2",
3097 FT_UINT16, BASE_HEX, NULL, 0, NULL, HFILL }
3098 },
3099 { &hf_ecat_reg_data3,
3100 {"EEPROM Data 3 (0x50e)", "ecat.reg.data3",
3101 FT_UINT16, BASE_HEX, NULL, 0, NULL, HFILL }
3102 },
3103
3104 { &hf_ecat_reg_mio_ctrlstat,
3105 {"Phy MIO Ctrl/Status (0x510)", "ecat.reg.mio.ctrlstat",
3106 FT_UINT16, BASE_HEX, NULL, 0, NULL, HFILL }
3107 },
3108 /* TODO: check these masks (ecat_esc_reg_510) against spec.
3109 * In particular hf_ecat_reg_mio_ctrlstat_offsphy is non-contiguous and overlaps wracc1 */
3110 { &hf_ecat_reg_mio_ctrlstat_wracc1,
3111 {"Write access", "ecat.reg.mio.ctrlstat.wracc1",
3112 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0001, NULL, HFILL }
3113 },
3114 { &hf_ecat_reg_mio_ctrlstat_offsphy,
3115 {"Offset Phy offset", "ecat.reg.mio.ctrlstat.offsphy",
3116 FT_UINT16, BASE_HEX, NULL, 0x008f, NULL, HFILL }
3117 },
3118 { &hf_ecat_reg_mio_ctrlstat_rdacc,
3119 {"Read access", "ecat.reg.mio.ctrlstat.rdacc",
3120 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0100, NULL, HFILL }
3121 },
3122 { &hf_ecat_reg_mio_ctrlstat_wracc2,
3123 {"Write access", "ecat.reg.mio.ctrlstat.wracc2",
3124 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0200, NULL, HFILL }
3125 },
3126 { &hf_ecat_reg_mio_ctrlstat_wrerr,
3127 {"Write error", "ecat.reg.mio.ctrlstat.wrerr",
3128 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x4000, NULL, HFILL }
3129 },
3130 { &hf_ecat_reg_mio_ctrlstat_busy,
3131 {"Busy", "ecat.reg.mio.ctrlstat.busy",
3132 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x8000, NULL, HFILL }
3133 },
3134
3135 { &hf_ecat_reg_mio_addr,
3136 {"Phy MIO Address (0x512)", "ecat.reg.mio.addr",
3137 FT_UINT16, BASE_HEX, NULL, 0, NULL, HFILL }
3138 },
3139 { &hf_ecat_reg_mio_addr_phyaddr,
3140 {"Phy address", "ecat.reg.mio.addr.phyaddr",
3141 FT_UINT16, BASE_HEX, NULL, 0x000F, NULL, HFILL }
3142 },
3143 { &hf_ecat_reg_mio_addr_mioaddr,
3144 {"MIO address", "ecat.reg.mio.addr.mioaddr",
3145 FT_UINT16, BASE_HEX, NULL, 0x0F00, NULL, HFILL }
3146 },
3147 { &hf_ecat_reg_mio_data,
3148 {"Phy MIO Data (0x514)", "ecat.reg.mio.data",
3149 FT_UINT16, BASE_HEX, NULL, 0, NULL, HFILL }
3150 },
3151 { &hf_ecat_reg_mio_access,
3152 {"MIO access (0x516)", "ecat.reg.mio.access",
3153 FT_UINT16, BASE_HEX, NULL, 0, NULL, HFILL }
3154 },
3155 { &hf_ecat_reg_mio_access_ecatacc,
3156 {"ECAT claims exclusive access", "ecat.reg.mio.access.ecatacc",
3157 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0001, NULL, HFILL }
3158 },
3159 { &hf_ecat_reg_mio_access_pdiacc,
3160 {"PDI has access to MII management", "ecat.reg.mio.access.pdiacc",
3161 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0100, NULL, HFILL }
3162 },
3163 { &hf_ecat_reg_mio_access_forcereset,
3164 {"Force PDI to reset 0517.0", "ecat.reg.mio.access.forcereset",
3165 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0200, NULL, HFILL }
3166 },
3167 { &hf_ecat_reg_mio_status0,
3168 {"MIO port status 0 (0x518)", "ecat.reg.mio.status0",
3169 FT_UINT8, BASE_HEX, NULL, 0, NULL, HFILL }
3170 },
3171 { &hf_ecat_reg_mio_status0_physlink,
3172 {"Physical link detected", "ecat.reg.mio.status0.physlink",
3173 FT_BOOLEAN, 8, TFS(&tfs_local_true_false), 0x01, NULL, HFILL }
3174 },
3175 { &hf_ecat_reg_mio_status0_link,
3176 {"Link detected", "ecat.reg.mio.status0.link",
3177 FT_BOOLEAN, 8, TFS(&tfs_local_true_false), 0x02, NULL, HFILL }
3178 },
3179 { &hf_ecat_reg_mio_status0_linkstatuserr,
3180 {"Link status error", "ecat.reg.mio.status0.linkstatuserr",
3181 FT_BOOLEAN, 8, TFS(&tfs_local_true_false), 0x04, NULL, HFILL }
3182 },
3183 { &hf_ecat_reg_mio_status0_readerr,
3184 {"Read error", "ecat.reg.mio.status0.readerr",
3185 FT_BOOLEAN, 8, TFS(&tfs_local_true_false), 0x08, NULL, HFILL }
3186 },
3187 { &hf_ecat_reg_mio_status0_linkpartnererr,
3188 {"Link partner error", "ecat.reg.mio.status0.linkpartnererr",
3189 FT_BOOLEAN, 8, TFS(&tfs_local_true_false), 0x10, NULL, HFILL }
3190 },
3191 { &hf_ecat_reg_mio_status0_phycfgupdated,
3192 {"Phy config updated", "ecat.reg.mio.status0.phycfgupdated",
3193 FT_BOOLEAN, 8, TFS(&tfs_local_true_false), 0x20, NULL, HFILL }
3194 },
3195 { &hf_ecat_reg_mio_status1,
3196 {"MIO port status 1 (0x519)", "ecat.reg.mio.status1",
3197 FT_UINT8, BASE_HEX, NULL, 0, NULL, HFILL }
3198 },
3199 { &hf_ecat_reg_mio_status1_physlink,
3200 {"Physical link detected", "ecat.reg.mio.status1.physlink",
3201 FT_BOOLEAN, 8, TFS(&tfs_local_true_false), 0x01, NULL, HFILL }
3202 },
3203 { &hf_ecat_reg_mio_status1_link,
3204 {"Link detected", "ecat.reg.mio.status1.link",
3205 FT_BOOLEAN, 8, TFS(&tfs_local_true_false), 0x02, NULL, HFILL }
3206 },
3207 { &hf_ecat_reg_mio_status1_linkstatuserr,
3208 {"Link status error", "ecat.reg.mio.status1.linkstatuserr",
3209 FT_BOOLEAN, 8, TFS(&tfs_local_true_false), 0x04, NULL, HFILL }
3210 },
3211 { &hf_ecat_reg_mio_status1_readerr,
3212 {"Read error", "ecat.reg.mio.status1.readerr",
3213 FT_BOOLEAN, 8, TFS(&tfs_local_true_false), 0x08, NULL, HFILL }
3214 },
3215 { &hf_ecat_reg_mio_status1_linkpartnererr,
3216 {"Link partner error", "ecat.reg.mio.status1.linkpartnererr",
3217 FT_BOOLEAN, 8, TFS(&tfs_local_true_false), 0x10, NULL, HFILL }
3218 },
3219 { &hf_ecat_reg_mio_status1_phycfgupdated,
3220 {"Phy config updated", "ecat.reg.mio.status1.phycfgupdated",
3221 FT_BOOLEAN, 8, TFS(&tfs_local_true_false), 0x20, NULL, HFILL }
3222 },
3223 { &hf_ecat_reg_mio_status2,
3224 {"MIO port status 2 (0x51A)", "ecat.reg.mio.status2",
3225 FT_UINT8, BASE_HEX, NULL, 0, NULL, HFILL }
3226 },
3227 { &hf_ecat_reg_mio_status2_physlink,
3228 {"Physical link detected", "ecat.reg.mio.status2.physlink",
3229 FT_BOOLEAN, 8, TFS(&tfs_local_true_false), 0x01, NULL, HFILL }
3230 },
3231 { &hf_ecat_reg_mio_status2_link,
3232 {"Link detected", "ecat.reg.mio.status2.link",
3233 FT_BOOLEAN, 8, TFS(&tfs_local_true_false), 0x02, NULL, HFILL }
3234 },
3235 { &hf_ecat_reg_mio_status2_linkstatuserr,
3236 {"Link status error", "ecat.reg.mio.status2.linkstatuserr",
3237 FT_BOOLEAN, 8, TFS(&tfs_local_true_false), 0x04, NULL, HFILL }
3238 },
3239 { &hf_ecat_reg_mio_status2_readerr,
3240 {"Read error", "ecat.reg.mio.status2.readerr",
3241 FT_BOOLEAN, 8, TFS(&tfs_local_true_false), 0x08, NULL, HFILL }
3242 },
3243 { &hf_ecat_reg_mio_status2_linkpartnererr,
3244 {"Link partner error", "ecat.reg.mio.status2.linkpartnererr",
3245 FT_BOOLEAN, 8, TFS(&tfs_local_true_false), 0x10, NULL, HFILL }
3246 },
3247 { &hf_ecat_reg_mio_status2_phycfgupdated,
3248 {"Phy config updated", "ecat.reg.mio.status2.phycfgupdated",
3249 FT_BOOLEAN, 8, TFS(&tfs_local_true_false), 0x20, NULL, HFILL }
3250 },
3251 { &hf_ecat_reg_mio_status3,
3252 {"MIO port status 3 (0x51B)", "ecat.reg.mio.status3",
3253 FT_UINT8, BASE_HEX, NULL, 0, NULL, HFILL }
3254 },
3255 { &hf_ecat_reg_mio_status3_physlink,
3256 {"Physical link detected", "ecat.reg.mio.status3.physlink",
3257 FT_BOOLEAN, 8, TFS(&tfs_local_true_false), 0x01, NULL, HFILL }
3258 },
3259 { &hf_ecat_reg_mio_status3_link,
3260 {"Link detected", "ecat.reg.mio.status3.link",
3261 FT_BOOLEAN, 8, TFS(&tfs_local_true_false), 0x02, NULL, HFILL }
3262 },
3263 { &hf_ecat_reg_mio_status3_linkstatuserr,
3264 {"Link status error", "ecat.reg.mio.status3.linkstatuserr",
3265 FT_BOOLEAN, 8, TFS(&tfs_local_true_false), 0x04, NULL, HFILL }
3266 },
3267 { &hf_ecat_reg_mio_status3_readerr,
3268 {"Read error", "ecat.reg.mio.status3.readerr",
3269 FT_BOOLEAN, 8, TFS(&tfs_local_true_false), 0x08, NULL, HFILL }
3270 },
3271 { &hf_ecat_reg_mio_status3_linkpartnererr,
3272 {"Link partner error", "ecat.reg.mio.status3.linkpartnererr",
3273 FT_BOOLEAN, 8, TFS(&tfs_local_true_false), 0x10, NULL, HFILL }
3274 },
3275 { &hf_ecat_reg_mio_status3_phycfgupdated,
3276 {"Phy config updated", "ecat.reg.mio.status3.phycfgupdated",
3277 FT_BOOLEAN, 8, TFS(&tfs_local_true_false), 0x20, NULL, HFILL }
3278 },
3279 { &hf_ecat_reg_fmmu,
3280 {"FMMU", "ecat.fmmu",
3281 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL }
3282 },
3283 { &hf_ecat_reg_fmmu_lstart,
3284 { "Log Start", "ecat.fmmu.lstart",
3285 FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL }
3286 },
3287 { &hf_ecat_reg_fmmu_llen,
3288 { "Log Length", "ecat.fmmu.llen",
3289 FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL }
3290 },
3291 { &hf_ecat_reg_fmmu_lstartbit,
3292 { "Log StartBit", "ecat.fmmu.lstartbit",
3293 FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL }
3294 },
3295 { &hf_ecat_reg_fmmu_lendbit,
3296 { "Log EndBit", "ecat.fmmu.lendbit",
3297 FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL }
3298 },
3299 { &hf_ecat_reg_fmmu_pstart,
3300 { "Phys Start", "ecat.fmmu.pstart",
3301 FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL }
3302 },
3303 { &hf_ecat_reg_fmmu_pstartbit,
3304 { "Phys StartBit", "ecat.fmmu.pstartbit",
3305 FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL }
3306 },
3307 { &hf_ecat_reg_fmmu_type,
3308 { "Type", "ecat.fmmu.type",
3309 FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL }
3310 },
3311 { &hf_ecat_reg_fmmu_typeread,
3312 { "Type", "ecat.fmmu.typeread",
3313 FT_BOOLEAN, 8, TFS(&tfs_ecat_fmmu_typeread), 0x01, NULL, HFILL }
3314 },
3315 { &hf_ecat_reg_fmmu_typewrite,
3316 { "Type", "ecat.fmmu.typewrite",
3317 FT_BOOLEAN, 8, TFS(&tfs_ecat_fmmu_typewrite), 0x02, NULL, HFILL }
3318 },
3319 { &hf_ecat_reg_fmmu_activate,
3320 { "Activate", "ecat.fmmu.activate",
3321 FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL }
3322 },
3323 { &hf_ecat_reg_fmmu_activate0,
3324 { "FMMU", "ecat.fmmu.activate0",
3325 FT_BOOLEAN, 8, TFS(&tfs_ecat_fmmu_activate), 0x01, NULL, HFILL }
3326 },
3327 { &hf_ecat_reg_syncman,
3328 {"SyncManager", "ecat.syncman",
3329 FT_BYTES, BASE_NONE, NULL, 0x0, NULL, HFILL }
3330 },
3331 { &hf_ecat_reg_syncman_start,
3332 {"SM Start", "ecat.syncman.start",
3333 FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL }
3334 },
3335 { &hf_ecat_reg_syncman_len,
3336 {"SM Length", "ecat.syncman.len",
3337 FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL }
3338 },
3339 { &hf_ecat_reg_syncman_ctrlstatus,
3340 {"SM Ctrl/Status", "ecat.syncman.ctrlstatus",
3341 FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL }
3342 },
3343 { &hf_ecat_reg_syncman_pmode,
3344 {"OpMode", "ecat.syncman.opmode",
3345 FT_UINT16, BASE_HEX, VALS(vals_esc_reg_8041), 0x0003, NULL, HFILL }
3346 },
3347 { &hf_ecat_reg_syncman_access,
3348 {"Access", "ecat.syncman.access",
3349 FT_UINT16, BASE_HEX, VALS(vals_esc_reg_8042), 0x000c, NULL, HFILL }
3350 },
3351 { &hf_ecat_reg_syncman_irq_ecat,
3352 {"ECAT IRQ", "ecat.syncman.irq.ecat",
3353 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0010, NULL, HFILL }
3354 },
3355 { &hf_ecat_reg_syncman_irq_pdi,
3356 {"PDI IRQ", "ecat.syncman.irq.pdi",
3357 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0020, NULL, HFILL }
3358 },
3359 { &hf_ecat_reg_syncman_wdt,
3360 {"Watchdog trigger", "ecat.syncman.wdt",
3361 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0040, NULL, HFILL }
3362 },
3363 { &hf_ecat_reg_syncman_irq_write,
3364 {"IRQ write", "ecat.syncman.irq.write",
3365 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0100, NULL, HFILL }
3366 },
3367 { &hf_ecat_reg_syncman_irq_read,
3368 {"IRQ read", "ecat.syncman.irq.read",
3369 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0200, NULL, HFILL }
3370 },
3371 { &hf_ecat_reg_syncman_1bufstate,
3372 {"1 buffer state", "ecat.syncman.1bufstate",
3373 FT_BOOLEAN, 16, TFS(&tfs_esc_reg_8051), 0x0800, NULL, HFILL }
3374 },
3375 { &hf_ecat_reg_syncman_3bufstate,
3376 {"3 buffer state", "ecat.syncman.3bufstate",
3377 FT_UINT16, BASE_HEX, VALS(vals_esc_reg_8052), 0x3000, NULL, HFILL }
3378 },
3379 { &hf_ecat_reg_syncman_sm_enable,
3380 {"SM Enable", "ecat.syncman.smenable",
3381 FT_UINT16, BASE_HEX, NULL, 0x0, NULL, HFILL }
3382 },
3383 { &hf_ecat_reg_syncman_enable,
3384 {"Enable", "ecat.syncman.enable",
3385 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0001, NULL, HFILL }
3386 },
3387 { &hf_ecat_reg_syncman_repeatreq,
3388 {"Repeat request", "ecat.syncman.repeatreq",
3389 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0002, NULL, HFILL }
3390 },
3391 { &hf_ecat_reg_syncman_latchsmchg_ecat,
3392 {"Latch SyncMan Change ECAT", "ecat.syncman.latchsmchg.ecat",
3393 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0040, NULL, HFILL }
3394 },
3395 { &hf_ecat_reg_syncman_latchsmchg_pdi,
3396 {"Latch SyncMan Change PDI", "ecat.syncman.latchsmchg.pdi",
3397 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0080, NULL, HFILL }
3398 },
3399 { &hf_ecat_reg_syncman_deactivate,
3400 {"Deactivate", "ecat.syncman.deactivate",
3401 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0100, NULL, HFILL }
3402 },
3403 { &hf_ecat_reg_syncman_repeatack,
3404 {"Repeat acknowledge", "ecat.syncman.repeatack",
3405 FT_BOOLEAN, 16, TFS(&tfs_local_true_false), 0x0200, NULL, HFILL }
3406 },
3407 { &hf_ecat_reg_dc_recv0,
3408 {"DC RecvTime_0 (0x900)", "ecat.reg.dc.recv0",
3409 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL }
3410 },
3411 { &hf_ecat_reg_dc_recv1,
3412 {"DC RecvTime_1 (0x904)", "ecat.reg.dc.recv1",
3413 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL }
3414 },
3415 { &hf_ecat_reg_dc_recv2,
3416 {"DC RecvTime_2 (0x908)", "ecat.reg.dc.recv2",
3417 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL }
3418 },
3419 { &hf_ecat_reg_dc_recv3,
3420 {"DC RecvTime_3 (0x90c)", "ecat.reg.dc.recv3",
3421 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL }
3422 },
3423 { &hf_ecat_reg_dc_systime,
3424 {"DC SysTime (0x910)", "ecat.reg.dc.systime",
3425 FT_UINT64, BASE_HEX, NULL, 0, NULL, HFILL }
3426 },
3427 { &hf_ecat_reg_dc_systimeL,
3428 {"DC SysTime L (0x910)", "ecat.reg.dc.systimeL",
3429 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL }
3430 },
3431 { &hf_ecat_reg_dc_systimeH,
3432 {"DC SysTime H (0x914)", "ecat.reg.dc.systimeH",
3433 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL }
3434 },
3435 { &hf_ecat_reg_dc_recvtime64,
3436 {"DC RecvTime (0x918)", "ecat.reg.dc.recvtime64",
3437 FT_UINT64, BASE_HEX, NULL, 0, NULL, HFILL }
3438 },
3439 { &hf_ecat_reg_dc_systimeoffs,
3440 {"DC SysTimeOffs (0x920)", "ecat.reg.dc.systimeoffs",
3441 FT_UINT64, BASE_HEX, NULL, 0, NULL, HFILL }
3442 },
3443 { &hf_ecat_reg_dc_systimeoffsl,
3444 {"DC SysTimeOffs L (0x920)", "ecat.reg.dc.systimeoffsl",
3445 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL }
3446 },
3447 { &hf_ecat_reg_dc_systimeoffsh,
3448 {"DC SysTimeOffs H (0x924)", "ecat.reg.dc.systimeoffsh",
3449 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL }
3450 },
3451 { &hf_ecat_reg_dc_systimedelay,
3452 {"DC SysTimeDelay (0x928)", "ecat.reg.dc.systimedelay",
3453 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL }
3454 },
3455 { &hf_ecat_reg_dc_ctrlerr,
3456 {"DC CtrlError (0x92c)", "ecat.reg.dc.ctrlerr",
3457 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL }
3458 },
3459 { &hf_ecat_reg_dc_speedstart,
3460 {"DC SpeedStart (0x930)", "ecat.reg.dc.speedstart",
3461 FT_UINT16, BASE_HEX, NULL, 0, NULL, HFILL }
3462 },
3463 { &hf_ecat_reg_dc_speeddiff,
3464 {"DC SpeedDiff (0x932)", "ecat.reg.dc.speeddiff",
3465 FT_UINT16, BASE_HEX, NULL, 0, NULL, HFILL }
3466 },
3467 { &hf_ecat_reg_dc_fltdepth_systimediff,
3468 {"DC Filter Depth System Time difference (0x934)", "ecat.reg.dc.fltdepth.systimediff",
3469 FT_UINT8, BASE_HEX, NULL, 0, NULL, HFILL }
3470 },
3471 { &hf_ecat_reg_dc_fltdepth_speedcnt,
3472 {"DC Filter Depth Speed counter (0x935)", "ecat.reg.dc.fltdepth.speedcnt",
3473 FT_UINT8, BASE_HEX, NULL, 0, NULL, HFILL }
3474 },
3475 { &hf_ecat_reg_dc_cycunitctrl,
3476 {"DC Cyclic Unit Control (0x980)", "ecat.reg.dc.cycunitctrl",
3477 FT_UINT8, BASE_HEX, NULL, 0, NULL, HFILL }
3478 },
3479 { &hf_ecat_reg_dc_cycunitctrl_access_cyclic,
3480 {"Write access cyclic", "ecat.reg.dc.cycunitctrl.access_cyclic",
3481 FT_BOOLEAN, 8, TFS(&tfs_esc_reg_9801), 0x01, NULL, HFILL }
3482 },
3483 { &hf_ecat_reg_dc_cycunitctrl_access_latch0,
3484 {"Write access latch 0", "ecat.reg.dc.cycunitctrl.access_latch0",
3485 FT_BOOLEAN, 8, TFS(&tfs_esc_reg_9801), 0x10, NULL, HFILL }
3486 },
3487 { &hf_ecat_reg_dc_cycunitctrl_access_latch1,
3488 {"Write access latch 1", "ecat.reg.dc.cycunitctrl.access_latch1",
3489 FT_BOOLEAN, 8, TFS(&tfs_esc_reg_9801), 0x20, NULL, HFILL }
3490 },
3491 { &hf_ecat_reg_dc_activation,
3492 {"DC Activation (0x981)", "ecat.reg.dc.activation",
3493 FT_UINT8, BASE_HEX, NULL, 0, NULL, HFILL }
3494 },
3495 { &hf_ecat_reg_dc_activation_enablecyclic,
3496 {"Enable cyclic", "ecat.reg.dc.activation.enablecyclic",
3497 FT_BOOLEAN, 8, TFS(&tfs_local_true_false), 0x01, NULL, HFILL }
3498 },
3499 { &hf_ecat_reg_dc_activation_gen_sync0,
3500 {"Generate SYNC 0", "ecat.reg.dc.activation.gen_sync0",
3501 FT_BOOLEAN, 8, TFS(&tfs_local_true_false), 0x02, NULL, HFILL }
3502 },
3503 { &hf_ecat_reg_dc_activation_gen_sync1,
3504 {"Generate SYNC 1", "ecat.reg.dc.activation.gen_sync1",
3505 FT_BOOLEAN, 8, TFS(&tfs_local_true_false), 0x04, NULL, HFILL }
3506 },
3507 { &hf_ecat_reg_dc_activation_autoactivation,
3508 {"Auto activation", "ecat.reg.dc.activation.autoactivation",
3509 FT_BOOLEAN, 8, TFS(&tfs_local_true_false), 0x08, NULL, HFILL }
3510 },
3511 { &hf_ecat_reg_dc_activation_stimeext,
3512 {"Start time extension 32->64", "ecat.reg.dc.activation.stimeext",
3513 FT_BOOLEAN, 8, TFS(&tfs_local_true_false), 0x10, NULL, HFILL }
3514 },
3515 { &hf_ecat_reg_dc_activation_stimecheck,
3516 {"Start time check", "ecat.reg.dc.activation.stimecheck",
3517 FT_BOOLEAN, 8, TFS(&tfs_local_true_false), 0x20, NULL, HFILL }
3518 },
3519 { &hf_ecat_reg_dc_activation_hlfrange,
3520 {"Half range", "ecat.reg.dc.activation.hlfrange",
3521 FT_BOOLEAN, 8, TFS(&tfs_local_true_false), 0x40, NULL, HFILL }
3522 },
3523 { &hf_ecat_reg_dc_activation_dblrange,
3524 {"Debug pulse", "ecat.reg.dc.activation.dblrange",
3525 FT_BOOLEAN, 8, TFS(&tfs_local_true_false), 0x80, NULL, HFILL }
3526 },
3527 { &hf_ecat_reg_dc_cycimpuls,
3528 {"DC CycImpulse (0x982)", "ecat.reg.dc.cycimpuls",
3529 FT_UINT16, BASE_HEX, NULL, 0, NULL, HFILL }
3530 },
3531 { &hf_ecat_reg_dc_activationstat,
3532 {"DC Activation status (0x984)", "ecat.reg.dc.activationstat",
3533 FT_UINT8, BASE_HEX, NULL, 0, NULL, HFILL }
3534 },
3535 { &hf_ecat_reg_dc_activationstat_sync0pend,
3536 {"SYNC 0 pending", "ecat.reg.dc.activationstat.sync0pend",
3537 FT_BOOLEAN, 8, TFS(&tfs_local_true_false), 0x01, NULL, HFILL }
3538 },
3539 { &hf_ecat_reg_dc_activationstat_sync1pend,
3540 {"SYNC 1 pending", "ecat.reg.dc.activationstat.sync1pend",
3541 FT_BOOLEAN, 8, TFS(&tfs_local_true_false), 0x02, NULL, HFILL }
3542 },
3543 { &hf_ecat_reg_dc_activationstat_stimeoutofrange,
3544 {"Start time out of range", "ecat.reg.dc.activationstat.stimeoutofrange",
3545 FT_BOOLEAN, 8, TFS(&tfs_local_true_false), 0x04, NULL, HFILL }
3546 },
3547 { &hf_ecat_reg_dc_sync0_status,
3548 {"DC Sync0 Status (0x98e)", "ecat.reg.dc.sync0.status",
3549 FT_UINT8, BASE_HEX, NULL, 0, NULL, HFILL }
3550 },
3551 { &hf_ecat_reg_dc_sync0_status_triggered,
3552 {"triggered", "ecat.reg.dc.sync0.status.triggered",
3553 FT_BOOLEAN, 8, TFS(&tfs_local_true_false), 0x01, NULL, HFILL }
3554 },
3555 { &hf_ecat_reg_dc_sync1_status,
3556 {"DC Sync0 Status1 (0x98f)", "ecat.reg.dc.sync1.status",
3557 FT_UINT8, BASE_HEX, NULL, 0, NULL, HFILL }
3558 },
3559 { &hf_ecat_reg_dc_sync1_status_triggered,
3560 {"triggered", "ecat.reg.dc.sync1.status.triggered",
3561 FT_BOOLEAN, 8, TFS(&tfs_local_true_false), 0x01, NULL, HFILL }
3562 },
3563 { &hf_ecat_reg_dc_starttime0,
3564 {"DC StartTime0 (0x990)", "ecat.reg.dc.starttime0",
3565 FT_UINT64, BASE_HEX, NULL, 0, NULL, HFILL }
3566 },
3567 { &hf_ecat_reg_dc_starttime1,
3568 {"DC StartTime1 (0x998)", "ecat.reg.dc.starttime1",
3569 FT_UINT64, BASE_HEX, NULL, 0, NULL, HFILL }
3570 },
3571 { &hf_ecat_reg_dc_cyctime0,
3572 {"DC CycTime0 (0x9a0)", "ecat.reg.dc.cyctime0",
3573 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL }
3574 },
3575 { &hf_ecat_reg_dc_cyctime1,
3576 {"DC CycTime1 (0x9a4)", "ecat.reg.dc.cyctime1",
3577 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL }
3578 },
3579 { &hf_ecat_reg_dc_latch0_ctrl,
3580 {"DC Latch0 Ctrl (0x9a8)", "ecat.reg.dc.latch0.ctrl",
3581 FT_UINT8, BASE_HEX, NULL, 0, NULL, HFILL }
3582 },
3583 { &hf_ecat_reg_dc_latch0_ctrl_pos,
3584 {"pos", "ecat.reg.dc.latch0.ctrl.pos",
3585 FT_BOOLEAN, 8, TFS(&tfs_esc_reg_9A8E1), 0x01, NULL, HFILL }
3586 },
3587 { &hf_ecat_reg_dc_latch0_ctrl_neg,
3588 {"neg", "ecat.reg.dc.latch0.ctrl.neg",
3589 FT_BOOLEAN, 8, TFS(&tfs_esc_reg_9A8E1), 0x02, NULL, HFILL }
3590 },
3591 { &hf_ecat_reg_dc_latch1_ctrl,
3592 {"DC Latch1 Ctrl (0x9a9)", "ecat.reg.dc.latch1.ctrl",
3593 FT_UINT8, BASE_HEX, NULL, 0, NULL, HFILL }
3594 },
3595 { &hf_ecat_reg_dc_latch1_ctrl_pos,
3596 {"pos", "ecat.reg.dc.latch1.ctrl.pos",
3597 FT_BOOLEAN, 8, TFS(&tfs_esc_reg_9A8E1), 0x01, NULL, HFILL }
3598 },
3599 { &hf_ecat_reg_dc_latch1_ctrl_neg,
3600 {"neg", "ecat.reg.dc.latch1.ctrl.neg",
3601 FT_BOOLEAN, 8, TFS(&tfs_esc_reg_9A8E1), 0x02, NULL, HFILL }
3602 },
3603 { &hf_ecat_reg_dc_latch0_status,
3604 {"DC Latch0 Status (0x9ae)", "ecat.reg.dc.latch0.status",
3605 FT_UINT8, BASE_HEX, NULL, 0, NULL, HFILL }
3606 },
3607 { &hf_ecat_reg_dc_latch0_status_eventpos,
3608 {"Event pos", "ecat.reg.dc.latch0.status.eventpos",
3609 FT_BOOLEAN, 8, TFS(&tfs_local_true_false), 0x01, NULL, HFILL }
3610 },
3611 { &hf_ecat_reg_dc_latch0_status_eventneg,
3612 {"Event neg", "ecat.reg.dc.latch0.status.eventneg",
3613 FT_BOOLEAN, 8, TFS(&tfs_local_true_false), 0x02, NULL, HFILL }
3614 },
3615 { &hf_ecat_reg_dc_latch0_status_pinstate,
3616 {"pin state", "ecat.reg.dc.latch0.status.pinstate",
3617 FT_BOOLEAN, 8, TFS(&tfs_local_true_false), 0x04, NULL, HFILL }
3618 },
3619 { &hf_ecat_reg_dc_latch1_status,
3620 {"DC Latch1 Status (0x9af)", "ecat.reg.dc.latch1.status",
3621 FT_UINT8, BASE_HEX, NULL, 0, NULL, HFILL }
3622 },
3623 { &hf_ecat_reg_dc_latch1_status_eventpos,
3624 {"Event pos", "ecat.reg.dc.latch1.status.eventpos",
3625 FT_BOOLEAN, 8, TFS(&tfs_local_true_false), 0x01, NULL, HFILL }
3626 },
3627 { &hf_ecat_reg_dc_latch1_status_eventneg,
3628 {"Event neg", "ecat.reg.dc.latch1.status.eventneg",
3629 FT_BOOLEAN, 8, TFS(&tfs_local_true_false), 0x02, NULL, HFILL }
3630 },
3631 { &hf_ecat_reg_dc_latch1_status_pinstate,
3632 {"pin state", "ecat.reg.dc.latch1.status.pinstate",
3633 FT_BOOLEAN, 8, TFS(&tfs_local_true_false), 0x04, NULL, HFILL }
3634 },
3635 { &hf_ecat_reg_dc_latch0_pos,
3636 {"DC Latch0 Pos (0x9b0)", "ecat.reg.dc.latch0.pos",
3637 FT_UINT64, BASE_HEX, NULL, 0, NULL, HFILL }
3638 },
3639 { &hf_ecat_reg_dc_latch0_neg,
3640 {"DC Latch0 Neg (0x9b8)", "ecat.reg.dc.latch0.neg",
3641 FT_UINT64, BASE_HEX, NULL, 0, NULL, HFILL }
3642 },
3643 { &hf_ecat_reg_dc_latch1_pos,
3644 {"DC Latch1 Pos (0x9c0)", "ecat.reg.dc.latch1.pos",
3645 FT_UINT64, BASE_HEX, NULL, 0, NULL, HFILL }
3646 },
3647 { &hf_ecat_reg_dc_latch1_neg,
3648 {"DC Latch1 Neg (0x9c8)", "ecat.reg.dc.latch1.neg",
3649 FT_UINT64, BASE_HEX, NULL, 0, NULL, HFILL }
3650 },
3651 { &hf_ecat_reg_dc_rcvsyncmanchg,
3652 {"DC RecvSyncManChange (0x9f0)", "ecat.reg.dc.rcvsyncmanchg",
3653 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL }
3654 },
3655 { &hf_ecat_reg_dc_pdismstart,
3656 {"DC PdiSyncManStart (0x9f8)", "ecat.reg.dc.pdismstart",
3657 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL }
3658 },
3659 { &hf_ecat_reg_dc_pdismchg,
3660 {"DC PdiSyncManChange (0x9fc)", "ecat.reg.dc.pdismchg",
3661 FT_UINT32, BASE_HEX, NULL, 0, NULL, HFILL }
3662 },
3663 };
3664
3665 static int *ett[] =
3666 {
3667 &ett_ecat,
3668 &ett_ecat_header,
3669 &ett_ecat_dc,
3670 &ett_ecat_length,
3671 &ett_ecat_padding,
3672 &ett_ecat_datagram_subtree,
3673 &ett_ecat_reg_esc_features,
3674 &ett_ecat_reg_dlctrl1,
3675 &ett_ecat_reg_dlctrl2,
3676 &ett_ecat_reg_dlctrl3,
3677 &ett_ecat_reg_dlctrl4,
3678 &ett_ecat_reg_dlstatus1,
3679 &ett_ecat_reg_dlstatus2,
3680 &ett_ecat_reg_alctrl,
3681 &ett_ecat_reg_alstatus,
3682 &ett_ecat_reg_pdictrl1,
3683 &ett_ecat_reg_pdictrl2,
3684 &ett_ecat_reg_ecat_mask,
3685 &ett_ecat_reg_pdiL,
3686 &ett_ecat_reg_ecat,
3687 &ett_ecat_reg_pdi1,
3688 &ett_ecat_reg_crc0,
3689 &ett_ecat_reg_crc1,
3690 &ett_ecat_reg_crc2,
3691 &ett_ecat_reg_crc3,
3692 &ett_ecat_reg_wd_status,
3693 &ett_ecat_reg_eeprom_assign,
3694 &ett_ecat_reg_ctrlstat,
3695 &ett_ecat_reg_mio_ctrlstat,
3696 &ett_ecat_mio_addr,
3697 &ett_ecat_mio_access,
3698 &ett_ecat_mio_status0,
3699 &ett_ecat_mio_status1,
3700 &ett_ecat_mio_status2,
3701 &ett_ecat_mio_status3,
3702 &ett_ecat_reg_fmmu,
3703 &ett_ecat_reg_syncman,
3704 &ett_ecat_reg_syncman_ctrlstatus,
3705 &ett_ecat_reg_syncman_sm_enable,
3706 &ett_ecat_reg_dc_cycunitctrl,
3707 &ett_ecat_dc_activation,
3708 &ett_ecat_dc_activationstat,
3709 &ett_ecat_dc_sync0_status,
3710 &ett_ecat_dc_sync1_status,
3711 &ett_ecat_dc_latch0_ctrl,
3712 &ett_ecat_dc_latch1_ctrl,
3713 &ett_ecat_dc_latch0_status,
3714 &ett_ecat_dc_latch1_status,
3715 };
3716
3717 proto_ecat_datagram = proto_register_protocol("EtherCAT datagram(s)", "ECAT", "ecat");
3718 proto_register_field_array(proto_ecat_datagram, hf, array_length(hf));
3719 proto_register_subtree_array(ett, array_length(ett));
3720 ecat_handle = register_dissector("ecat", dissect_ecat_datagram, proto_ecat_datagram);
3721
3722 /* Sub dissector code */
3723 heur_subdissector_list = register_heur_dissector_list_with_description("ecat.data", "EtherCAT payload", proto_ecat_datagram);
3724 }
3725
3726 /* The registration hand-off routing */
3727 void proto_reg_handoff_ecat(void)
3728 {
3729 /* Register this dissector as a sub dissector to EtherCAT frame based on
3730 ether type. */
3731 dissector_add_uint("ecatf.type", 1 /* EtherCAT type */, ecat_handle);
3732
3733 ecat_mailbox_handle = find_dissector_add_dependency("ecat_mailbox", proto_ecat_datagram);
3734 }
3735
3736 /*
3737 * Editor modelines - https://www.wireshark.org/tools/modelines.html
3738 *
3739 * Local Variables:
3740 * c-basic-offset: 3
3741 * tab-width: 8
3742 * indent-tabs-mode: nil
3743 * End:
3744 *
3745 * ex: set shiftwidth=3 tabstop=8 expandtab:
3746 * :indentSize=3:tabSize=8:noTabs=true:
3747 */
Metzes wireshark repo