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MSWSP: add ids for another unknown Property Set
[wireshark-wip.git] / plugins / wimax / msg_reg_req.c
blobd4125ea732c7a2a65eae7ecca4f8c006e979ff04
1 /* msg_reg_req.c
2 * WiMax MAC Management REG-REQ Message decoder
3 *
4 * Copyright (c) 2007 by Intel Corporation.
5 *
6 * Author: John R. Underwood <junderx@yahoo.com>
7 *
8 * $Id$
9 *
10 * Wireshark - Network traffic analyzer
11 * By Gerald Combs <gerald@wireshark.org>
12 * Copyright 1999 Gerald Combs
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License
16 * as published by the Free Software Foundation; either version 2
17 * of the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
27 */
28
29 /* Include files */
30
31 #include "config.h"
32
33 #define WIMAX_16E_2005
34
35 #include <glib.h>
36 #include <epan/packet.h>
37 #include "crc.h"
38 #include "wimax_tlv.h"
39 #include "wimax_mac.h"
40 #include "wimax_utils.h"
41
42 extern gboolean include_cor2_changes;
43
44 static gint proto_mac_mgmt_msg_reg_req_decoder = -1;
45 static gint ett_mac_mgmt_msg_reg_req_decoder = -1;
46
47 /* REG-REQ fields */
48 static gint hf_reg_ss_mgmt_support = -1;
49 static gint hf_reg_ip_mgmt_mode = -1;
50 static gint hf_reg_ip_version = -1;
51 static gint hf_reg_req_secondary_mgmt_cid = -1;
52 static gint hf_reg_ul_cids = -1;
53 static gint hf_reg_max_classifiers = -1;
54 static gint hf_reg_phs = -1;
55 static gint hf_reg_arq = -1;
56 static gint hf_reg_dsx_flow_control = -1;
57 static gint hf_reg_mac_crc_support = -1;
58 static gint hf_reg_mca_flow_control = -1;
59 static gint hf_reg_mcast_polling_cids = -1;
60 static gint hf_reg_num_dl_trans_cid = -1;
61 static gint hf_reg_mac_address = -1;
62 static gint hf_reg_tlv_t_20_1_max_mac_level_data_per_dl_frame = -1;
63 static gint hf_reg_tlv_t_20_2_max_mac_level_data_per_ul_frame = -1;
64 static gint hf_reg_tlv_t_21_packing_support = -1;
65 static gint hf_reg_tlv_t_22_mac_extended_rtps_support = -1;
66 static gint hf_reg_tlv_t_23_max_num_bursts_concurrently_to_the_ms = -1;
67 static gint hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_dhcp = -1;
68 static gint hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_mobile_ipv4 = -1;
69 static gint hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_dhcpv6 = -1;
70 static gint hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_ipv6 = -1;
71 static gint hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_rsvd = -1;
72 static gint hf_reg_tlv_t_27_handover_fbss_mdho_ho_disable = -1;
73 static gint hf_reg_tlv_t_27_handover_fbss_mdho_dl_rf_monitoring_maps = -1;
74 static gint hf_reg_tlv_t_27_handover_mdho_dl_monitoring_single_map = -1;
75 static gint hf_reg_tlv_t_27_handover_mdho_dl_monitoring_maps = -1;
76 static gint hf_reg_tlv_t_27_handover_mdho_ul_multiple = -1;
77 static gint hf_reg_tlv_t_27_handover_reserved = -1;
78 static gint hf_reg_tlv_t_29_ho_process_opt_ms_timer = -1;
79 static gint hf_reg_tlv_t_31_mobility_handover = -1;
80 static gint hf_reg_tlv_t_31_mobility_sleep_mode = -1;
81 static gint hf_reg_tlv_t_31_mobility_idle_mode = -1;
82 static gint hf_reg_req_tlv_t_32_sleep_mode_recovery_time = -1;
83 static gint hf_ms_previous_ip_address_v4 = -1;
84 static gint hf_ms_previous_ip_address_v6 = -1;
85 static gint hf_idle_mode_timeout = -1;
86 static gint hf_reg_req_tlv_t_45_ms_periodic_ranging_timer = -1;
87 static gint hf_reg_tlv_t_40_arq_ack_type_selective_ack_entry = -1;
88 static gint hf_reg_tlv_t_40_arq_ack_type_cumulative_ack_entry = -1;
89 static gint hf_reg_tlv_t_40_arq_ack_type_cumulative_with_selective_ack_entry = -1;
90 static gint hf_reg_tlv_t_40_arq_ack_type_cumulative_ack_with_block_sequence_ack = -1;
91 static gint hf_reg_tlv_t_40_arq_ack_type_reserved = -1;
92 static gint hf_reg_tlv_t_41_ho_connections_param_processing_time = -1;
93 static gint hf_reg_tlv_t_42_ho_tek_processing_time = -1;
94 static gint hf_reg_tlv_t_43_bandwidth_request_ul_tx_power_report_header_support = -1;
95 static gint hf_reg_tlv_t_43_bandwidth_request_cinr_report_header_support = -1;
96 static gint hf_reg_tlv_t_43_cqich_allocation_request_header_support = -1;
97 static gint hf_reg_tlv_t_43_phy_channel_report_header_support = -1;
98 static gint hf_reg_tlv_t_43_bandwidth_request_ul_sleep_control_header_support = -1;
99 static gint hf_reg_tlv_t_43_sn_report_header_support = -1;
100 static gint hf_reg_tlv_t_43_feedback_header_support = -1;
101 static gint hf_reg_tlv_t_43_sdu_sn_extended_subheader_support_and_parameter = -1;
102 static gint hf_reg_tlv_t_43_sdu_sn_parameter = -1;
103 static gint hf_reg_tlv_t_43_dl_sleep_control_extended_subheader = -1;
104 static gint hf_reg_tlv_t_43_feedback_request_extended_subheader = -1;
105 static gint hf_reg_tlv_t_43_mimo_mode_feedback_extended_subheader = -1;
106 static gint hf_reg_tlv_t_43_ul_tx_power_report_extended_subheader = -1;
107 static gint hf_reg_tlv_t_43_mini_feedback_extended_subheader = -1;
108 static gint hf_reg_tlv_t_43_sn_request_extended_subheader = -1;
109 static gint hf_reg_tlv_t_43_pdu_sn_short_extended_subheader = -1;
110 static gint hf_reg_tlv_t_43_pdu_sn_long_extended_subheader = -1;
111 static gint hf_reg_tlv_t_43_reserved = -1;
112 static gint hf_reg_tlv_t_46_handover_indication_readiness_timer = -1;
113 static gint hf_reg_req_min_time_for_intra_fa = -1;
114 static gint hf_reg_req_min_time_for_inter_fa = -1;
115 static gint hf_reg_encap_atm_4 = -1;
116 static gint hf_reg_encap_ipv4_4 = -1;
117 static gint hf_reg_encap_ipv6_4 = -1;
118 static gint hf_reg_encap_802_3_4 = -1;
119 static gint hf_reg_encap_802_1q_4 = -1;
120 static gint hf_reg_encap_ipv4_802_3_4 = -1;
121 static gint hf_reg_encap_ipv6_802_3_4 = -1;
122 static gint hf_reg_encap_ipv4_802_1q_4 = -1;
123 static gint hf_reg_encap_ipv6_802_1q_4 = -1;
124 static gint hf_reg_encap_packet_8023_ethernet_and_rohc_header_compression_4 = -1;
125 static gint hf_reg_encap_packet_8023_ethernet_and_ecrtp_header_compression_4 = -1;
126 static gint hf_reg_encap_packet_ip_rohc_header_compression_4 = -1;
127 static gint hf_reg_encap_packet_ip_ecrtp_header_compression_4 = -1;
128 static gint hf_reg_encap_rsvd_4 = -1;
129 static gint hf_reg_encap_atm_2 = -1;
130 static gint hf_reg_encap_ipv4_2 = -1;
131 static gint hf_reg_encap_ipv6_2 = -1;
132 static gint hf_reg_encap_802_3_2 = -1;
133 static gint hf_reg_encap_802_1q_2 = -1;
134 static gint hf_reg_encap_ipv4_802_3_2 = -1;
135 static gint hf_reg_encap_ipv6_802_3_2 = -1;
136 static gint hf_reg_encap_ipv4_802_1q_2 = -1;
137 static gint hf_reg_encap_ipv6_802_1q_2 = -1;
138 static gint hf_reg_encap_packet_8023_ethernet_and_rohc_header_compression_2 = -1;
139 static gint hf_reg_encap_packet_8023_ethernet_and_ecrtp_header_compression_2 = -1;
140 static gint hf_reg_encap_packet_ip_rohc_header_compression_2 = -1;
141 static gint hf_reg_encap_packet_ip_ecrtp_header_compression_2 = -1;
142 static gint hf_reg_encap_rsvd_2 = -1;
143 static gint hf_tlv_type = -1;
144 static gint hf_reg_invalid_tlv = -1;
145 static gint hf_reg_power_saving_class_type_i = -1;
146 static gint hf_reg_power_saving_class_type_ii = -1;
147 static gint hf_reg_power_saving_class_type_iii = -1;
148 static gint hf_reg_multi_active_power_saving_classes = -1;
149 static gint hf_reg_total_power_saving_class_instances = -1;
150 static gint hf_reg_power_saving_class_reserved = -1;
151 static gint hf_reg_power_saving_class_capability = -1;
152 static gint hf_reg_ip_phs_sdu_encap = -1;
153 static gint hf_reg_tlv_t_26_method_alloc_ip_addr_secondary_mgmnt_conn = -1;
154 static gint hf_reg_tlv_t_27_handover_supported = -1;
155 static gint hf_reg_tlv_t_31_mobility_features_supported = -1;
156 static gint hf_reg_tlv_t_40_arq_ack_type = -1;
157 static gint hf_reg_tlv_t_43_mac_header_ext_header_support = -1;
158 static gint hf_reg_req_bs_switching_timer = -1;
159
160 /* STRING RESOURCES */
161
162 static const true_false_string tfs_reg_ip_mgmt_mode = {
163 "IP-managed mode",
164 "Unmanaged mode"
165 };
166
167 static const true_false_string tfs_reg_ss_mgmt_support = {
168 "secondary management connection",
169 "no secondary management connection"
170 };
171
172 #if 0
173 static const true_false_string tfs_arq_enable = {
174 "ARQ Requested/Accepted",
175 "ARQ Not Requested/Accepted"
176 };
177 #endif
178
179 #if 0
180 static const true_false_string tfs_arq_deliver_in_order = {
181 "Order of delivery is preserved",
182 "Order of delivery is not preserved"
183 };
184 #endif
185
186 static const true_false_string tfs_reg_fbss_mdho_ho_disable = {
187 "Disable",
188 "Enable"
189 };
190
191 static const value_string vals_reg_ip_version[] = {
192 {0x1, "IPv4"},
193 {0x2, "IPV6"},
194 {0, NULL}
195 };
196
197 static const value_string vals_reg_phs_support[] = {
198 {0, "no PHS support"},
199 {1, "ATM PHS"},
200 {2, "Packet PHS"},
201 {3, "ATM and Packet PHS"},
202 {0, NULL}
203 };
204
205 static const true_false_string tfs_supported = {
206 "supported",
207 "unsupported"
208 };
209
210 static const true_false_string tfs_mac_crc_support = {
211 "MAC CRC Support (Default)",
212 "No MAC CRC Support"
213 };
214
215 static const value_string tfs_support[] = {
216 {0, "not supported"},
217 {1, "supported"},
218 {0, NULL}
219 };
220
221 /* Decode REG-REQ sub-TLV's. */
222 void dissect_extended_tlv(proto_tree *reg_req_tree, gint tlv_type, tvbuff_t *tvb, guint tlv_offset, guint tlv_len, packet_info *pinfo, guint offset, gint proto_registry)
223 {
224 proto_item *tlv_item;
225 proto_tree *tlv_tree;
226 guint tvb_len;
227 tlv_info_t tlv_info;
228 guint tlv_end;
229 guint length;
230 guint nblocks;
231
232 /* Get the tvb reported length */
233 tvb_len = tvb_reported_length(tvb);
234
235 /* get the TLV information */
236 init_tlv_info(&tlv_info, tvb, offset);
237
238 #ifdef WIMAX_16E_2005
239 switch (tlv_type) {
240 case REG_ARQ_PARAMETERS:
241 /* display ARQ Service Flow Encodings info */
242 /* add subtree */
243 tlv_tree = add_protocol_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_registry, tvb, offset, tlv_len, "ARQ Service Flow Encodings");
244 /* decode and display the DL Service Flow Encodings */
245 wimax_service_flow_encodings_decoder(tvb_new_subset_length(tvb, tlv_offset, tlv_len), pinfo, tlv_tree);
246 break;
247 case REG_SS_MGMT_SUPPORT:
248 add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_ss_mgmt_support, tvb, offset, ENC_BIG_ENDIAN);
249 break;
250 case REG_IP_MGMT_MODE:
251 add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_ip_mgmt_mode, tvb, offset, ENC_BIG_ENDIAN);
252 break;
253 case REG_IP_VERSION:
254 add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_ip_version, tvb, offset, ENC_BIG_ENDIAN);
255 break;
256 case REG_UL_TRANSPORT_CIDS_SUPPORTED:
257 add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_ul_cids, tvb, offset, ENC_BIG_ENDIAN);
258 break;
259
260 case REG_POWER_SAVING_CLASS_CAPABILITY:
261 tlv_item = add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_power_saving_class_capability, tvb, offset, ENC_BIG_ENDIAN);
262 tlv_tree = proto_item_add_subtree(tlv_item, ett_mac_mgmt_msg_reg_req_decoder);
263 proto_tree_add_item(tlv_tree, hf_reg_power_saving_class_type_i, tvb, tlv_offset, 2, ENC_BIG_ENDIAN);
264 proto_tree_add_item(tlv_tree, hf_reg_power_saving_class_type_ii, tvb, tlv_offset, 2, ENC_BIG_ENDIAN);
265 proto_tree_add_item(tlv_tree, hf_reg_power_saving_class_type_iii, tvb, tlv_offset, 2, ENC_BIG_ENDIAN);
266 proto_tree_add_item(tlv_tree, hf_reg_multi_active_power_saving_classes, tvb, tlv_offset, 2, ENC_BIG_ENDIAN);
267 proto_tree_add_item(tlv_tree, hf_reg_total_power_saving_class_instances, tvb, tlv_offset, 2, ENC_BIG_ENDIAN);
268 proto_tree_add_item(tlv_tree, hf_reg_power_saving_class_reserved, tvb, tlv_offset, 2, ENC_BIG_ENDIAN);
269 break;
270 case REG_IP_PHS_SDU_ENCAP:
271 tlv_item = add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_ip_phs_sdu_encap, tvb, offset, ENC_BIG_ENDIAN);
272 tlv_tree = proto_item_add_subtree(tlv_item, ett_mac_mgmt_msg_reg_req_decoder);
273
274 #ifdef WIMAX_16E_2005
275 if (tlv_len == 2){
276 proto_tree_add_item(tlv_tree, hf_reg_encap_atm_2, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
277 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv4_2, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
278 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv6_2, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
279 proto_tree_add_item(tlv_tree, hf_reg_encap_802_3_2, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
280 proto_tree_add_item(tlv_tree, hf_reg_encap_802_1q_2, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
281 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv4_802_3_2, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
282 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv6_802_3_2, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
283 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv4_802_1q_2, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
284 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv6_802_1q_2, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
285 proto_tree_add_item(tlv_tree, hf_reg_encap_packet_8023_ethernet_and_rohc_header_compression_2, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
286 proto_tree_add_item(tlv_tree, hf_reg_encap_packet_8023_ethernet_and_ecrtp_header_compression_2, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
287 proto_tree_add_item(tlv_tree, hf_reg_encap_packet_ip_rohc_header_compression_2, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
288 proto_tree_add_item(tlv_tree, hf_reg_encap_packet_ip_ecrtp_header_compression_2, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
289 proto_tree_add_item(tlv_tree, hf_reg_encap_rsvd_2, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
290 } else if(tlv_len == 4){
291 proto_tree_add_item(tlv_tree, hf_reg_encap_atm_4, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
292 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv4_4, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
293 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv6_4, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
294 proto_tree_add_item(tlv_tree, hf_reg_encap_802_3_4, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
295 proto_tree_add_item(tlv_tree, hf_reg_encap_802_1q_4, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
296 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv4_802_3_4, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
297 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv6_802_3_4, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
298 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv4_802_1q_4, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
299 proto_tree_add_item(tlv_tree, hf_reg_encap_ipv6_802_1q_4, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
300 proto_tree_add_item(tlv_tree, hf_reg_encap_packet_8023_ethernet_and_rohc_header_compression_4, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
301 proto_tree_add_item(tlv_tree, hf_reg_encap_packet_8023_ethernet_and_ecrtp_header_compression_4, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
302 proto_tree_add_item(tlv_tree, hf_reg_encap_packet_ip_rohc_header_compression_4, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
303 proto_tree_add_item(tlv_tree, hf_reg_encap_packet_ip_ecrtp_header_compression_4, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
304 proto_tree_add_item(tlv_tree, hf_reg_encap_rsvd_4, tvb, tlv_offset, tlv_len, ENC_BIG_ENDIAN);
305 }
306 #endif
307 break;
308 case REG_MAX_CLASSIFIERS_SUPPORTED:
309 add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_max_classifiers, tvb, offset, ENC_BIG_ENDIAN);
310 break;
311 case REG_PHS_SUPPORT:
312 add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_phs, tvb, offset, ENC_BIG_ENDIAN);
313 break;
314 case REG_ARQ_SUPPORT:
315 add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_arq, tvb, offset, ENC_BIG_ENDIAN);
316 break;
317 case REG_DSX_FLOW_CONTROL:
318 tlv_item = add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_dsx_flow_control, tvb, offset, ENC_BIG_ENDIAN);
319 if (tvb_get_guint8(tvb, tlv_offset) == 0) {
320 proto_item_append_text(tlv_item, " (no limit)");
321 }
322 break;
323 case REG_MAC_CRC_SUPPORT:
324 if (!include_cor2_changes) {
325 add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_mac_crc_support, tvb, offset, ENC_NA);
326 } else {
327 /* Unknown TLV Type */
328 add_tlv_subtree(&tlv_info, reg_req_tree, hf_tlv_type, tvb, offset, ENC_NA);
329 }
330 break;
331 case REG_MCA_FLOW_CONTROL:
332 tlv_item = add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_mca_flow_control, tvb, offset, ENC_BIG_ENDIAN);
333 if (tvb_get_guint8(tvb, tlv_offset) == 0) {
334 proto_item_append_text(tlv_item, " (no limit)");
335 }
336 break;
337 case REG_MCAST_POLLING_CIDS:
338 add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_mcast_polling_cids, tvb, offset, ENC_BIG_ENDIAN);
339 break;
340 case REG_NUM_DL_TRANS_CID:
341 add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_num_dl_trans_cid, tvb, offset, ENC_BIG_ENDIAN);
342 break;
343 case REG_MAC_ADDRESS:
344 add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_mac_address, tvb, offset, ENC_NA);
345 break;
346 case REG_TLV_T_20_MAX_MAC_DATA_PER_FRAME_SUPPORT:
347 /* display Maximum MAC level data per frame info */
348 /* add subtree */
349 tlv_tree = add_protocol_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_registry, tvb, offset, tlv_len, "Maximum MAC level data per frame");
350 /* decode and display Maximum MAC level data per frame for UL & DL */
351 /* Set endpoint of the subTLVs (tlv_offset + length) */
352 tlv_end = tlv_offset + tlv_len;
353 /* process subTLVs */
354 while ( tlv_offset < tlv_end )
355 { /* get the TLV information */
356 init_tlv_info(&tlv_info, tvb, tlv_offset);
357 /* get the TLV type */
358 tlv_type = get_tlv_type(&tlv_info);
359 /* get the TLV length */
360 length = get_tlv_length(&tlv_info);
361 if(tlv_type == -1 || length > MAX_TLV_LEN || length < 1)
362 { /* invalid tlv info */
363 col_append_sep_str(pinfo->cinfo, COL_INFO, NULL, "REG-REQ TLV error");
364 proto_tree_add_item(reg_req_tree, hf_reg_invalid_tlv, tvb, offset, (tvb_len - offset), ENC_NA);
365 break;
366 }
367 /* update the offset */
368 tlv_offset += get_tlv_value_offset(&tlv_info);
369 nblocks = tvb_get_ntohs(tvb, tlv_offset);
370 switch (tlv_type)
371 {
372 case REG_TLV_T_20_1_MAX_MAC_LEVEL_DATA_PER_DL_FRAME:
373 tlv_item = add_tlv_subtree(&tlv_info, tlv_tree, hf_reg_tlv_t_20_1_max_mac_level_data_per_dl_frame, tvb, tlv_offset-get_tlv_value_offset(&tlv_info), ENC_BIG_ENDIAN);
374 if ( nblocks == 0 )
375 {
376 proto_item_append_text(tlv_item, " (Unlimited bytes)");
377 } else {
378 proto_item_append_text(tlv_item, " (%d bytes)", 256 * nblocks);
379 }
380 break;
381 case REG_TLV_T_20_2_MAX_MAC_LEVEL_DATA_PER_UL_FRAME:
382 tlv_item = add_tlv_subtree(&tlv_info, tlv_tree, hf_reg_tlv_t_20_2_max_mac_level_data_per_ul_frame, tvb, tlv_offset-get_tlv_value_offset(&tlv_info), ENC_BIG_ENDIAN);
383 if ( nblocks == 0 )
384 {
385 proto_item_append_text(tlv_item, " (Unlimited bytes)");
386 } else {
387 proto_item_append_text(tlv_item, " (%d bytes)", 256 * nblocks);
388 }
389 break;
390 default:
391 add_tlv_subtree(&tlv_info, tlv_tree, hf_reg_invalid_tlv, tvb, tlv_offset-get_tlv_value_offset(&tlv_info), ENC_NA);
392 break;
393 }
394 tlv_offset += length;
395 }
396 break;
397
398 case REG_TLV_T_21_PACKING_SUPPORT:
399 add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_tlv_t_21_packing_support, tvb, offset, ENC_BIG_ENDIAN);
400 break;
401 case REG_TLV_T_22_MAC_EXTENDED_RTPS_SUPPORT:
402 add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_tlv_t_22_mac_extended_rtps_support, tvb, offset, ENC_BIG_ENDIAN);
403 break;
404 case REG_TLV_T_23_MAX_NUM_BURSTS_TRANSMITTED_CONCURRENTLY_TO_THE_MS:
405 add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_tlv_t_23_max_num_bursts_concurrently_to_the_ms, tvb, offset, ENC_BIG_ENDIAN);
406 break;
407 case REG_TLV_T_26_METHOD_FOR_ALLOCATING_IP_ADDR_SECONDARY_MGMNT_CONNECTION:
408 tlv_item = add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_tlv_t_26_method_alloc_ip_addr_secondary_mgmnt_conn, tvb, offset, ENC_BIG_ENDIAN);
409 tlv_tree = proto_item_add_subtree(tlv_item, ett_mac_mgmt_msg_reg_req_decoder);
410 proto_tree_add_item(tlv_tree, hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_dhcp, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
411 proto_tree_add_item(tlv_tree, hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_mobile_ipv4, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
412 proto_tree_add_item(tlv_tree, hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_dhcpv6, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
413 proto_tree_add_item(tlv_tree, hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_ipv6, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
414 proto_tree_add_item(tlv_tree, hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_rsvd, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
415 break;
416 case REG_TLV_T_27_HANDOVER_SUPPORTED:
417 tlv_item = add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_tlv_t_27_handover_supported, tvb, offset, ENC_BIG_ENDIAN);
418 tlv_tree = proto_item_add_subtree(tlv_item, ett_mac_mgmt_msg_reg_req_decoder);
419 proto_tree_add_item(tlv_tree, hf_reg_tlv_t_27_handover_fbss_mdho_ho_disable, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
420 proto_tree_add_item(tlv_tree, hf_reg_tlv_t_27_handover_fbss_mdho_dl_rf_monitoring_maps, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
421 proto_tree_add_item(tlv_tree, hf_reg_tlv_t_27_handover_mdho_dl_monitoring_single_map, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
422 proto_tree_add_item(tlv_tree, hf_reg_tlv_t_27_handover_mdho_dl_monitoring_maps, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
423 proto_tree_add_item(tlv_tree, hf_reg_tlv_t_27_handover_mdho_ul_multiple, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
424 proto_tree_add_item(tlv_tree, hf_reg_tlv_t_27_handover_reserved, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
425 break;
426 case REG_TLV_T_29_HO_PROCESS_OPTIMIZATION_MS_TIMER:
427 add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_tlv_t_29_ho_process_opt_ms_timer, tvb, offset, ENC_BIG_ENDIAN);
428 break;
429 case REG_TLV_T_31_MOBILITY_FEATURES_SUPPORTED:
430 tlv_item = add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_tlv_t_31_mobility_features_supported, tvb, offset, ENC_BIG_ENDIAN);
431 tlv_tree = proto_item_add_subtree(tlv_item, ett_mac_mgmt_msg_reg_req_decoder);
432 proto_tree_add_item(tlv_tree, hf_reg_tlv_t_31_mobility_handover, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
433 proto_tree_add_item(tlv_tree, hf_reg_tlv_t_31_mobility_sleep_mode, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
434 proto_tree_add_item(tlv_tree, hf_reg_tlv_t_31_mobility_idle_mode, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
435 break;
436 case REG_TLV_T_40_ARQ_ACK_TYPE:
437 tlv_item = add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_tlv_t_40_arq_ack_type, tvb, offset, ENC_BIG_ENDIAN);
438 tlv_tree = proto_item_add_subtree(tlv_item, ett_mac_mgmt_msg_reg_req_decoder);
439 proto_tree_add_item(tlv_tree, hf_reg_tlv_t_40_arq_ack_type_selective_ack_entry, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
440 proto_tree_add_item(tlv_tree, hf_reg_tlv_t_40_arq_ack_type_cumulative_ack_entry, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
441 proto_tree_add_item(tlv_tree, hf_reg_tlv_t_40_arq_ack_type_cumulative_with_selective_ack_entry, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
442 proto_tree_add_item(tlv_tree, hf_reg_tlv_t_40_arq_ack_type_cumulative_ack_with_block_sequence_ack, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
443 proto_tree_add_item(tlv_tree, hf_reg_tlv_t_40_arq_ack_type_reserved, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
444 break;
445 case REG_TLV_T_41_MS_HO_CONNECTIONS_PARAM_PROCESSING_TIME:
446 add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_tlv_t_41_ho_connections_param_processing_time, tvb, offset, ENC_BIG_ENDIAN);
447 break;
448 case REG_TLV_T_42_MS_HO_TEK_PROCESSING_TIME:
449 add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_tlv_t_42_ho_tek_processing_time, tvb, offset, ENC_BIG_ENDIAN);
450 break;
451 case REG_TLV_T_43_MAC_HEADER_AND_EXTENDED_SUBHEADER_SUPPORT:
452 tlv_item = add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_tlv_t_43_mac_header_ext_header_support, tvb, offset, ENC_BIG_ENDIAN);
453 tlv_tree = proto_item_add_subtree(tlv_item, ett_mac_mgmt_msg_reg_req_decoder);
454 proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_bandwidth_request_ul_tx_power_report_header_support, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
455 proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_bandwidth_request_cinr_report_header_support, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
456 proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_cqich_allocation_request_header_support, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
457 proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_phy_channel_report_header_support, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
458 proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_bandwidth_request_ul_sleep_control_header_support, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
459 proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_sn_report_header_support, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
460 proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_feedback_header_support, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
461 proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_sdu_sn_extended_subheader_support_and_parameter, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
462 proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_sdu_sn_parameter, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
463 proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_dl_sleep_control_extended_subheader, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
464 proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_feedback_request_extended_subheader, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
465 proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_mimo_mode_feedback_extended_subheader, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
466 proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_ul_tx_power_report_extended_subheader, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
467 proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_mini_feedback_extended_subheader, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
468 proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_sn_request_extended_subheader, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
469 proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_pdu_sn_short_extended_subheader, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
470 proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_pdu_sn_long_extended_subheader, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
471 proto_tree_add_item(tlv_tree, hf_reg_tlv_t_43_reserved, tvb, tlv_offset, 3, ENC_BIG_ENDIAN);
472 break;
473 case REG_REQ_BS_SWITCHING_TIMER:
474 tlv_item = add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_req_bs_switching_timer, tvb, offset, ENC_BIG_ENDIAN);
475 tlv_tree = proto_item_add_subtree(tlv_item, ett_mac_mgmt_msg_reg_req_decoder);
476 proto_tree_add_item(tlv_tree, hf_reg_req_min_time_for_intra_fa, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
477 proto_tree_add_item(tlv_tree, hf_reg_req_min_time_for_inter_fa, tvb, tlv_offset, 1, ENC_BIG_ENDIAN);
478 break;
479 case VENDOR_SPECIFIC_INFO:
480 case VENDOR_ID_ENCODING:
481 case CURRENT_TX_POWER:
482 case MAC_VERSION_ENCODING:
483 case CMAC_TUPLE: /* Table 348b */
484 wimax_common_tlv_encoding_decoder(tvb_new_subset_remaining(tvb, offset), pinfo, reg_req_tree);
485 break;
486 default:
487 add_tlv_subtree(&tlv_info, reg_req_tree, proto_registry, tvb, offset, ENC_NA);
488 break;
489 }
490 #endif
491 }
492
493
494 /* Decode REG-REQ messages. */
495 static void dissect_mac_mgmt_msg_reg_req_decoder(tvbuff_t *tvb, packet_info *pinfo, proto_tree *tree)
496 {
497 guint offset = 0;
498 guint tlv_offset;
499 guint tvb_len;
500 proto_item *reg_req_item = NULL;
501 proto_tree *reg_req_tree = NULL;
502 proto_tree *tlv_tree = NULL;
503 gboolean hmac_found = FALSE;
504 tlv_info_t tlv_info;
505 gint tlv_type;
506 gint tlv_len;
507
508 { /* we are being asked for details */
509
510 /* Get the tvb reported length */
511 tvb_len = tvb_reported_length(tvb);
512 /* display MAC payload type REG-REQ */
513 reg_req_item = proto_tree_add_protocol_format(tree, proto_mac_mgmt_msg_reg_req_decoder, tvb, offset, tvb_len, "MAC Management Message, REG-REQ");
514 /* add MAC REG-REQ subtree */
515 reg_req_tree = proto_item_add_subtree(reg_req_item, ett_mac_mgmt_msg_reg_req_decoder);
516
517 while(offset < tvb_len)
518 {
519 /* Get the TLV data. */
520 init_tlv_info(&tlv_info, tvb, offset);
521 /* get the TLV type */
522 tlv_type = get_tlv_type(&tlv_info);
523 /* get the TLV length */
524 tlv_len = get_tlv_length(&tlv_info);
525 if(tlv_type == -1 || tlv_len > MAX_TLV_LEN || tlv_len < 1)
526 { /* invalid tlv info */
527 col_append_sep_str(pinfo->cinfo, COL_INFO, NULL, "REG-REQ TLV error");
528 proto_tree_add_item(reg_req_tree, hf_reg_invalid_tlv, tvb, offset, (tvb_len - offset), ENC_NA);
529 break;
530 }
531 /* get the offset to the TLV data */
532 tlv_offset = offset + get_tlv_value_offset(&tlv_info);
533
534 switch (tlv_type) {
535 case REG_ARQ_PARAMETERS:
536 case REG_SS_MGMT_SUPPORT:
537 case REG_IP_MGMT_MODE:
538 case REG_IP_VERSION:
539 case REG_UL_TRANSPORT_CIDS_SUPPORTED:
540 case REG_IP_PHS_SDU_ENCAP:
541 case REG_MAX_CLASSIFIERS_SUPPORTED:
542 case REG_PHS_SUPPORT:
543 case REG_ARQ_SUPPORT:
544 case REG_DSX_FLOW_CONTROL:
545 case REG_MAC_CRC_SUPPORT:
546 case REG_MCA_FLOW_CONTROL:
547 case REG_MCAST_POLLING_CIDS:
548 case REG_NUM_DL_TRANS_CID:
549 case REG_MAC_ADDRESS:
550 #ifdef WIMAX_16E_2005
551 case REG_TLV_T_20_MAX_MAC_DATA_PER_FRAME_SUPPORT:
552 case REG_TLV_T_21_PACKING_SUPPORT:
553 case REG_TLV_T_22_MAC_EXTENDED_RTPS_SUPPORT:
554 case REG_TLV_T_23_MAX_NUM_BURSTS_TRANSMITTED_CONCURRENTLY_TO_THE_MS:
555 case REG_TLV_T_26_METHOD_FOR_ALLOCATING_IP_ADDR_SECONDARY_MGMNT_CONNECTION:
556 case REG_TLV_T_27_HANDOVER_SUPPORTED:
557 case REG_TLV_T_29_HO_PROCESS_OPTIMIZATION_MS_TIMER:
558 case REG_TLV_T_31_MOBILITY_FEATURES_SUPPORTED:
559 case REG_TLV_T_40_ARQ_ACK_TYPE:
560 case REG_TLV_T_41_MS_HO_CONNECTIONS_PARAM_PROCESSING_TIME:
561 case REG_TLV_T_42_MS_HO_TEK_PROCESSING_TIME:
562 case REG_TLV_T_43_MAC_HEADER_AND_EXTENDED_SUBHEADER_SUPPORT:
563 case REG_REQ_BS_SWITCHING_TIMER:
564 case REG_POWER_SAVING_CLASS_CAPABILITY:
565 #endif
566 /* Decode REG-REQ sub-TLV's. */
567 dissect_extended_tlv(reg_req_tree, tlv_type, tvb, tlv_offset, tlv_len, pinfo, offset, proto_mac_mgmt_msg_reg_req_decoder);
568 break;
569 case REG_REQ_SECONDARY_MGMT_CID:
570 add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_req_secondary_mgmt_cid, tvb, offset, ENC_BIG_ENDIAN);
571 break;
572 case REG_REQ_TLV_T_32_SLEEP_MODE_RECOVERY_TIME:
573 add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_req_tlv_t_32_sleep_mode_recovery_time, tvb, offset, ENC_BIG_ENDIAN);
574 break;
575 case REG_REQ_TLV_T_33_MS_PREV_IP_ADDR:
576 if ( tlv_len == 4 ) {
577 add_tlv_subtree(&tlv_info, reg_req_tree, hf_ms_previous_ip_address_v4, tvb, offset, ENC_BIG_ENDIAN);
578 } else if ( tlv_len == 16 ) {
579 add_tlv_subtree(&tlv_info, reg_req_tree, hf_ms_previous_ip_address_v6, tvb, offset, ENC_NA);
580 }
581 break;
582 case REG_TLV_T_37_IDLE_MODE_TIMEOUT:
583 add_tlv_subtree(&tlv_info, reg_req_tree, hf_idle_mode_timeout, tvb, offset, ENC_BIG_ENDIAN);
584 break;
585 case REG_REQ_TLV_T_45_MS_PERIODIC_RANGING_TIMER_INFO:
586 add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_req_tlv_t_45_ms_periodic_ranging_timer, tvb, offset, ENC_BIG_ENDIAN);
587 break;
588 case REG_HANDOVER_INDICATION_READINESS_TIMER:
589 add_tlv_subtree(&tlv_info, reg_req_tree, hf_reg_tlv_t_46_handover_indication_readiness_timer, tvb, offset, ENC_BIG_ENDIAN);
590 break;
591
592 case DSx_UPLINK_FLOW:
593 /* display Uplink Service Flow Encodings info */
594 /* add subtree */
595 tlv_tree = add_protocol_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_mac_mgmt_msg_reg_req_decoder, tvb, offset, tlv_len, "Uplink Service Flow Encodings");
596 /* decode and display the DL Service Flow Encodings */
597 wimax_service_flow_encodings_decoder(tvb_new_subset_length(tvb, tlv_offset, tlv_len), pinfo, tlv_tree);
598 break;
599 case DSx_DOWNLINK_FLOW:
600 /* display Downlink Service Flow Encodings info */
601 /* add subtree */
602 tlv_tree = add_protocol_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_mac_mgmt_msg_reg_req_decoder, tvb, offset, tlv_len, "Downlink Service Flow Encodings");
603 /* decode and display the DL Service Flow Encodings */
604 wimax_service_flow_encodings_decoder(tvb_new_subset_length(tvb, tlv_offset, tlv_len), pinfo, tlv_tree);
605 break;
606 case HMAC_TUPLE: /* Table 348d */
607 /* decode and display the HMAC Tuple */
608 tlv_tree = add_protocol_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_mac_mgmt_msg_reg_req_decoder, tvb, offset, tlv_len, "HMAC Tuple");
609 wimax_hmac_tuple_decoder(tlv_tree, tvb, tlv_offset, tlv_len);
610 hmac_found = TRUE;
611 break;
612 case CMAC_TUPLE: /* Table 348b */
613 /* decode and display the CMAC Tuple */
614 tlv_tree = add_protocol_subtree(&tlv_info, ett_mac_mgmt_msg_reg_req_decoder, reg_req_tree, proto_mac_mgmt_msg_reg_req_decoder, tvb, offset, tlv_len, "CMAC Tuple");
615 wimax_cmac_tuple_decoder(tlv_tree, tvb, tlv_offset, tlv_len);
616 break;
617 default:
618 add_tlv_subtree(&tlv_info, reg_req_tree, hf_tlv_type, tvb, offset, ENC_NA);
619 break;
620 }
621 /* update the offset */
622 offset = tlv_len + tlv_offset;
623 } /* End while() looping through the tvb. */
624 if (!hmac_found)
625 proto_item_append_text(reg_req_tree, " (HMAC Tuple is missing !)");
626 }
627 }
628
629 /* Register Wimax Mac Payload Protocol and Dissector */
630 void proto_register_mac_mgmt_msg_reg_req(void)
631 {
632 /* REG-REQ fields display */
633 static hf_register_info hf[] =
634 {
635 {
636 &hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_dhcp,
637 {
638 "DHCP", "wmx.reg.alloc_sec_mgmt_dhcp",
639 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x01, NULL, HFILL
640 }
641 },
642 {
643 &hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_dhcpv6,
644 {
645 "DHCPv6", "wmx.reg.alloc_sec_mgmt_dhcpv6",
646 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x04, NULL, HFILL
647 }
648 },
649 {
650 &hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_ipv6,
651 {
652 "IPv6 Stateless Address Autoconfiguration", "wmx.reg.alloc_sec_mgmt_ipv6",
653 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x08, NULL, HFILL
654 }
655 },
656 {
657 &hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_mobile_ipv4,
658 {
659 "Mobile IPv4", "wmx.reg.alloc_sec_mgmt_mobile_ipv4",
660 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x02, NULL, HFILL
661 }
662 },
663 {
664 &hf_reg_method_for_allocating_ip_addr_sec_mgmt_conn_rsvd,
665 {
666 "Reserved", "wmx.reg.alloc_sec_mgmt_rsvd",
667 FT_UINT8, BASE_DEC, NULL, 0xF0, NULL, HFILL
668 }
669 },
670 {
671 &hf_reg_arq,
672 {
673 "ARQ support", "wmx.reg.arq",
674 FT_BOOLEAN, BASE_NONE, TFS(&tfs_supported), 0x0, NULL, HFILL
675 }
676 },
677 {
678 &hf_reg_tlv_t_40_arq_ack_type_cumulative_ack_entry,
679 {
680 "Cumulative ACK entry", "wmx.reg.arq_ack_type_cumulative_ack_entry",
681 FT_UINT8, BASE_DEC, NULL, 0x2, NULL, HFILL
682 }
683 },
684 {
685 &hf_reg_tlv_t_40_arq_ack_type_cumulative_ack_with_block_sequence_ack,
686 {
687 "Cumulative ACK with Block Sequence ACK", "wmx.reg.arq_ack_type_cumulative_ack_with_block_sequence_ack",
688 FT_UINT8, BASE_DEC, NULL, 0x8, NULL, HFILL
689 }
690 },
691 {
692 &hf_reg_tlv_t_40_arq_ack_type_cumulative_with_selective_ack_entry,
693 {
694 "Cumulative with Selective ACK entry", "wmx.reg.arq_ack_type_cumulative_with_selective_ack_entry",
695 FT_UINT8, BASE_DEC, NULL, 0x4, NULL, HFILL
696 }
697 },
698 {
699 &hf_reg_tlv_t_40_arq_ack_type_reserved,
700 {
701 "Reserved", "wmx.reg.arq_ack_type_reserved",
702 FT_UINT8, BASE_DEC, NULL, 0xf0, NULL, HFILL
703 }
704 },
705 {
706 &hf_reg_tlv_t_40_arq_ack_type_selective_ack_entry,
707 {
708 "Selective ACK entry", "wmx.reg.arq_ack_type_selective_ack_entry",
709 FT_UINT8, BASE_DEC, NULL, 0x1, NULL, HFILL
710 }
711 },
712 {
713 &hf_reg_tlv_t_43_bandwidth_request_cinr_report_header_support,
714 {
715 "Bandwidth request and CINR report header support", "wmx.reg.bandwidth_request_cinr_report_header_support",
716 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x2, NULL, HFILL
717 }
718 },
719 {
720 &hf_reg_tlv_t_43_bandwidth_request_ul_sleep_control_header_support,
721 {
722 "Bandwidth request and uplink sleep control header support", "wmx.reg.bandwidth_request_ul_sleep_control_header_support",
723 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x10, NULL, HFILL
724 }
725 },
726 {
727 &hf_reg_tlv_t_43_cqich_allocation_request_header_support,
728 {
729 "CQICH Allocation Request header support", "wmx.reg.cqich_allocation_request_header_support",
730 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x4, NULL, HFILL
731 }
732 },
733 {
734 &hf_reg_tlv_t_43_dl_sleep_control_extended_subheader,
735 {
736 "Downlink sleep control extended subheader", "wmx.reg.dl_sleep_control_extended_subheader",
737 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x800, NULL, HFILL
738 }
739 },
740 {
741 &hf_reg_dsx_flow_control,
742 {
743 "DSx flow control", "wmx.reg.dsx_flow_control",
744 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL
745 }
746 },
747 /* When REG-REQ TLV 7 is length 2 */
748 {
749 &hf_reg_encap_802_1q_2,
750 {
751 "Packet, 802.1Q VLAN", "wmx.reg.encap_802_1q",
752 FT_UINT16, BASE_HEX, NULL, 0x0010, NULL, HFILL
753 }
754 },
755 {
756 &hf_reg_encap_802_3_2,
757 {
758 "Packet, 802.3/Ethernet", "wmx.reg.encap_802_3",
759 FT_UINT16, BASE_HEX, NULL, 0x00000008, NULL, HFILL
760 }
761 },
762 {
763 &hf_reg_encap_atm_2,
764 {
765 "ATM", "wmx.reg.encap_atm",
766 FT_UINT16, BASE_HEX, NULL, 0x00000001, NULL, HFILL
767 }
768 },
769 {
770 &hf_reg_encap_ipv4_2,
771 {
772 "Packet, IPv4", "wmx.reg.encap_ipv4",
773 FT_UINT16, BASE_HEX, NULL, 0x00000002, NULL, HFILL
774 }
775 },
776 {
777 &hf_reg_encap_ipv6_2,
778 {
779 "Packet, IPv6", "wmx.reg.encap_ipv6",
780 FT_UINT16, BASE_HEX, NULL, 0x00000004, NULL, HFILL
781 }
782 },
783 {
784 &hf_reg_encap_ipv4_802_1q_2,
785 {
786 "Packet, IPv4 over 802.1Q VLAN", "wmx.reg.encap_ipv4_802_1q",
787 FT_UINT16, BASE_HEX, NULL, 0x00000080, NULL, HFILL
788 }
789 },
790 {
791 &hf_reg_encap_ipv4_802_3_2,
792 {
793 "Packet, IPv4 over 802.3/Ethernet", "wmx.reg.encap_ipv4_802_3",
794 FT_UINT16, BASE_HEX, NULL, 0x00000020, NULL, HFILL
795 }
796 },
797 {
798 &hf_reg_encap_ipv6_802_1q_2,
799 {
800 "Packet, IPv6 over 802.1Q VLAN", "wmx.reg.encap_ipv6_802_1q",
801 FT_UINT16, BASE_HEX, NULL, 0x00000100, NULL, HFILL
802 }
803 },
804 {
805 &hf_reg_encap_ipv6_802_3_2,
806 {
807 "Packet, IPv6 over 802.3/Ethernet", "wmx.reg.encap_ipv6_802_3",
808 FT_UINT16, BASE_HEX, NULL, 0x00000040, NULL, HFILL
809 }
810 },
811 {
812 &hf_reg_encap_packet_8023_ethernet_and_ecrtp_header_compression_2,
813 {
814 "Packet, 802.3/Ethernet (with optional 802.1Q VLAN tags) and ECRTP header compression", "wmx.reg.encap_packet_802_3_ethernet_and_ecrtp_header_compression",
815 FT_UINT16, BASE_HEX, NULL, 0x00000400, NULL, HFILL
816 }
817 },
818 {
819 &hf_reg_encap_packet_8023_ethernet_and_rohc_header_compression_2,
820 {
821 "Packet, 802.3/Ethernet (with optional 802.1Q VLAN tags) and ROHC header compression", "wmx.reg.encap_packet_802_3_ethernet_and_rohc_header_compression",
822 FT_UINT16, BASE_HEX, NULL, 0x00000200, NULL, HFILL
823 }
824 },
825 {
826 &hf_reg_encap_packet_ip_ecrtp_header_compression_2,
827 {
828 "Packet, IP (v4 or v6) with ECRTP header compression", "wmx.reg.encap_packet_ip_ecrtp_header_compression",
829 FT_UINT16, BASE_HEX, NULL, 0x00001000, NULL, HFILL
830 }
831 },
832 {
833 &hf_reg_encap_packet_ip_rohc_header_compression_2,
834 {
835 "Packet, IP (v4 or v6) with ROHC header compression", "wmx.reg.encap_packet_ip_rohc_header_compression",
836 FT_UINT16, BASE_HEX, NULL, 0x00000800, NULL, HFILL
837 }
838 },
839 {
840 &hf_reg_encap_rsvd_2,
841 {
842 "Reserved", "wmx.reg.encap_rsvd",
843 FT_UINT16, BASE_HEX, NULL, 0x0000E000, NULL, HFILL
844 }
845 },
846 /* When REG-REQ TLV 7 is length 4 */
847 {
848 &hf_reg_encap_802_1q_4,
849 {
850 "Packet, 802.1Q VLAN", "wmx.reg.encap_802_1q",
851 FT_UINT32, BASE_HEX, NULL, 0x0010, NULL, HFILL
852 }
853 },
854 {
855 &hf_reg_encap_802_3_4,
856 {
857 "Packet, 802.3/Ethernet", "wmx.reg.encap_802_3",
858 FT_UINT32, BASE_HEX, NULL, 0x00000008, NULL, HFILL
859 }
860 },
861 {
862 &hf_reg_encap_atm_4,
863 {
864 "ATM", "wmx.reg.encap_atm",
865 FT_UINT32, BASE_HEX, NULL, 0x00000001, NULL, HFILL
866 }
867 },
868 {
869 &hf_reg_encap_ipv4_4,
870 {
871 "Packet, IPv4", "wmx.reg.encap_ipv4",
872 FT_UINT32, BASE_HEX, NULL, 0x00000002, NULL, HFILL
873 }
874 },
875 {
876 &hf_reg_encap_ipv4_802_1q_4,
877 {
878 "Packet, IPv4 over 802.1Q VLAN", "wmx.reg.encap_ipv4_802_1q",
879 FT_UINT32, BASE_HEX, NULL, 0x00000080, NULL, HFILL
880 }
881 },
882 {
883 &hf_reg_encap_ipv4_802_3_4,
884 {
885 "Packet, IPv4 over 802.3/Ethernet", "wmx.reg.encap_ipv4_802_3",
886 FT_UINT32, BASE_HEX, NULL, 0x00000020, NULL, HFILL
887 }
888 },
889 {
890 &hf_reg_encap_ipv6_4,
891 {
892 "Packet, IPv6", "wmx.reg.encap_ipv6",
893 FT_UINT32, BASE_HEX, NULL, 0x00000004, NULL, HFILL
894 }
895 },
896 {
897 &hf_reg_encap_ipv6_802_1q_4,
898 {
899 "Packet, IPv6 over 802.1Q VLAN", "wmx.reg.encap_ipv6_802_1q",
900 FT_UINT32, BASE_HEX, NULL, 0x00000100, NULL, HFILL
901 }
902 },
903 {
904 &hf_reg_encap_ipv6_802_3_4,
905 {
906 "Packet, IPv6 over 802.3/Ethernet", "wmx.reg.encap_ipv6_802_3",
907 FT_UINT32, BASE_HEX, NULL, 0x00000040, NULL, HFILL
908 }
909 },
910 {
911 &hf_reg_encap_packet_8023_ethernet_and_ecrtp_header_compression_4,
912 {
913 "Packet, 802.3/Ethernet (with optional 802.1Q VLAN tags) and ECRTP header compression", "wmx.reg.encap_packet_802_3_ethernet_and_ecrtp_header_compression",
914 FT_UINT32, BASE_HEX, NULL, 0x00000400, NULL, HFILL
915 }
916 },
917 {
918 &hf_reg_encap_packet_8023_ethernet_and_rohc_header_compression_4,
919 {
920 "Packet, 802.3/Ethernet (with optional 802.1Q VLAN tags) and ROHC header compression", "wmx.reg.encap_packet_802_3_ethernet_and_rohc_header_compression",
921 FT_UINT32, BASE_HEX, NULL, 0x00000200, NULL, HFILL
922 }
923 },
924 {
925 &hf_reg_encap_packet_ip_ecrtp_header_compression_4,
926 {
927 "Packet, IP (v4 or v6) with ECRTP header compression", "wmx.reg.encap_packet_ip_ecrtp_header_compression",
928 FT_UINT32, BASE_HEX, NULL, 0x00001000, NULL, HFILL
929 }
930 },
931 {
932 &hf_reg_encap_packet_ip_rohc_header_compression_4,
933 {
934 "Packet, IP (v4 or v6) with ROHC header compression", "wmx.reg.encap_packet_ip_rohc_header_compression",
935 FT_UINT32, BASE_HEX, NULL, 0x00000800, NULL, HFILL
936 }
937 },
938 {
939 &hf_reg_encap_rsvd_4,
940 {
941 "Reserved", "wmx.reg.encap_rsvd",
942 FT_UINT32, BASE_HEX, NULL, 0xFFFFE000, NULL, HFILL
943 }
944 },
945 {
946 &hf_reg_tlv_t_22_mac_extended_rtps_support,
947 {
948 "MAC extended rtPS support", "wmx.reg.ext_rtps_support",
949 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x01, NULL, HFILL
950 }
951 },
952 {
953 &hf_reg_tlv_t_27_handover_fbss_mdho_dl_rf_monitoring_maps,
954 {
955 "FBSS/MDHO DL RF Combining with monitoring MAPs from active BSs", "wmx.reg.fbss_mdho_dl_rf_combining",
956 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x02, NULL, HFILL
957 }
958 },
959 {
960 &hf_reg_tlv_t_43_bandwidth_request_ul_tx_power_report_header_support,
961 {
962 "Bandwidth request and UL Tx Power Report header support",
963 "wimax.reg.bandwidth_request_ul_tx_pwr_report_header_support",
964 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x1, NULL, HFILL
965 }
966 },
967 {
968 &hf_reg_tlv_t_27_handover_fbss_mdho_ho_disable,
969 {
970 "MDHO/FBSS HO. BS ignore all other bits when set to 1", "wmx.reg.fbss_mdho_ho_disable",
971 FT_BOOLEAN, 8, TFS(&tfs_reg_fbss_mdho_ho_disable), 0x01, NULL, HFILL
972 }
973 },
974 {
975 &hf_reg_tlv_t_43_feedback_header_support,
976 {
977 "Feedback header support", "wmx.reg.feedback_header_support",
978 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x40, NULL, HFILL
979 }
980 },
981 {
982 &hf_reg_tlv_t_43_feedback_request_extended_subheader,
983 {
984 "Feedback request extended subheader", "wmx.reg.feedback_request_extended_subheader",
985 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x1000, NULL, HFILL
986 }
987 },
988 {
989 &hf_reg_tlv_t_46_handover_indication_readiness_timer,
990 {
991 "Handover indication readiness timer", "wmx.reg.handover_indication_readiness_timer",
992 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL
993 }
994 },
995 {
996 &hf_reg_tlv_t_27_handover_reserved,
997 {
998 "Reserved", "wmx.reg.handover_reserved",
999 FT_UINT8, BASE_DEC, NULL, 0xE0, NULL, HFILL
1000 }
1001 },
1002 {
1003 &hf_reg_tlv_t_41_ho_connections_param_processing_time,
1004 {
1005 "MS HO connections parameters processing time", "wmx.reg.ho_connections_param_processing_time",
1006 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL
1007 }
1008 },
1009 {
1010 &hf_reg_tlv_t_29_ho_process_opt_ms_timer,
1011 {
1012 "HO Process Optimization MS Timer", "wmx.reg.ho_process_opt_ms_timer",
1013 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL
1014 }
1015 },
1016 {
1017 &hf_reg_tlv_t_42_ho_tek_processing_time,
1018 {
1019 "MS HO TEK processing time", "wmx.reg.ho_tek_processing_time",
1020 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL
1021 }
1022 },
1023 {
1024 &hf_idle_mode_timeout,
1025 {
1026 "Idle Mode Timeout", "wmx.reg.idle_mode_timeout",
1027 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL
1028 }
1029 },
1030 {
1031 &hf_reg_ip_mgmt_mode,
1032 {
1033 "IP management mode", "wmx.reg.ip_mgmt_mode",
1034 FT_BOOLEAN, BASE_NONE, TFS(&tfs_reg_ip_mgmt_mode), 0x0, NULL, HFILL
1035 }
1036 },
1037 {
1038 &hf_reg_ip_version,
1039 {
1040 "IP version", "wmx.reg.ip_version",
1041 FT_UINT8, BASE_HEX, VALS(vals_reg_ip_version), 0x0, NULL, HFILL
1042 }
1043 },
1044 {
1045 &hf_reg_mac_address,
1046 {
1047 "MAC Address of the SS", "wmx.reg.mac_address",
1048 FT_ETHER, BASE_NONE, NULL, 0x0, NULL, HFILL
1049 }
1050 },
1051 {
1052 &hf_reg_mac_crc_support,
1053 {
1054 "MAC CRC", "wmx.reg.mac_crc_support",
1055 FT_BOOLEAN, BASE_NONE, TFS(&tfs_mac_crc_support), 0x0, NULL, HFILL
1056 }
1057 },
1058 {
1059 &hf_reg_max_classifiers,
1060 {
1061 "Maximum number of classification rules", "wmx.reg.max_classifiers",
1062 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL
1063 }
1064 },
1065 {
1066 &hf_reg_tlv_t_23_max_num_bursts_concurrently_to_the_ms,
1067 {
1068 "Maximum number of bursts transmitted concurrently to the MS", "wmx.reg.max_num_bursts_to_ms",
1069 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL
1070 }
1071 },
1072 {
1073 &hf_reg_mca_flow_control,
1074 {
1075 "MCA flow control", "wmx.reg.mca_flow_control",
1076 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL
1077 }
1078 },
1079 {
1080 &hf_reg_mcast_polling_cids,
1081 {
1082 "Multicast polling group CID support", "wmx.reg.mcast_polling_cids",
1083 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL
1084 }
1085 },
1086 {
1087 &hf_reg_tlv_t_27_handover_mdho_ul_multiple,
1088 {
1089 "MDHO UL Multiple transmission", "wmx.reg.mdh_ul_multiple",
1090 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x10, NULL, HFILL
1091 }
1092 },
1093 {
1094 &hf_reg_tlv_t_27_handover_mdho_dl_monitoring_maps,
1095 {
1096 "MDHO DL soft combining with monitoring MAPs from active BSs", "wmx.reg.mdho_dl_monitor_maps",
1097 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x08, NULL, HFILL
1098 }
1099 },
1100 {
1101 &hf_reg_tlv_t_27_handover_mdho_dl_monitoring_single_map,
1102 {
1103 "MDHO DL soft Combining with monitoring single MAP from anchor BS", "wmx.reg.mdho_dl_monitor_single_map",
1104 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x04, NULL, HFILL
1105 }
1106 },
1107 {
1108 &hf_reg_tlv_t_43_mimo_mode_feedback_extended_subheader,
1109 {
1110 "MIMO mode feedback request extended subheader", "wmx.reg.mimo_mode_feedback_request_extended_subheader",
1111 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x2000, NULL, HFILL
1112 }
1113 },
1114 {
1115 &hf_reg_tlv_t_43_mini_feedback_extended_subheader,
1116 {
1117 "Mini-feedback extended subheader", "wmx.reg.mini_feedback_extended_subheader",
1118 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x8000, NULL, HFILL
1119 }
1120 },
1121 {
1122 &hf_reg_tlv_t_31_mobility_handover,
1123 {
1124 "Mobility (handover)", "wmx.reg.mobility_handover",
1125 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x01, NULL, HFILL
1126 }
1127 },
1128 {
1129 &hf_reg_tlv_t_31_mobility_idle_mode,
1130 {
1131 "Idle mode", "wmx.reg.mobility_idle_mode",
1132 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x04, NULL, HFILL
1133 }
1134 },
1135 {
1136 &hf_reg_tlv_t_31_mobility_sleep_mode,
1137 {
1138 "Sleep mode", "wmx.reg.mobility_sleep_mode",
1139 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x02, NULL, HFILL
1140 }
1141 },
1142 {
1143 &hf_reg_num_dl_trans_cid,
1144 {
1145 "Number of Downlink transport CIDs the SS can support", "wmx.reg.dl_cids_supported",
1146 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL
1147 }
1148 },
1149 {
1150 &hf_reg_tlv_t_21_packing_support,
1151 {
1152 "Packing support", "wmx.reg.packing.support",
1153 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x01, NULL, HFILL
1154 }
1155 },
1156 {
1157 &hf_reg_tlv_t_43_pdu_sn_long_extended_subheader,
1158 {
1159 "PDU SN (long) extended subheader", "wmx.reg.pdu_sn_long_extended_subheader",
1160 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x40000, NULL, HFILL
1161 }
1162 },
1163 {
1164 &hf_reg_tlv_t_43_pdu_sn_short_extended_subheader,
1165 {
1166 "PDU SN (short) extended subheader", "wmx.reg.pdu_sn_short_extended_subheader",
1167 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x20000, NULL, HFILL
1168 }
1169 },
1170 {
1171 &hf_reg_phs,
1172 {
1173 "PHS support", "wmx.reg.phs",
1174 FT_UINT8, BASE_DEC, VALS(vals_reg_phs_support), 0x0, NULL, HFILL
1175 }
1176 },
1177 {
1178 &hf_reg_tlv_t_43_phy_channel_report_header_support,
1179 {
1180 "PHY channel report header support", "wmx.reg.phy_channel_report_header_support",
1181 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x8, NULL, HFILL
1182 }
1183 },
1184 {
1185 &hf_reg_tlv_t_43_reserved,
1186 {
1187 "Reserved", "wmx.reg.reserved",
1188 FT_UINT24, BASE_DEC, NULL, 0xf80000, NULL, HFILL
1189 }
1190 },
1191 {
1192 &hf_reg_tlv_t_43_sdu_sn_extended_subheader_support_and_parameter,
1193 {
1194 "SDU_SN extended subheader support", "wmx.reg.sdu_sn_extended_subheader_support",
1195 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x80, NULL, HFILL
1196 }
1197 },
1198 {
1199 &hf_reg_tlv_t_43_sdu_sn_parameter,
1200 {
1201 "SDU_SN parameter", "wmx.reg.sdu_sn_parameter",
1202 FT_UINT24, BASE_DEC, NULL, 0x700, NULL, HFILL
1203 }
1204 },
1205 {
1206 &hf_reg_tlv_t_43_sn_report_header_support,
1207 {
1208 "SN report header support", "wmx.reg.sn_report_header_support",
1209 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x20, NULL, HFILL
1210 }
1211 },
1212 {
1213 &hf_reg_tlv_t_43_sn_request_extended_subheader,
1214 {
1215 "SN request extended subheader", "wmx.reg.sn_request_extended_subheader",
1216 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x10000, NULL, HFILL
1217 }
1218 },
1219 {
1220 &hf_reg_ss_mgmt_support,
1221 {
1222 "SS management support", "wmx.reg.ss_mgmt_support",
1223 FT_BOOLEAN, BASE_NONE, TFS(&tfs_reg_ss_mgmt_support), 0x0, NULL, HFILL
1224 }
1225 },
1226 {
1227 &hf_reg_ul_cids,
1228 {
1229 "Number of Uplink transport CIDs the SS can support", "wmx.reg.ul_cids_supported",
1230 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL
1231 }
1232 },
1233 {
1234 &hf_reg_tlv_t_43_ul_tx_power_report_extended_subheader,
1235 {
1236 "UL Tx power report extended subheader", "wmx.reg.ul_tx_power_report_extended_subheader",
1237 FT_UINT24, BASE_DEC, VALS(tfs_support), 0x4000, NULL, HFILL
1238 }
1239 },
1240 {
1241 &hf_tlv_type,
1242 {
1243 "Unknown TLV Type", "wmx.reg.unknown_tlv_type",
1244 FT_BYTES, BASE_NONE, NULL, 0x00, NULL, HFILL
1245 }
1246 },
1247 {
1248 &hf_reg_invalid_tlv,
1249 {
1250 "Invalid TLV", "wmx.reg_req.invalid_tlv",
1251 FT_BYTES, BASE_NONE, NULL, 0, NULL, HFILL
1252 }
1253 },
1254 {
1255 &hf_reg_tlv_t_20_1_max_mac_level_data_per_dl_frame,
1256 {
1257 "Maximum MAC level DL data per frame", "wmx.reg_req.max_mac_dl_data",
1258 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL
1259 }
1260 },
1261 {
1262 &hf_reg_tlv_t_20_2_max_mac_level_data_per_ul_frame,
1263 {
1264 "Maximum MAC level UL data per frame", "wmx.reg_req.max_mac_ul_data",
1265 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL
1266 }
1267 },
1268 {
1269 &hf_reg_req_min_time_for_inter_fa,
1270 {
1271 "Minimum time for inter-FA HO, default=3", "wmx.reg_req.min_time_for_inter_fa",
1272 FT_UINT8, BASE_HEX, NULL, 0xF0, NULL, HFILL
1273 }
1274 },
1275 {
1276 &hf_reg_req_min_time_for_intra_fa,
1277 {
1278 "Minimum time for intra-FA HO, default=2", "wmx.reg_req.min_time_for_intra_fa",
1279 FT_UINT8, BASE_HEX, NULL, 0x0F, NULL, HFILL
1280 }
1281 },
1282 {
1283 &hf_reg_req_tlv_t_45_ms_periodic_ranging_timer,
1284 {
1285 "MS periodic ranging timer information", "wmx.reg_req.ms_periodic_ranging_timer_info",
1286 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL
1287 }
1288 },
1289 { /* IPv4 Mask */
1290 &hf_ms_previous_ip_address_v4,
1291 {
1292 "MS Previous IP address", "wmx.reg_req.ms_prev_ip_addr_v4",
1293 FT_IPv4, BASE_NONE, NULL, 0x0, NULL, HFILL
1294 }
1295 },
1296 { /* IPv6 Source Address */
1297 &hf_ms_previous_ip_address_v6,
1298 {
1299 "MS Previous IP address", "wmx.reg_req.ms_prev_ip_addr_v6",
1300 FT_IPv6, BASE_NONE, NULL, 0x0, NULL, HFILL
1301 }
1302 },
1303 {
1304 &hf_reg_req_secondary_mgmt_cid,
1305 {
1306 "Secondary Management CID", "wmx.reg_req.secondary_mgmt_cid",
1307 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL
1308 }
1309 },
1310 {
1311 &hf_reg_req_tlv_t_32_sleep_mode_recovery_time,
1312 {
1313 "Frames required for the MS to switch from sleep to awake-mode", "wmx.reg_req.sleep_recovery",
1314 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL
1315 }
1316 },
1317 {
1318 &hf_reg_power_saving_class_type_i,
1319 {
1320 "Power saving class type I supported", "wmx.reg.power_saving_class_type_i",
1321 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x01, NULL, HFILL
1322 }
1323 },
1324 {
1325 &hf_reg_power_saving_class_type_ii,
1326 {
1327 "Power saving class type II supported", "wmx.reg.power_saving_class_type_ii",
1328 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x02, NULL, HFILL
1329 }
1330 },
1331 {
1332 &hf_reg_power_saving_class_type_iii,
1333 {
1334 "Power saving class type III supported", "wmx.reg.power_saving_class_type_iii",
1335 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x04, NULL, HFILL
1336 }
1337 },
1338 {
1339 &hf_reg_multi_active_power_saving_classes,
1340 {
1341 "Multiple active power saving classes supported", "wmx.reg.multi_active_power_saving_classes",
1342 FT_BOOLEAN, 8, TFS(&tfs_supported), 0x08, NULL, HFILL
1343 }
1344 },
1345 {
1346 &hf_reg_total_power_saving_class_instances,
1347 {
1348 "Total number of power saving class instances of all", "wmx.reg_req.total_power_saving_class_instances",
1349 FT_UINT16, BASE_DEC, NULL, 0x1F0, NULL, HFILL
1350 }
1351 },
1352 {
1353 &hf_reg_power_saving_class_reserved,
1354 {
1355 "Reserved", "wmx.reg.reserved",
1356 FT_UINT16, BASE_DEC, NULL, 0xFE00, NULL, HFILL
1357 }
1358 },
1359 {
1360 &hf_reg_power_saving_class_capability,
1361 {
1362 "Power saving class capability", "wmx.reg.power_saving_class_capability",
1363 FT_UINT16, BASE_DEC, NULL, 0x0, NULL, HFILL
1364 }
1365 },
1366 {
1367 &hf_reg_ip_phs_sdu_encap,
1368 {
1369 "Classification/PHS options and SDU encapsulation support", "wmx.reg.ip_phs_sdu_encap",
1370 FT_UINT32, BASE_HEX, NULL, 0x0, NULL, HFILL
1371 }
1372 },
1373 {
1374 &hf_reg_tlv_t_26_method_alloc_ip_addr_secondary_mgmnt_conn,
1375 {
1376 "Method for allocating IP address for the secondary management connection", "wmx.reg.method_alloc_ip_addr_secondary_mgmnt_conn",
1377 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL
1378 }
1379 },
1380 {
1381 &hf_reg_tlv_t_27_handover_supported,
1382 {
1383 "Handover Support", "wmx.reg.handover_supported",
1384 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL
1385 }
1386 },
1387 {
1388 &hf_reg_tlv_t_31_mobility_features_supported,
1389 {
1390 "Mobility Features Supported", "wmx.reg.mobility_features_supported",
1391 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL
1392 }
1393 },
1394 {
1395 &hf_reg_tlv_t_40_arq_ack_type,
1396 {
1397 "ARQ ACK Type", "wmx.reg.arq_ack_type",
1398 FT_UINT8, BASE_HEX, NULL, 0x0, NULL, HFILL
1399 }
1400 },
1401 {
1402 &hf_reg_tlv_t_43_mac_header_ext_header_support,
1403 {
1404 "MAC header and extended subheader support", "wmx.reg.mac_header_ext_header_support",
1405 FT_UINT24, BASE_DEC, NULL, 0x0, NULL, HFILL
1406 }
1407 },
1408 {
1409 &hf_reg_req_bs_switching_timer,
1410 {
1411 "BS switching timer", "wmx.reg.bs_switching_timer",
1412 FT_UINT8, BASE_DEC, NULL, 0x0, NULL, HFILL
1413 }
1414 },
1415 };
1416
1417 /* Setup protocol subtree array */
1418 static gint *ett[] =
1419 {
1420 &ett_mac_mgmt_msg_reg_req_decoder
1421 };
1422
1423
1424 proto_mac_mgmt_msg_reg_req_decoder = proto_register_protocol (
1425 "WiMax REG-REQ Messages", /* name */
1426 "WiMax REG-REQ", /* short name */
1427 "wmx.reg_req" /* abbrev */
1428 );
1429
1430 proto_register_field_array(proto_mac_mgmt_msg_reg_req_decoder, hf, array_length(hf));
1431 proto_register_subtree_array(ett, array_length(ett));
1432 }
1433
1434 void proto_reg_handoff_mac_mgmt_msg_reg_req(void)
1435 {
1436 dissector_handle_t reg_req_handle;
1437
1438 reg_req_handle = create_dissector_handle(dissect_mac_mgmt_msg_reg_req_decoder, proto_mac_mgmt_msg_reg_req_decoder);
1439 dissector_add_uint("wmx.mgmtmsg", MAC_MGMT_MSG_REG_REQ, reg_req_handle);
1440 }