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Merge master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
[wrt350n-kernel.git] / drivers / video / pm2fb.c
blob5fe197943deb4a1c1deea3fa3b71e716a93265b0
1 /*
2 * Permedia2 framebuffer driver.
3 *
4 * 2.5/2.6 driver:
5 * Copyright (c) 2003 Jim Hague (jim.hague@acm.org)
6 *
7 * based on 2.4 driver:
8 * Copyright (c) 1998-2000 Ilario Nardinocchi (nardinoc@CS.UniBO.IT)
9 * Copyright (c) 1999 Jakub Jelinek (jakub@redhat.com)
10 *
11 * and additional input from James Simmon's port of Hannu Mallat's tdfx
12 * driver.
13 *
14 * I have a Creative Graphics Blaster Exxtreme card - pm2fb on x86. I
15 * have no access to other pm2fb implementations. Sparc (and thus
16 * hopefully other big-endian) devices now work, thanks to a lot of
17 * testing work by Ron Murray. I have no access to CVision hardware,
18 * and therefore for now I am omitting the CVision code.
19 *
20 * Multiple boards support has been on the TODO list for ages.
21 * Don't expect this to change.
22 *
23 * This file is subject to the terms and conditions of the GNU General Public
24 * License. See the file COPYING in the main directory of this archive for
25 * more details.
26 *
27 *
28 */
29
30 #include <linux/config.h>
31 #include <linux/module.h>
32 #include <linux/moduleparam.h>
33 #include <linux/kernel.h>
34 #include <linux/errno.h>
35 #include <linux/string.h>
36 #include <linux/mm.h>
37 #include <linux/tty.h>
38 #include <linux/slab.h>
39 #include <linux/delay.h>
40 #include <linux/fb.h>
41 #include <linux/init.h>
42 #include <linux/pci.h>
43
44 #include <video/permedia2.h>
45 #include <video/cvisionppc.h>
46
47 #if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN)
48 #error "The endianness of the target host has not been defined."
49 #endif
50
51 #if !defined(CONFIG_PCI)
52 #error "Only generic PCI cards supported."
53 #endif
54
55 #undef PM2FB_MASTER_DEBUG
56 #ifdef PM2FB_MASTER_DEBUG
57 #define DPRINTK(a,b...) printk(KERN_DEBUG "pm2fb: %s: " a, __FUNCTION__ , ## b)
58 #else
59 #define DPRINTK(a,b...)
60 #endif
61
62 /*
63 * Driver data
64 */
65 static char *mode __devinitdata = NULL;
66
67 /*
68 * The XFree GLINT driver will (I think to implement hardware cursor
69 * support on TVP4010 and similar where there is no RAMDAC - see
70 * comment in set_video) always request +ve sync regardless of what
71 * the mode requires. This screws me because I have a Sun
72 * fixed-frequency monitor which absolutely has to have -ve sync. So
73 * these flags allow the user to specify that requests for +ve sync
74 * should be silently turned in -ve sync.
75 */
76 static int lowhsync __devinitdata = 0;
77 static int lowvsync __devinitdata = 0;
78
79 /*
80 * The hardware state of the graphics card that isn't part of the
81 * screeninfo.
82 */
83 struct pm2fb_par
84 {
85 pm2type_t type; /* Board type */
86 u32 fb_size; /* framebuffer memory size */
87 unsigned char __iomem *v_fb; /* virtual address of frame buffer */
88 unsigned char __iomem *v_regs;/* virtual address of p_regs */
89 u32 memclock; /* memclock */
90 u32 video; /* video flags before blanking */
91 u32 mem_config; /* MemConfig reg at probe */
92 u32 mem_control; /* MemControl reg at probe */
93 u32 boot_address; /* BootAddress reg at probe */
94 u32 palette[16];
95 };
96
97 /*
98 * Here we define the default structs fb_fix_screeninfo and fb_var_screeninfo
99 * if we don't use modedb.
100 */
101 static struct fb_fix_screeninfo pm2fb_fix __devinitdata = {
102 .id = "",
103 .type = FB_TYPE_PACKED_PIXELS,
104 .visual = FB_VISUAL_PSEUDOCOLOR,
105 .xpanstep = 1,
106 .ypanstep = 1,
107 .ywrapstep = 0,
108 .accel = FB_ACCEL_NONE,
109 };
110
111 /*
112 * Default video mode. In case the modedb doesn't work.
113 */
114 static struct fb_var_screeninfo pm2fb_var __devinitdata = {
115 /* "640x480, 8 bpp @ 60 Hz */
116 .xres = 640,
117 .yres = 480,
118 .xres_virtual = 640,
119 .yres_virtual = 480,
120 .bits_per_pixel =8,
121 .red = {0, 8, 0},
122 .blue = {0, 8, 0},
123 .green = {0, 8, 0},
124 .activate = FB_ACTIVATE_NOW,
125 .height = -1,
126 .width = -1,
127 .accel_flags = 0,
128 .pixclock = 39721,
129 .left_margin = 40,
130 .right_margin = 24,
131 .upper_margin = 32,
132 .lower_margin = 11,
133 .hsync_len = 96,
134 .vsync_len = 2,
135 .vmode = FB_VMODE_NONINTERLACED
136 };
137
138 /*
139 * Utility functions
140 */
141
142 static inline u32 RD32(unsigned char __iomem *base, s32 off)
143 {
144 return fb_readl(base + off);
145 }
146
147 static inline void WR32(unsigned char __iomem *base, s32 off, u32 v)
148 {
149 fb_writel(v, base + off);
150 }
151
152 static inline u32 pm2_RD(struct pm2fb_par* p, s32 off)
153 {
154 return RD32(p->v_regs, off);
155 }
156
157 static inline void pm2_WR(struct pm2fb_par* p, s32 off, u32 v)
158 {
159 WR32(p->v_regs, off, v);
160 }
161
162 static inline u32 pm2_RDAC_RD(struct pm2fb_par* p, s32 idx)
163 {
164 int index = PM2R_RD_INDEXED_DATA;
165 switch (p->type) {
166 case PM2_TYPE_PERMEDIA2:
167 pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, idx);
168 break;
169 case PM2_TYPE_PERMEDIA2V:
170 pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff);
171 index = PM2VR_RD_INDEXED_DATA;
172 break;
173 }
174 mb();
175 return pm2_RD(p, index);
176 }
177
178 static inline void pm2_RDAC_WR(struct pm2fb_par* p, s32 idx, u32 v)
179 {
180 int index = PM2R_RD_INDEXED_DATA;
181 switch (p->type) {
182 case PM2_TYPE_PERMEDIA2:
183 pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, idx);
184 break;
185 case PM2_TYPE_PERMEDIA2V:
186 pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff);
187 index = PM2VR_RD_INDEXED_DATA;
188 break;
189 }
190 mb();
191 pm2_WR(p, index, v);
192 }
193
194 static inline void pm2v_RDAC_WR(struct pm2fb_par* p, s32 idx, u32 v)
195 {
196 pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff);
197 mb();
198 pm2_WR(p, PM2VR_RD_INDEXED_DATA, v);
199 }
200
201 #ifdef CONFIG_FB_PM2_FIFO_DISCONNECT
202 #define WAIT_FIFO(p,a)
203 #else
204 static inline void WAIT_FIFO(struct pm2fb_par* p, u32 a)
205 {
206 while( pm2_RD(p, PM2R_IN_FIFO_SPACE) < a );
207 mb();
208 }
209 #endif
210
211 /*
212 * partial products for the supported horizontal resolutions.
213 */
214 #define PACKPP(p0,p1,p2) (((p2) << 6) | ((p1) << 3) | (p0))
215 static const struct {
216 u16 width;
217 u16 pp;
218 } pp_table[] = {
219 { 32, PACKPP(1, 0, 0) }, { 64, PACKPP(1, 1, 0) },
220 { 96, PACKPP(1, 1, 1) }, { 128, PACKPP(2, 1, 1) },
221 { 160, PACKPP(2, 2, 1) }, { 192, PACKPP(2, 2, 2) },
222 { 224, PACKPP(3, 2, 1) }, { 256, PACKPP(3, 2, 2) },
223 { 288, PACKPP(3, 3, 1) }, { 320, PACKPP(3, 3, 2) },
224 { 384, PACKPP(3, 3, 3) }, { 416, PACKPP(4, 3, 1) },
225 { 448, PACKPP(4, 3, 2) }, { 512, PACKPP(4, 3, 3) },
226 { 544, PACKPP(4, 4, 1) }, { 576, PACKPP(4, 4, 2) },
227 { 640, PACKPP(4, 4, 3) }, { 768, PACKPP(4, 4, 4) },
228 { 800, PACKPP(5, 4, 1) }, { 832, PACKPP(5, 4, 2) },
229 { 896, PACKPP(5, 4, 3) }, { 1024, PACKPP(5, 4, 4) },
230 { 1056, PACKPP(5, 5, 1) }, { 1088, PACKPP(5, 5, 2) },
231 { 1152, PACKPP(5, 5, 3) }, { 1280, PACKPP(5, 5, 4) },
232 { 1536, PACKPP(5, 5, 5) }, { 1568, PACKPP(6, 5, 1) },
233 { 1600, PACKPP(6, 5, 2) }, { 1664, PACKPP(6, 5, 3) },
234 { 1792, PACKPP(6, 5, 4) }, { 2048, PACKPP(6, 5, 5) },
235 { 0, 0 } };
236
237 static u32 partprod(u32 xres)
238 {
239 int i;
240
241 for (i = 0; pp_table[i].width && pp_table[i].width != xres; i++)
242 ;
243 if ( pp_table[i].width == 0 )
244 DPRINTK("invalid width %u\n", xres);
245 return pp_table[i].pp;
246 }
247
248 static u32 to3264(u32 timing, int bpp, int is64)
249 {
250 switch (bpp) {
251 case 8:
252 timing >>= 2 + is64;
253 break;
254 case 16:
255 timing >>= 1 + is64;
256 break;
257 case 24:
258 timing = (timing * 3) >> (2 + is64);
259 break;
260 case 32:
261 if (is64)
262 timing >>= 1;
263 break;
264 }
265 return timing;
266 }
267
268 static void pm2_mnp(u32 clk, unsigned char* mm, unsigned char* nn,
269 unsigned char* pp)
270 {
271 unsigned char m;
272 unsigned char n;
273 unsigned char p;
274 u32 f;
275 s32 curr;
276 s32 delta = 100000;
277
278 *mm = *nn = *pp = 0;
279 for (n = 2; n < 15; n++) {
280 for (m = 2; m; m++) {
281 f = PM2_REFERENCE_CLOCK * m / n;
282 if (f >= 150000 && f <= 300000) {
283 for ( p = 0; p < 5; p++, f >>= 1) {
284 curr = ( clk > f ) ? clk - f : f - clk;
285 if ( curr < delta ) {
286 delta=curr;
287 *mm=m;
288 *nn=n;
289 *pp=p;
290 }
291 }
292 }
293 }
294 }
295 }
296
297 static void pm2v_mnp(u32 clk, unsigned char* mm, unsigned char* nn,
298 unsigned char* pp)
299 {
300 unsigned char m;
301 unsigned char n;
302 unsigned char p;
303 u32 f;
304 s32 delta = 1000;
305
306 *mm = *nn = *pp = 0;
307 for (n = 1; n; n++) {
308 for ( m = 1; m; m++) {
309 for ( p = 0; p < 2; p++) {
310 f = PM2_REFERENCE_CLOCK * n / (m * (1 << (p + 1)));
311 if ( clk > f - delta && clk < f + delta ) {
312 delta = ( clk > f ) ? clk - f : f - clk;
313 *mm=m;
314 *nn=n;
315 *pp=p;
316 }
317 }
318 }
319 }
320 }
321
322 static void clear_palette(struct pm2fb_par* p) {
323 int i=256;
324
325 WAIT_FIFO(p, 1);
326 pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, 0);
327 wmb();
328 while (i--) {
329 WAIT_FIFO(p, 3);
330 pm2_WR(p, PM2R_RD_PALETTE_DATA, 0);
331 pm2_WR(p, PM2R_RD_PALETTE_DATA, 0);
332 pm2_WR(p, PM2R_RD_PALETTE_DATA, 0);
333 }
334 }
335
336 static void reset_card(struct pm2fb_par* p)
337 {
338 if (p->type == PM2_TYPE_PERMEDIA2V)
339 pm2_WR(p, PM2VR_RD_INDEX_HIGH, 0);
340 pm2_WR(p, PM2R_RESET_STATUS, 0);
341 mb();
342 while (pm2_RD(p, PM2R_RESET_STATUS) & PM2F_BEING_RESET)
343 ;
344 mb();
345 #ifdef CONFIG_FB_PM2_FIFO_DISCONNECT
346 DPRINTK("FIFO disconnect enabled\n");
347 pm2_WR(p, PM2R_FIFO_DISCON, 1);
348 mb();
349 #endif
350
351 /* Restore stashed memory config information from probe */
352 WAIT_FIFO(p, 3);
353 pm2_WR(p, PM2R_MEM_CONTROL, p->mem_control);
354 pm2_WR(p, PM2R_BOOT_ADDRESS, p->boot_address);
355 wmb();
356 pm2_WR(p, PM2R_MEM_CONFIG, p->mem_config);
357 }
358
359 static void reset_config(struct pm2fb_par* p)
360 {
361 WAIT_FIFO(p, 52);
362 pm2_WR(p, PM2R_CHIP_CONFIG, pm2_RD(p, PM2R_CHIP_CONFIG)&
363 ~(PM2F_VGA_ENABLE|PM2F_VGA_FIXED));
364 pm2_WR(p, PM2R_BYPASS_WRITE_MASK, ~(0L));
365 pm2_WR(p, PM2R_FRAMEBUFFER_WRITE_MASK, ~(0L));
366 pm2_WR(p, PM2R_FIFO_CONTROL, 0);
367 pm2_WR(p, PM2R_APERTURE_ONE, 0);
368 pm2_WR(p, PM2R_APERTURE_TWO, 0);
369 pm2_WR(p, PM2R_RASTERIZER_MODE, 0);
370 pm2_WR(p, PM2R_DELTA_MODE, PM2F_DELTA_ORDER_RGB);
371 pm2_WR(p, PM2R_LB_READ_FORMAT, 0);
372 pm2_WR(p, PM2R_LB_WRITE_FORMAT, 0);
373 pm2_WR(p, PM2R_LB_READ_MODE, 0);
374 pm2_WR(p, PM2R_LB_SOURCE_OFFSET, 0);
375 pm2_WR(p, PM2R_FB_SOURCE_OFFSET, 0);
376 pm2_WR(p, PM2R_FB_PIXEL_OFFSET, 0);
377 pm2_WR(p, PM2R_FB_WINDOW_BASE, 0);
378 pm2_WR(p, PM2R_LB_WINDOW_BASE, 0);
379 pm2_WR(p, PM2R_FB_SOFT_WRITE_MASK, ~(0L));
380 pm2_WR(p, PM2R_FB_HARD_WRITE_MASK, ~(0L));
381 pm2_WR(p, PM2R_FB_READ_PIXEL, 0);
382 pm2_WR(p, PM2R_DITHER_MODE, 0);
383 pm2_WR(p, PM2R_AREA_STIPPLE_MODE, 0);
384 pm2_WR(p, PM2R_DEPTH_MODE, 0);
385 pm2_WR(p, PM2R_STENCIL_MODE, 0);
386 pm2_WR(p, PM2R_TEXTURE_ADDRESS_MODE, 0);
387 pm2_WR(p, PM2R_TEXTURE_READ_MODE, 0);
388 pm2_WR(p, PM2R_TEXEL_LUT_MODE, 0);
389 pm2_WR(p, PM2R_YUV_MODE, 0);
390 pm2_WR(p, PM2R_COLOR_DDA_MODE, 0);
391 pm2_WR(p, PM2R_TEXTURE_COLOR_MODE, 0);
392 pm2_WR(p, PM2R_FOG_MODE, 0);
393 pm2_WR(p, PM2R_ALPHA_BLEND_MODE, 0);
394 pm2_WR(p, PM2R_LOGICAL_OP_MODE, 0);
395 pm2_WR(p, PM2R_STATISTICS_MODE, 0);
396 pm2_WR(p, PM2R_SCISSOR_MODE, 0);
397 pm2_WR(p, PM2R_FILTER_MODE, PM2F_SYNCHRONIZATION);
398 switch (p->type) {
399 case PM2_TYPE_PERMEDIA2:
400 pm2_RDAC_WR(p, PM2I_RD_MODE_CONTROL, 0); /* no overlay */
401 pm2_RDAC_WR(p, PM2I_RD_CURSOR_CONTROL, 0);
402 pm2_RDAC_WR(p, PM2I_RD_MISC_CONTROL, PM2F_RD_PALETTE_WIDTH_8);
403 break;
404 case PM2_TYPE_PERMEDIA2V:
405 pm2v_RDAC_WR(p, PM2VI_RD_MISC_CONTROL, 1); /* 8bit */
406 break;
407 }
408 pm2_RDAC_WR(p, PM2I_RD_COLOR_KEY_CONTROL, 0);
409 pm2_RDAC_WR(p, PM2I_RD_OVERLAY_KEY, 0);
410 pm2_RDAC_WR(p, PM2I_RD_RED_KEY, 0);
411 pm2_RDAC_WR(p, PM2I_RD_GREEN_KEY, 0);
412 pm2_RDAC_WR(p, PM2I_RD_BLUE_KEY, 0);
413 }
414
415 static void set_aperture(struct pm2fb_par* p, u32 depth)
416 {
417 /*
418 * The hardware is little-endian. When used in big-endian
419 * hosts, the on-chip aperture settings are used where
420 * possible to translate from host to card byte order.
421 */
422 WAIT_FIFO(p, 4);
423 #ifdef __LITTLE_ENDIAN
424 pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_STANDARD);
425 #else
426 switch (depth) {
427 case 24: /* RGB->BGR */
428 /*
429 * We can't use the aperture to translate host to
430 * card byte order here, so we switch to BGR mode
431 * in pm2fb_set_par().
432 */
433 case 8: /* B->B */
434 pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_STANDARD);
435 break;
436 case 16: /* HL->LH */
437 pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_HALFWORDSWAP);
438 break;
439 case 32: /* RGBA->ABGR */
440 pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_BYTESWAP);
441 break;
442 }
443 #endif
444
445 // We don't use aperture two, so this may be superflous
446 pm2_WR(p, PM2R_APERTURE_TWO, PM2F_APERTURE_STANDARD);
447 }
448
449 static void set_color(struct pm2fb_par* p, unsigned char regno,
450 unsigned char r, unsigned char g, unsigned char b)
451 {
452 WAIT_FIFO(p, 4);
453 pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, regno);
454 wmb();
455 pm2_WR(p, PM2R_RD_PALETTE_DATA, r);
456 wmb();
457 pm2_WR(p, PM2R_RD_PALETTE_DATA, g);
458 wmb();
459 pm2_WR(p, PM2R_RD_PALETTE_DATA, b);
460 }
461
462 static void set_memclock(struct pm2fb_par* par, u32 clk)
463 {
464 int i;
465 unsigned char m, n, p;
466
467 pm2_mnp(clk, &m, &n, &p);
468 WAIT_FIFO(par, 10);
469 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_3, 6);
470 wmb();
471 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_1, m);
472 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_2, n);
473 wmb();
474 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_3, 8|p);
475 wmb();
476 pm2_RDAC_RD(par, PM2I_RD_MEMORY_CLOCK_STATUS);
477 rmb();
478 for (i = 256;
479 i && !(pm2_RD(par, PM2R_RD_INDEXED_DATA) & PM2F_PLL_LOCKED);
480 i--)
481 ;
482 }
483
484 static void set_pixclock(struct pm2fb_par* par, u32 clk)
485 {
486 int i;
487 unsigned char m, n, p;
488
489 switch (par->type) {
490 case PM2_TYPE_PERMEDIA2:
491 pm2_mnp(clk, &m, &n, &p);
492 WAIT_FIFO(par, 8);
493 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A3, 0);
494 wmb();
495 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A1, m);
496 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A2, n);
497 wmb();
498 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A3, 8|p);
499 wmb();
500 pm2_RDAC_RD(par, PM2I_RD_PIXEL_CLOCK_STATUS);
501 rmb();
502 for (i = 256;
503 i && !(pm2_RD(par, PM2R_RD_INDEXED_DATA) & PM2F_PLL_LOCKED);
504 i--)
505 ;
506 break;
507 case PM2_TYPE_PERMEDIA2V:
508 pm2v_mnp(clk/2, &m, &n, &p);
509 WAIT_FIFO(par, 8);
510 pm2_WR(par, PM2VR_RD_INDEX_HIGH, PM2VI_RD_CLK0_PRESCALE >> 8);
511 pm2v_RDAC_WR(par, PM2VI_RD_CLK0_PRESCALE, m);
512 pm2v_RDAC_WR(par, PM2VI_RD_CLK0_FEEDBACK, n);
513 pm2v_RDAC_WR(par, PM2VI_RD_CLK0_POSTSCALE, p);
514 pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0);
515 break;
516 }
517 }
518
519 static void set_video(struct pm2fb_par* p, u32 video) {
520 u32 tmp;
521 u32 vsync;
522
523 vsync = video;
524
525 DPRINTK("video = 0x%x\n", video);
526
527 /*
528 * The hardware cursor needs +vsync to recognise vert retrace.
529 * We may not be using the hardware cursor, but the X Glint
530 * driver may well. So always set +hsync/+vsync and then set
531 * the RAMDAC to invert the sync if necessary.
532 */
533 vsync &= ~(PM2F_HSYNC_MASK|PM2F_VSYNC_MASK);
534 vsync |= PM2F_HSYNC_ACT_HIGH|PM2F_VSYNC_ACT_HIGH;
535
536 WAIT_FIFO(p, 5);
537 pm2_WR(p, PM2R_VIDEO_CONTROL, vsync);
538
539 switch (p->type) {
540 case PM2_TYPE_PERMEDIA2:
541 tmp = PM2F_RD_PALETTE_WIDTH_8;
542 if ((video & PM2F_HSYNC_MASK) == PM2F_HSYNC_ACT_LOW)
543 tmp |= 4; /* invert hsync */
544 if ((video & PM2F_VSYNC_MASK) == PM2F_VSYNC_ACT_LOW)
545 tmp |= 8; /* invert vsync */
546 pm2_RDAC_WR(p, PM2I_RD_MISC_CONTROL, tmp);
547 break;
548 case PM2_TYPE_PERMEDIA2V:
549 tmp = 0;
550 if ((video & PM2F_HSYNC_MASK) == PM2F_HSYNC_ACT_LOW)
551 tmp |= 1; /* invert hsync */
552 if ((video & PM2F_VSYNC_MASK) == PM2F_VSYNC_ACT_LOW)
553 tmp |= 4; /* invert vsync */
554 pm2v_RDAC_WR(p, PM2VI_RD_SYNC_CONTROL, tmp);
555 pm2v_RDAC_WR(p, PM2VI_RD_MISC_CONTROL, 1);
556 break;
557 }
558 }
559
560 /*
561 *
562 */
563
564 /**
565 * pm2fb_check_var - Optional function. Validates a var passed in.
566 * @var: frame buffer variable screen structure
567 * @info: frame buffer structure that represents a single frame buffer
568 *
569 * Checks to see if the hardware supports the state requested by
570 * var passed in.
571 *
572 * Returns negative errno on error, or zero on success.
573 */
574 static int pm2fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
575 {
576 u32 lpitch;
577
578 if (var->bits_per_pixel != 8 && var->bits_per_pixel != 16 &&
579 var->bits_per_pixel != 24 && var->bits_per_pixel != 32) {
580 DPRINTK("depth not supported: %u\n", var->bits_per_pixel);
581 return -EINVAL;
582 }
583
584 if (var->xres != var->xres_virtual) {
585 DPRINTK("virtual x resolution != physical x resolution not supported\n");
586 return -EINVAL;
587 }
588
589 if (var->yres > var->yres_virtual) {
590 DPRINTK("virtual y resolution < physical y resolution not possible\n");
591 return -EINVAL;
592 }
593
594 if (var->xoffset) {
595 DPRINTK("xoffset not supported\n");
596 return -EINVAL;
597 }
598
599 if ((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
600 DPRINTK("interlace not supported\n");
601 return -EINVAL;
602 }
603
604 var->xres = (var->xres + 15) & ~15; /* could sometimes be 8 */
605 lpitch = var->xres * ((var->bits_per_pixel + 7)>>3);
606
607 if (var->xres < 320 || var->xres > 1600) {
608 DPRINTK("width not supported: %u\n", var->xres);
609 return -EINVAL;
610 }
611
612 if (var->yres < 200 || var->yres > 1200) {
613 DPRINTK("height not supported: %u\n", var->yres);
614 return -EINVAL;
615 }
616
617 if (lpitch * var->yres_virtual > info->fix.smem_len) {
618 DPRINTK("no memory for screen (%ux%ux%u)\n",
619 var->xres, var->yres_virtual, var->bits_per_pixel);
620 return -EINVAL;
621 }
622
623 if (PICOS2KHZ(var->pixclock) > PM2_MAX_PIXCLOCK) {
624 DPRINTK("pixclock too high (%ldKHz)\n", PICOS2KHZ(var->pixclock));
625 return -EINVAL;
626 }
627
628 switch(var->bits_per_pixel) {
629 case 8:
630 var->red.length = var->green.length = var->blue.length = 8;
631 break;
632 case 16:
633 var->red.offset = 11;
634 var->red.length = 5;
635 var->green.offset = 5;
636 var->green.length = 6;
637 var->blue.offset = 0;
638 var->blue.length = 5;
639 break;
640 case 32:
641 var->transp.offset = 24;
642 var->transp.length = 8;
643 var->red.offset = 16;
644 var->green.offset = 8;
645 var->blue.offset = 0;
646 var->red.length = var->green.length = var->blue.length = 8;
647 break;
648 case 24:
649 #ifdef __BIG_ENDIAN
650 var->red.offset = 0;
651 var->blue.offset = 16;
652 #else
653 var->red.offset = 16;
654 var->blue.offset = 0;
655 #endif
656 var->green.offset = 8;
657 var->red.length = var->green.length = var->blue.length = 8;
658 break;
659 }
660 var->height = var->width = -1;
661
662 var->accel_flags = 0; /* Can't mmap if this is on */
663
664 DPRINTK("Checking graphics mode at %dx%d depth %d\n",
665 var->xres, var->yres, var->bits_per_pixel);
666 return 0;
667 }
668
669 /**
670 * pm2fb_set_par - Alters the hardware state.
671 * @info: frame buffer structure that represents a single frame buffer
672 *
673 * Using the fb_var_screeninfo in fb_info we set the resolution of the
674 * this particular framebuffer.
675 */
676 static int pm2fb_set_par(struct fb_info *info)
677 {
678 struct pm2fb_par *par = info->par;
679 u32 pixclock;
680 u32 width, height, depth;
681 u32 hsstart, hsend, hbend, htotal;
682 u32 vsstart, vsend, vbend, vtotal;
683 u32 stride;
684 u32 base;
685 u32 video = 0;
686 u32 clrmode = PM2F_RD_COLOR_MODE_RGB | PM2F_RD_GUI_ACTIVE;
687 u32 txtmap = 0;
688 u32 pixsize = 0;
689 u32 clrformat = 0;
690 u32 xres;
691 int data64;
692
693 reset_card(par);
694 reset_config(par);
695 clear_palette(par);
696 if ( par->memclock )
697 set_memclock(par, par->memclock);
698
699 width = (info->var.xres_virtual + 7) & ~7;
700 height = info->var.yres_virtual;
701 depth = (info->var.bits_per_pixel + 7) & ~7;
702 depth = (depth > 32) ? 32 : depth;
703 data64 = depth > 8 || par->type == PM2_TYPE_PERMEDIA2V;
704
705 xres = (info->var.xres + 31) & ~31;
706 pixclock = PICOS2KHZ(info->var.pixclock);
707 if (pixclock > PM2_MAX_PIXCLOCK) {
708 DPRINTK("pixclock too high (%uKHz)\n", pixclock);
709 return -EINVAL;
710 }
711
712 hsstart = to3264(info->var.right_margin, depth, data64);
713 hsend = hsstart + to3264(info->var.hsync_len, depth, data64);
714 hbend = hsend + to3264(info->var.left_margin, depth, data64);
715 htotal = to3264(xres, depth, data64) + hbend - 1;
716 vsstart = (info->var.lower_margin)
717 ? info->var.lower_margin - 1
718 : 0; /* FIXME! */
719 vsend = info->var.lower_margin + info->var.vsync_len - 1;
720 vbend = info->var.lower_margin + info->var.vsync_len + info->var.upper_margin;
721 vtotal = info->var.yres + vbend - 1;
722 stride = to3264(width, depth, 1);
723 base = to3264(info->var.yoffset * xres + info->var.xoffset, depth, 1);
724 if (data64)
725 video |= PM2F_DATA_64_ENABLE;
726
727 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT) {
728 if (lowhsync) {
729 DPRINTK("ignoring +hsync, using -hsync.\n");
730 video |= PM2F_HSYNC_ACT_LOW;
731 } else
732 video |= PM2F_HSYNC_ACT_HIGH;
733 }
734 else
735 video |= PM2F_HSYNC_ACT_LOW;
736 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT) {
737 if (lowvsync) {
738 DPRINTK("ignoring +vsync, using -vsync.\n");
739 video |= PM2F_VSYNC_ACT_LOW;
740 } else
741 video |= PM2F_VSYNC_ACT_HIGH;
742 }
743 else
744 video |= PM2F_VSYNC_ACT_LOW;
745 if ((info->var.vmode & FB_VMODE_MASK)==FB_VMODE_INTERLACED) {
746 DPRINTK("interlaced not supported\n");
747 return -EINVAL;
748 }
749 if ((info->var.vmode & FB_VMODE_MASK)==FB_VMODE_DOUBLE)
750 video |= PM2F_LINE_DOUBLE;
751 if ((info->var.activate & FB_ACTIVATE_MASK)==FB_ACTIVATE_NOW)
752 video |= PM2F_VIDEO_ENABLE;
753 par->video = video;
754
755 info->fix.visual =
756 (depth == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
757 info->fix.line_length = info->var.xres * depth / 8;
758 info->cmap.len = 256;
759
760 /*
761 * Settings calculated. Now write them out.
762 */
763 if (par->type == PM2_TYPE_PERMEDIA2V) {
764 WAIT_FIFO(par, 1);
765 pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0);
766 }
767
768 set_aperture(par, depth);
769
770 mb();
771 WAIT_FIFO(par, 19);
772 pm2_RDAC_WR(par, PM2I_RD_COLOR_KEY_CONTROL,
773 ( depth == 8 ) ? 0 : PM2F_COLOR_KEY_TEST_OFF);
774 switch (depth) {
775 case 8:
776 pm2_WR(par, PM2R_FB_READ_PIXEL, 0);
777 clrformat = 0x0e;
778 break;
779 case 16:
780 pm2_WR(par, PM2R_FB_READ_PIXEL, 1);
781 clrmode |= PM2F_RD_TRUECOLOR | PM2F_RD_PIXELFORMAT_RGB565;
782 txtmap = PM2F_TEXTEL_SIZE_16;
783 pixsize = 1;
784 clrformat = 0x70;
785 break;
786 case 32:
787 pm2_WR(par, PM2R_FB_READ_PIXEL, 2);
788 clrmode |= PM2F_RD_TRUECOLOR | PM2F_RD_PIXELFORMAT_RGBA8888;
789 txtmap = PM2F_TEXTEL_SIZE_32;
790 pixsize = 2;
791 clrformat = 0x20;
792 break;
793 case 24:
794 pm2_WR(par, PM2R_FB_READ_PIXEL, 4);
795 clrmode |= PM2F_RD_TRUECOLOR | PM2F_RD_PIXELFORMAT_RGB888;
796 txtmap = PM2F_TEXTEL_SIZE_24;
797 pixsize = 4;
798 clrformat = 0x20;
799 break;
800 }
801 pm2_WR(par, PM2R_FB_WRITE_MODE, PM2F_FB_WRITE_ENABLE);
802 pm2_WR(par, PM2R_FB_READ_MODE, partprod(xres));
803 pm2_WR(par, PM2R_LB_READ_MODE, partprod(xres));
804 pm2_WR(par, PM2R_TEXTURE_MAP_FORMAT, txtmap | partprod(xres));
805 pm2_WR(par, PM2R_H_TOTAL, htotal);
806 pm2_WR(par, PM2R_HS_START, hsstart);
807 pm2_WR(par, PM2R_HS_END, hsend);
808 pm2_WR(par, PM2R_HG_END, hbend);
809 pm2_WR(par, PM2R_HB_END, hbend);
810 pm2_WR(par, PM2R_V_TOTAL, vtotal);
811 pm2_WR(par, PM2R_VS_START, vsstart);
812 pm2_WR(par, PM2R_VS_END, vsend);
813 pm2_WR(par, PM2R_VB_END, vbend);
814 pm2_WR(par, PM2R_SCREEN_STRIDE, stride);
815 wmb();
816 pm2_WR(par, PM2R_WINDOW_ORIGIN, 0);
817 pm2_WR(par, PM2R_SCREEN_SIZE, (height << 16) | width);
818 pm2_WR(par, PM2R_SCISSOR_MODE, PM2F_SCREEN_SCISSOR_ENABLE);
819 wmb();
820 pm2_WR(par, PM2R_SCREEN_BASE, base);
821 wmb();
822 set_video(par, video);
823 WAIT_FIFO(par, 4);
824 switch (par->type) {
825 case PM2_TYPE_PERMEDIA2:
826 pm2_RDAC_WR(par, PM2I_RD_COLOR_MODE, clrmode);
827 break;
828 case PM2_TYPE_PERMEDIA2V:
829 pm2v_RDAC_WR(par, PM2VI_RD_PIXEL_SIZE, pixsize);
830 pm2v_RDAC_WR(par, PM2VI_RD_COLOR_FORMAT, clrformat);
831 break;
832 }
833 set_pixclock(par, pixclock);
834 DPRINTK("Setting graphics mode at %dx%d depth %d\n",
835 info->var.xres, info->var.yres, info->var.bits_per_pixel);
836 return 0;
837 }
838
839 /**
840 * pm2fb_setcolreg - Sets a color register.
841 * @regno: boolean, 0 copy local, 1 get_user() function
842 * @red: frame buffer colormap structure
843 * @green: The green value which can be up to 16 bits wide
844 * @blue: The blue value which can be up to 16 bits wide.
845 * @transp: If supported the alpha value which can be up to 16 bits wide.
846 * @info: frame buffer info structure
847 *
848 * Set a single color register. The values supplied have a 16 bit
849 * magnitude which needs to be scaled in this function for the hardware.
850 * Pretty much a direct lift from tdfxfb.c.
851 *
852 * Returns negative errno on error, or zero on success.
853 */
854 static int pm2fb_setcolreg(unsigned regno, unsigned red, unsigned green,
855 unsigned blue, unsigned transp,
856 struct fb_info *info)
857 {
858 struct pm2fb_par *par = info->par;
859
860 if (regno >= info->cmap.len) /* no. of hw registers */
861 return 1;
862 /*
863 * Program hardware... do anything you want with transp
864 */
865
866 /* grayscale works only partially under directcolor */
867 if (info->var.grayscale) {
868 /* grayscale = 0.30*R + 0.59*G + 0.11*B */
869 red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
870 }
871
872 /* Directcolor:
873 * var->{color}.offset contains start of bitfield
874 * var->{color}.length contains length of bitfield
875 * {hardwarespecific} contains width of DAC
876 * cmap[X] is programmed to
877 * (X << red.offset) | (X << green.offset) | (X << blue.offset)
878 * RAMDAC[X] is programmed to (red, green, blue)
879 *
880 * Pseudocolor:
881 * uses offset = 0 && length = DAC register width.
882 * var->{color}.offset is 0
883 * var->{color}.length contains widht of DAC
884 * cmap is not used
885 * DAC[X] is programmed to (red, green, blue)
886 * Truecolor:
887 * does not use RAMDAC (usually has 3 of them).
888 * var->{color}.offset contains start of bitfield
889 * var->{color}.length contains length of bitfield
890 * cmap is programmed to
891 * (red << red.offset) | (green << green.offset) |
892 * (blue << blue.offset) | (transp << transp.offset)
893 * RAMDAC does not exist
894 */
895 #define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16)
896 switch (info->fix.visual) {
897 case FB_VISUAL_TRUECOLOR:
898 case FB_VISUAL_PSEUDOCOLOR:
899 red = CNVT_TOHW(red, info->var.red.length);
900 green = CNVT_TOHW(green, info->var.green.length);
901 blue = CNVT_TOHW(blue, info->var.blue.length);
902 transp = CNVT_TOHW(transp, info->var.transp.length);
903 break;
904 case FB_VISUAL_DIRECTCOLOR:
905 /* example here assumes 8 bit DAC. Might be different
906 * for your hardware */
907 red = CNVT_TOHW(red, 8);
908 green = CNVT_TOHW(green, 8);
909 blue = CNVT_TOHW(blue, 8);
910 /* hey, there is bug in transp handling... */
911 transp = CNVT_TOHW(transp, 8);
912 break;
913 }
914 #undef CNVT_TOHW
915 /* Truecolor has hardware independent palette */
916 if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
917 u32 v;
918
919 if (regno >= 16)
920 return 1;
921
922 v = (red << info->var.red.offset) |
923 (green << info->var.green.offset) |
924 (blue << info->var.blue.offset) |
925 (transp << info->var.transp.offset);
926
927 switch (info->var.bits_per_pixel) {
928 case 8:
929 break;
930 case 16:
931 case 24:
932 case 32:
933 par->palette[regno] = v;
934 break;
935 }
936 return 0;
937 }
938 else if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR)
939 set_color(par, regno, red, green, blue);
940
941 return 0;
942 }
943
944 /**
945 * pm2fb_pan_display - Pans the display.
946 * @var: frame buffer variable screen structure
947 * @info: frame buffer structure that represents a single frame buffer
948 *
949 * Pan (or wrap, depending on the `vmode' field) the display using the
950 * `xoffset' and `yoffset' fields of the `var' structure.
951 * If the values don't fit, return -EINVAL.
952 *
953 * Returns negative errno on error, or zero on success.
954 *
955 */
956 static int pm2fb_pan_display(struct fb_var_screeninfo *var,
957 struct fb_info *info)
958 {
959 struct pm2fb_par *p = info->par;
960 u32 base;
961 u32 depth;
962 u32 xres;
963
964 xres = (var->xres + 31) & ~31;
965 depth = (var->bits_per_pixel + 7) & ~7;
966 depth = (depth > 32) ? 32 : depth;
967 base = to3264(var->yoffset * xres + var->xoffset, depth, 1);
968 WAIT_FIFO(p, 1);
969 pm2_WR(p, PM2R_SCREEN_BASE, base);
970 return 0;
971 }
972
973 /**
974 * pm2fb_blank - Blanks the display.
975 * @blank_mode: the blank mode we want.
976 * @info: frame buffer structure that represents a single frame buffer
977 *
978 * Blank the screen if blank_mode != 0, else unblank. Return 0 if
979 * blanking succeeded, != 0 if un-/blanking failed due to e.g. a
980 * video mode which doesn't support it. Implements VESA suspend
981 * and powerdown modes on hardware that supports disabling hsync/vsync:
982 * blank_mode == 2: suspend vsync
983 * blank_mode == 3: suspend hsync
984 * blank_mode == 4: powerdown
985 *
986 * Returns negative errno on error, or zero on success.
987 *
988 */
989 static int pm2fb_blank(int blank_mode, struct fb_info *info)
990 {
991 struct pm2fb_par *par = info->par;
992 u32 video = par->video;
993
994 DPRINTK("blank_mode %d\n", blank_mode);
995
996 switch (blank_mode) {
997 case FB_BLANK_UNBLANK:
998 /* Screen: On */
999 video |= PM2F_VIDEO_ENABLE;
1000 break;
1001 case FB_BLANK_NORMAL:
1002 /* Screen: Off */
1003 video &= ~PM2F_VIDEO_ENABLE;
1004 break;
1005 case FB_BLANK_VSYNC_SUSPEND:
1006 /* VSync: Off */
1007 video &= ~(PM2F_VSYNC_MASK | PM2F_BLANK_LOW );
1008 break;
1009 case FB_BLANK_HSYNC_SUSPEND:
1010 /* HSync: Off */
1011 video &= ~(PM2F_HSYNC_MASK | PM2F_BLANK_LOW );
1012 break;
1013 case FB_BLANK_POWERDOWN:
1014 /* HSync: Off, VSync: Off */
1015 video &= ~(PM2F_VSYNC_MASK | PM2F_HSYNC_MASK| PM2F_BLANK_LOW);
1016 break;
1017 }
1018 set_video(par, video);
1019 return 0;
1020 }
1021
1022 /* ------------ Hardware Independent Functions ------------ */
1023
1024 /*
1025 * Frame buffer operations
1026 */
1027
1028 static struct fb_ops pm2fb_ops = {
1029 .owner = THIS_MODULE,
1030 .fb_check_var = pm2fb_check_var,
1031 .fb_set_par = pm2fb_set_par,
1032 .fb_setcolreg = pm2fb_setcolreg,
1033 .fb_blank = pm2fb_blank,
1034 .fb_pan_display = pm2fb_pan_display,
1035 .fb_fillrect = cfb_fillrect,
1036 .fb_copyarea = cfb_copyarea,
1037 .fb_imageblit = cfb_imageblit,
1038 };
1039
1040 /*
1041 * PCI stuff
1042 */
1043
1044
1045 /**
1046 * Device initialisation
1047 *
1048 * Initialise and allocate resource for PCI device.
1049 *
1050 * @param pdev PCI device.
1051 * @param id PCI device ID.
1052 */
1053 static int __devinit pm2fb_probe(struct pci_dev *pdev,
1054 const struct pci_device_id *id)
1055 {
1056 struct pm2fb_par *default_par;
1057 struct fb_info *info;
1058 int err, err_retval = -ENXIO;
1059
1060 err = pci_enable_device(pdev);
1061 if ( err ) {
1062 printk(KERN_WARNING "pm2fb: Can't enable pdev: %d\n", err);
1063 return err;
1064 }
1065
1066 info = framebuffer_alloc(sizeof(struct pm2fb_par), &pdev->dev);
1067 if ( !info )
1068 return -ENOMEM;
1069 default_par = info->par;
1070
1071 switch (pdev->device) {
1072 case PCI_DEVICE_ID_TI_TVP4020:
1073 strcpy(pm2fb_fix.id, "TVP4020");
1074 default_par->type = PM2_TYPE_PERMEDIA2;
1075 break;
1076 case PCI_DEVICE_ID_3DLABS_PERMEDIA2:
1077 strcpy(pm2fb_fix.id, "Permedia2");
1078 default_par->type = PM2_TYPE_PERMEDIA2;
1079 break;
1080 case PCI_DEVICE_ID_3DLABS_PERMEDIA2V:
1081 strcpy(pm2fb_fix.id, "Permedia2v");
1082 default_par->type = PM2_TYPE_PERMEDIA2V;
1083 break;
1084 }
1085
1086 pm2fb_fix.mmio_start = pci_resource_start(pdev, 0);
1087 pm2fb_fix.mmio_len = PM2_REGS_SIZE;
1088
1089 #if defined(__BIG_ENDIAN)
1090 /*
1091 * PM2 has a 64k register file, mapped twice in 128k. Lower
1092 * map is little-endian, upper map is big-endian.
1093 */
1094 pm2fb_fix.mmio_start += PM2_REGS_SIZE;
1095 DPRINTK("Adjusting register base for big-endian.\n");
1096 #endif
1097 DPRINTK("Register base at 0x%lx\n", pm2fb_fix.mmio_start);
1098
1099 /* Registers - request region and map it. */
1100 if ( !request_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len,
1101 "pm2fb regbase") ) {
1102 printk(KERN_WARNING "pm2fb: Can't reserve regbase.\n");
1103 goto err_exit_neither;
1104 }
1105 default_par->v_regs =
1106 ioremap_nocache(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len);
1107 if ( !default_par->v_regs ) {
1108 printk(KERN_WARNING "pm2fb: Can't remap %s register area.\n",
1109 pm2fb_fix.id);
1110 release_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len);
1111 goto err_exit_neither;
1112 }
1113
1114 /* Stash away memory register info for use when we reset the board */
1115 default_par->mem_control = pm2_RD(default_par, PM2R_MEM_CONTROL);
1116 default_par->boot_address = pm2_RD(default_par, PM2R_BOOT_ADDRESS);
1117 default_par->mem_config = pm2_RD(default_par, PM2R_MEM_CONFIG);
1118 DPRINTK("MemControl 0x%x BootAddress 0x%x MemConfig 0x%x\n",
1119 default_par->mem_control, default_par->boot_address,
1120 default_par->mem_config);
1121
1122 if(default_par->mem_control == 0 &&
1123 default_par->boot_address == 0x31 &&
1124 default_par->mem_config == 0x259fffff &&
1125 pdev->subsystem_vendor == 0x1048 &&
1126 pdev->subsystem_device == 0x0a31) {
1127 DPRINTK("subsystem_vendor: %04x, subsystem_device: %04x\n",
1128 pdev->subsystem_vendor, pdev->subsystem_device);
1129 DPRINTK("We have not been initialized by VGA BIOS "
1130 "and are running on an Elsa Winner 2000 Office\n");
1131 DPRINTK("Initializing card timings manually...\n");
1132 default_par->mem_control=0;
1133 default_par->boot_address=0x20;
1134 default_par->mem_config=0xe6002021;
1135 default_par->memclock=100000;
1136 }
1137
1138 /* Now work out how big lfb is going to be. */
1139 switch(default_par->mem_config & PM2F_MEM_CONFIG_RAM_MASK) {
1140 case PM2F_MEM_BANKS_1:
1141 default_par->fb_size=0x200000;
1142 break;
1143 case PM2F_MEM_BANKS_2:
1144 default_par->fb_size=0x400000;
1145 break;
1146 case PM2F_MEM_BANKS_3:
1147 default_par->fb_size=0x600000;
1148 break;
1149 case PM2F_MEM_BANKS_4:
1150 default_par->fb_size=0x800000;
1151 break;
1152 }
1153 default_par->memclock = CVPPC_MEMCLOCK;
1154 pm2fb_fix.smem_start = pci_resource_start(pdev, 1);
1155 pm2fb_fix.smem_len = default_par->fb_size;
1156
1157 /* Linear frame buffer - request region and map it. */
1158 if ( !request_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len,
1159 "pm2fb smem") ) {
1160 printk(KERN_WARNING "pm2fb: Can't reserve smem.\n");
1161 goto err_exit_mmio;
1162 }
1163 info->screen_base = default_par->v_fb =
1164 ioremap_nocache(pm2fb_fix.smem_start, pm2fb_fix.smem_len);
1165 if ( !default_par->v_fb ) {
1166 printk(KERN_WARNING "pm2fb: Can't ioremap smem area.\n");
1167 release_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len);
1168 goto err_exit_mmio;
1169 }
1170
1171 info->fbops = &pm2fb_ops;
1172 info->fix = pm2fb_fix;
1173 info->pseudo_palette = default_par->palette;
1174 info->flags = FBINFO_DEFAULT |
1175 FBINFO_HWACCEL_YPAN;
1176
1177 if (!mode)
1178 mode = "640x480@60";
1179
1180 err = fb_find_mode(&info->var, info, mode, NULL, 0, NULL, 8);
1181 if (!err || err == 4)
1182 info->var = pm2fb_var;
1183
1184 if (fb_alloc_cmap(&info->cmap, 256, 0) < 0)
1185 goto err_exit_all;
1186
1187 if (register_framebuffer(info) < 0)
1188 goto err_exit_both;
1189
1190 printk(KERN_INFO "fb%d: %s frame buffer device, memory = %dK.\n",
1191 info->node, info->fix.id, default_par->fb_size / 1024);
1192
1193 /*
1194 * Our driver data
1195 */
1196 pci_set_drvdata(pdev, info);
1197
1198 return 0;
1199
1200 err_exit_all:
1201 fb_dealloc_cmap(&info->cmap);
1202 err_exit_both:
1203 iounmap(info->screen_base);
1204 release_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len);
1205 err_exit_mmio:
1206 iounmap(default_par->v_regs);
1207 release_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len);
1208 err_exit_neither:
1209 framebuffer_release(info);
1210 return err_retval;
1211 }
1212
1213 /**
1214 * Device removal.
1215 *
1216 * Release all device resources.
1217 *
1218 * @param pdev PCI device to clean up.
1219 */
1220 static void __devexit pm2fb_remove(struct pci_dev *pdev)
1221 {
1222 struct fb_info* info = pci_get_drvdata(pdev);
1223 struct fb_fix_screeninfo* fix = &info->fix;
1224 struct pm2fb_par *par = info->par;
1225
1226 unregister_framebuffer(info);
1227
1228 iounmap(info->screen_base);
1229 release_mem_region(fix->smem_start, fix->smem_len);
1230 iounmap(par->v_regs);
1231 release_mem_region(fix->mmio_start, fix->mmio_len);
1232
1233 pci_set_drvdata(pdev, NULL);
1234 kfree(info);
1235 }
1236
1237 static struct pci_device_id pm2fb_id_table[] = {
1238 { PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TVP4020,
1239 PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
1240 0xff0000, 0 },
1241 { PCI_VENDOR_ID_3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2,
1242 PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
1243 0xff0000, 0 },
1244 { PCI_VENDOR_ID_3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2V,
1245 PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
1246 0xff0000, 0 },
1247 { 0, }
1248 };
1249
1250 static struct pci_driver pm2fb_driver = {
1251 .name = "pm2fb",
1252 .id_table = pm2fb_id_table,
1253 .probe = pm2fb_probe,
1254 .remove = __devexit_p(pm2fb_remove),
1255 };
1256
1257 MODULE_DEVICE_TABLE(pci, pm2fb_id_table);
1258
1259
1260 #ifndef MODULE
1261 /**
1262 * Parse user speficied options.
1263 *
1264 * This is, comma-separated options following `video=pm2fb:'.
1265 */
1266 static int __init pm2fb_setup(char *options)
1267 {
1268 char* this_opt;
1269
1270 if (!options || !*options)
1271 return 0;
1272
1273 while ((this_opt = strsep(&options, ",")) != NULL) {
1274 if (!*this_opt)
1275 continue;
1276 if(!strcmp(this_opt, "lowhsync")) {
1277 lowhsync = 1;
1278 } else if(!strcmp(this_opt, "lowvsync")) {
1279 lowvsync = 1;
1280 } else {
1281 mode = this_opt;
1282 }
1283 }
1284 return 0;
1285 }
1286 #endif
1287
1288
1289 static int __init pm2fb_init(void)
1290 {
1291 #ifndef MODULE
1292 char *option = NULL;
1293
1294 if (fb_get_options("pm2fb", &option))
1295 return -ENODEV;
1296 pm2fb_setup(option);
1297 #endif
1298
1299 return pci_register_driver(&pm2fb_driver);
1300 }
1301
1302 module_init(pm2fb_init);
1303
1304 #ifdef MODULE
1305 /*
1306 * Cleanup
1307 */
1308
1309 static void __exit pm2fb_exit(void)
1310 {
1311 pci_unregister_driver(&pm2fb_driver);
1312 }
1313 #endif
1314
1315 #ifdef MODULE
1316 module_exit(pm2fb_exit);
1317
1318 module_param(mode, charp, 0);
1319 MODULE_PARM_DESC(mode, "Preferred video mode e.g. '648x480-8@60'");
1320 module_param(lowhsync, bool, 0);
1321 MODULE_PARM_DESC(lowhsync, "Force horizontal sync low regardless of mode");
1322 module_param(lowvsync, bool, 0);
1323 MODULE_PARM_DESC(lowvsync, "Force vertical sync low regardless of mode");
1324
1325 MODULE_AUTHOR("Jim Hague <jim.hague@acm.org>");
1326 MODULE_DESCRIPTION("Permedia2 framebuffer device driver");
1327 MODULE_LICENSE("GPL");
1328 #endif
WRT350N Kernel Patches