drivers/net/ibm_emac/ibm_emac.h

   1 /*
   2  * drivers/net/ibm_emac/ibm_emac.h
   3  *
   4  * Register definitions for PowerPC 4xx on-chip ethernet contoller
   5  *
   6  * Copyright (c) 2004, 2005 Zultys Technologies.
   7  * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
   8  *
   9  * Based on original work by
  10  *      Matt Porter <mporter@kernel.crashing.org>
  11  *      Armin Kuster <akuster@mvista.com>
  12  *      Copyright 2002-2004 MontaVista Software Inc.
  13  *
  14  * This program is free software; you can redistribute  it and/or modify it
  15  * under  the terms of  the GNU General  Public License as published by the
  16  * Free Software Foundation;  either version 2 of the  License, or (at your
  17  * option) any later version.
  18  *
  19  */
  20 #ifndef __IBM_EMAC_H_
  21 #define __IBM_EMAC_H_
  22
  23 #include <linux/types.h>
  24
  25 /* This is a simple check to prevent use of this driver on non-tested SoCs */
  26 #if !defined(CONFIG_405GP) && !defined(CONFIG_405GPR) && !defined(CONFIG_405EP) && \
  27     !defined(CONFIG_440GP) && !defined(CONFIG_440GX) && !defined(CONFIG_440SP) && \
  28     !defined(CONFIG_440EP) && !defined(CONFIG_NP405H) && !defined(CONFIG_440SPE) && \
  29     !defined(CONFIG_440GR)
  30 #error  "Unknown SoC. Please, check chip user manual and make sure EMAC defines are OK"
  31 #endif
  32
  33 /* EMAC registers               Write Access rules */
  34 struct emac_regs {
  35         u32 mr0;                /* special      */
  36         u32 mr1;                /* Reset        */
  37         u32 tmr0;               /* special      */
  38         u32 tmr1;               /* special      */
  39         u32 rmr;                /* Reset        */
  40         u32 isr;                /* Always       */
  41         u32 iser;               /* Reset        */
  42         u32 iahr;               /* Reset, R, T  */
  43         u32 ialr;               /* Reset, R, T  */
  44         u32 vtpid;              /* Reset, R, T  */
  45         u32 vtci;               /* Reset, R, T  */
  46         u32 ptr;                /* Reset,    T  */
  47         u32 iaht1;              /* Reset, R     */
  48         u32 iaht2;              /* Reset, R     */
  49         u32 iaht3;              /* Reset, R     */
  50         u32 iaht4;              /* Reset, R     */
  51         u32 gaht1;              /* Reset, R     */
  52         u32 gaht2;              /* Reset, R     */
  53         u32 gaht3;              /* Reset, R     */
  54         u32 gaht4;              /* Reset, R     */
  55         u32 lsah;
  56         u32 lsal;
  57         u32 ipgvr;              /* Reset,    T  */
  58         u32 stacr;              /* special      */
  59         u32 trtr;               /* special      */
  60         u32 rwmr;               /* Reset        */
  61         u32 octx;
  62         u32 ocrx;
  63         u32 ipcr;
  64 };
  65
  66 #if !defined(CONFIG_IBM_EMAC4)
  67 #define EMAC_ETHTOOL_REGS_VER           0
  68 #define EMAC_ETHTOOL_REGS_SIZE          (sizeof(struct emac_regs) - sizeof(u32))
  69 #else
  70 #define EMAC_ETHTOOL_REGS_VER           1
  71 #define EMAC_ETHTOOL_REGS_SIZE          sizeof(struct emac_regs)
  72 #endif
  73
  74 /* EMACx_MR0 */
  75 #define EMAC_MR0_RXI                    0x80000000
  76 #define EMAC_MR0_TXI                    0x40000000
  77 #define EMAC_MR0_SRST                   0x20000000
  78 #define EMAC_MR0_TXE                    0x10000000
  79 #define EMAC_MR0_RXE                    0x08000000
  80 #define EMAC_MR0_WKE                    0x04000000
  81
  82 /* EMACx_MR1 */
  83 #define EMAC_MR1_FDE                    0x80000000
  84 #define EMAC_MR1_ILE                    0x40000000
  85 #define EMAC_MR1_VLE                    0x20000000
  86 #define EMAC_MR1_EIFC                   0x10000000
  87 #define EMAC_MR1_APP                    0x08000000
  88 #define EMAC_MR1_IST                    0x01000000
  89
  90 #define EMAC_MR1_MF_MASK                0x00c00000
  91 #define EMAC_MR1_MF_10                  0x00000000
  92 #define EMAC_MR1_MF_100                 0x00400000
  93 #if !defined(CONFIG_IBM_EMAC4)
  94 #define EMAC_MR1_MF_1000                0x00000000
  95 #define EMAC_MR1_MF_1000GPCS            0x00000000
  96 #define EMAC_MR1_MF_IPPA(id)            0x00000000
  97 #else
  98 #define EMAC_MR1_MF_1000                0x00800000
  99 #define EMAC_MR1_MF_1000GPCS            0x00c00000
 100 #define EMAC_MR1_MF_IPPA(id)            (((id) & 0x1f) << 6)
 101 #endif
 102
 103 #define EMAC_TX_FIFO_SIZE               2048
 104
 105 #if !defined(CONFIG_IBM_EMAC4)
 106 #define EMAC_MR1_RFS_4K                 0x00300000
 107 #define EMAC_MR1_RFS_16K                0x00000000
 108 #define EMAC_RX_FIFO_SIZE(gige)         4096
 109 #define EMAC_MR1_TFS_2K                 0x00080000
 110 #define EMAC_MR1_TR0_MULT               0x00008000
 111 #define EMAC_MR1_JPSM                   0x00000000
 112 #define EMAC_MR1_MWSW_001               0x00000000
 113 #define EMAC_MR1_BASE(opb)              (EMAC_MR1_TFS_2K | EMAC_MR1_TR0_MULT)
 114 #else
 115 #define EMAC_MR1_RFS_4K                 0x00180000
 116 #define EMAC_MR1_RFS_16K                0x00280000
 117 #define EMAC_RX_FIFO_SIZE(gige)         ((gige) ? 16384 : 4096)
 118 #define EMAC_MR1_TFS_2K                 0x00020000
 119 #define EMAC_MR1_TR                     0x00008000
 120 #define EMAC_MR1_MWSW_001               0x00001000
 121 #define EMAC_MR1_JPSM                   0x00000800
 122 #define EMAC_MR1_OBCI_MASK              0x00000038
 123 #define EMAC_MR1_OBCI_50                0x00000000
 124 #define EMAC_MR1_OBCI_66                0x00000008
 125 #define EMAC_MR1_OBCI_83                0x00000010
 126 #define EMAC_MR1_OBCI_100               0x00000018
 127 #define EMAC_MR1_OBCI_100P              0x00000020
 128 #define EMAC_MR1_OBCI(freq)             ((freq) <= 50  ? EMAC_MR1_OBCI_50 : \
 129                                          (freq) <= 66  ? EMAC_MR1_OBCI_66 : \
 130                                          (freq) <= 83  ? EMAC_MR1_OBCI_83 : \
 131                                          (freq) <= 100 ? EMAC_MR1_OBCI_100 : EMAC_MR1_OBCI_100P)
 132 #define EMAC_MR1_BASE(opb)              (EMAC_MR1_TFS_2K | EMAC_MR1_TR | \
 133                                          EMAC_MR1_OBCI(opb))
 134 #endif
 135
 136 /* EMACx_TMR0 */
 137 #define EMAC_TMR0_GNP                   0x80000000
 138 #if !defined(CONFIG_IBM_EMAC4)
 139 #define EMAC_TMR0_DEFAULT               0x00000000
 140 #else
 141 #define EMAC_TMR0_TFAE_2_32             0x00000001
 142 #define EMAC_TMR0_TFAE_4_64             0x00000002
 143 #define EMAC_TMR0_TFAE_8_128            0x00000003
 144 #define EMAC_TMR0_TFAE_16_256           0x00000004
 145 #define EMAC_TMR0_TFAE_32_512           0x00000005
 146 #define EMAC_TMR0_TFAE_64_1024          0x00000006
 147 #define EMAC_TMR0_TFAE_128_2048         0x00000007
 148 #define EMAC_TMR0_DEFAULT               EMAC_TMR0_TFAE_2_32
 149 #endif
 150 #define EMAC_TMR0_XMIT                  (EMAC_TMR0_GNP | EMAC_TMR0_DEFAULT)
 151
 152 /* EMACx_TMR1 */
 153
 154 /* IBM manuals are not very clear here.
 155  * This is my interpretation of how things are. --ebs
 156  */
 157 #if defined(CONFIG_40x)
 158 #define EMAC_FIFO_ENTRY_SIZE            8
 159 #define EMAC_MAL_BURST_SIZE             (16 * 4)
 160 #else
 161 #define EMAC_FIFO_ENTRY_SIZE            16
 162 #define EMAC_MAL_BURST_SIZE             (64 * 4)
 163 #endif
 164
 165 #if !defined(CONFIG_IBM_EMAC4)
 166 #define EMAC_TMR1(l,h)                  (((l) << 27) | (((h) & 0xff) << 16))
 167 #else
 168 #define EMAC_TMR1(l,h)                  (((l) << 27) | (((h) & 0x3ff) << 14))
 169 #endif
 170
 171 /* EMACx_RMR */
 172 #define EMAC_RMR_SP                     0x80000000
 173 #define EMAC_RMR_SFCS                   0x40000000
 174 #define EMAC_RMR_RRP                    0x20000000
 175 #define EMAC_RMR_RFP                    0x10000000
 176 #define EMAC_RMR_ROP                    0x08000000
 177 #define EMAC_RMR_RPIR                   0x04000000
 178 #define EMAC_RMR_PPP                    0x02000000
 179 #define EMAC_RMR_PME                    0x01000000
 180 #define EMAC_RMR_PMME                   0x00800000
 181 #define EMAC_RMR_IAE                    0x00400000
 182 #define EMAC_RMR_MIAE                   0x00200000
 183 #define EMAC_RMR_BAE                    0x00100000
 184 #define EMAC_RMR_MAE                    0x00080000
 185 #if !defined(CONFIG_IBM_EMAC4)
 186 #define EMAC_RMR_BASE                   0x00000000
 187 #else
 188 #define EMAC_RMR_RFAF_2_32              0x00000001
 189 #define EMAC_RMR_RFAF_4_64              0x00000002
 190 #define EMAC_RMR_RFAF_8_128             0x00000003
 191 #define EMAC_RMR_RFAF_16_256            0x00000004
 192 #define EMAC_RMR_RFAF_32_512            0x00000005
 193 #define EMAC_RMR_RFAF_64_1024           0x00000006
 194 #define EMAC_RMR_RFAF_128_2048          0x00000007
 195 #define EMAC_RMR_BASE                   EMAC_RMR_RFAF_128_2048
 196 #endif
 197
 198 /* EMACx_ISR & EMACx_ISER */
 199 #if !defined(CONFIG_IBM_EMAC4)
 200 #define EMAC_ISR_TXPE                   0x00000000
 201 #define EMAC_ISR_RXPE                   0x00000000
 202 #define EMAC_ISR_TXUE                   0x00000000
 203 #define EMAC_ISR_RXOE                   0x00000000
 204 #else
 205 #define EMAC_ISR_TXPE                   0x20000000
 206 #define EMAC_ISR_RXPE                   0x10000000
 207 #define EMAC_ISR_TXUE                   0x08000000
 208 #define EMAC_ISR_RXOE                   0x04000000
 209 #endif
 210 #define EMAC_ISR_OVR                    0x02000000
 211 #define EMAC_ISR_PP                     0x01000000
 212 #define EMAC_ISR_BP                     0x00800000
 213 #define EMAC_ISR_RP                     0x00400000
 214 #define EMAC_ISR_SE                     0x00200000
 215 #define EMAC_ISR_ALE                    0x00100000
 216 #define EMAC_ISR_BFCS                   0x00080000
 217 #define EMAC_ISR_PTLE                   0x00040000
 218 #define EMAC_ISR_ORE                    0x00020000
 219 #define EMAC_ISR_IRE                    0x00010000
 220 #define EMAC_ISR_SQE                    0x00000080
 221 #define EMAC_ISR_TE                     0x00000040
 222 #define EMAC_ISR_MOS                    0x00000002
 223 #define EMAC_ISR_MOF                    0x00000001
 224
 225 /* EMACx_STACR */
 226 #define EMAC_STACR_PHYD_MASK            0xffff
 227 #define EMAC_STACR_PHYD_SHIFT           16
 228 #define EMAC_STACR_OC                   0x00008000
 229 #define EMAC_STACR_PHYE                 0x00004000
 230 #define EMAC_STACR_STAC_MASK            0x00003000
 231 #define EMAC_STACR_STAC_READ            0x00001000
 232 #define EMAC_STACR_STAC_WRITE           0x00002000
 233 #if !defined(CONFIG_IBM_EMAC4)
 234 #define EMAC_STACR_OPBC_MASK            0x00000C00
 235 #define EMAC_STACR_OPBC_50              0x00000000
 236 #define EMAC_STACR_OPBC_66              0x00000400
 237 #define EMAC_STACR_OPBC_83              0x00000800
 238 #define EMAC_STACR_OPBC_100             0x00000C00
 239 #define EMAC_STACR_OPBC(freq)           ((freq) <= 50 ? EMAC_STACR_OPBC_50 : \
 240                                          (freq) <= 66 ? EMAC_STACR_OPBC_66 : \
 241                                          (freq) <= 83 ? EMAC_STACR_OPBC_83 : EMAC_STACR_OPBC_100)
 242 #define EMAC_STACR_BASE(opb)            EMAC_STACR_OPBC(opb)
 243 #else
 244 #define EMAC_STACR_BASE(opb)            0x00000000
 245 #endif
 246 #define EMAC_STACR_PCDA_MASK            0x1f
 247 #define EMAC_STACR_PCDA_SHIFT           5
 248 #define EMAC_STACR_PRA_MASK             0x1f
 249
 250 /*
 251  * For the 440SPe, AMCC inexplicably changed the polarity of
 252  * the "operation complete" bit in the MII control register.
 253  */
 254 #if defined(CONFIG_440SPE)
 255 static inline int emac_phy_done(u32 stacr)
 256 {
 257         return !(stacr & EMAC_STACR_OC);
 258 };
 259 #define EMAC_STACR_START                EMAC_STACR_OC
 260
 261 #else /* CONFIG_440SPE */
 262 static inline int emac_phy_done(u32 stacr)
 263 {
 264         return stacr & EMAC_STACR_OC;
 265 };
 266 #define EMAC_STACR_START                0
 267 #endif /* !CONFIG_440SPE */
 268
 269 /* EMACx_TRTR */
 270 #if !defined(CONFIG_IBM_EMAC4)
 271 #define EMAC_TRTR_SHIFT                 27
 272 #else
 273 #define EMAC_TRTR_SHIFT                 24
 274 #endif
 275 #define EMAC_TRTR(size)                 ((((size) >> 6) - 1) << EMAC_TRTR_SHIFT)
 276
 277 /* EMACx_RWMR */
 278 #if !defined(CONFIG_IBM_EMAC4)
 279 #define EMAC_RWMR(l,h)                  (((l) << 23) | ( ((h) & 0x1ff) << 7))
 280 #else
 281 #define EMAC_RWMR(l,h)                  (((l) << 22) | ( ((h) & 0x3ff) << 6))
 282 #endif
 283
 284 /* EMAC specific TX descriptor control fields (write access) */
 285 #define EMAC_TX_CTRL_GFCS               0x0200
 286 #define EMAC_TX_CTRL_GP                 0x0100
 287 #define EMAC_TX_CTRL_ISA                0x0080
 288 #define EMAC_TX_CTRL_RSA                0x0040
 289 #define EMAC_TX_CTRL_IVT                0x0020
 290 #define EMAC_TX_CTRL_RVT                0x0010
 291 #define EMAC_TX_CTRL_TAH_CSUM           0x000e
 292
 293 /* EMAC specific TX descriptor status fields (read access) */
 294 #define EMAC_TX_ST_BFCS                 0x0200
 295 #define EMAC_TX_ST_LCS                  0x0080
 296 #define EMAC_TX_ST_ED                   0x0040
 297 #define EMAC_TX_ST_EC                   0x0020
 298 #define EMAC_TX_ST_LC                   0x0010
 299 #define EMAC_TX_ST_MC                   0x0008
 300 #define EMAC_TX_ST_SC                   0x0004
 301 #define EMAC_TX_ST_UR                   0x0002
 302 #define EMAC_TX_ST_SQE                  0x0001
 303 #if !defined(CONFIG_IBM_EMAC_TAH)
 304 #define EMAC_IS_BAD_TX(v)               ((v) & (EMAC_TX_ST_LCS | EMAC_TX_ST_ED | \
 305                                          EMAC_TX_ST_EC | EMAC_TX_ST_LC | \
 306                                          EMAC_TX_ST_MC | EMAC_TX_ST_UR))
 307 #else
 308 #define EMAC_IS_BAD_TX(v)               ((v) & (EMAC_TX_ST_LCS | EMAC_TX_ST_ED | \
 309                                          EMAC_TX_ST_EC | EMAC_TX_ST_LC))
 310 #endif
 311
 312 /* EMAC specific RX descriptor status fields (read access) */
 313 #define EMAC_RX_ST_OE                   0x0200
 314 #define EMAC_RX_ST_PP                   0x0100
 315 #define EMAC_RX_ST_BP                   0x0080
 316 #define EMAC_RX_ST_RP                   0x0040
 317 #define EMAC_RX_ST_SE                   0x0020
 318 #define EMAC_RX_ST_AE                   0x0010
 319 #define EMAC_RX_ST_BFCS                 0x0008
 320 #define EMAC_RX_ST_PTL                  0x0004
 321 #define EMAC_RX_ST_ORE                  0x0002
 322 #define EMAC_RX_ST_IRE                  0x0001
 323 #define EMAC_RX_TAH_BAD_CSUM            0x0003
 324 #define EMAC_BAD_RX_MASK                (EMAC_RX_ST_OE | EMAC_RX_ST_BP | \
 325                                          EMAC_RX_ST_RP | EMAC_RX_ST_SE | \
 326                                          EMAC_RX_ST_AE | EMAC_RX_ST_BFCS | \
 327                                          EMAC_RX_ST_PTL | EMAC_RX_ST_ORE | \
 328                                          EMAC_RX_ST_IRE )
 329 #endif /* __IBM_EMAC_H_ */