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sched: clean up wakeup balancing, move wake_affine()
[wrt350n-kernel.git] / drivers / video / tridentfb.c
blob0a4e07d43d2d44712e66477294175801b98e38fd
1 /*
2 * Frame buffer driver for Trident Blade and Image series
3 *
4 * Copyright 2001, 2002 - Jani Monoses <jani@iv.ro>
5 *
6 *
7 * CREDITS:(in order of appearance)
8 * skeletonfb.c by Geert Uytterhoeven and other fb code in drivers/video
9 * Special thanks ;) to Mattia Crivellini <tia@mclink.it>
10 * much inspired by the XFree86 4.x Trident driver sources
11 * by Alan Hourihane the FreeVGA project
12 * Francesco Salvestrini <salvestrini@users.sf.net> XP support,
13 * code, suggestions
14 * TODO:
15 * timing value tweaking so it looks good on every monitor in every mode
16 * TGUI acceleration
17 */
18
19 #include <linux/module.h>
20 #include <linux/fb.h>
21 #include <linux/init.h>
22 #include <linux/pci.h>
23
24 #include <linux/delay.h>
25 #include <video/trident.h>
26
27 #define VERSION "0.7.8-NEWAPI"
28
29 struct tridentfb_par {
30 int vclk; /* in MHz */
31 void __iomem *io_virt; /* iospace virtual memory address */
32 };
33
34 static unsigned char eng_oper; /* engine operation... */
35 static struct fb_ops tridentfb_ops;
36
37 static struct tridentfb_par default_par;
38
39 /* FIXME:kmalloc these 3 instead */
40 static struct fb_info fb_info;
41 static u32 pseudo_pal[16];
42
43 static struct fb_var_screeninfo default_var;
44
45 static struct fb_fix_screeninfo tridentfb_fix = {
46 .id = "Trident",
47 .type = FB_TYPE_PACKED_PIXELS,
48 .ypanstep = 1,
49 .visual = FB_VISUAL_PSEUDOCOLOR,
50 .accel = FB_ACCEL_NONE,
51 };
52
53 static int chip_id;
54
55 static int defaultaccel;
56 static int displaytype;
57
58 /* defaults which are normally overriden by user values */
59
60 /* video mode */
61 static char *mode = "640x480";
62 static int bpp = 8;
63
64 static int noaccel;
65
66 static int center;
67 static int stretch;
68
69 static int fp;
70 static int crt;
71
72 static int memsize;
73 static int memdiff;
74 static int nativex;
75
76 module_param(mode, charp, 0);
77 module_param(bpp, int, 0);
78 module_param(center, int, 0);
79 module_param(stretch, int, 0);
80 module_param(noaccel, int, 0);
81 module_param(memsize, int, 0);
82 module_param(memdiff, int, 0);
83 module_param(nativex, int, 0);
84 module_param(fp, int, 0);
85 module_param(crt, int, 0);
86
87 static int chip3D;
88 static int chipcyber;
89
90 static int is3Dchip(int id)
91 {
92 return ((id == BLADE3D) || (id == CYBERBLADEE4) ||
93 (id == CYBERBLADEi7) || (id == CYBERBLADEi7D) ||
94 (id == CYBER9397) || (id == CYBER9397DVD) ||
95 (id == CYBER9520) || (id == CYBER9525DVD) ||
96 (id == IMAGE975) || (id == IMAGE985) ||
97 (id == CYBERBLADEi1) || (id == CYBERBLADEi1D) ||
98 (id == CYBERBLADEAi1) || (id == CYBERBLADEAi1D) ||
99 (id == CYBERBLADEXPm8) || (id == CYBERBLADEXPm16) ||
100 (id == CYBERBLADEXPAi1));
101 }
102
103 static int iscyber(int id)
104 {
105 switch (id) {
106 case CYBER9388:
107 case CYBER9382:
108 case CYBER9385:
109 case CYBER9397:
110 case CYBER9397DVD:
111 case CYBER9520:
112 case CYBER9525DVD:
113 case CYBERBLADEE4:
114 case CYBERBLADEi7D:
115 case CYBERBLADEi1:
116 case CYBERBLADEi1D:
117 case CYBERBLADEAi1:
118 case CYBERBLADEAi1D:
119 case CYBERBLADEXPAi1:
120 return 1;
121
122 case CYBER9320:
123 case TGUI9660:
124 case IMAGE975:
125 case IMAGE985:
126 case BLADE3D:
127 case CYBERBLADEi7: /* VIA MPV4 integrated version */
128
129 default:
130 /* case CYBERBLDAEXPm8: Strange */
131 /* case CYBERBLDAEXPm16: Strange */
132 return 0;
133 }
134 }
135
136 #define CRT 0x3D0 /* CRTC registers offset for color display */
137
138 #ifndef TRIDENT_MMIO
139 #define TRIDENT_MMIO 1
140 #endif
141
142 #if TRIDENT_MMIO
143 #define t_outb(val, reg) writeb(val,((struct tridentfb_par *)(fb_info.par))->io_virt + reg)
144 #define t_inb(reg) readb(((struct tridentfb_par*)(fb_info.par))->io_virt + reg)
145 #else
146 #define t_outb(val, reg) outb(val, reg)
147 #define t_inb(reg) inb(reg)
148 #endif
149
150
151 static struct accel_switch {
152 void (*init_accel) (int, int);
153 void (*wait_engine) (void);
154 void (*fill_rect) (u32, u32, u32, u32, u32, u32);
155 void (*copy_rect) (u32, u32, u32, u32, u32, u32);
156 } *acc;
157
158 #define writemmr(r, v) writel(v, ((struct tridentfb_par *)fb_info.par)->io_virt + r)
159 #define readmmr(r) readl(((struct tridentfb_par *)fb_info.par)->io_virt + r)
160
161 /*
162 * Blade specific acceleration.
163 */
164
165 #define point(x, y) ((y) << 16 | (x))
166 #define STA 0x2120
167 #define CMD 0x2144
168 #define ROP 0x2148
169 #define CLR 0x2160
170 #define SR1 0x2100
171 #define SR2 0x2104
172 #define DR1 0x2108
173 #define DR2 0x210C
174
175 #define ROP_S 0xCC
176
177 static void blade_init_accel(int pitch, int bpp)
178 {
179 int v1 = (pitch >> 3) << 20;
180 int tmp = 0, v2;
181 switch (bpp) {
182 case 8:
183 tmp = 0;
184 break;
185 case 15:
186 tmp = 5;
187 break;
188 case 16:
189 tmp = 1;
190 break;
191 case 24:
192 case 32:
193 tmp = 2;
194 break;
195 }
196 v2 = v1 | (tmp << 29);
197 writemmr(0x21C0, v2);
198 writemmr(0x21C4, v2);
199 writemmr(0x21B8, v2);
200 writemmr(0x21BC, v2);
201 writemmr(0x21D0, v1);
202 writemmr(0x21D4, v1);
203 writemmr(0x21C8, v1);
204 writemmr(0x21CC, v1);
205 writemmr(0x216C, 0);
206 }
207
208 static void blade_wait_engine(void)
209 {
210 while (readmmr(STA) & 0xFA800000) ;
211 }
212
213 static void blade_fill_rect(u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
214 {
215 writemmr(CLR, c);
216 writemmr(ROP, rop ? 0x66 : ROP_S);
217 writemmr(CMD, 0x20000000 | 1 << 19 | 1 << 4 | 2 << 2);
218
219 writemmr(DR1, point(x, y));
220 writemmr(DR2, point(x + w - 1, y + h - 1));
221 }
222
223 static void blade_copy_rect(u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
224 {
225 u32 s1, s2, d1, d2;
226 int direction = 2;
227 s1 = point(x1, y1);
228 s2 = point(x1 + w - 1, y1 + h - 1);
229 d1 = point(x2, y2);
230 d2 = point(x2 + w - 1, y2 + h - 1);
231
232 if ((y1 > y2) || ((y1 == y2) && (x1 > x2)))
233 direction = 0;
234
235 writemmr(ROP, ROP_S);
236 writemmr(CMD, 0xE0000000 | 1 << 19 | 1 << 4 | 1 << 2 | direction);
237
238 writemmr(SR1, direction ? s2 : s1);
239 writemmr(SR2, direction ? s1 : s2);
240 writemmr(DR1, direction ? d2 : d1);
241 writemmr(DR2, direction ? d1 : d2);
242 }
243
244 static struct accel_switch accel_blade = {
245 blade_init_accel,
246 blade_wait_engine,
247 blade_fill_rect,
248 blade_copy_rect,
249 };
250
251 /*
252 * BladeXP specific acceleration functions
253 */
254
255 #define ROP_P 0xF0
256 #define masked_point(x, y) ((y & 0xffff)<<16|(x & 0xffff))
257
258 static void xp_init_accel(int pitch, int bpp)
259 {
260 int tmp = 0, v1;
261 unsigned char x = 0;
262
263 switch (bpp) {
264 case 8:
265 x = 0;
266 break;
267 case 16:
268 x = 1;
269 break;
270 case 24:
271 x = 3;
272 break;
273 case 32:
274 x = 2;
275 break;
276 }
277
278 switch (pitch << (bpp >> 3)) {
279 case 8192:
280 case 512:
281 x |= 0x00;
282 break;
283 case 1024:
284 x |= 0x04;
285 break;
286 case 2048:
287 x |= 0x08;
288 break;
289 case 4096:
290 x |= 0x0C;
291 break;
292 }
293
294 t_outb(x, 0x2125);
295
296 eng_oper = x | 0x40;
297
298 switch (bpp) {
299 case 8:
300 tmp = 18;
301 break;
302 case 15:
303 case 16:
304 tmp = 19;
305 break;
306 case 24:
307 case 32:
308 tmp = 20;
309 break;
310 }
311
312 v1 = pitch << tmp;
313
314 writemmr(0x2154, v1);
315 writemmr(0x2150, v1);
316 t_outb(3, 0x2126);
317 }
318
319 static void xp_wait_engine(void)
320 {
321 int busy;
322 int count, timeout;
323
324 count = 0;
325 timeout = 0;
326 for (;;) {
327 busy = t_inb(STA) & 0x80;
328 if (busy != 0x80)
329 return;
330 count++;
331 if (count == 10000000) {
332 /* Timeout */
333 count = 9990000;
334 timeout++;
335 if (timeout == 8) {
336 /* Reset engine */
337 t_outb(0x00, 0x2120);
338 return;
339 }
340 }
341 }
342 }
343
344 static void xp_fill_rect(u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
345 {
346 writemmr(0x2127, ROP_P);
347 writemmr(0x2158, c);
348 writemmr(0x2128, 0x4000);
349 writemmr(0x2140, masked_point(h, w));
350 writemmr(0x2138, masked_point(y, x));
351 t_outb(0x01, 0x2124);
352 t_outb(eng_oper, 0x2125);
353 }
354
355 static void xp_copy_rect(u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
356 {
357 int direction;
358 u32 x1_tmp, x2_tmp, y1_tmp, y2_tmp;
359
360 direction = 0x0004;
361
362 if ((x1 < x2) && (y1 == y2)) {
363 direction |= 0x0200;
364 x1_tmp = x1 + w - 1;
365 x2_tmp = x2 + w - 1;
366 } else {
367 x1_tmp = x1;
368 x2_tmp = x2;
369 }
370
371 if (y1 < y2) {
372 direction |= 0x0100;
373 y1_tmp = y1 + h - 1;
374 y2_tmp = y2 + h - 1;
375 } else {
376 y1_tmp = y1;
377 y2_tmp = y2;
378 }
379
380 writemmr(0x2128, direction);
381 t_outb(ROP_S, 0x2127);
382 writemmr(0x213C, masked_point(y1_tmp, x1_tmp));
383 writemmr(0x2138, masked_point(y2_tmp, x2_tmp));
384 writemmr(0x2140, masked_point(h, w));
385 t_outb(0x01, 0x2124);
386 }
387
388 static struct accel_switch accel_xp = {
389 xp_init_accel,
390 xp_wait_engine,
391 xp_fill_rect,
392 xp_copy_rect,
393 };
394
395 /*
396 * Image specific acceleration functions
397 */
398 static void image_init_accel(int pitch, int bpp)
399 {
400 int tmp = 0;
401 switch (bpp) {
402 case 8:
403 tmp = 0;
404 break;
405 case 15:
406 tmp = 5;
407 break;
408 case 16:
409 tmp = 1;
410 break;
411 case 24:
412 case 32:
413 tmp = 2;
414 break;
415 }
416 writemmr(0x2120, 0xF0000000);
417 writemmr(0x2120, 0x40000000 | tmp);
418 writemmr(0x2120, 0x80000000);
419 writemmr(0x2144, 0x00000000);
420 writemmr(0x2148, 0x00000000);
421 writemmr(0x2150, 0x00000000);
422 writemmr(0x2154, 0x00000000);
423 writemmr(0x2120, 0x60000000 | (pitch << 16) | pitch);
424 writemmr(0x216C, 0x00000000);
425 writemmr(0x2170, 0x00000000);
426 writemmr(0x217C, 0x00000000);
427 writemmr(0x2120, 0x10000000);
428 writemmr(0x2130, (2047 << 16) | 2047);
429 }
430
431 static void image_wait_engine(void)
432 {
433 while (readmmr(0x2164) & 0xF0000000) ;
434 }
435
436 static void image_fill_rect(u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
437 {
438 writemmr(0x2120, 0x80000000);
439 writemmr(0x2120, 0x90000000 | ROP_S);
440
441 writemmr(0x2144, c);
442
443 writemmr(DR1, point(x, y));
444 writemmr(DR2, point(x + w - 1, y + h - 1));
445
446 writemmr(0x2124, 0x80000000 | 3 << 22 | 1 << 10 | 1 << 9);
447 }
448
449 static void image_copy_rect(u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
450 {
451 u32 s1, s2, d1, d2;
452 int direction = 2;
453 s1 = point(x1, y1);
454 s2 = point(x1 + w - 1, y1 + h - 1);
455 d1 = point(x2, y2);
456 d2 = point(x2 + w - 1, y2 + h - 1);
457
458 if ((y1 > y2) || ((y1 == y2) && (x1 > x2)))
459 direction = 0;
460
461 writemmr(0x2120, 0x80000000);
462 writemmr(0x2120, 0x90000000 | ROP_S);
463
464 writemmr(SR1, direction ? s2 : s1);
465 writemmr(SR2, direction ? s1 : s2);
466 writemmr(DR1, direction ? d2 : d1);
467 writemmr(DR2, direction ? d1 : d2);
468 writemmr(0x2124, 0x80000000 | 1 << 22 | 1 << 10 | 1 << 7 | direction);
469 }
470
471 static struct accel_switch accel_image = {
472 image_init_accel,
473 image_wait_engine,
474 image_fill_rect,
475 image_copy_rect,
476 };
477
478 /*
479 * Accel functions called by the upper layers
480 */
481 #ifdef CONFIG_FB_TRIDENT_ACCEL
482 static void tridentfb_fillrect(struct fb_info *info,
483 const struct fb_fillrect *fr)
484 {
485 int bpp = info->var.bits_per_pixel;
486 int col = 0;
487
488 switch (bpp) {
489 default:
490 case 8:
491 col |= fr->color;
492 col |= col << 8;
493 col |= col << 16;
494 break;
495 case 16:
496 col = ((u32 *)(info->pseudo_palette))[fr->color];
497 break;
498 case 32:
499 col = ((u32 *)(info->pseudo_palette))[fr->color];
500 break;
501 }
502
503 acc->fill_rect(fr->dx, fr->dy, fr->width, fr->height, col, fr->rop);
504 acc->wait_engine();
505 }
506 static void tridentfb_copyarea(struct fb_info *info,
507 const struct fb_copyarea *ca)
508 {
509 acc->copy_rect(ca->sx, ca->sy, ca->dx, ca->dy, ca->width, ca->height);
510 acc->wait_engine();
511 }
512 #else /* !CONFIG_FB_TRIDENT_ACCEL */
513 #define tridentfb_fillrect cfb_fillrect
514 #define tridentfb_copyarea cfb_copyarea
515 #endif /* CONFIG_FB_TRIDENT_ACCEL */
516
517
518 /*
519 * Hardware access functions
520 */
521
522 static inline unsigned char read3X4(int reg)
523 {
524 struct tridentfb_par *par = (struct tridentfb_par *)fb_info.par;
525 writeb(reg, par->io_virt + CRT + 4);
526 return readb(par->io_virt + CRT + 5);
527 }
528
529 static inline void write3X4(int reg, unsigned char val)
530 {
531 struct tridentfb_par *par = (struct tridentfb_par *)fb_info.par;
532 writeb(reg, par->io_virt + CRT + 4);
533 writeb(val, par->io_virt + CRT + 5);
534 }
535
536 static inline unsigned char read3C4(int reg)
537 {
538 t_outb(reg, 0x3C4);
539 return t_inb(0x3C5);
540 }
541
542 static inline void write3C4(int reg, unsigned char val)
543 {
544 t_outb(reg, 0x3C4);
545 t_outb(val, 0x3C5);
546 }
547
548 static inline unsigned char read3CE(int reg)
549 {
550 t_outb(reg, 0x3CE);
551 return t_inb(0x3CF);
552 }
553
554 static inline void writeAttr(int reg, unsigned char val)
555 {
556 readb(((struct tridentfb_par *)fb_info.par)->io_virt + CRT + 0x0A); /* flip-flop to index */
557 t_outb(reg, 0x3C0);
558 t_outb(val, 0x3C0);
559 }
560
561 static inline void write3CE(int reg, unsigned char val)
562 {
563 t_outb(reg, 0x3CE);
564 t_outb(val, 0x3CF);
565 }
566
567 static void enable_mmio(void)
568 {
569 /* Goto New Mode */
570 outb(0x0B, 0x3C4);
571 inb(0x3C5);
572
573 /* Unprotect registers */
574 outb(NewMode1, 0x3C4);
575 outb(0x80, 0x3C5);
576
577 /* Enable MMIO */
578 outb(PCIReg, 0x3D4);
579 outb(inb(0x3D5) | 0x01, 0x3D5);
580 }
581
582 static void disable_mmio(void)
583 {
584 /* Goto New Mode */
585 t_outb(0x0B, 0x3C4);
586 t_inb(0x3C5);
587
588 /* Unprotect registers */
589 t_outb(NewMode1, 0x3C4);
590 t_outb(0x80, 0x3C5);
591
592 /* Disable MMIO */
593 t_outb(PCIReg, 0x3D4);
594 t_outb(t_inb(0x3D5) & ~0x01, 0x3D5);
595 }
596
597 #define crtc_unlock() write3X4(CRTVSyncEnd, read3X4(CRTVSyncEnd) & 0x7F)
598
599 /* Return flat panel's maximum x resolution */
600 static int __devinit get_nativex(void)
601 {
602 int x, y, tmp;
603
604 if (nativex)
605 return nativex;
606
607 tmp = (read3CE(VertStretch) >> 4) & 3;
608
609 switch (tmp) {
610 case 0:
611 x = 1280; y = 1024;
612 break;
613 case 2:
614 x = 1024; y = 768;
615 break;
616 case 3:
617 x = 800; y = 600;
618 break;
619 case 4:
620 x = 1400; y = 1050;
621 break;
622 case 1:
623 default:
624 x = 640; y = 480;
625 break;
626 }
627
628 output("%dx%d flat panel found\n", x, y);
629 return x;
630 }
631
632 /* Set pitch */
633 static void set_lwidth(int width)
634 {
635 write3X4(Offset, width & 0xFF);
636 write3X4(AddColReg,
637 (read3X4(AddColReg) & 0xCF) | ((width & 0x300) >> 4));
638 }
639
640 /* For resolutions smaller than FP resolution stretch */
641 static void screen_stretch(void)
642 {
643 if (chip_id != CYBERBLADEXPAi1)
644 write3CE(BiosReg, 0);
645 else
646 write3CE(BiosReg, 8);
647 write3CE(VertStretch, (read3CE(VertStretch) & 0x7C) | 1);
648 write3CE(HorStretch, (read3CE(HorStretch) & 0x7C) | 1);
649 }
650
651 /* For resolutions smaller than FP resolution center */
652 static void screen_center(void)
653 {
654 write3CE(VertStretch, (read3CE(VertStretch) & 0x7C) | 0x80);
655 write3CE(HorStretch, (read3CE(HorStretch) & 0x7C) | 0x80);
656 }
657
658 /* Address of first shown pixel in display memory */
659 static void set_screen_start(int base)
660 {
661 write3X4(StartAddrLow, base & 0xFF);
662 write3X4(StartAddrHigh, (base & 0xFF00) >> 8);
663 write3X4(CRTCModuleTest,
664 (read3X4(CRTCModuleTest) & 0xDF) | ((base & 0x10000) >> 11));
665 write3X4(CRTHiOrd,
666 (read3X4(CRTHiOrd) & 0xF8) | ((base & 0xE0000) >> 17));
667 }
668
669 /* Use 20.12 fixed-point for NTSC value and frequency calculation */
670 #define calc_freq(n, m, k) ( ((unsigned long)0xE517 * (n + 8) / ((m + 2) * (1 << k))) >> 12 )
671
672 /* Set dotclock frequency */
673 static void set_vclk(int freq)
674 {
675 int m, n, k;
676 int f, fi, d, di;
677 unsigned char lo = 0, hi = 0;
678
679 d = 20;
680 for (k = 2; k >= 0; k--)
681 for (m = 0; m < 63; m++)
682 for (n = 0; n < 128; n++) {
683 fi = calc_freq(n, m, k);
684 if ((di = abs(fi - freq)) < d) {
685 d = di;
686 f = fi;
687 lo = n;
688 hi = (k << 6) | m;
689 }
690 }
691 if (chip3D) {
692 write3C4(ClockHigh, hi);
693 write3C4(ClockLow, lo);
694 } else {
695 outb(lo, 0x43C8);
696 outb(hi, 0x43C9);
697 }
698 debug("VCLK = %X %X\n", hi, lo);
699 }
700
701 /* Set number of lines for flat panels*/
702 static void set_number_of_lines(int lines)
703 {
704 int tmp = read3CE(CyberEnhance) & 0x8F;
705 if (lines > 1024)
706 tmp |= 0x50;
707 else if (lines > 768)
708 tmp |= 0x30;
709 else if (lines > 600)
710 tmp |= 0x20;
711 else if (lines > 480)
712 tmp |= 0x10;
713 write3CE(CyberEnhance, tmp);
714 }
715
716 /*
717 * If we see that FP is active we assume we have one.
718 * Otherwise we have a CRT display.User can override.
719 */
720 static unsigned int __devinit get_displaytype(void)
721 {
722 if (fp)
723 return DISPLAY_FP;
724 if (crt || !chipcyber)
725 return DISPLAY_CRT;
726 return (read3CE(FPConfig) & 0x10) ? DISPLAY_FP : DISPLAY_CRT;
727 }
728
729 /* Try detecting the video memory size */
730 static unsigned int __devinit get_memsize(void)
731 {
732 unsigned char tmp, tmp2;
733 unsigned int k;
734
735 /* If memory size provided by user */
736 if (memsize)
737 k = memsize * Kb;
738 else
739 switch (chip_id) {
740 case CYBER9525DVD:
741 k = 2560 * Kb;
742 break;
743 default:
744 tmp = read3X4(SPR) & 0x0F;
745 switch (tmp) {
746
747 case 0x01:
748 k = 512 * Kb;
749 break;
750 case 0x02:
751 k = 6 * Mb; /* XP */
752 break;
753 case 0x03:
754 k = 1 * Mb;
755 break;
756 case 0x04:
757 k = 8 * Mb;
758 break;
759 case 0x06:
760 k = 10 * Mb; /* XP */
761 break;
762 case 0x07:
763 k = 2 * Mb;
764 break;
765 case 0x08:
766 k = 12 * Mb; /* XP */
767 break;
768 case 0x0A:
769 k = 14 * Mb; /* XP */
770 break;
771 case 0x0C:
772 k = 16 * Mb; /* XP */
773 break;
774 case 0x0E: /* XP */
775
776 tmp2 = read3C4(0xC1);
777 switch (tmp2) {
778 case 0x00:
779 k = 20 * Mb;
780 break;
781 case 0x01:
782 k = 24 * Mb;
783 break;
784 case 0x10:
785 k = 28 * Mb;
786 break;
787 case 0x11:
788 k = 32 * Mb;
789 break;
790 default:
791 k = 1 * Mb;
792 break;
793 }
794 break;
795
796 case 0x0F:
797 k = 4 * Mb;
798 break;
799 default:
800 k = 1 * Mb;
801 break;
802 }
803 }
804
805 k -= memdiff * Kb;
806 output("framebuffer size = %d Kb\n", k / Kb);
807 return k;
808 }
809
810 /* See if we can handle the video mode described in var */
811 static int tridentfb_check_var(struct fb_var_screeninfo *var,
812 struct fb_info *info)
813 {
814 int bpp = var->bits_per_pixel;
815 debug("enter\n");
816
817 /* check color depth */
818 if (bpp == 24)
819 bpp = var->bits_per_pixel = 32;
820 /* check whether resolution fits on panel and in memory */
821 if (flatpanel && nativex && var->xres > nativex)
822 return -EINVAL;
823 if (var->xres * var->yres_virtual * bpp / 8 > info->fix.smem_len)
824 return -EINVAL;
825
826 switch (bpp) {
827 case 8:
828 var->red.offset = 0;
829 var->green.offset = 0;
830 var->blue.offset = 0;
831 var->red.length = 6;
832 var->green.length = 6;
833 var->blue.length = 6;
834 break;
835 case 16:
836 var->red.offset = 11;
837 var->green.offset = 5;
838 var->blue.offset = 0;
839 var->red.length = 5;
840 var->green.length = 6;
841 var->blue.length = 5;
842 break;
843 case 32:
844 var->red.offset = 16;
845 var->green.offset = 8;
846 var->blue.offset = 0;
847 var->red.length = 8;
848 var->green.length = 8;
849 var->blue.length = 8;
850 break;
851 default:
852 return -EINVAL;
853 }
854 debug("exit\n");
855
856 return 0;
857
858 }
859
860 /* Pan the display */
861 static int tridentfb_pan_display(struct fb_var_screeninfo *var,
862 struct fb_info *info)
863 {
864 unsigned int offset;
865
866 debug("enter\n");
867 offset = (var->xoffset + (var->yoffset * var->xres))
868 * var->bits_per_pixel / 32;
869 info->var.xoffset = var->xoffset;
870 info->var.yoffset = var->yoffset;
871 set_screen_start(offset);
872 debug("exit\n");
873 return 0;
874 }
875
876 #define shadowmode_on() write3CE(CyberControl, read3CE(CyberControl) | 0x81)
877 #define shadowmode_off() write3CE(CyberControl, read3CE(CyberControl) & 0x7E)
878
879 /* Set the hardware to the requested video mode */
880 static int tridentfb_set_par(struct fb_info *info)
881 {
882 struct tridentfb_par *par = (struct tridentfb_par *)(info->par);
883 u32 htotal, hdispend, hsyncstart, hsyncend, hblankstart, hblankend;
884 u32 vtotal, vdispend, vsyncstart, vsyncend, vblankstart, vblankend;
885 struct fb_var_screeninfo *var = &info->var;
886 int bpp = var->bits_per_pixel;
887 unsigned char tmp;
888 debug("enter\n");
889 hdispend = var->xres / 8 - 1;
890 hsyncstart = (var->xres + var->right_margin) / 8;
891 hsyncend = var->hsync_len / 8;
892 htotal =
893 (var->xres + var->left_margin + var->right_margin +
894 var->hsync_len) / 8 - 10;
895 hblankstart = hdispend + 1;
896 hblankend = htotal + 5;
897
898 vdispend = var->yres - 1;
899 vsyncstart = var->yres + var->lower_margin;
900 vsyncend = var->vsync_len;
901 vtotal = var->upper_margin + vsyncstart + vsyncend - 2;
902 vblankstart = var->yres;
903 vblankend = vtotal + 2;
904
905 enable_mmio();
906 crtc_unlock();
907 write3CE(CyberControl, 8);
908
909 if (flatpanel && var->xres < nativex) {
910 /*
911 * on flat panels with native size larger
912 * than requested resolution decide whether
913 * we stretch or center
914 */
915 t_outb(0xEB, 0x3C2);
916
917 shadowmode_on();
918
919 if (center)
920 screen_center();
921 else if (stretch)
922 screen_stretch();
923
924 } else {
925 t_outb(0x2B, 0x3C2);
926 write3CE(CyberControl, 8);
927 }
928
929 /* vertical timing values */
930 write3X4(CRTVTotal, vtotal & 0xFF);
931 write3X4(CRTVDispEnd, vdispend & 0xFF);
932 write3X4(CRTVSyncStart, vsyncstart & 0xFF);
933 write3X4(CRTVSyncEnd, (vsyncend & 0x0F));
934 write3X4(CRTVBlankStart, vblankstart & 0xFF);
935 write3X4(CRTVBlankEnd, 0 /* p->vblankend & 0xFF */ );
936
937 /* horizontal timing values */
938 write3X4(CRTHTotal, htotal & 0xFF);
939 write3X4(CRTHDispEnd, hdispend & 0xFF);
940 write3X4(CRTHSyncStart, hsyncstart & 0xFF);
941 write3X4(CRTHSyncEnd, (hsyncend & 0x1F) | ((hblankend & 0x20) << 2));
942 write3X4(CRTHBlankStart, hblankstart & 0xFF);
943 write3X4(CRTHBlankEnd, 0 /* (p->hblankend & 0x1F) */ );
944
945 /* higher bits of vertical timing values */
946 tmp = 0x10;
947 if (vtotal & 0x100) tmp |= 0x01;
948 if (vdispend & 0x100) tmp |= 0x02;
949 if (vsyncstart & 0x100) tmp |= 0x04;
950 if (vblankstart & 0x100) tmp |= 0x08;
951
952 if (vtotal & 0x200) tmp |= 0x20;
953 if (vdispend & 0x200) tmp |= 0x40;
954 if (vsyncstart & 0x200) tmp |= 0x80;
955 write3X4(CRTOverflow, tmp);
956
957 tmp = read3X4(CRTHiOrd) | 0x08; /* line compare bit 10 */
958 if (vtotal & 0x400) tmp |= 0x80;
959 if (vblankstart & 0x400) tmp |= 0x40;
960 if (vsyncstart & 0x400) tmp |= 0x20;
961 if (vdispend & 0x400) tmp |= 0x10;
962 write3X4(CRTHiOrd, tmp);
963
964 tmp = 0;
965 if (htotal & 0x800) tmp |= 0x800 >> 11;
966 if (hblankstart & 0x800) tmp |= 0x800 >> 7;
967 write3X4(HorizOverflow, tmp);
968
969 tmp = 0x40;
970 if (vblankstart & 0x200) tmp |= 0x20;
971 //FIXME if (info->var.vmode & FB_VMODE_DOUBLE) tmp |= 0x80; /* double scan for 200 line modes */
972 write3X4(CRTMaxScanLine, tmp);
973
974 write3X4(CRTLineCompare, 0xFF);
975 write3X4(CRTPRowScan, 0);
976 write3X4(CRTModeControl, 0xC3);
977
978 write3X4(LinearAddReg, 0x20); /* enable linear addressing */
979
980 tmp = (info->var.vmode & FB_VMODE_INTERLACED) ? 0x84 : 0x80;
981 write3X4(CRTCModuleTest, tmp); /* enable access extended memory */
982
983 write3X4(GraphEngReg, 0x80); /* enable GE for text acceleration */
984
985 #ifdef CONFIG_FB_TRIDENT_ACCEL
986 acc->init_accel(info->var.xres, bpp);
987 #endif
988
989 switch (bpp) {
990 case 8:
991 tmp = 0x00;
992 break;
993 case 16:
994 tmp = 0x05;
995 break;
996 case 24:
997 tmp = 0x29;
998 break;
999 case 32:
1000 tmp = 0x09;
1001 break;
1002 }
1003
1004 write3X4(PixelBusReg, tmp);
1005
1006 tmp = 0x10;
1007 if (chipcyber)
1008 tmp |= 0x20;
1009 write3X4(DRAMControl, tmp); /* both IO, linear enable */
1010
1011 write3X4(InterfaceSel, read3X4(InterfaceSel) | 0x40);
1012 write3X4(Performance, 0x92);
1013 write3X4(PCIReg, 0x07); /* MMIO & PCI read and write burst enable */
1014
1015 /* convert from picoseconds to MHz */
1016 par->vclk = 1000000 / info->var.pixclock;
1017 if (bpp == 32)
1018 par->vclk *= 2;
1019 set_vclk(par->vclk);
1020
1021 write3C4(0, 3);
1022 write3C4(1, 1); /* set char clock 8 dots wide */
1023 write3C4(2, 0x0F); /* enable 4 maps because needed in chain4 mode */
1024 write3C4(3, 0);
1025 write3C4(4, 0x0E); /* memory mode enable bitmaps ?? */
1026
1027 write3CE(MiscExtFunc, (bpp == 32) ? 0x1A : 0x12); /* divide clock by 2 if 32bpp */
1028 /* chain4 mode display and CPU path */
1029 write3CE(0x5, 0x40); /* no CGA compat, allow 256 col */
1030 write3CE(0x6, 0x05); /* graphics mode */
1031 write3CE(0x7, 0x0F); /* planes? */
1032
1033 if (chip_id == CYBERBLADEXPAi1) {
1034 /* This fixes snow-effect in 32 bpp */
1035 write3X4(CRTHSyncStart, 0x84);
1036 }
1037
1038 writeAttr(0x10, 0x41); /* graphics mode and support 256 color modes */
1039 writeAttr(0x12, 0x0F); /* planes */
1040 writeAttr(0x13, 0); /* horizontal pel panning */
1041
1042 /* colors */
1043 for (tmp = 0; tmp < 0x10; tmp++)
1044 writeAttr(tmp, tmp);
1045 readb(par->io_virt + CRT + 0x0A); /* flip-flop to index */
1046 t_outb(0x20, 0x3C0); /* enable attr */
1047
1048 switch (bpp) {
1049 case 8:
1050 tmp = 0;
1051 break;
1052 case 15:
1053 tmp = 0x10;
1054 break;
1055 case 16:
1056 tmp = 0x30;
1057 break;
1058 case 24:
1059 case 32:
1060 tmp = 0xD0;
1061 break;
1062 }
1063
1064 t_inb(0x3C8);
1065 t_inb(0x3C6);
1066 t_inb(0x3C6);
1067 t_inb(0x3C6);
1068 t_inb(0x3C6);
1069 t_outb(tmp, 0x3C6);
1070 t_inb(0x3C8);
1071
1072 if (flatpanel)
1073 set_number_of_lines(info->var.yres);
1074 set_lwidth(info->var.xres * bpp / (4 * 16));
1075 info->fix.visual = (bpp == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
1076 info->fix.line_length = info->var.xres * (bpp >> 3);
1077 info->cmap.len = (bpp == 8) ? 256 : 16;
1078 debug("exit\n");
1079 return 0;
1080 }
1081
1082 /* Set one color register */
1083 static int tridentfb_setcolreg(unsigned regno, unsigned red, unsigned green,
1084 unsigned blue, unsigned transp,
1085 struct fb_info *info)
1086 {
1087 int bpp = info->var.bits_per_pixel;
1088
1089 if (regno >= info->cmap.len)
1090 return 1;
1091
1092 if (bpp == 8) {
1093 t_outb(0xFF, 0x3C6);
1094 t_outb(regno, 0x3C8);
1095
1096 t_outb(red >> 10, 0x3C9);
1097 t_outb(green >> 10, 0x3C9);
1098 t_outb(blue >> 10, 0x3C9);
1099
1100 } else if (regno < 16) {
1101 if (bpp == 16) { /* RGB 565 */
1102 u32 col;
1103
1104 col = (red & 0xF800) | ((green & 0xFC00) >> 5) |
1105 ((blue & 0xF800) >> 11);
1106 col |= col << 16;
1107 ((u32 *)(info->pseudo_palette))[regno] = col;
1108 } else if (bpp == 32) /* ARGB 8888 */
1109 ((u32*)info->pseudo_palette)[regno] =
1110 ((transp & 0xFF00) << 16) |
1111 ((red & 0xFF00) << 8) |
1112 ((green & 0xFF00)) |
1113 ((blue & 0xFF00) >> 8);
1114 }
1115
1116 /* debug("exit\n"); */
1117 return 0;
1118 }
1119
1120 /* Try blanking the screen.For flat panels it does nothing */
1121 static int tridentfb_blank(int blank_mode, struct fb_info *info)
1122 {
1123 unsigned char PMCont, DPMSCont;
1124
1125 debug("enter\n");
1126 if (flatpanel)
1127 return 0;
1128 t_outb(0x04, 0x83C8); /* Read DPMS Control */
1129 PMCont = t_inb(0x83C6) & 0xFC;
1130 DPMSCont = read3CE(PowerStatus) & 0xFC;
1131 switch (blank_mode) {
1132 case FB_BLANK_UNBLANK:
1133 /* Screen: On, HSync: On, VSync: On */
1134 case FB_BLANK_NORMAL:
1135 /* Screen: Off, HSync: On, VSync: On */
1136 PMCont |= 0x03;
1137 DPMSCont |= 0x00;
1138 break;
1139 case FB_BLANK_HSYNC_SUSPEND:
1140 /* Screen: Off, HSync: Off, VSync: On */
1141 PMCont |= 0x02;
1142 DPMSCont |= 0x01;
1143 break;
1144 case FB_BLANK_VSYNC_SUSPEND:
1145 /* Screen: Off, HSync: On, VSync: Off */
1146 PMCont |= 0x02;
1147 DPMSCont |= 0x02;
1148 break;
1149 case FB_BLANK_POWERDOWN:
1150 /* Screen: Off, HSync: Off, VSync: Off */
1151 PMCont |= 0x00;
1152 DPMSCont |= 0x03;
1153 break;
1154 }
1155
1156 write3CE(PowerStatus, DPMSCont);
1157 t_outb(4, 0x83C8);
1158 t_outb(PMCont, 0x83C6);
1159
1160 debug("exit\n");
1161
1162 /* let fbcon do a softblank for us */
1163 return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0;
1164 }
1165
1166 static struct fb_ops tridentfb_ops = {
1167 .owner = THIS_MODULE,
1168 .fb_setcolreg = tridentfb_setcolreg,
1169 .fb_pan_display = tridentfb_pan_display,
1170 .fb_blank = tridentfb_blank,
1171 .fb_check_var = tridentfb_check_var,
1172 .fb_set_par = tridentfb_set_par,
1173 .fb_fillrect = tridentfb_fillrect,
1174 .fb_copyarea = tridentfb_copyarea,
1175 .fb_imageblit = cfb_imageblit,
1176 };
1177
1178 static int __devinit trident_pci_probe(struct pci_dev * dev,
1179 const struct pci_device_id * id)
1180 {
1181 int err;
1182 unsigned char revision;
1183
1184 err = pci_enable_device(dev);
1185 if (err)
1186 return err;
1187
1188 chip_id = id->device;
1189
1190 if (chip_id == CYBERBLADEi1)
1191 output("*** Please do use cyblafb, Cyberblade/i1 support "
1192 "will soon be removed from tridentfb!\n");
1193
1194
1195 /* If PCI id is 0x9660 then further detect chip type */
1196
1197 if (chip_id == TGUI9660) {
1198 outb(RevisionID, 0x3C4);
1199 revision = inb(0x3C5);
1200
1201 switch (revision) {
1202 case 0x22:
1203 case 0x23:
1204 chip_id = CYBER9397;
1205 break;
1206 case 0x2A:
1207 chip_id = CYBER9397DVD;
1208 break;
1209 case 0x30:
1210 case 0x33:
1211 case 0x34:
1212 case 0x35:
1213 case 0x38:
1214 case 0x3A:
1215 case 0xB3:
1216 chip_id = CYBER9385;
1217 break;
1218 case 0x40 ... 0x43:
1219 chip_id = CYBER9382;
1220 break;
1221 case 0x4A:
1222 chip_id = CYBER9388;
1223 break;
1224 default:
1225 break;
1226 }
1227 }
1228
1229 chip3D = is3Dchip(chip_id);
1230 chipcyber = iscyber(chip_id);
1231
1232 if (is_xp(chip_id)) {
1233 acc = &accel_xp;
1234 } else if (is_blade(chip_id)) {
1235 acc = &accel_blade;
1236 } else {
1237 acc = &accel_image;
1238 }
1239
1240 /* acceleration is on by default for 3D chips */
1241 defaultaccel = chip3D && !noaccel;
1242
1243 fb_info.par = &default_par;
1244
1245 /* setup MMIO region */
1246 tridentfb_fix.mmio_start = pci_resource_start(dev, 1);
1247 tridentfb_fix.mmio_len = chip3D ? 0x20000 : 0x10000;
1248
1249 if (!request_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len, "tridentfb")) {
1250 debug("request_region failed!\n");
1251 return -1;
1252 }
1253
1254 default_par.io_virt = ioremap_nocache(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len);
1255
1256 if (!default_par.io_virt) {
1257 debug("ioremap failed\n");
1258 err = -1;
1259 goto out_unmap1;
1260 }
1261
1262 enable_mmio();
1263
1264 /* setup framebuffer memory */
1265 tridentfb_fix.smem_start = pci_resource_start(dev, 0);
1266 tridentfb_fix.smem_len = get_memsize();
1267
1268 if (!request_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len, "tridentfb")) {
1269 debug("request_mem_region failed!\n");
1270 disable_mmio();
1271 err = -1;
1272 goto out_unmap1;
1273 }
1274
1275 fb_info.screen_base = ioremap_nocache(tridentfb_fix.smem_start,
1276 tridentfb_fix.smem_len);
1277
1278 if (!fb_info.screen_base) {
1279 debug("ioremap failed\n");
1280 err = -1;
1281 goto out_unmap2;
1282 }
1283
1284 output("%s board found\n", pci_name(dev));
1285 displaytype = get_displaytype();
1286
1287 if (flatpanel)
1288 nativex = get_nativex();
1289
1290 fb_info.fix = tridentfb_fix;
1291 fb_info.fbops = &tridentfb_ops;
1292
1293
1294 fb_info.flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
1295 #ifdef CONFIG_FB_TRIDENT_ACCEL
1296 fb_info.flags |= FBINFO_HWACCEL_COPYAREA | FBINFO_HWACCEL_FILLRECT;
1297 #endif
1298 fb_info.pseudo_palette = pseudo_pal;
1299
1300 if (!fb_find_mode(&default_var, &fb_info, mode, NULL, 0, NULL, bpp)) {
1301 err = -EINVAL;
1302 goto out_unmap2;
1303 }
1304 err = fb_alloc_cmap(&fb_info.cmap, 256, 0);
1305 if (err < 0)
1306 goto out_unmap2;
1307
1308 if (defaultaccel && acc)
1309 default_var.accel_flags |= FB_ACCELF_TEXT;
1310 else
1311 default_var.accel_flags &= ~FB_ACCELF_TEXT;
1312 default_var.activate |= FB_ACTIVATE_NOW;
1313 fb_info.var = default_var;
1314 fb_info.device = &dev->dev;
1315 if (register_framebuffer(&fb_info) < 0) {
1316 printk(KERN_ERR "tridentfb: could not register Trident framebuffer\n");
1317 fb_dealloc_cmap(&fb_info.cmap);
1318 err = -EINVAL;
1319 goto out_unmap2;
1320 }
1321 output("fb%d: %s frame buffer device %dx%d-%dbpp\n",
1322 fb_info.node, fb_info.fix.id, default_var.xres,
1323 default_var.yres, default_var.bits_per_pixel);
1324 return 0;
1325
1326 out_unmap2:
1327 if (fb_info.screen_base)
1328 iounmap(fb_info.screen_base);
1329 release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len);
1330 disable_mmio();
1331 out_unmap1:
1332 if (default_par.io_virt)
1333 iounmap(default_par.io_virt);
1334 release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len);
1335 return err;
1336 }
1337
1338 static void __devexit trident_pci_remove(struct pci_dev *dev)
1339 {
1340 struct tridentfb_par *par = (struct tridentfb_par*)fb_info.par;
1341 unregister_framebuffer(&fb_info);
1342 iounmap(par->io_virt);
1343 iounmap(fb_info.screen_base);
1344 release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len);
1345 release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len);
1346 }
1347
1348 /* List of boards that we are trying to support */
1349 static struct pci_device_id trident_devices[] = {
1350 {PCI_VENDOR_ID_TRIDENT, BLADE3D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1351 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1352 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1353 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1354 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1355 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1356 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1357 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEE4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1358 {PCI_VENDOR_ID_TRIDENT, TGUI9660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1359 {PCI_VENDOR_ID_TRIDENT, IMAGE975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1360 {PCI_VENDOR_ID_TRIDENT, IMAGE985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1361 {PCI_VENDOR_ID_TRIDENT, CYBER9320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1362 {PCI_VENDOR_ID_TRIDENT, CYBER9388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1363 {PCI_VENDOR_ID_TRIDENT, CYBER9520, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1364 {PCI_VENDOR_ID_TRIDENT, CYBER9525DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1365 {PCI_VENDOR_ID_TRIDENT, CYBER9397, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1366 {PCI_VENDOR_ID_TRIDENT, CYBER9397DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1367 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1368 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1369 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm16, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1370 {0,}
1371 };
1372
1373 MODULE_DEVICE_TABLE(pci, trident_devices);
1374
1375 static struct pci_driver tridentfb_pci_driver = {
1376 .name = "tridentfb",
1377 .id_table = trident_devices,
1378 .probe = trident_pci_probe,
1379 .remove = __devexit_p(trident_pci_remove)
1380 };
1381
1382 /*
1383 * Parse user specified options (`video=trident:')
1384 * example:
1385 * video=trident:800x600,bpp=16,noaccel
1386 */
1387 #ifndef MODULE
1388 static int tridentfb_setup(char *options)
1389 {
1390 char *opt;
1391 if (!options || !*options)
1392 return 0;
1393 while ((opt = strsep(&options, ",")) != NULL) {
1394 if (!*opt)
1395 continue;
1396 if (!strncmp(opt, "noaccel", 7))
1397 noaccel = 1;
1398 else if (!strncmp(opt, "fp", 2))
1399 displaytype = DISPLAY_FP;
1400 else if (!strncmp(opt, "crt", 3))
1401 displaytype = DISPLAY_CRT;
1402 else if (!strncmp(opt, "bpp=", 4))
1403 bpp = simple_strtoul(opt + 4, NULL, 0);
1404 else if (!strncmp(opt, "center", 6))
1405 center = 1;
1406 else if (!strncmp(opt, "stretch", 7))
1407 stretch = 1;
1408 else if (!strncmp(opt, "memsize=", 8))
1409 memsize = simple_strtoul(opt + 8, NULL, 0);
1410 else if (!strncmp(opt, "memdiff=", 8))
1411 memdiff = simple_strtoul(opt + 8, NULL, 0);
1412 else if (!strncmp(opt, "nativex=", 8))
1413 nativex = simple_strtoul(opt + 8, NULL, 0);
1414 else
1415 mode = opt;
1416 }
1417 return 0;
1418 }
1419 #endif
1420
1421 static int __init tridentfb_init(void)
1422 {
1423 #ifndef MODULE
1424 char *option = NULL;
1425
1426 if (fb_get_options("tridentfb", &option))
1427 return -ENODEV;
1428 tridentfb_setup(option);
1429 #endif
1430 output("Trident framebuffer %s initializing\n", VERSION);
1431 return pci_register_driver(&tridentfb_pci_driver);
1432 }
1433
1434 static void __exit tridentfb_exit(void)
1435 {
1436 pci_unregister_driver(&tridentfb_pci_driver);
1437 }
1438
1439 module_init(tridentfb_init);
1440 module_exit(tridentfb_exit);
1441
1442 MODULE_AUTHOR("Jani Monoses <jani@iv.ro>");
1443 MODULE_DESCRIPTION("Framebuffer driver for Trident cards");
1444 MODULE_LICENSE("GPL");
1445
WRT350N Kernel Patches