drivers/ide/pci/scc_pata.c

   1 /*
   2  * Support for IDE interfaces on Celleb platform
   3  *
   4  * (C) Copyright 2006 TOSHIBA CORPORATION
   5  *
   6  * This code is based on drivers/ide/pci/siimage.c:
   7  * Copyright (C) 2001-2002      Andre Hedrick <andre@linux-ide.org>
   8  * Copyright (C) 2003           Red Hat <alan@redhat.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License along
  21  * with this program; if not, write to the Free Software Foundation, Inc.,
  22  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  23  */
  24
  25 #include <linux/types.h>
  26 #include <linux/module.h>
  27 #include <linux/pci.h>
  28 #include <linux/delay.h>
  29 #include <linux/hdreg.h>
  30 #include <linux/ide.h>
  31 #include <linux/init.h>
  32
  33 #define PCI_DEVICE_ID_TOSHIBA_SCC_ATA            0x01b4
  34
  35 #define SCC_PATA_NAME           "scc IDE"
  36
  37 #define TDVHSEL_MASTER          0x00000001
  38 #define TDVHSEL_SLAVE           0x00000004
  39
  40 #define MODE_JCUSFEN            0x00000080
  41
  42 #define CCKCTRL_ATARESET        0x00040000
  43 #define CCKCTRL_BUFCNT          0x00020000
  44 #define CCKCTRL_CRST            0x00010000
  45 #define CCKCTRL_OCLKEN          0x00000100
  46 #define CCKCTRL_ATACLKOEN       0x00000002
  47 #define CCKCTRL_LCLKEN          0x00000001
  48
  49 #define QCHCD_IOS_SS            0x00000001
  50
  51 #define QCHSD_STPDIAG           0x00020000
  52
  53 #define INTMASK_MSK             0xD1000012
  54 #define INTSTS_SERROR           0x80000000
  55 #define INTSTS_PRERR            0x40000000
  56 #define INTSTS_RERR             0x10000000
  57 #define INTSTS_ICERR            0x01000000
  58 #define INTSTS_BMSINT           0x00000010
  59 #define INTSTS_BMHE             0x00000008
  60 #define INTSTS_IOIRQS           0x00000004
  61 #define INTSTS_INTRQ            0x00000002
  62 #define INTSTS_ACTEINT          0x00000001
  63
  64 #define ECMODE_VALUE 0x01
  65
  66 static struct scc_ports {
  67         unsigned long ctl, dma;
  68         unsigned char hwif_id;  /* for removing hwif from system */
  69 } scc_ports[MAX_HWIFS];
  70
  71 /* PIO transfer mode  table */
  72 /* JCHST */
  73 static unsigned long JCHSTtbl[2][7] = {
  74         {0x0E, 0x05, 0x02, 0x03, 0x02, 0x00, 0x00},   /* 100MHz */
  75         {0x13, 0x07, 0x04, 0x04, 0x03, 0x00, 0x00}    /* 133MHz */
  76 };
  77
  78 /* JCHHT */
  79 static unsigned long JCHHTtbl[2][7] = {
  80         {0x0E, 0x02, 0x02, 0x02, 0x02, 0x00, 0x00},   /* 100MHz */
  81         {0x13, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00}    /* 133MHz */
  82 };
  83
  84 /* JCHCT */
  85 static unsigned long JCHCTtbl[2][7] = {
  86         {0x1D, 0x1D, 0x1C, 0x0B, 0x06, 0x00, 0x00},   /* 100MHz */
  87         {0x27, 0x26, 0x26, 0x0E, 0x09, 0x00, 0x00}    /* 133MHz */
  88 };
  89
  90
  91 /* DMA transfer mode  table */
  92 /* JCHDCTM/JCHDCTS */
  93 static unsigned long JCHDCTxtbl[2][7] = {
  94         {0x0A, 0x06, 0x04, 0x03, 0x01, 0x00, 0x00},   /* 100MHz */
  95         {0x0E, 0x09, 0x06, 0x04, 0x02, 0x01, 0x00}    /* 133MHz */
  96 };
  97
  98 /* JCSTWTM/JCSTWTS  */
  99 static unsigned long JCSTWTxtbl[2][7] = {
 100         {0x06, 0x04, 0x03, 0x02, 0x02, 0x02, 0x00},   /* 100MHz */
 101         {0x09, 0x06, 0x04, 0x02, 0x02, 0x02, 0x02}    /* 133MHz */
 102 };
 103
 104 /* JCTSS */
 105 static unsigned long JCTSStbl[2][7] = {
 106         {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x00},   /* 100MHz */
 107         {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05}    /* 133MHz */
 108 };
 109
 110 /* JCENVT */
 111 static unsigned long JCENVTtbl[2][7] = {
 112         {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00},   /* 100MHz */
 113         {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02}    /* 133MHz */
 114 };
 115
 116 /* JCACTSELS/JCACTSELM */
 117 static unsigned long JCACTSELtbl[2][7] = {
 118         {0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00},   /* 100MHz */
 119         {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01}    /* 133MHz */
 120 };
 121
 122
 123 static u8 scc_ide_inb(unsigned long port)
 124 {
 125         u32 data = in_be32((void*)port);
 126         return (u8)data;
 127 }
 128
 129 static u16 scc_ide_inw(unsigned long port)
 130 {
 131         u32 data = in_be32((void*)port);
 132         return (u16)data;
 133 }
 134
 135 static void scc_ide_insw(unsigned long port, void *addr, u32 count)
 136 {
 137         u16 *ptr = (u16 *)addr;
 138         while (count--) {
 139                 *ptr++ = le16_to_cpu(in_be32((void*)port));
 140         }
 141 }
 142
 143 static void scc_ide_insl(unsigned long port, void *addr, u32 count)
 144 {
 145         u16 *ptr = (u16 *)addr;
 146         while (count--) {
 147                 *ptr++ = le16_to_cpu(in_be32((void*)port));
 148                 *ptr++ = le16_to_cpu(in_be32((void*)port));
 149         }
 150 }
 151
 152 static void scc_ide_outb(u8 addr, unsigned long port)
 153 {
 154         out_be32((void*)port, addr);
 155 }
 156
 157 static void scc_ide_outw(u16 addr, unsigned long port)
 158 {
 159         out_be32((void*)port, addr);
 160 }
 161
 162 static void
 163 scc_ide_outbsync(ide_drive_t * drive, u8 addr, unsigned long port)
 164 {
 165         ide_hwif_t *hwif = HWIF(drive);
 166
 167         out_be32((void*)port, addr);
 168         eieio();
 169         in_be32((void*)(hwif->dma_base + 0x01c));
 170         eieio();
 171 }
 172
 173 static void
 174 scc_ide_outsw(unsigned long port, void *addr, u32 count)
 175 {
 176         u16 *ptr = (u16 *)addr;
 177         while (count--) {
 178                 out_be32((void*)port, cpu_to_le16(*ptr++));
 179         }
 180 }
 181
 182 static void
 183 scc_ide_outsl(unsigned long port, void *addr, u32 count)
 184 {
 185         u16 *ptr = (u16 *)addr;
 186         while (count--) {
 187                 out_be32((void*)port, cpu_to_le16(*ptr++));
 188                 out_be32((void*)port, cpu_to_le16(*ptr++));
 189         }
 190 }
 191
 192 /**
 193  *      scc_tune_pio    -       tune a drive PIO mode
 194  *      @drive: drive to tune
 195  *      @mode_wanted: the target operating mode
 196  *
 197  *      Load the timing settings for this device mode into the
 198  *      controller.
 199  */
 200
 201 static void scc_tune_pio(ide_drive_t *drive, const u8 pio)
 202 {
 203         ide_hwif_t *hwif = HWIF(drive);
 204         struct scc_ports *ports = ide_get_hwifdata(hwif);
 205         unsigned long ctl_base = ports->ctl;
 206         unsigned long cckctrl_port = ctl_base + 0xff0;
 207         unsigned long piosht_port = ctl_base + 0x000;
 208         unsigned long pioct_port = ctl_base + 0x004;
 209         unsigned long reg;
 210         int offset;
 211
 212         reg = in_be32((void __iomem *)cckctrl_port);
 213         if (reg & CCKCTRL_ATACLKOEN) {
 214                 offset = 1; /* 133MHz */
 215         } else {
 216                 offset = 0; /* 100MHz */
 217         }
 218         reg = JCHSTtbl[offset][pio] << 16 | JCHHTtbl[offset][pio];
 219         out_be32((void __iomem *)piosht_port, reg);
 220         reg = JCHCTtbl[offset][pio];
 221         out_be32((void __iomem *)pioct_port, reg);
 222 }
 223
 224 static void scc_tuneproc(ide_drive_t *drive, u8 pio)
 225 {
 226         pio = ide_get_best_pio_mode(drive, pio, 4);
 227         scc_tune_pio(drive, pio);
 228         ide_config_drive_speed(drive, XFER_PIO_0 + pio);
 229 }
 230
 231 /**
 232  *      scc_tune_chipset        -       tune a drive DMA mode
 233  *      @drive: Drive to set up
 234  *      @xferspeed: speed we want to achieve
 235  *
 236  *      Load the timing settings for this device mode into the
 237  *      controller.
 238  */
 239
 240 static int scc_tune_chipset(ide_drive_t *drive, byte xferspeed)
 241 {
 242         ide_hwif_t *hwif = HWIF(drive);
 243         u8 speed = ide_rate_filter(drive, xferspeed);
 244         struct scc_ports *ports = ide_get_hwifdata(hwif);
 245         unsigned long ctl_base = ports->ctl;
 246         unsigned long cckctrl_port = ctl_base + 0xff0;
 247         unsigned long mdmact_port = ctl_base + 0x008;
 248         unsigned long mcrcst_port = ctl_base + 0x00c;
 249         unsigned long sdmact_port = ctl_base + 0x010;
 250         unsigned long scrcst_port = ctl_base + 0x014;
 251         unsigned long udenvt_port = ctl_base + 0x018;
 252         unsigned long tdvhsel_port   = ctl_base + 0x020;
 253         int is_slave = (&hwif->drives[1] == drive);
 254         int offset, idx;
 255         unsigned long reg;
 256         unsigned long jcactsel;
 257
 258         reg = in_be32((void __iomem *)cckctrl_port);
 259         if (reg & CCKCTRL_ATACLKOEN) {
 260                 offset = 1; /* 133MHz */
 261         } else {
 262                 offset = 0; /* 100MHz */
 263         }
 264
 265         switch (speed) {
 266         case XFER_UDMA_6:
 267         case XFER_UDMA_5:
 268         case XFER_UDMA_4:
 269         case XFER_UDMA_3:
 270         case XFER_UDMA_2:
 271         case XFER_UDMA_1:
 272         case XFER_UDMA_0:
 273                 idx = speed - XFER_UDMA_0;
 274                 break;
 275         case XFER_PIO_4:
 276         case XFER_PIO_3:
 277         case XFER_PIO_2:
 278         case XFER_PIO_1:
 279         case XFER_PIO_0:
 280                 scc_tune_pio(drive, speed - XFER_PIO_0);
 281                 return ide_config_drive_speed(drive, speed);
 282         default:
 283                 return 1;
 284         }
 285
 286         jcactsel = JCACTSELtbl[offset][idx];
 287         if (is_slave) {
 288                 out_be32((void __iomem *)sdmact_port, JCHDCTxtbl[offset][idx]);
 289                 out_be32((void __iomem *)scrcst_port, JCSTWTxtbl[offset][idx]);
 290                 jcactsel = jcactsel << 2;
 291                 out_be32((void __iomem *)tdvhsel_port, (in_be32((void __iomem *)tdvhsel_port) & ~TDVHSEL_SLAVE) | jcactsel);
 292         } else {
 293                 out_be32((void __iomem *)mdmact_port, JCHDCTxtbl[offset][idx]);
 294                 out_be32((void __iomem *)mcrcst_port, JCSTWTxtbl[offset][idx]);
 295                 out_be32((void __iomem *)tdvhsel_port, (in_be32((void __iomem *)tdvhsel_port) & ~TDVHSEL_MASTER) | jcactsel);
 296         }
 297         reg = JCTSStbl[offset][idx] << 16 | JCENVTtbl[offset][idx];
 298         out_be32((void __iomem *)udenvt_port, reg);
 299
 300         return ide_config_drive_speed(drive, speed);
 301 }
 302
 303 /**
 304  *      scc_configure_drive_for_dma     -       set up for DMA transfers
 305  *      @drive: drive we are going to set up
 306  *
 307  *      Set up the drive for DMA, tune the controller and drive as
 308  *      required.
 309  *      If the drive isn't suitable for DMA or we hit other problems
 310  *      then we will drop down to PIO and set up PIO appropriately.
 311  *      (return -1)
 312  */
 313
 314 static int scc_config_drive_for_dma(ide_drive_t *drive)
 315 {
 316         if (ide_tune_dma(drive))
 317                 return 0;
 318
 319         if (ide_use_fast_pio(drive))
 320                 scc_tuneproc(drive, 255);
 321
 322         return -1;
 323 }
 324
 325 /**
 326  *      scc_ide_dma_setup       -       begin a DMA phase
 327  *      @drive: target device
 328  *
 329  *      Build an IDE DMA PRD (IDE speak for scatter gather table)
 330  *      and then set up the DMA transfer registers.
 331  *
 332  *      Returns 0 on success. If a PIO fallback is required then 1
 333  *      is returned.
 334  */
 335
 336 static int scc_dma_setup(ide_drive_t *drive)
 337 {
 338         ide_hwif_t *hwif = drive->hwif;
 339         struct request *rq = HWGROUP(drive)->rq;
 340         unsigned int reading;
 341         u8 dma_stat;
 342
 343         if (rq_data_dir(rq))
 344                 reading = 0;
 345         else
 346                 reading = 1 << 3;
 347
 348         /* fall back to pio! */
 349         if (!ide_build_dmatable(drive, rq)) {
 350                 ide_map_sg(drive, rq);
 351                 return 1;
 352         }
 353
 354         /* PRD table */
 355         out_be32((void __iomem *)hwif->dma_prdtable, hwif->dmatable_dma);
 356
 357         /* specify r/w */
 358         out_be32((void __iomem *)hwif->dma_command, reading);
 359
 360         /* read dma_status for INTR & ERROR flags */
 361         dma_stat = in_be32((void __iomem *)hwif->dma_status);
 362
 363         /* clear INTR & ERROR flags */
 364         out_be32((void __iomem *)hwif->dma_status, dma_stat|6);
 365         drive->waiting_for_dma = 1;
 366         return 0;
 367 }
 368
 369
 370 /**
 371  *      scc_ide_dma_end -       Stop DMA
 372  *      @drive: IDE drive
 373  *
 374  *      Check and clear INT Status register.
 375  *      Then call __ide_dma_end().
 376  */
 377
 378 static int scc_ide_dma_end(ide_drive_t * drive)
 379 {
 380         ide_hwif_t *hwif = HWIF(drive);
 381         unsigned long intsts_port = hwif->dma_base + 0x014;
 382         u32 reg;
 383         int dma_stat, data_loss = 0;
 384         static int retry = 0;
 385
 386         /* errata A308 workaround: Step5 (check data loss) */
 387         /* We don't check non ide_disk because it is limited to UDMA4 */
 388         if (!(in_be32((void __iomem *)IDE_ALTSTATUS_REG) & ERR_STAT) &&
 389             drive->media == ide_disk && drive->current_speed > XFER_UDMA_4) {
 390                 reg = in_be32((void __iomem *)intsts_port);
 391                 if (!(reg & INTSTS_ACTEINT)) {
 392                         printk(KERN_WARNING "%s: operation failed (transfer data loss)\n",
 393                                drive->name);
 394                         data_loss = 1;
 395                         if (retry++) {
 396                                 struct request *rq = HWGROUP(drive)->rq;
 397                                 int unit;
 398                                 /* ERROR_RESET and drive->crc_count are needed
 399                                  * to reduce DMA transfer mode in retry process.
 400                                  */
 401                                 if (rq)
 402                                         rq->errors |= ERROR_RESET;
 403                                 for (unit = 0; unit < MAX_DRIVES; unit++) {
 404                                         ide_drive_t *drive = &hwif->drives[unit];
 405                                         drive->crc_count++;
 406                                 }
 407                         }
 408                 }
 409         }
 410
 411         while (1) {
 412                 reg = in_be32((void __iomem *)intsts_port);
 413
 414                 if (reg & INTSTS_SERROR) {
 415                         printk(KERN_WARNING "%s: SERROR\n", SCC_PATA_NAME);
 416                         out_be32((void __iomem *)intsts_port, INTSTS_SERROR|INTSTS_BMSINT);
 417
 418                         out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS);
 419                         continue;
 420                 }
 421
 422                 if (reg & INTSTS_PRERR) {
 423                         u32 maea0, maec0;
 424                         unsigned long ctl_base = hwif->config_data;
 425
 426                         maea0 = in_be32((void __iomem *)(ctl_base + 0xF50));
 427                         maec0 = in_be32((void __iomem *)(ctl_base + 0xF54));
 428
 429                         printk(KERN_WARNING "%s: PRERR [addr:%x cmd:%x]\n", SCC_PATA_NAME, maea0, maec0);
 430
 431                         out_be32((void __iomem *)intsts_port, INTSTS_PRERR|INTSTS_BMSINT);
 432
 433                         out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS);
 434                         continue;
 435                 }
 436
 437                 if (reg & INTSTS_RERR) {
 438                         printk(KERN_WARNING "%s: Response Error\n", SCC_PATA_NAME);
 439                         out_be32((void __iomem *)intsts_port, INTSTS_RERR|INTSTS_BMSINT);
 440
 441                         out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS);
 442                         continue;
 443                 }
 444
 445                 if (reg & INTSTS_ICERR) {
 446                         out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS);
 447
 448                         printk(KERN_WARNING "%s: Illegal Configuration\n", SCC_PATA_NAME);
 449                         out_be32((void __iomem *)intsts_port, INTSTS_ICERR|INTSTS_BMSINT);
 450                         continue;
 451                 }
 452
 453                 if (reg & INTSTS_BMSINT) {
 454                         printk(KERN_WARNING "%s: Internal Bus Error\n", SCC_PATA_NAME);
 455                         out_be32((void __iomem *)intsts_port, INTSTS_BMSINT);
 456
 457                         ide_do_reset(drive);
 458                         continue;
 459                 }
 460
 461                 if (reg & INTSTS_BMHE) {
 462                         out_be32((void __iomem *)intsts_port, INTSTS_BMHE);
 463                         continue;
 464                 }
 465
 466                 if (reg & INTSTS_ACTEINT) {
 467                         out_be32((void __iomem *)intsts_port, INTSTS_ACTEINT);
 468                         continue;
 469                 }
 470
 471                 if (reg & INTSTS_IOIRQS) {
 472                         out_be32((void __iomem *)intsts_port, INTSTS_IOIRQS);
 473                         continue;
 474                 }
 475                 break;
 476         }
 477
 478         dma_stat = __ide_dma_end(drive);
 479         if (data_loss)
 480                 dma_stat |= 2; /* emulate DMA error (to retry command) */
 481         return dma_stat;
 482 }
 483
 484 /* returns 1 if dma irq issued, 0 otherwise */
 485 static int scc_dma_test_irq(ide_drive_t *drive)
 486 {
 487         ide_hwif_t *hwif = HWIF(drive);
 488         u32 int_stat = in_be32((void __iomem *)hwif->dma_base + 0x014);
 489
 490         /* SCC errata A252,A308 workaround: Step4 */
 491         if ((in_be32((void __iomem *)IDE_ALTSTATUS_REG) & ERR_STAT) &&
 492             (int_stat & INTSTS_INTRQ))
 493                 return 1;
 494
 495         /* SCC errata A308 workaround: Step5 (polling IOIRQS) */
 496         if (int_stat & INTSTS_IOIRQS)
 497                 return 1;
 498
 499         if (!drive->waiting_for_dma)
 500                 printk(KERN_WARNING "%s: (%s) called while not waiting\n",
 501                         drive->name, __FUNCTION__);
 502         return 0;
 503 }
 504
 505 static u8 scc_udma_filter(ide_drive_t *drive)
 506 {
 507         ide_hwif_t *hwif = drive->hwif;
 508         u8 mask = hwif->ultra_mask;
 509
 510         /* errata A308 workaround: limit non ide_disk drive to UDMA4 */
 511         if ((drive->media != ide_disk) && (mask & 0xE0)) {
 512                 printk(KERN_INFO "%s: limit %s to UDMA4\n",
 513                        SCC_PATA_NAME, drive->name);
 514                 mask = 0x1F;
 515         }
 516
 517         return mask;
 518 }
 519
 520 /**
 521  *      setup_mmio_scc  -       map CTRL/BMID region
 522  *      @dev: PCI device we are configuring
 523  *      @name: device name
 524  *
 525  */
 526
 527 static int setup_mmio_scc (struct pci_dev *dev, const char *name)
 528 {
 529         unsigned long ctl_base = pci_resource_start(dev, 0);
 530         unsigned long dma_base = pci_resource_start(dev, 1);
 531         unsigned long ctl_size = pci_resource_len(dev, 0);
 532         unsigned long dma_size = pci_resource_len(dev, 1);
 533         void __iomem *ctl_addr;
 534         void __iomem *dma_addr;
 535         int i;
 536
 537         for (i = 0; i < MAX_HWIFS; i++) {
 538                 if (scc_ports[i].ctl == 0)
 539                         break;
 540         }
 541         if (i >= MAX_HWIFS)
 542                 return -ENOMEM;
 543
 544         if (!request_mem_region(ctl_base, ctl_size, name)) {
 545                 printk(KERN_WARNING "%s: IDE controller MMIO ports not available.\n", SCC_PATA_NAME);
 546                 goto fail_0;
 547         }
 548
 549         if (!request_mem_region(dma_base, dma_size, name)) {
 550                 printk(KERN_WARNING "%s: IDE controller MMIO ports not available.\n", SCC_PATA_NAME);
 551                 goto fail_1;
 552         }
 553
 554         if ((ctl_addr = ioremap(ctl_base, ctl_size)) == NULL)
 555                 goto fail_2;
 556
 557         if ((dma_addr = ioremap(dma_base, dma_size)) == NULL)
 558                 goto fail_3;
 559
 560         pci_set_master(dev);
 561         scc_ports[i].ctl = (unsigned long)ctl_addr;
 562         scc_ports[i].dma = (unsigned long)dma_addr;
 563         pci_set_drvdata(dev, (void *) &scc_ports[i]);
 564
 565         return 1;
 566
 567  fail_3:
 568         iounmap(ctl_addr);
 569  fail_2:
 570         release_mem_region(dma_base, dma_size);
 571  fail_1:
 572         release_mem_region(ctl_base, ctl_size);
 573  fail_0:
 574         return -ENOMEM;
 575 }
 576
 577 /**
 578  *      init_setup_scc  -       set up an SCC PATA Controller
 579  *      @dev: PCI device
 580  *      @d: IDE PCI device
 581  *
 582  *      Perform the initial set up for this device.
 583  */
 584
 585 static int __devinit init_setup_scc(struct pci_dev *dev, ide_pci_device_t *d)
 586 {
 587         unsigned long ctl_base;
 588         unsigned long dma_base;
 589         unsigned long cckctrl_port;
 590         unsigned long intmask_port;
 591         unsigned long mode_port;
 592         unsigned long ecmode_port;
 593         unsigned long dma_status_port;
 594         u32 reg = 0;
 595         struct scc_ports *ports;
 596         int rc;
 597
 598         rc = setup_mmio_scc(dev, d->name);
 599         if (rc < 0) {
 600                 return rc;
 601         }
 602
 603         ports = pci_get_drvdata(dev);
 604         ctl_base = ports->ctl;
 605         dma_base = ports->dma;
 606         cckctrl_port = ctl_base + 0xff0;
 607         intmask_port = dma_base + 0x010;
 608         mode_port = ctl_base + 0x024;
 609         ecmode_port = ctl_base + 0xf00;
 610         dma_status_port = dma_base + 0x004;
 611
 612         /* controller initialization */
 613         reg = 0;
 614         out_be32((void*)cckctrl_port, reg);
 615         reg |= CCKCTRL_ATACLKOEN;
 616         out_be32((void*)cckctrl_port, reg);
 617         reg |= CCKCTRL_LCLKEN | CCKCTRL_OCLKEN;
 618         out_be32((void*)cckctrl_port, reg);
 619         reg |= CCKCTRL_CRST;
 620         out_be32((void*)cckctrl_port, reg);
 621
 622         for (;;) {
 623                 reg = in_be32((void*)cckctrl_port);
 624                 if (reg & CCKCTRL_CRST)
 625                         break;
 626                 udelay(5000);
 627         }
 628
 629         reg |= CCKCTRL_ATARESET;
 630         out_be32((void*)cckctrl_port, reg);
 631
 632         out_be32((void*)ecmode_port, ECMODE_VALUE);
 633         out_be32((void*)mode_port, MODE_JCUSFEN);
 634         out_be32((void*)intmask_port, INTMASK_MSK);
 635
 636         return ide_setup_pci_device(dev, d);
 637 }
 638
 639 /**
 640  *      init_mmio_iops_scc      -       set up the iops for MMIO
 641  *      @hwif: interface to set up
 642  *
 643  */
 644
 645 static void __devinit init_mmio_iops_scc(ide_hwif_t *hwif)
 646 {
 647         struct pci_dev *dev = hwif->pci_dev;
 648         struct scc_ports *ports = pci_get_drvdata(dev);
 649         unsigned long dma_base = ports->dma;
 650
 651         ide_set_hwifdata(hwif, ports);
 652
 653         hwif->INB = scc_ide_inb;
 654         hwif->INW = scc_ide_inw;
 655         hwif->INSW = scc_ide_insw;
 656         hwif->INSL = scc_ide_insl;
 657         hwif->OUTB = scc_ide_outb;
 658         hwif->OUTBSYNC = scc_ide_outbsync;
 659         hwif->OUTW = scc_ide_outw;
 660         hwif->OUTSW = scc_ide_outsw;
 661         hwif->OUTSL = scc_ide_outsl;
 662
 663         hwif->io_ports[IDE_DATA_OFFSET] = dma_base + 0x20;
 664         hwif->io_ports[IDE_ERROR_OFFSET] = dma_base + 0x24;
 665         hwif->io_ports[IDE_NSECTOR_OFFSET] = dma_base + 0x28;
 666         hwif->io_ports[IDE_SECTOR_OFFSET] = dma_base + 0x2c;
 667         hwif->io_ports[IDE_LCYL_OFFSET] = dma_base + 0x30;
 668         hwif->io_ports[IDE_HCYL_OFFSET] = dma_base + 0x34;
 669         hwif->io_ports[IDE_SELECT_OFFSET] = dma_base + 0x38;
 670         hwif->io_ports[IDE_STATUS_OFFSET] = dma_base + 0x3c;
 671         hwif->io_ports[IDE_CONTROL_OFFSET] = dma_base + 0x40;
 672
 673         hwif->irq = hwif->pci_dev->irq;
 674         hwif->dma_base = dma_base;
 675         hwif->config_data = ports->ctl;
 676         hwif->mmio = 1;
 677 }
 678
 679 /**
 680  *      init_iops_scc   -       set up iops
 681  *      @hwif: interface to set up
 682  *
 683  *      Do the basic setup for the SCC hardware interface
 684  *      and then do the MMIO setup.
 685  */
 686
 687 static void __devinit init_iops_scc(ide_hwif_t *hwif)
 688 {
 689         struct pci_dev *dev =  hwif->pci_dev;
 690         hwif->hwif_data = NULL;
 691         if (pci_get_drvdata(dev) == NULL)
 692                 return;
 693         init_mmio_iops_scc(hwif);
 694 }
 695
 696 /**
 697  *      init_hwif_scc   -       set up hwif
 698  *      @hwif: interface to set up
 699  *
 700  *      We do the basic set up of the interface structure. The SCC
 701  *      requires several custom handlers so we override the default
 702  *      ide DMA handlers appropriately.
 703  */
 704
 705 static void __devinit init_hwif_scc(ide_hwif_t *hwif)
 706 {
 707         struct scc_ports *ports = ide_get_hwifdata(hwif);
 708
 709         ports->hwif_id = hwif->index;
 710
 711         hwif->dma_command = hwif->dma_base;
 712         hwif->dma_status = hwif->dma_base + 0x04;
 713         hwif->dma_prdtable = hwif->dma_base + 0x08;
 714
 715         /* PTERADD */
 716         out_be32((void __iomem *)(hwif->dma_base + 0x018), hwif->dmatable_dma);
 717
 718         hwif->dma_setup = scc_dma_setup;
 719         hwif->ide_dma_end = scc_ide_dma_end;
 720         hwif->speedproc = scc_tune_chipset;
 721         hwif->tuneproc = scc_tuneproc;
 722         hwif->ide_dma_check = scc_config_drive_for_dma;
 723         hwif->ide_dma_test_irq = scc_dma_test_irq;
 724         hwif->udma_filter = scc_udma_filter;
 725
 726         hwif->drives[0].autotune = IDE_TUNE_AUTO;
 727         hwif->drives[1].autotune = IDE_TUNE_AUTO;
 728
 729         if (in_be32((void __iomem *)(hwif->config_data + 0xff0)) & CCKCTRL_ATACLKOEN) {
 730                 hwif->ultra_mask = 0x7f; /* 133MHz */
 731         } else {
 732                 hwif->ultra_mask = 0x3f; /* 100MHz */
 733         }
 734         hwif->mwdma_mask = 0x00;
 735         hwif->swdma_mask = 0x00;
 736         hwif->atapi_dma = 1;
 737
 738         /* we support 80c cable only. */
 739         hwif->cbl = ATA_CBL_PATA80;
 740
 741         hwif->autodma = 0;
 742         if (!noautodma)
 743                 hwif->autodma = 1;
 744         hwif->drives[0].autodma = hwif->autodma;
 745         hwif->drives[1].autodma = hwif->autodma;
 746 }
 747
 748 #define DECLARE_SCC_DEV(name_str)                       \
 749   {                                                     \
 750       .name             = name_str,                     \
 751       .init_setup       = init_setup_scc,               \
 752       .init_iops        = init_iops_scc,                \
 753       .init_hwif        = init_hwif_scc,                \
 754       .autodma  = AUTODMA,                              \
 755       .bootable = ON_BOARD,                             \
 756       .host_flags       = IDE_HFLAG_SINGLE,             \
 757       .pio_mask         = ATA_PIO4,                     \
 758   }
 759
 760 static ide_pci_device_t scc_chipsets[] __devinitdata = {
 761         /* 0 */ DECLARE_SCC_DEV("sccIDE"),
 762 };
 763
 764 /**
 765  *      scc_init_one    -       pci layer discovery entry
 766  *      @dev: PCI device
 767  *      @id: ident table entry
 768  *
 769  *      Called by the PCI code when it finds an SCC PATA controller.
 770  *      We then use the IDE PCI generic helper to do most of the work.
 771  */
 772
 773 static int __devinit scc_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 774 {
 775         ide_pci_device_t *d = &scc_chipsets[id->driver_data];
 776         return d->init_setup(dev, d);
 777 }
 778
 779 /**
 780  *      scc_remove      -       pci layer remove entry
 781  *      @dev: PCI device
 782  *
 783  *      Called by the PCI code when it removes an SCC PATA controller.
 784  */
 785
 786 static void __devexit scc_remove(struct pci_dev *dev)
 787 {
 788         struct scc_ports *ports = pci_get_drvdata(dev);
 789         ide_hwif_t *hwif = &ide_hwifs[ports->hwif_id];
 790         unsigned long ctl_base = pci_resource_start(dev, 0);
 791         unsigned long dma_base = pci_resource_start(dev, 1);
 792         unsigned long ctl_size = pci_resource_len(dev, 0);
 793         unsigned long dma_size = pci_resource_len(dev, 1);
 794
 795         if (hwif->dmatable_cpu) {
 796                 pci_free_consistent(hwif->pci_dev,
 797                                     PRD_ENTRIES * PRD_BYTES,
 798                                     hwif->dmatable_cpu,
 799                                     hwif->dmatable_dma);
 800                 hwif->dmatable_cpu = NULL;
 801         }
 802
 803         ide_unregister(hwif->index);
 804
 805         hwif->chipset = ide_unknown;
 806         iounmap((void*)ports->dma);
 807         iounmap((void*)ports->ctl);
 808         release_mem_region(dma_base, dma_size);
 809         release_mem_region(ctl_base, ctl_size);
 810         memset(ports, 0, sizeof(*ports));
 811 }
 812
 813 static struct pci_device_id scc_pci_tbl[] = {
 814         { PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_SCC_ATA,  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 815         { 0, },
 816 };
 817 MODULE_DEVICE_TABLE(pci, scc_pci_tbl);
 818
 819 static struct pci_driver driver = {
 820         .name = "SCC IDE",
 821         .id_table = scc_pci_tbl,
 822         .probe = scc_init_one,
 823         .remove = scc_remove,
 824 };
 825
 826 static int scc_ide_init(void)
 827 {
 828         return ide_pci_register_driver(&driver);
 829 }
 830
 831 module_init(scc_ide_init);
 832 /* -- No exit code?
 833 static void scc_ide_exit(void)
 834 {
 835         ide_pci_unregister_driver(&driver);
 836 }
 837 module_exit(scc_ide_exit);
 838  */
 839
 840
 841 MODULE_DESCRIPTION("PCI driver module for Toshiba SCC IDE");
 842 MODULE_LICENSE("GPL");