arch/alpha/kernel/core_tsunami.c

   1 /*
   2  *      linux/arch/alpha/kernel/core_tsunami.c
   3  *
   4  * Based on code written by David A. Rusling (david.rusling@reo.mts.dec.com).
   5  *
   6  * Code common to all TSUNAMI core logic chips.
   7  */
   8
   9 #define __EXTERN_INLINE inline
  10 #include <asm/io.h>
  11 #include <asm/core_tsunami.h>
  12 #undef __EXTERN_INLINE
  13
  14 #include <linux/types.h>
  15 #include <linux/pci.h>
  16 #include <linux/sched.h>
  17 #include <linux/init.h>
  18 #include <linux/bootmem.h>
  19
  20 #include <asm/ptrace.h>
  21 #include <asm/smp.h>
  22 #include <asm/vga.h>
  23
  24 #include "proto.h"
  25 #include "pci_impl.h"
  26
  27 /* Save Tsunami configuration data as the console had it set up.  */
  28
  29 struct
  30 {
  31         unsigned long wsba[4];
  32         unsigned long wsm[4];
  33         unsigned long tba[4];
  34 } saved_config[2] __attribute__((common));
  35
  36 /*
  37  * NOTE: Herein lie back-to-back mb instructions.  They are magic.
  38  * One plausible explanation is that the I/O controller does not properly
  39  * handle the system transaction.  Another involves timing.  Ho hum.
  40  */
  41
  42 /*
  43  * BIOS32-style PCI interface:
  44  */
  45
  46 #define DEBUG_CONFIG 0
  47
  48 #if DEBUG_CONFIG
  49 # define DBG_CFG(args)  printk args
  50 #else
  51 # define DBG_CFG(args)
  52 #endif
  53
  54
  55 /*
  56  * Given a bus, device, and function number, compute resulting
  57  * configuration space address
  58  * accordingly.  It is therefore not safe to have concurrent
  59  * invocations to configuration space access routines, but there
  60  * really shouldn't be any need for this.
  61  *
  62  * Note that all config space accesses use Type 1 address format.
  63  *
  64  * Note also that type 1 is determined by non-zero bus number.
  65  *
  66  * Type 1:
  67  *
  68  *  3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
  69  *  3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
  70  * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
  71  * | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1|
  72  * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
  73  *
  74  *      31:24   reserved
  75  *      23:16   bus number (8 bits = 128 possible buses)
  76  *      15:11   Device number (5 bits)
  77  *      10:8    function number
  78  *       7:2    register number
  79  *
  80  * Notes:
  81  *      The function number selects which function of a multi-function device
  82  *      (e.g., SCSI and Ethernet).
  83  *
  84  *      The register selects a DWORD (32 bit) register offset.  Hence it
  85  *      doesn't get shifted by 2 bits as we want to "drop" the bottom two
  86  *      bits.
  87  */
  88
  89 static int
  90 mk_conf_addr(struct pci_bus *pbus, unsigned int device_fn, int where,
  91              unsigned long *pci_addr, unsigned char *type1)
  92 {
  93         struct pci_controller *hose = pbus->sysdata;
  94         unsigned long addr;
  95         u8 bus = pbus->number;
  96
  97         DBG_CFG(("mk_conf_addr(bus=%d ,device_fn=0x%x, where=0x%x, "
  98                  "pci_addr=0x%p, type1=0x%p)\n",
  99                  bus, device_fn, where, pci_addr, type1));
 100
 101         if (!pbus->parent) /* No parent means peer PCI bus. */
 102                 bus = 0;
 103         *type1 = (bus != 0);
 104
 105         addr = (bus << 16) | (device_fn << 8) | where;
 106         addr |= hose->config_space_base;
 107
 108         *pci_addr = addr;
 109         DBG_CFG(("mk_conf_addr: returning pci_addr 0x%lx\n", addr));
 110         return 0;
 111 }
 112
 113 static int
 114 tsunami_read_config(struct pci_bus *bus, unsigned int devfn, int where,
 115                     int size, u32 *value)
 116 {
 117         unsigned long addr;
 118         unsigned char type1;
 119
 120         if (mk_conf_addr(bus, devfn, where, &addr, &type1))
 121                 return PCIBIOS_DEVICE_NOT_FOUND;
 122
 123         switch (size) {
 124         case 1:
 125                 *value = __kernel_ldbu(*(vucp)addr);
 126                 break;
 127         case 2:
 128                 *value = __kernel_ldwu(*(vusp)addr);
 129                 break;
 130         case 4:
 131                 *value = *(vuip)addr;
 132                 break;
 133         }
 134
 135         return PCIBIOS_SUCCESSFUL;
 136 }
 137
 138 static int
 139 tsunami_write_config(struct pci_bus *bus, unsigned int devfn, int where,
 140                      int size, u32 value)
 141 {
 142         unsigned long addr;
 143         unsigned char type1;
 144
 145         if (mk_conf_addr(bus, devfn, where, &addr, &type1))
 146                 return PCIBIOS_DEVICE_NOT_FOUND;
 147
 148         switch (size) {
 149         case 1:
 150                 __kernel_stb(value, *(vucp)addr);
 151                 mb();
 152                 __kernel_ldbu(*(vucp)addr);
 153                 break;
 154         case 2:
 155                 __kernel_stw(value, *(vusp)addr);
 156                 mb();
 157                 __kernel_ldwu(*(vusp)addr);
 158                 break;
 159         case 4:
 160                 *(vuip)addr = value;
 161                 mb();
 162                 *(vuip)addr;
 163                 break;
 164         }
 165
 166         return PCIBIOS_SUCCESSFUL;
 167 }
 168
 169 struct pci_ops tsunami_pci_ops =
 170 {
 171         .read =         tsunami_read_config,
 172         .write =        tsunami_write_config,
 173 };
 174 \f
 175 void
 176 tsunami_pci_tbi(struct pci_controller *hose, dma_addr_t start, dma_addr_t end)
 177 {
 178         tsunami_pchip *pchip = hose->index ? TSUNAMI_pchip1 : TSUNAMI_pchip0;
 179         volatile unsigned long *csr;
 180         unsigned long value;
 181
 182         /* We can invalidate up to 8 tlb entries in a go.  The flush
 183            matches against <31:16> in the pci address.  */
 184         csr = &pchip->tlbia.csr;
 185         if (((start ^ end) & 0xffff0000) == 0)
 186                 csr = &pchip->tlbiv.csr;
 187
 188         /* For TBIA, it doesn't matter what value we write.  For TBI,
 189            it's the shifted tag bits.  */
 190         value = (start & 0xffff0000) >> 12;
 191
 192         *csr = value;
 193         mb();
 194         *csr;
 195 }
 196 \f
 197 #ifdef NXM_MACHINE_CHECKS_ON_TSUNAMI
 198 static long __init
 199 tsunami_probe_read(volatile unsigned long *vaddr)
 200 {
 201         long dont_care, probe_result;
 202         int cpu = smp_processor_id();
 203         int s = swpipl(IPL_MCHECK - 1);
 204
 205         mcheck_taken(cpu) = 0;
 206         mcheck_expected(cpu) = 1;
 207         mb();
 208         dont_care = *vaddr;
 209         draina();
 210         mcheck_expected(cpu) = 0;
 211         probe_result = !mcheck_taken(cpu);
 212         mcheck_taken(cpu) = 0;
 213         setipl(s);
 214
 215         printk("dont_care == 0x%lx\n", dont_care);
 216
 217         return probe_result;
 218 }
 219
 220 static long __init
 221 tsunami_probe_write(volatile unsigned long *vaddr)
 222 {
 223         long true_contents, probe_result = 1;
 224
 225         TSUNAMI_cchip->misc.csr |= (1L << 28); /* clear NXM... */
 226         true_contents = *vaddr;
 227         *vaddr = 0;
 228         draina();
 229         if (TSUNAMI_cchip->misc.csr & (1L << 28)) {
 230                 int source = (TSUNAMI_cchip->misc.csr >> 29) & 7;
 231                 TSUNAMI_cchip->misc.csr |= (1L << 28); /* ...and unlock NXS. */
 232                 probe_result = 0;
 233                 printk("tsunami_probe_write: unit %d at 0x%016lx\n", source,
 234                        (unsigned long)vaddr);
 235         }
 236         if (probe_result)
 237                 *vaddr = true_contents;
 238         return probe_result;
 239 }
 240 #else
 241 #define tsunami_probe_read(ADDR) 1
 242 #endif /* NXM_MACHINE_CHECKS_ON_TSUNAMI */
 243
 244 #define FN __FUNCTION__
 245
 246 static void __init
 247 tsunami_init_one_pchip(tsunami_pchip *pchip, int index)
 248 {
 249         struct pci_controller *hose;
 250
 251         if (tsunami_probe_read(&pchip->pctl.csr) == 0)
 252                 return;
 253
 254         hose = alloc_pci_controller();
 255         if (index == 0)
 256                 pci_isa_hose = hose;
 257         hose->io_space = alloc_resource();
 258         hose->mem_space = alloc_resource();
 259
 260         /* This is for userland consumption.  For some reason, the 40-bit
 261            PIO bias that we use in the kernel through KSEG didn't work for
 262            the page table based user mappings.  So make sure we get the
 263            43-bit PIO bias.  */
 264         hose->sparse_mem_base = 0;
 265         hose->sparse_io_base = 0;
 266         hose->dense_mem_base
 267           = (TSUNAMI_MEM(index) & 0xffffffffffL) | 0x80000000000L;
 268         hose->dense_io_base
 269           = (TSUNAMI_IO(index) & 0xffffffffffL) | 0x80000000000L;
 270
 271         hose->config_space_base = TSUNAMI_CONF(index);
 272         hose->index = index;
 273
 274         hose->io_space->start = TSUNAMI_IO(index) - TSUNAMI_IO_BIAS;
 275         hose->io_space->end = hose->io_space->start + TSUNAMI_IO_SPACE - 1;
 276         hose->io_space->name = pci_io_names[index];
 277         hose->io_space->flags = IORESOURCE_IO;
 278
 279         hose->mem_space->start = TSUNAMI_MEM(index) - TSUNAMI_MEM_BIAS;
 280         hose->mem_space->end = hose->mem_space->start + 0xffffffff;
 281         hose->mem_space->name = pci_mem_names[index];
 282         hose->mem_space->flags = IORESOURCE_MEM;
 283
 284         if (request_resource(&ioport_resource, hose->io_space) < 0)
 285                 printk(KERN_ERR "Failed to request IO on hose %d\n", index);
 286         if (request_resource(&iomem_resource, hose->mem_space) < 0)
 287                 printk(KERN_ERR "Failed to request MEM on hose %d\n", index);
 288
 289         /*
 290          * Save the existing PCI window translations.  SRM will
 291          * need them when we go to reboot.
 292          */
 293
 294         saved_config[index].wsba[0] = pchip->wsba[0].csr;
 295         saved_config[index].wsm[0] = pchip->wsm[0].csr;
 296         saved_config[index].tba[0] = pchip->tba[0].csr;
 297
 298         saved_config[index].wsba[1] = pchip->wsba[1].csr;
 299         saved_config[index].wsm[1] = pchip->wsm[1].csr;
 300         saved_config[index].tba[1] = pchip->tba[1].csr;
 301
 302         saved_config[index].wsba[2] = pchip->wsba[2].csr;
 303         saved_config[index].wsm[2] = pchip->wsm[2].csr;
 304         saved_config[index].tba[2] = pchip->tba[2].csr;
 305
 306         saved_config[index].wsba[3] = pchip->wsba[3].csr;
 307         saved_config[index].wsm[3] = pchip->wsm[3].csr;
 308         saved_config[index].tba[3] = pchip->tba[3].csr;
 309
 310         /*
 311          * Set up the PCI to main memory translation windows.
 312          *
 313          * Note: Window 3 is scatter-gather only
 314          *
 315          * Window 0 is scatter-gather 8MB at 8MB (for isa)
 316          * Window 1 is scatter-gather (up to) 1GB at 1GB
 317          * Window 2 is direct access 2GB at 2GB
 318          *
 319          * NOTE: we need the align_entry settings for Acer devices on ES40,
 320          * specifically floppy and IDE when memory is larger than 2GB.
 321          */
 322         hose->sg_isa = iommu_arena_new(hose, 0x00800000, 0x00800000, 0);
 323         /* Initially set for 4 PTEs, but will be overridden to 64K for ISA. */
 324         hose->sg_isa->align_entry = 4;
 325
 326         hose->sg_pci = iommu_arena_new(hose, 0x40000000,
 327                                        size_for_memory(0x40000000), 0);
 328         hose->sg_pci->align_entry = 4; /* Tsunami caches 4 PTEs at a time */
 329
 330         __direct_map_base = 0x80000000;
 331         __direct_map_size = 0x80000000;
 332
 333         pchip->wsba[0].csr = hose->sg_isa->dma_base | 3;
 334         pchip->wsm[0].csr  = (hose->sg_isa->size - 1) & 0xfff00000;
 335         pchip->tba[0].csr  = virt_to_phys(hose->sg_isa->ptes);
 336
 337         pchip->wsba[1].csr = hose->sg_pci->dma_base | 3;
 338         pchip->wsm[1].csr  = (hose->sg_pci->size - 1) & 0xfff00000;
 339         pchip->tba[1].csr  = virt_to_phys(hose->sg_pci->ptes);
 340
 341         pchip->wsba[2].csr = 0x80000000 | 1;
 342         pchip->wsm[2].csr  = (0x80000000 - 1) & 0xfff00000;
 343         pchip->tba[2].csr  = 0;
 344
 345         pchip->wsba[3].csr = 0;
 346
 347         /* Enable the Monster Window to make DAC pci64 possible. */
 348         pchip->pctl.csr |= pctl_m_mwin;
 349
 350         tsunami_pci_tbi(hose, 0, -1);
 351 }
 352
 353
 354 void __iomem *
 355 tsunami_ioportmap(unsigned long addr)
 356 {
 357         FIXUP_IOADDR_VGA(addr);
 358         return (void __iomem *)(addr + TSUNAMI_IO_BIAS);
 359 }
 360
 361 void __iomem *
 362 tsunami_ioremap(unsigned long addr, unsigned long size)
 363 {
 364         FIXUP_MEMADDR_VGA(addr);
 365         return (void __iomem *)(addr + TSUNAMI_MEM_BIAS);
 366 }
 367
 368 #ifndef CONFIG_ALPHA_GENERIC
 369 EXPORT_SYMBOL(tsunami_ioportmap);
 370 EXPORT_SYMBOL(tsunami_ioremap);
 371 #endif
 372
 373 void __init
 374 tsunami_init_arch(void)
 375 {
 376 #ifdef NXM_MACHINE_CHECKS_ON_TSUNAMI
 377         unsigned long tmp;
 378
 379         /* Ho hum.. init_arch is called before init_IRQ, but we need to be
 380            able to handle machine checks.  So install the handler now.  */
 381         wrent(entInt, 0);
 382
 383         /* NXMs just don't matter to Tsunami--unless they make it
 384            choke completely. */
 385         tmp = (unsigned long)(TSUNAMI_cchip - 1);
 386         printk("%s: probing bogus address:  0x%016lx\n", FN, bogus_addr);
 387         printk("\tprobe %s\n",
 388                tsunami_probe_write((unsigned long *)bogus_addr)
 389                ? "succeeded" : "failed");
 390 #endif /* NXM_MACHINE_CHECKS_ON_TSUNAMI */
 391
 392 #if 0
 393         printk("%s: CChip registers:\n", FN);
 394         printk("%s: CSR_CSC 0x%lx\n", FN, TSUNAMI_cchip->csc.csr);
 395         printk("%s: CSR_MTR 0x%lx\n", FN, TSUNAMI_cchip.mtr.csr);
 396         printk("%s: CSR_MISC 0x%lx\n", FN, TSUNAMI_cchip->misc.csr);
 397         printk("%s: CSR_DIM0 0x%lx\n", FN, TSUNAMI_cchip->dim0.csr);
 398         printk("%s: CSR_DIM1 0x%lx\n", FN, TSUNAMI_cchip->dim1.csr);
 399         printk("%s: CSR_DIR0 0x%lx\n", FN, TSUNAMI_cchip->dir0.csr);
 400         printk("%s: CSR_DIR1 0x%lx\n", FN, TSUNAMI_cchip->dir1.csr);
 401         printk("%s: CSR_DRIR 0x%lx\n", FN, TSUNAMI_cchip->drir.csr);
 402
 403         printk("%s: DChip registers:\n");
 404         printk("%s: CSR_DSC 0x%lx\n", FN, TSUNAMI_dchip->dsc.csr);
 405         printk("%s: CSR_STR 0x%lx\n", FN, TSUNAMI_dchip->str.csr);
 406         printk("%s: CSR_DREV 0x%lx\n", FN, TSUNAMI_dchip->drev.csr);
 407 #endif
 408         /* With multiple PCI busses, we play with I/O as physical addrs.  */
 409         ioport_resource.end = ~0UL;
 410
 411         /* Find how many hoses we have, and initialize them.  TSUNAMI
 412            and TYPHOON can have 2, but might only have 1 (DS10).  */
 413
 414         tsunami_init_one_pchip(TSUNAMI_pchip0, 0);
 415         if (TSUNAMI_cchip->csc.csr & 1L<<14)
 416                 tsunami_init_one_pchip(TSUNAMI_pchip1, 1);
 417
 418         /* Check for graphic console location (if any).  */
 419         find_console_vga_hose();
 420 }
 421
 422 static void
 423 tsunami_kill_one_pchip(tsunami_pchip *pchip, int index)
 424 {
 425         pchip->wsba[0].csr = saved_config[index].wsba[0];
 426         pchip->wsm[0].csr = saved_config[index].wsm[0];
 427         pchip->tba[0].csr = saved_config[index].tba[0];
 428
 429         pchip->wsba[1].csr = saved_config[index].wsba[1];
 430         pchip->wsm[1].csr = saved_config[index].wsm[1];
 431         pchip->tba[1].csr = saved_config[index].tba[1];
 432
 433         pchip->wsba[2].csr = saved_config[index].wsba[2];
 434         pchip->wsm[2].csr = saved_config[index].wsm[2];
 435         pchip->tba[2].csr = saved_config[index].tba[2];
 436
 437         pchip->wsba[3].csr = saved_config[index].wsba[3];
 438         pchip->wsm[3].csr = saved_config[index].wsm[3];
 439         pchip->tba[3].csr = saved_config[index].tba[3];
 440 }
 441
 442 void
 443 tsunami_kill_arch(int mode)
 444 {
 445         tsunami_kill_one_pchip(TSUNAMI_pchip0, 0);
 446         if (TSUNAMI_cchip->csc.csr & 1L<<14)
 447                 tsunami_kill_one_pchip(TSUNAMI_pchip1, 1);
 448 }
 449
 450 static inline void
 451 tsunami_pci_clr_err_1(tsunami_pchip *pchip)
 452 {
 453         pchip->perror.csr;
 454         pchip->perror.csr = 0x040;
 455         mb();
 456         pchip->perror.csr;
 457 }
 458
 459 static inline void
 460 tsunami_pci_clr_err(void)
 461 {
 462         tsunami_pci_clr_err_1(TSUNAMI_pchip0);
 463
 464         /* TSUNAMI and TYPHOON can have 2, but might only have 1 (DS10) */
 465         if (TSUNAMI_cchip->csc.csr & 1L<<14)
 466                 tsunami_pci_clr_err_1(TSUNAMI_pchip1);
 467 }
 468
 469 void
 470 tsunami_machine_check(unsigned long vector, unsigned long la_ptr)
 471 {
 472         /* Clear error before any reporting.  */
 473         mb();
 474         mb();  /* magic */
 475         draina();
 476         tsunami_pci_clr_err();
 477         wrmces(0x7);
 478         mb();
 479
 480         process_mcheck_info(vector, la_ptr, "TSUNAMI",
 481                             mcheck_expected(smp_processor_id()));
 482 }