drivers/net/pasemi_mac.h

   1 /*
   2  * Copyright (C) 2006 PA Semi, Inc
   3  *
   4  * Driver for the PA6T-1682M onchip 1G/10G Ethernet MACs, soft state and
   5  * hardware register layouts.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  19  */
  20
  21 #ifndef PASEMI_MAC_H
  22 #define PASEMI_MAC_H
  23
  24 #include <linux/ethtool.h>
  25 #include <linux/netdevice.h>
  26 #include <linux/spinlock.h>
  27 #include <linux/phy.h>
  28
  29 #define MAX_LRO_DESCRIPTORS 8
  30
  31 struct pasemi_mac_txring {
  32         struct pasemi_dmachan chan; /* Must be first */
  33         spinlock_t       lock;
  34         unsigned int     size;
  35         unsigned int     next_to_fill;
  36         unsigned int     next_to_clean;
  37         struct pasemi_mac_buffer *ring_info;
  38         struct pasemi_mac *mac; /* Needed in intr handler */
  39         struct timer_list clean_timer;
  40 };
  41
  42 struct pasemi_mac_rxring {
  43         struct pasemi_dmachan chan; /* Must be first */
  44         spinlock_t       lock;
  45         u64             *buffers;       /* RX interface buffer ring */
  46         dma_addr_t       buf_dma;
  47         unsigned int     size;
  48         unsigned int     next_to_fill;
  49         unsigned int     next_to_clean;
  50         struct pasemi_mac_buffer *ring_info;
  51         struct pasemi_mac *mac; /* Needed in intr handler */
  52 };
  53
  54 struct pasemi_mac {
  55         struct net_device *netdev;
  56         struct pci_dev *pdev;
  57         struct pci_dev *dma_pdev;
  58         struct pci_dev *iob_pdev;
  59         struct phy_device *phydev;
  60         struct napi_struct napi;
  61
  62         int             bufsz; /* RX ring buffer size */
  63         u8              type;
  64 #define MAC_TYPE_GMAC   1
  65 #define MAC_TYPE_XAUI   2
  66         u32     dma_if;
  67
  68         u8              mac_addr[6];
  69
  70         struct net_lro_mgr      lro_mgr;
  71         struct net_lro_desc     lro_desc[MAX_LRO_DESCRIPTORS];
  72         struct timer_list       rxtimer;
  73         unsigned int            lro_max_aggr;
  74
  75         struct pasemi_mac_txring *tx;
  76         struct pasemi_mac_rxring *rx;
  77         char            tx_irq_name[10];                /* "eth%d tx" */
  78         char            rx_irq_name[10];                /* "eth%d rx" */
  79         int     link;
  80         int     speed;
  81         int     duplex;
  82
  83         unsigned int    msg_enable;
  84         char    phy_id[BUS_ID_SIZE];
  85 };
  86
  87 /* Software status descriptor (ring_info) */
  88 struct pasemi_mac_buffer {
  89         struct sk_buff *skb;
  90         dma_addr_t      dma;
  91 };
  92
  93
  94 /* PCI register offsets and formats */
  95
  96
  97 /* MAC CFG register offsets */
  98 enum {
  99         PAS_MAC_CFG_PCFG = 0x80,
 100         PAS_MAC_CFG_MACCFG = 0x84,
 101         PAS_MAC_CFG_ADR0 = 0x8c,
 102         PAS_MAC_CFG_ADR1 = 0x90,
 103         PAS_MAC_CFG_TXP = 0x98,
 104         PAS_MAC_IPC_CHNL = 0x208,
 105 };
 106
 107 /* MAC CFG register fields */
 108 #define PAS_MAC_CFG_PCFG_PE             0x80000000
 109 #define PAS_MAC_CFG_PCFG_CE             0x40000000
 110 #define PAS_MAC_CFG_PCFG_BU             0x20000000
 111 #define PAS_MAC_CFG_PCFG_TT             0x10000000
 112 #define PAS_MAC_CFG_PCFG_TSR_M          0x0c000000
 113 #define PAS_MAC_CFG_PCFG_TSR_10M        0x00000000
 114 #define PAS_MAC_CFG_PCFG_TSR_100M       0x04000000
 115 #define PAS_MAC_CFG_PCFG_TSR_1G         0x08000000
 116 #define PAS_MAC_CFG_PCFG_TSR_10G        0x0c000000
 117 #define PAS_MAC_CFG_PCFG_T24            0x02000000
 118 #define PAS_MAC_CFG_PCFG_PR             0x01000000
 119 #define PAS_MAC_CFG_PCFG_CRO_M          0x00ff0000
 120 #define PAS_MAC_CFG_PCFG_CRO_S  16
 121 #define PAS_MAC_CFG_PCFG_IPO_M          0x0000ff00
 122 #define PAS_MAC_CFG_PCFG_IPO_S  8
 123 #define PAS_MAC_CFG_PCFG_S1             0x00000080
 124 #define PAS_MAC_CFG_PCFG_IO_M           0x00000060
 125 #define PAS_MAC_CFG_PCFG_IO_MAC         0x00000000
 126 #define PAS_MAC_CFG_PCFG_IO_OFF         0x00000020
 127 #define PAS_MAC_CFG_PCFG_IO_IND_ETH     0x00000040
 128 #define PAS_MAC_CFG_PCFG_IO_IND_IP      0x00000060
 129 #define PAS_MAC_CFG_PCFG_LP             0x00000010
 130 #define PAS_MAC_CFG_PCFG_TS             0x00000008
 131 #define PAS_MAC_CFG_PCFG_HD             0x00000004
 132 #define PAS_MAC_CFG_PCFG_SPD_M          0x00000003
 133 #define PAS_MAC_CFG_PCFG_SPD_10M        0x00000000
 134 #define PAS_MAC_CFG_PCFG_SPD_100M       0x00000001
 135 #define PAS_MAC_CFG_PCFG_SPD_1G         0x00000002
 136 #define PAS_MAC_CFG_PCFG_SPD_10G        0x00000003
 137
 138 #define PAS_MAC_CFG_MACCFG_TXT_M        0x70000000
 139 #define PAS_MAC_CFG_MACCFG_TXT_S        28
 140 #define PAS_MAC_CFG_MACCFG_PRES_M       0x0f000000
 141 #define PAS_MAC_CFG_MACCFG_PRES_S       24
 142 #define PAS_MAC_CFG_MACCFG_MAXF_M       0x00ffff00
 143 #define PAS_MAC_CFG_MACCFG_MAXF_S       8
 144 #define PAS_MAC_CFG_MACCFG_MAXF(x)      (((x) << PAS_MAC_CFG_MACCFG_MAXF_S) & \
 145                                          PAS_MAC_CFG_MACCFG_MAXF_M)
 146 #define PAS_MAC_CFG_MACCFG_MINF_M       0x000000ff
 147 #define PAS_MAC_CFG_MACCFG_MINF_S       0
 148
 149 #define PAS_MAC_CFG_TXP_FCF             0x01000000
 150 #define PAS_MAC_CFG_TXP_FCE             0x00800000
 151 #define PAS_MAC_CFG_TXP_FC              0x00400000
 152 #define PAS_MAC_CFG_TXP_FPC_M           0x00300000
 153 #define PAS_MAC_CFG_TXP_FPC_S           20
 154 #define PAS_MAC_CFG_TXP_FPC(x)          (((x) << PAS_MAC_CFG_TXP_FPC_S) & \
 155                                          PAS_MAC_CFG_TXP_FPC_M)
 156 #define PAS_MAC_CFG_TXP_RT              0x00080000
 157 #define PAS_MAC_CFG_TXP_BL              0x00040000
 158 #define PAS_MAC_CFG_TXP_SL_M            0x00030000
 159 #define PAS_MAC_CFG_TXP_SL_S            16
 160 #define PAS_MAC_CFG_TXP_SL(x)           (((x) << PAS_MAC_CFG_TXP_SL_S) & \
 161                                          PAS_MAC_CFG_TXP_SL_M)
 162 #define PAS_MAC_CFG_TXP_COB_M           0x0000f000
 163 #define PAS_MAC_CFG_TXP_COB_S           12
 164 #define PAS_MAC_CFG_TXP_COB(x)          (((x) << PAS_MAC_CFG_TXP_COB_S) & \
 165                                          PAS_MAC_CFG_TXP_COB_M)
 166 #define PAS_MAC_CFG_TXP_TIFT_M          0x00000f00
 167 #define PAS_MAC_CFG_TXP_TIFT_S          8
 168 #define PAS_MAC_CFG_TXP_TIFT(x)         (((x) << PAS_MAC_CFG_TXP_TIFT_S) & \
 169                                          PAS_MAC_CFG_TXP_TIFT_M)
 170 #define PAS_MAC_CFG_TXP_TIFG_M          0x000000ff
 171 #define PAS_MAC_CFG_TXP_TIFG_S          0
 172 #define PAS_MAC_CFG_TXP_TIFG(x)         (((x) << PAS_MAC_CFG_TXP_TIFG_S) & \
 173                                          PAS_MAC_CFG_TXP_TIFG_M)
 174
 175 #define PAS_MAC_IPC_CHNL_DCHNO_M        0x003f0000
 176 #define PAS_MAC_IPC_CHNL_DCHNO_S        16
 177 #define PAS_MAC_IPC_CHNL_DCHNO(x)       (((x) << PAS_MAC_IPC_CHNL_DCHNO_S) & \
 178                                          PAS_MAC_IPC_CHNL_DCHNO_M)
 179 #define PAS_MAC_IPC_CHNL_BCH_M          0x0000003f
 180 #define PAS_MAC_IPC_CHNL_BCH_S          0
 181 #define PAS_MAC_IPC_CHNL_BCH(x)         (((x) << PAS_MAC_IPC_CHNL_BCH_S) & \
 182                                          PAS_MAC_IPC_CHNL_BCH_M)
 183
 184 #endif /* PASEMI_MAC_H */