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Char: mxser, reorder mxser_cardinfo fields
[wrt350n-kernel.git] / drivers / serial / netx-serial.c
blobb56f7db4503100097471c7e037e76a2a967d1349
1 /*
2 * drivers/serial/netx-serial.c
3 *
4 * Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2
8 * as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #if defined(CONFIG_SERIAL_NETX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21 #define SUPPORT_SYSRQ
22 #endif
23
24 #include <linux/device.h>
25 #include <linux/module.h>
26 #include <linux/ioport.h>
27 #include <linux/init.h>
28 #include <linux/console.h>
29 #include <linux/sysrq.h>
30 #include <linux/platform_device.h>
31 #include <linux/tty.h>
32 #include <linux/tty_flip.h>
33 #include <linux/serial_core.h>
34 #include <linux/serial.h>
35
36 #include <asm/io.h>
37 #include <asm/irq.h>
38 #include <asm/hardware.h>
39 #include <asm/arch/netx-regs.h>
40
41 /* We've been assigned a range on the "Low-density serial ports" major */
42 #define SERIAL_NX_MAJOR 204
43 #define MINOR_START 170
44
45 #ifdef CONFIG_SERIAL_NETX_CONSOLE
46
47 enum uart_regs {
48 UART_DR = 0x00,
49 UART_SR = 0x04,
50 UART_LINE_CR = 0x08,
51 UART_BAUDDIV_MSB = 0x0c,
52 UART_BAUDDIV_LSB = 0x10,
53 UART_CR = 0x14,
54 UART_FR = 0x18,
55 UART_IIR = 0x1c,
56 UART_ILPR = 0x20,
57 UART_RTS_CR = 0x24,
58 UART_RTS_LEAD = 0x28,
59 UART_RTS_TRAIL = 0x2c,
60 UART_DRV_ENABLE = 0x30,
61 UART_BRM_CR = 0x34,
62 UART_RXFIFO_IRQLEVEL = 0x38,
63 UART_TXFIFO_IRQLEVEL = 0x3c,
64 };
65
66 #define SR_FE (1<<0)
67 #define SR_PE (1<<1)
68 #define SR_BE (1<<2)
69 #define SR_OE (1<<3)
70
71 #define LINE_CR_BRK (1<<0)
72 #define LINE_CR_PEN (1<<1)
73 #define LINE_CR_EPS (1<<2)
74 #define LINE_CR_STP2 (1<<3)
75 #define LINE_CR_FEN (1<<4)
76 #define LINE_CR_5BIT (0<<5)
77 #define LINE_CR_6BIT (1<<5)
78 #define LINE_CR_7BIT (2<<5)
79 #define LINE_CR_8BIT (3<<5)
80 #define LINE_CR_BITS_MASK (3<<5)
81
82 #define CR_UART_EN (1<<0)
83 #define CR_SIREN (1<<1)
84 #define CR_SIRLP (1<<2)
85 #define CR_MSIE (1<<3)
86 #define CR_RIE (1<<4)
87 #define CR_TIE (1<<5)
88 #define CR_RTIE (1<<6)
89 #define CR_LBE (1<<7)
90
91 #define FR_CTS (1<<0)
92 #define FR_DSR (1<<1)
93 #define FR_DCD (1<<2)
94 #define FR_BUSY (1<<3)
95 #define FR_RXFE (1<<4)
96 #define FR_TXFF (1<<5)
97 #define FR_RXFF (1<<6)
98 #define FR_TXFE (1<<7)
99
100 #define IIR_MIS (1<<0)
101 #define IIR_RIS (1<<1)
102 #define IIR_TIS (1<<2)
103 #define IIR_RTIS (1<<3)
104 #define IIR_MASK 0xf
105
106 #define RTS_CR_AUTO (1<<0)
107 #define RTS_CR_RTS (1<<1)
108 #define RTS_CR_COUNT (1<<2)
109 #define RTS_CR_MOD2 (1<<3)
110 #define RTS_CR_RTS_POL (1<<4)
111 #define RTS_CR_CTS_CTR (1<<5)
112 #define RTS_CR_CTS_POL (1<<6)
113 #define RTS_CR_STICK (1<<7)
114
115 #define UART_PORT_SIZE 0x40
116 #define DRIVER_NAME "netx-uart"
117
118 struct netx_port {
119 struct uart_port port;
120 };
121
122 static void netx_stop_tx(struct uart_port *port)
123 {
124 unsigned int val;
125 val = readl(port->membase + UART_CR);
126 writel(val & ~CR_TIE, port->membase + UART_CR);
127 }
128
129 static void netx_stop_rx(struct uart_port *port)
130 {
131 unsigned int val;
132 val = readl(port->membase + UART_CR);
133 writel(val & ~CR_RIE, port->membase + UART_CR);
134 }
135
136 static void netx_enable_ms(struct uart_port *port)
137 {
138 unsigned int val;
139 val = readl(port->membase + UART_CR);
140 writel(val | CR_MSIE, port->membase + UART_CR);
141 }
142
143 static inline void netx_transmit_buffer(struct uart_port *port)
144 {
145 struct circ_buf *xmit = &port->info->xmit;
146
147 if (port->x_char) {
148 writel(port->x_char, port->membase + UART_DR);
149 port->icount.tx++;
150 port->x_char = 0;
151 return;
152 }
153
154 if (uart_tx_stopped(port) || uart_circ_empty(xmit)) {
155 netx_stop_tx(port);
156 return;
157 }
158
159 do {
160 /* send xmit->buf[xmit->tail]
161 * out the port here */
162 writel(xmit->buf[xmit->tail], port->membase + UART_DR);
163 xmit->tail = (xmit->tail + 1) &
164 (UART_XMIT_SIZE - 1);
165 port->icount.tx++;
166 if (uart_circ_empty(xmit))
167 break;
168 } while (!(readl(port->membase + UART_FR) & FR_TXFF));
169
170 if (uart_circ_empty(xmit))
171 netx_stop_tx(port);
172 }
173
174 static void netx_start_tx(struct uart_port *port)
175 {
176 writel(
177 readl(port->membase + UART_CR) | CR_TIE, port->membase + UART_CR);
178
179 if (!(readl(port->membase + UART_FR) & FR_TXFF))
180 netx_transmit_buffer(port);
181 }
182
183 static unsigned int netx_tx_empty(struct uart_port *port)
184 {
185 return readl(port->membase + UART_FR) & FR_BUSY ? 0 : TIOCSER_TEMT;
186 }
187
188 static void netx_txint(struct uart_port *port)
189 {
190 struct circ_buf *xmit = &port->info->xmit;
191
192 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
193 netx_stop_tx(port);
194 return;
195 }
196
197 netx_transmit_buffer(port);
198
199 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
200 uart_write_wakeup(port);
201 }
202
203 static void netx_rxint(struct uart_port *port)
204 {
205 unsigned char rx, flg, status;
206 struct tty_struct *tty = port->info->tty;
207
208 while (!(readl(port->membase + UART_FR) & FR_RXFE)) {
209 rx = readl(port->membase + UART_DR);
210 flg = TTY_NORMAL;
211 port->icount.rx++;
212 status = readl(port->membase + UART_SR);
213 if (status & SR_BE) {
214 writel(0, port->membase + UART_SR);
215 if (uart_handle_break(port))
216 continue;
217 }
218
219 if (unlikely(status & (SR_FE | SR_PE | SR_OE))) {
220
221 if (status & SR_PE)
222 port->icount.parity++;
223 else if (status & SR_FE)
224 port->icount.frame++;
225 if (status & SR_OE)
226 port->icount.overrun++;
227
228 status &= port->read_status_mask;
229
230 if (status & SR_BE)
231 flg = TTY_BREAK;
232 else if (status & SR_PE)
233 flg = TTY_PARITY;
234 else if (status & SR_FE)
235 flg = TTY_FRAME;
236 }
237
238 if (uart_handle_sysrq_char(port, rx))
239 continue;
240
241 uart_insert_char(port, status, SR_OE, rx, flg);
242 }
243
244 tty_flip_buffer_push(tty);
245 return;
246 }
247
248 static irqreturn_t netx_int(int irq, void *dev_id)
249 {
250 struct uart_port *port = dev_id;
251 unsigned long flags;
252 unsigned char status;
253
254 spin_lock_irqsave(&port->lock,flags);
255
256 status = readl(port->membase + UART_IIR) & IIR_MASK;
257 while (status) {
258 if (status & IIR_RIS)
259 netx_rxint(port);
260 if (status & IIR_TIS)
261 netx_txint(port);
262 if (status & IIR_MIS) {
263 if (readl(port->membase + UART_FR) & FR_CTS)
264 uart_handle_cts_change(port, 1);
265 else
266 uart_handle_cts_change(port, 0);
267 }
268 writel(0, port->membase + UART_IIR);
269 status = readl(port->membase + UART_IIR) & IIR_MASK;
270 }
271
272 spin_unlock_irqrestore(&port->lock,flags);
273 return IRQ_HANDLED;
274 }
275
276 static unsigned int netx_get_mctrl(struct uart_port *port)
277 {
278 unsigned int ret = TIOCM_DSR | TIOCM_CAR;
279
280 if (readl(port->membase + UART_FR) & FR_CTS)
281 ret |= TIOCM_CTS;
282
283 return ret;
284 }
285
286 static void netx_set_mctrl(struct uart_port *port, unsigned int mctrl)
287 {
288 unsigned int val;
289
290 if (mctrl & TIOCM_RTS) {
291 val = readl(port->membase + UART_RTS_CR);
292 writel(val | RTS_CR_RTS, port->membase + UART_RTS_CR);
293 }
294 }
295
296 static void netx_break_ctl(struct uart_port *port, int break_state)
297 {
298 unsigned int line_cr;
299 spin_lock_irq(&port->lock);
300
301 line_cr = readl(port->membase + UART_LINE_CR);
302 if (break_state != 0)
303 line_cr |= LINE_CR_BRK;
304 else
305 line_cr &= ~LINE_CR_BRK;
306 writel(line_cr, port->membase + UART_LINE_CR);
307
308 spin_unlock_irq(&port->lock);
309 }
310
311 static int netx_startup(struct uart_port *port)
312 {
313 int ret;
314
315 ret = request_irq(port->irq, netx_int, 0,
316 DRIVER_NAME, port);
317 if (ret) {
318 dev_err(port->dev, "unable to grab irq%d\n",port->irq);
319 goto exit;
320 }
321
322 writel(readl(port->membase + UART_LINE_CR) | LINE_CR_FEN,
323 port->membase + UART_LINE_CR);
324
325 writel(CR_MSIE | CR_RIE | CR_TIE | CR_RTIE | CR_UART_EN,
326 port->membase + UART_CR);
327
328 exit:
329 return ret;
330 }
331
332 static void netx_shutdown(struct uart_port *port)
333 {
334 writel(0, port->membase + UART_CR) ;
335
336 free_irq(port->irq, port);
337 }
338
339 static void
340 netx_set_termios(struct uart_port *port, struct ktermios *termios,
341 struct ktermios *old)
342 {
343 unsigned int baud, quot;
344 unsigned char old_cr;
345 unsigned char line_cr = LINE_CR_FEN;
346 unsigned char rts_cr = 0;
347
348 switch (termios->c_cflag & CSIZE) {
349 case CS5:
350 line_cr |= LINE_CR_5BIT;
351 break;
352 case CS6:
353 line_cr |= LINE_CR_6BIT;
354 break;
355 case CS7:
356 line_cr |= LINE_CR_7BIT;
357 break;
358 case CS8:
359 line_cr |= LINE_CR_8BIT;
360 break;
361 }
362
363 if (termios->c_cflag & CSTOPB)
364 line_cr |= LINE_CR_STP2;
365
366 if (termios->c_cflag & PARENB) {
367 line_cr |= LINE_CR_PEN;
368 if (!(termios->c_cflag & PARODD))
369 line_cr |= LINE_CR_EPS;
370 }
371
372 if (termios->c_cflag & CRTSCTS)
373 rts_cr = RTS_CR_AUTO | RTS_CR_CTS_CTR | RTS_CR_RTS_POL;
374
375 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
376 quot = baud * 4096;
377 quot /= 1000;
378 quot *= 256;
379 quot /= 100000;
380
381 spin_lock_irq(&port->lock);
382
383 uart_update_timeout(port, termios->c_cflag, baud);
384
385 old_cr = readl(port->membase + UART_CR);
386
387 /* disable interrupts */
388 writel(old_cr & ~(CR_MSIE | CR_RIE | CR_TIE | CR_RTIE),
389 port->membase + UART_CR);
390
391 /* drain transmitter */
392 while (readl(port->membase + UART_FR) & FR_BUSY);
393
394 /* disable UART */
395 writel(old_cr & ~CR_UART_EN, port->membase + UART_CR);
396
397 /* modem status interrupts */
398 old_cr &= ~CR_MSIE;
399 if (UART_ENABLE_MS(port, termios->c_cflag))
400 old_cr |= CR_MSIE;
401
402 writel((quot>>8) & 0xff, port->membase + UART_BAUDDIV_MSB);
403 writel(quot & 0xff, port->membase + UART_BAUDDIV_LSB);
404 writel(line_cr, port->membase + UART_LINE_CR);
405
406 writel(rts_cr, port->membase + UART_RTS_CR);
407
408 /*
409 * Characters to ignore
410 */
411 port->ignore_status_mask = 0;
412 if (termios->c_iflag & IGNPAR)
413 port->ignore_status_mask |= SR_PE;
414 if (termios->c_iflag & IGNBRK) {
415 port->ignore_status_mask |= SR_BE;
416 /*
417 * If we're ignoring parity and break indicators,
418 * ignore overruns too (for real raw support).
419 */
420 if (termios->c_iflag & IGNPAR)
421 port->ignore_status_mask |= SR_PE;
422 }
423
424 port->read_status_mask = 0;
425 if (termios->c_iflag & (BRKINT | PARMRK))
426 port->read_status_mask |= SR_BE;
427 if (termios->c_iflag & INPCK)
428 port->read_status_mask |= SR_PE | SR_FE;
429
430 writel(old_cr, port->membase + UART_CR);
431
432 spin_unlock_irq(&port->lock);
433 }
434
435 static const char *netx_type(struct uart_port *port)
436 {
437 return port->type == PORT_NETX ? "NETX" : NULL;
438 }
439
440 static void netx_release_port(struct uart_port *port)
441 {
442 release_mem_region(port->mapbase, UART_PORT_SIZE);
443 }
444
445 static int netx_request_port(struct uart_port *port)
446 {
447 return request_mem_region(port->mapbase, UART_PORT_SIZE,
448 DRIVER_NAME) != NULL ? 0 : -EBUSY;
449 }
450
451 static void netx_config_port(struct uart_port *port, int flags)
452 {
453 if (flags & UART_CONFIG_TYPE && netx_request_port(port) == 0)
454 port->type = PORT_NETX;
455 }
456
457 static int
458 netx_verify_port(struct uart_port *port, struct serial_struct *ser)
459 {
460 int ret = 0;
461
462 if (ser->type != PORT_UNKNOWN && ser->type != PORT_NETX)
463 ret = -EINVAL;
464
465 return ret;
466 }
467
468 static struct uart_ops netx_pops = {
469 .tx_empty = netx_tx_empty,
470 .set_mctrl = netx_set_mctrl,
471 .get_mctrl = netx_get_mctrl,
472 .stop_tx = netx_stop_tx,
473 .start_tx = netx_start_tx,
474 .stop_rx = netx_stop_rx,
475 .enable_ms = netx_enable_ms,
476 .break_ctl = netx_break_ctl,
477 .startup = netx_startup,
478 .shutdown = netx_shutdown,
479 .set_termios = netx_set_termios,
480 .type = netx_type,
481 .release_port = netx_release_port,
482 .request_port = netx_request_port,
483 .config_port = netx_config_port,
484 .verify_port = netx_verify_port,
485 };
486
487 static struct netx_port netx_ports[] = {
488 {
489 .port = {
490 .type = PORT_NETX,
491 .iotype = UPIO_MEM,
492 .membase = (char __iomem *)io_p2v(NETX_PA_UART0),
493 .mapbase = NETX_PA_UART0,
494 .irq = NETX_IRQ_UART0,
495 .uartclk = 100000000,
496 .fifosize = 16,
497 .flags = UPF_BOOT_AUTOCONF,
498 .ops = &netx_pops,
499 .line = 0,
500 },
501 }, {
502 .port = {
503 .type = PORT_NETX,
504 .iotype = UPIO_MEM,
505 .membase = (char __iomem *)io_p2v(NETX_PA_UART1),
506 .mapbase = NETX_PA_UART1,
507 .irq = NETX_IRQ_UART1,
508 .uartclk = 100000000,
509 .fifosize = 16,
510 .flags = UPF_BOOT_AUTOCONF,
511 .ops = &netx_pops,
512 .line = 1,
513 },
514 }, {
515 .port = {
516 .type = PORT_NETX,
517 .iotype = UPIO_MEM,
518 .membase = (char __iomem *)io_p2v(NETX_PA_UART2),
519 .mapbase = NETX_PA_UART2,
520 .irq = NETX_IRQ_UART2,
521 .uartclk = 100000000,
522 .fifosize = 16,
523 .flags = UPF_BOOT_AUTOCONF,
524 .ops = &netx_pops,
525 .line = 2,
526 },
527 }
528 };
529
530 static void netx_console_putchar(struct uart_port *port, int ch)
531 {
532 while (readl(port->membase + UART_FR) & FR_BUSY);
533 writel(ch, port->membase + UART_DR);
534 }
535
536 static void
537 netx_console_write(struct console *co, const char *s, unsigned int count)
538 {
539 struct uart_port *port = &netx_ports[co->index].port;
540 unsigned char cr_save;
541
542 cr_save = readl(port->membase + UART_CR);
543 writel(cr_save | CR_UART_EN, port->membase + UART_CR);
544
545 uart_console_write(port, s, count, netx_console_putchar);
546
547 while (readl(port->membase + UART_FR) & FR_BUSY);
548 writel(cr_save, port->membase + UART_CR);
549 }
550
551 static void __init
552 netx_console_get_options(struct uart_port *port, int *baud,
553 int *parity, int *bits, int *flow)
554 {
555 unsigned char line_cr;
556
557 *baud = (readl(port->membase + UART_BAUDDIV_MSB) << 8) |
558 readl(port->membase + UART_BAUDDIV_LSB);
559 *baud *= 1000;
560 *baud /= 4096;
561 *baud *= 1000;
562 *baud /= 256;
563 *baud *= 100;
564
565 line_cr = readl(port->membase + UART_LINE_CR);
566 *parity = 'n';
567 if (line_cr & LINE_CR_PEN) {
568 if (line_cr & LINE_CR_EPS)
569 *parity = 'e';
570 else
571 *parity = 'o';
572 }
573
574 switch (line_cr & LINE_CR_BITS_MASK) {
575 case LINE_CR_8BIT:
576 *bits = 8;
577 break;
578 case LINE_CR_7BIT:
579 *bits = 7;
580 break;
581 case LINE_CR_6BIT:
582 *bits = 6;
583 break;
584 case LINE_CR_5BIT:
585 *bits = 5;
586 break;
587 }
588
589 if (readl(port->membase + UART_RTS_CR) & RTS_CR_AUTO)
590 *flow = 'r';
591 }
592
593 static int __init
594 netx_console_setup(struct console *co, char *options)
595 {
596 struct netx_port *sport;
597 int baud = 9600;
598 int bits = 8;
599 int parity = 'n';
600 int flow = 'n';
601
602 /*
603 * Check whether an invalid uart number has been specified, and
604 * if so, search for the first available port that does have
605 * console support.
606 */
607 if (co->index == -1 || co->index >= ARRAY_SIZE(netx_ports))
608 co->index = 0;
609 sport = &netx_ports[co->index];
610
611 if (options) {
612 uart_parse_options(options, &baud, &parity, &bits, &flow);
613 } else {
614 /* if the UART is enabled, assume it has been correctly setup
615 * by the bootloader and get the options
616 */
617 if (readl(sport->port.membase + UART_CR) & CR_UART_EN) {
618 netx_console_get_options(&sport->port, &baud,
619 &parity, &bits, &flow);
620 }
621
622 }
623
624 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
625 }
626
627 static struct uart_driver netx_reg;
628 static struct console netx_console = {
629 .name = "ttyNX",
630 .write = netx_console_write,
631 .device = uart_console_device,
632 .setup = netx_console_setup,
633 .flags = CON_PRINTBUFFER,
634 .index = -1,
635 .data = &netx_reg,
636 };
637
638 static int __init netx_console_init(void)
639 {
640 register_console(&netx_console);
641 return 0;
642 }
643 console_initcall(netx_console_init);
644
645 #define NETX_CONSOLE &netx_console
646 #else
647 #define NETX_CONSOLE NULL
648 #endif
649
650 static struct uart_driver netx_reg = {
651 .owner = THIS_MODULE,
652 .driver_name = DRIVER_NAME,
653 .dev_name = "ttyNX",
654 .major = SERIAL_NX_MAJOR,
655 .minor = MINOR_START,
656 .nr = ARRAY_SIZE(netx_ports),
657 .cons = NETX_CONSOLE,
658 };
659
660 static int serial_netx_suspend(struct platform_device *pdev, pm_message_t state)
661 {
662 struct netx_port *sport = platform_get_drvdata(pdev);
663
664 if (sport)
665 uart_suspend_port(&netx_reg, &sport->port);
666
667 return 0;
668 }
669
670 static int serial_netx_resume(struct platform_device *pdev)
671 {
672 struct netx_port *sport = platform_get_drvdata(pdev);
673
674 if (sport)
675 uart_resume_port(&netx_reg, &sport->port);
676
677 return 0;
678 }
679
680 static int serial_netx_probe(struct platform_device *pdev)
681 {
682 struct uart_port *port = &netx_ports[pdev->id].port;
683
684 dev_info(&pdev->dev, "initialising\n");
685
686 port->dev = &pdev->dev;
687
688 writel(1, port->membase + UART_RXFIFO_IRQLEVEL);
689 uart_add_one_port(&netx_reg, &netx_ports[pdev->id].port);
690 platform_set_drvdata(pdev, &netx_ports[pdev->id]);
691
692 return 0;
693 }
694
695 static int serial_netx_remove(struct platform_device *pdev)
696 {
697 struct netx_port *sport = platform_get_drvdata(pdev);
698
699 platform_set_drvdata(pdev, NULL);
700
701 if (sport)
702 uart_remove_one_port(&netx_reg, &sport->port);
703
704 return 0;
705 }
706
707 static struct platform_driver serial_netx_driver = {
708 .probe = serial_netx_probe,
709 .remove = serial_netx_remove,
710
711 .suspend = serial_netx_suspend,
712 .resume = serial_netx_resume,
713
714 .driver = {
715 .name = DRIVER_NAME,
716 },
717 };
718
719 static int __init netx_serial_init(void)
720 {
721 int ret;
722
723 printk(KERN_INFO "Serial: NetX driver\n");
724
725 ret = uart_register_driver(&netx_reg);
726 if (ret)
727 return ret;
728
729 ret = platform_driver_register(&serial_netx_driver);
730 if (ret != 0)
731 uart_unregister_driver(&netx_reg);
732
733 return 0;
734 }
735
736 static void __exit netx_serial_exit(void)
737 {
738 platform_driver_unregister(&serial_netx_driver);
739 uart_unregister_driver(&netx_reg);
740 }
741
742 module_init(netx_serial_init);
743 module_exit(netx_serial_exit);
744
745 MODULE_AUTHOR("Sascha Hauer");
746 MODULE_DESCRIPTION("NetX serial port driver");
747 MODULE_LICENSE("GPL");
WRT350N Kernel Patches