?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Char: mxser, reorder mxser_cardinfo fields
[wrt350n-kernel.git] / drivers / serial / pmac_zilog.c
blob794bd0f50d7374533489a888ae19cf2763704fe4
1 /*
2 * linux/drivers/serial/pmac_zilog.c
3 *
4 * Driver for PowerMac Z85c30 based ESCC cell found in the
5 * "macio" ASICs of various PowerMac models
6 *
7 * Copyright (C) 2003 Ben. Herrenschmidt (benh@kernel.crashing.org)
8 *
9 * Derived from drivers/macintosh/macserial.c by Paul Mackerras
10 * and drivers/serial/sunzilog.c by David S. Miller
11 *
12 * Hrm... actually, I ripped most of sunzilog (Thanks David !) and
13 * adapted special tweaks needed for us. I don't think it's worth
14 * merging back those though. The DMA code still has to get in
15 * and once done, I expect that driver to remain fairly stable in
16 * the long term, unless we change the driver model again...
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 *
32 * 2004-08-06 Harald Welte <laforge@gnumonks.org>
33 * - Enable BREAK interrupt
34 * - Add support for sysreq
35 *
36 * TODO: - Add DMA support
37 * - Defer port shutdown to a few seconds after close
38 * - maybe put something right into uap->clk_divisor
39 */
40
41 #undef DEBUG
42 #undef DEBUG_HARD
43 #undef USE_CTRL_O_SYSRQ
44
45 #include <linux/module.h>
46 #include <linux/tty.h>
47
48 #include <linux/tty_flip.h>
49 #include <linux/major.h>
50 #include <linux/string.h>
51 #include <linux/fcntl.h>
52 #include <linux/mm.h>
53 #include <linux/kernel.h>
54 #include <linux/delay.h>
55 #include <linux/init.h>
56 #include <linux/console.h>
57 #include <linux/slab.h>
58 #include <linux/adb.h>
59 #include <linux/pmu.h>
60 #include <linux/bitops.h>
61 #include <linux/sysrq.h>
62 #include <linux/mutex.h>
63 #include <asm/sections.h>
64 #include <asm/io.h>
65 #include <asm/irq.h>
66 #include <asm/prom.h>
67 #include <asm/machdep.h>
68 #include <asm/pmac_feature.h>
69 #include <asm/dbdma.h>
70 #include <asm/macio.h>
71
72 #if defined (CONFIG_SERIAL_PMACZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
73 #define SUPPORT_SYSRQ
74 #endif
75
76 #include <linux/serial.h>
77 #include <linux/serial_core.h>
78
79 #include "pmac_zilog.h"
80
81 /* Not yet implemented */
82 #undef HAS_DBDMA
83
84 static char version[] __initdata = "pmac_zilog: 0.6 (Benjamin Herrenschmidt <benh@kernel.crashing.org>)";
85 MODULE_AUTHOR("Benjamin Herrenschmidt <benh@kernel.crashing.org>");
86 MODULE_DESCRIPTION("Driver for the PowerMac serial ports.");
87 MODULE_LICENSE("GPL");
88
89 #define PWRDBG(fmt, arg...) printk(KERN_DEBUG fmt , ## arg)
90
91 #ifdef CONFIG_SERIAL_PMACZILOG_TTYS
92 #define PMACZILOG_MAJOR TTY_MAJOR
93 #define PMACZILOG_MINOR 64
94 #define PMACZILOG_NAME "ttyS"
95 #else
96 #define PMACZILOG_MAJOR 204
97 #define PMACZILOG_MINOR 192
98 #define PMACZILOG_NAME "ttyPZ"
99 #endif
100
101
102 /*
103 * For the sake of early serial console, we can do a pre-probe
104 * (optional) of the ports at rather early boot time.
105 */
106 static struct uart_pmac_port pmz_ports[MAX_ZS_PORTS];
107 static int pmz_ports_count;
108 static DEFINE_MUTEX(pmz_irq_mutex);
109
110 static struct uart_driver pmz_uart_reg = {
111 .owner = THIS_MODULE,
112 .driver_name = PMACZILOG_NAME,
113 .dev_name = PMACZILOG_NAME,
114 .major = PMACZILOG_MAJOR,
115 .minor = PMACZILOG_MINOR,
116 };
117
118
119 /*
120 * Load all registers to reprogram the port
121 * This function must only be called when the TX is not busy. The UART
122 * port lock must be held and local interrupts disabled.
123 */
124 static void pmz_load_zsregs(struct uart_pmac_port *uap, u8 *regs)
125 {
126 int i;
127
128 if (ZS_IS_ASLEEP(uap))
129 return;
130
131 /* Let pending transmits finish. */
132 for (i = 0; i < 1000; i++) {
133 unsigned char stat = read_zsreg(uap, R1);
134 if (stat & ALL_SNT)
135 break;
136 udelay(100);
137 }
138
139 ZS_CLEARERR(uap);
140 zssync(uap);
141 ZS_CLEARFIFO(uap);
142 zssync(uap);
143 ZS_CLEARERR(uap);
144
145 /* Disable all interrupts. */
146 write_zsreg(uap, R1,
147 regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB));
148
149 /* Set parity, sync config, stop bits, and clock divisor. */
150 write_zsreg(uap, R4, regs[R4]);
151
152 /* Set misc. TX/RX control bits. */
153 write_zsreg(uap, R10, regs[R10]);
154
155 /* Set TX/RX controls sans the enable bits. */
156 write_zsreg(uap, R3, regs[R3] & ~RxENABLE);
157 write_zsreg(uap, R5, regs[R5] & ~TxENABLE);
158
159 /* now set R7 "prime" on ESCC */
160 write_zsreg(uap, R15, regs[R15] | EN85C30);
161 write_zsreg(uap, R7, regs[R7P]);
162
163 /* make sure we use R7 "non-prime" on ESCC */
164 write_zsreg(uap, R15, regs[R15] & ~EN85C30);
165
166 /* Synchronous mode config. */
167 write_zsreg(uap, R6, regs[R6]);
168 write_zsreg(uap, R7, regs[R7]);
169
170 /* Disable baud generator. */
171 write_zsreg(uap, R14, regs[R14] & ~BRENAB);
172
173 /* Clock mode control. */
174 write_zsreg(uap, R11, regs[R11]);
175
176 /* Lower and upper byte of baud rate generator divisor. */
177 write_zsreg(uap, R12, regs[R12]);
178 write_zsreg(uap, R13, regs[R13]);
179
180 /* Now rewrite R14, with BRENAB (if set). */
181 write_zsreg(uap, R14, regs[R14]);
182
183 /* Reset external status interrupts. */
184 write_zsreg(uap, R0, RES_EXT_INT);
185 write_zsreg(uap, R0, RES_EXT_INT);
186
187 /* Rewrite R3/R5, this time without enables masked. */
188 write_zsreg(uap, R3, regs[R3]);
189 write_zsreg(uap, R5, regs[R5]);
190
191 /* Rewrite R1, this time without IRQ enabled masked. */
192 write_zsreg(uap, R1, regs[R1]);
193
194 /* Enable interrupts */
195 write_zsreg(uap, R9, regs[R9]);
196 }
197
198 /*
199 * We do like sunzilog to avoid disrupting pending Tx
200 * Reprogram the Zilog channel HW registers with the copies found in the
201 * software state struct. If the transmitter is busy, we defer this update
202 * until the next TX complete interrupt. Else, we do it right now.
203 *
204 * The UART port lock must be held and local interrupts disabled.
205 */
206 static void pmz_maybe_update_regs(struct uart_pmac_port *uap)
207 {
208 if (!ZS_REGS_HELD(uap)) {
209 if (ZS_TX_ACTIVE(uap)) {
210 uap->flags |= PMACZILOG_FLAG_REGS_HELD;
211 } else {
212 pmz_debug("pmz: maybe_update_regs: updating\n");
213 pmz_load_zsregs(uap, uap->curregs);
214 }
215 }
216 }
217
218 static struct tty_struct *pmz_receive_chars(struct uart_pmac_port *uap)
219 {
220 struct tty_struct *tty = NULL;
221 unsigned char ch, r1, drop, error, flag;
222 int loops = 0;
223
224 /* The interrupt can be enabled when the port isn't open, typically
225 * that happens when using one port is open and the other closed (stale
226 * interrupt) or when one port is used as a console.
227 */
228 if (!ZS_IS_OPEN(uap)) {
229 pmz_debug("pmz: draining input\n");
230 /* Port is closed, drain input data */
231 for (;;) {
232 if ((++loops) > 1000)
233 goto flood;
234 (void)read_zsreg(uap, R1);
235 write_zsreg(uap, R0, ERR_RES);
236 (void)read_zsdata(uap);
237 ch = read_zsreg(uap, R0);
238 if (!(ch & Rx_CH_AV))
239 break;
240 }
241 return NULL;
242 }
243
244 /* Sanity check, make sure the old bug is no longer happening */
245 if (uap->port.info == NULL || uap->port.info->tty == NULL) {
246 WARN_ON(1);
247 (void)read_zsdata(uap);
248 return NULL;
249 }
250 tty = uap->port.info->tty;
251
252 while (1) {
253 error = 0;
254 drop = 0;
255
256 r1 = read_zsreg(uap, R1);
257 ch = read_zsdata(uap);
258
259 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
260 write_zsreg(uap, R0, ERR_RES);
261 zssync(uap);
262 }
263
264 ch &= uap->parity_mask;
265 if (ch == 0 && uap->flags & PMACZILOG_FLAG_BREAK) {
266 uap->flags &= ~PMACZILOG_FLAG_BREAK;
267 }
268
269 #if defined(CONFIG_MAGIC_SYSRQ) && defined(CONFIG_SERIAL_CORE_CONSOLE)
270 #ifdef USE_CTRL_O_SYSRQ
271 /* Handle the SysRq ^O Hack */
272 if (ch == '\x0f') {
273 uap->port.sysrq = jiffies + HZ*5;
274 goto next_char;
275 }
276 #endif /* USE_CTRL_O_SYSRQ */
277 if (uap->port.sysrq) {
278 int swallow;
279 spin_unlock(&uap->port.lock);
280 swallow = uart_handle_sysrq_char(&uap->port, ch);
281 spin_lock(&uap->port.lock);
282 if (swallow)
283 goto next_char;
284 }
285 #endif /* CONFIG_MAGIC_SYSRQ && CONFIG_SERIAL_CORE_CONSOLE */
286
287 /* A real serial line, record the character and status. */
288 if (drop)
289 goto next_char;
290
291 flag = TTY_NORMAL;
292 uap->port.icount.rx++;
293
294 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR | BRK_ABRT)) {
295 error = 1;
296 if (r1 & BRK_ABRT) {
297 pmz_debug("pmz: got break !\n");
298 r1 &= ~(PAR_ERR | CRC_ERR);
299 uap->port.icount.brk++;
300 if (uart_handle_break(&uap->port))
301 goto next_char;
302 }
303 else if (r1 & PAR_ERR)
304 uap->port.icount.parity++;
305 else if (r1 & CRC_ERR)
306 uap->port.icount.frame++;
307 if (r1 & Rx_OVR)
308 uap->port.icount.overrun++;
309 r1 &= uap->port.read_status_mask;
310 if (r1 & BRK_ABRT)
311 flag = TTY_BREAK;
312 else if (r1 & PAR_ERR)
313 flag = TTY_PARITY;
314 else if (r1 & CRC_ERR)
315 flag = TTY_FRAME;
316 }
317
318 if (uap->port.ignore_status_mask == 0xff ||
319 (r1 & uap->port.ignore_status_mask) == 0) {
320 tty_insert_flip_char(tty, ch, flag);
321 }
322 if (r1 & Rx_OVR)
323 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
324 next_char:
325 /* We can get stuck in an infinite loop getting char 0 when the
326 * line is in a wrong HW state, we break that here.
327 * When that happens, I disable the receive side of the driver.
328 * Note that what I've been experiencing is a real irq loop where
329 * I'm getting flooded regardless of the actual port speed.
330 * Something stange is going on with the HW
331 */
332 if ((++loops) > 1000)
333 goto flood;
334 ch = read_zsreg(uap, R0);
335 if (!(ch & Rx_CH_AV))
336 break;
337 }
338
339 return tty;
340 flood:
341 uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
342 write_zsreg(uap, R1, uap->curregs[R1]);
343 zssync(uap);
344 dev_err(&uap->dev->ofdev.dev, "pmz: rx irq flood !\n");
345 return tty;
346 }
347
348 static void pmz_status_handle(struct uart_pmac_port *uap)
349 {
350 unsigned char status;
351
352 status = read_zsreg(uap, R0);
353 write_zsreg(uap, R0, RES_EXT_INT);
354 zssync(uap);
355
356 if (ZS_IS_OPEN(uap) && ZS_WANTS_MODEM_STATUS(uap)) {
357 if (status & SYNC_HUNT)
358 uap->port.icount.dsr++;
359
360 /* The Zilog just gives us an interrupt when DCD/CTS/etc. change.
361 * But it does not tell us which bit has changed, we have to keep
362 * track of this ourselves.
363 * The CTS input is inverted for some reason. -- paulus
364 */
365 if ((status ^ uap->prev_status) & DCD)
366 uart_handle_dcd_change(&uap->port,
367 (status & DCD));
368 if ((status ^ uap->prev_status) & CTS)
369 uart_handle_cts_change(&uap->port,
370 !(status & CTS));
371
372 wake_up_interruptible(&uap->port.info->delta_msr_wait);
373 }
374
375 if (status & BRK_ABRT)
376 uap->flags |= PMACZILOG_FLAG_BREAK;
377
378 uap->prev_status = status;
379 }
380
381 static void pmz_transmit_chars(struct uart_pmac_port *uap)
382 {
383 struct circ_buf *xmit;
384
385 if (ZS_IS_ASLEEP(uap))
386 return;
387 if (ZS_IS_CONS(uap)) {
388 unsigned char status = read_zsreg(uap, R0);
389
390 /* TX still busy? Just wait for the next TX done interrupt.
391 *
392 * It can occur because of how we do serial console writes. It would
393 * be nice to transmit console writes just like we normally would for
394 * a TTY line. (ie. buffered and TX interrupt driven). That is not
395 * easy because console writes cannot sleep. One solution might be
396 * to poll on enough port->xmit space becomming free. -DaveM
397 */
398 if (!(status & Tx_BUF_EMP))
399 return;
400 }
401
402 uap->flags &= ~PMACZILOG_FLAG_TX_ACTIVE;
403
404 if (ZS_REGS_HELD(uap)) {
405 pmz_load_zsregs(uap, uap->curregs);
406 uap->flags &= ~PMACZILOG_FLAG_REGS_HELD;
407 }
408
409 if (ZS_TX_STOPPED(uap)) {
410 uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED;
411 goto ack_tx_int;
412 }
413
414 if (uap->port.x_char) {
415 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
416 write_zsdata(uap, uap->port.x_char);
417 zssync(uap);
418 uap->port.icount.tx++;
419 uap->port.x_char = 0;
420 return;
421 }
422
423 if (uap->port.info == NULL)
424 goto ack_tx_int;
425 xmit = &uap->port.info->xmit;
426 if (uart_circ_empty(xmit)) {
427 uart_write_wakeup(&uap->port);
428 goto ack_tx_int;
429 }
430 if (uart_tx_stopped(&uap->port))
431 goto ack_tx_int;
432
433 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
434 write_zsdata(uap, xmit->buf[xmit->tail]);
435 zssync(uap);
436
437 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
438 uap->port.icount.tx++;
439
440 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
441 uart_write_wakeup(&uap->port);
442
443 return;
444
445 ack_tx_int:
446 write_zsreg(uap, R0, RES_Tx_P);
447 zssync(uap);
448 }
449
450 /* Hrm... we register that twice, fixme later.... */
451 static irqreturn_t pmz_interrupt(int irq, void *dev_id)
452 {
453 struct uart_pmac_port *uap = dev_id;
454 struct uart_pmac_port *uap_a;
455 struct uart_pmac_port *uap_b;
456 int rc = IRQ_NONE;
457 struct tty_struct *tty;
458 u8 r3;
459
460 uap_a = pmz_get_port_A(uap);
461 uap_b = uap_a->mate;
462
463 spin_lock(&uap_a->port.lock);
464 r3 = read_zsreg(uap_a, R3);
465
466 #ifdef DEBUG_HARD
467 pmz_debug("irq, r3: %x\n", r3);
468 #endif
469 /* Channel A */
470 tty = NULL;
471 if (r3 & (CHAEXT | CHATxIP | CHARxIP)) {
472 write_zsreg(uap_a, R0, RES_H_IUS);
473 zssync(uap_a);
474 if (r3 & CHAEXT)
475 pmz_status_handle(uap_a);
476 if (r3 & CHARxIP)
477 tty = pmz_receive_chars(uap_a);
478 if (r3 & CHATxIP)
479 pmz_transmit_chars(uap_a);
480 rc = IRQ_HANDLED;
481 }
482 spin_unlock(&uap_a->port.lock);
483 if (tty != NULL)
484 tty_flip_buffer_push(tty);
485
486 if (uap_b->node == NULL)
487 goto out;
488
489 spin_lock(&uap_b->port.lock);
490 tty = NULL;
491 if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) {
492 write_zsreg(uap_b, R0, RES_H_IUS);
493 zssync(uap_b);
494 if (r3 & CHBEXT)
495 pmz_status_handle(uap_b);
496 if (r3 & CHBRxIP)
497 tty = pmz_receive_chars(uap_b);
498 if (r3 & CHBTxIP)
499 pmz_transmit_chars(uap_b);
500 rc = IRQ_HANDLED;
501 }
502 spin_unlock(&uap_b->port.lock);
503 if (tty != NULL)
504 tty_flip_buffer_push(tty);
505
506 out:
507 #ifdef DEBUG_HARD
508 pmz_debug("irq done.\n");
509 #endif
510 return rc;
511 }
512
513 /*
514 * Peek the status register, lock not held by caller
515 */
516 static inline u8 pmz_peek_status(struct uart_pmac_port *uap)
517 {
518 unsigned long flags;
519 u8 status;
520
521 spin_lock_irqsave(&uap->port.lock, flags);
522 status = read_zsreg(uap, R0);
523 spin_unlock_irqrestore(&uap->port.lock, flags);
524
525 return status;
526 }
527
528 /*
529 * Check if transmitter is empty
530 * The port lock is not held.
531 */
532 static unsigned int pmz_tx_empty(struct uart_port *port)
533 {
534 struct uart_pmac_port *uap = to_pmz(port);
535 unsigned char status;
536
537 if (ZS_IS_ASLEEP(uap) || uap->node == NULL)
538 return TIOCSER_TEMT;
539
540 status = pmz_peek_status(to_pmz(port));
541 if (status & Tx_BUF_EMP)
542 return TIOCSER_TEMT;
543 return 0;
544 }
545
546 /*
547 * Set Modem Control (RTS & DTR) bits
548 * The port lock is held and interrupts are disabled.
549 * Note: Shall we really filter out RTS on external ports or
550 * should that be dealt at higher level only ?
551 */
552 static void pmz_set_mctrl(struct uart_port *port, unsigned int mctrl)
553 {
554 struct uart_pmac_port *uap = to_pmz(port);
555 unsigned char set_bits, clear_bits;
556
557 /* Do nothing for irda for now... */
558 if (ZS_IS_IRDA(uap))
559 return;
560 /* We get called during boot with a port not up yet */
561 if (ZS_IS_ASLEEP(uap) ||
562 !(ZS_IS_OPEN(uap) || ZS_IS_CONS(uap)))
563 return;
564
565 set_bits = clear_bits = 0;
566
567 if (ZS_IS_INTMODEM(uap)) {
568 if (mctrl & TIOCM_RTS)
569 set_bits |= RTS;
570 else
571 clear_bits |= RTS;
572 }
573 if (mctrl & TIOCM_DTR)
574 set_bits |= DTR;
575 else
576 clear_bits |= DTR;
577
578 /* NOTE: Not subject to 'transmitter active' rule. */
579 uap->curregs[R5] |= set_bits;
580 uap->curregs[R5] &= ~clear_bits;
581 if (ZS_IS_ASLEEP(uap))
582 return;
583 write_zsreg(uap, R5, uap->curregs[R5]);
584 pmz_debug("pmz_set_mctrl: set bits: %x, clear bits: %x -> %x\n",
585 set_bits, clear_bits, uap->curregs[R5]);
586 zssync(uap);
587 }
588
589 /*
590 * Get Modem Control bits (only the input ones, the core will
591 * or that with a cached value of the control ones)
592 * The port lock is held and interrupts are disabled.
593 */
594 static unsigned int pmz_get_mctrl(struct uart_port *port)
595 {
596 struct uart_pmac_port *uap = to_pmz(port);
597 unsigned char status;
598 unsigned int ret;
599
600 if (ZS_IS_ASLEEP(uap) || uap->node == NULL)
601 return 0;
602
603 status = read_zsreg(uap, R0);
604
605 ret = 0;
606 if (status & DCD)
607 ret |= TIOCM_CAR;
608 if (status & SYNC_HUNT)
609 ret |= TIOCM_DSR;
610 if (!(status & CTS))
611 ret |= TIOCM_CTS;
612
613 return ret;
614 }
615
616 /*
617 * Stop TX side. Dealt like sunzilog at next Tx interrupt,
618 * though for DMA, we will have to do a bit more.
619 * The port lock is held and interrupts are disabled.
620 */
621 static void pmz_stop_tx(struct uart_port *port)
622 {
623 to_pmz(port)->flags |= PMACZILOG_FLAG_TX_STOPPED;
624 }
625
626 /*
627 * Kick the Tx side.
628 * The port lock is held and interrupts are disabled.
629 */
630 static void pmz_start_tx(struct uart_port *port)
631 {
632 struct uart_pmac_port *uap = to_pmz(port);
633 unsigned char status;
634
635 pmz_debug("pmz: start_tx()\n");
636
637 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
638 uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED;
639
640 if (ZS_IS_ASLEEP(uap) || uap->node == NULL)
641 return;
642
643 status = read_zsreg(uap, R0);
644
645 /* TX busy? Just wait for the TX done interrupt. */
646 if (!(status & Tx_BUF_EMP))
647 return;
648
649 /* Send the first character to jump-start the TX done
650 * IRQ sending engine.
651 */
652 if (port->x_char) {
653 write_zsdata(uap, port->x_char);
654 zssync(uap);
655 port->icount.tx++;
656 port->x_char = 0;
657 } else {
658 struct circ_buf *xmit = &port->info->xmit;
659
660 write_zsdata(uap, xmit->buf[xmit->tail]);
661 zssync(uap);
662 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
663 port->icount.tx++;
664
665 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
666 uart_write_wakeup(&uap->port);
667 }
668 pmz_debug("pmz: start_tx() done.\n");
669 }
670
671 /*
672 * Stop Rx side, basically disable emitting of
673 * Rx interrupts on the port. We don't disable the rx
674 * side of the chip proper though
675 * The port lock is held.
676 */
677 static void pmz_stop_rx(struct uart_port *port)
678 {
679 struct uart_pmac_port *uap = to_pmz(port);
680
681 if (ZS_IS_ASLEEP(uap) || uap->node == NULL)
682 return;
683
684 pmz_debug("pmz: stop_rx()()\n");
685
686 /* Disable all RX interrupts. */
687 uap->curregs[R1] &= ~RxINT_MASK;
688 pmz_maybe_update_regs(uap);
689
690 pmz_debug("pmz: stop_rx() done.\n");
691 }
692
693 /*
694 * Enable modem status change interrupts
695 * The port lock is held.
696 */
697 static void pmz_enable_ms(struct uart_port *port)
698 {
699 struct uart_pmac_port *uap = to_pmz(port);
700 unsigned char new_reg;
701
702 if (ZS_IS_IRDA(uap) || uap->node == NULL)
703 return;
704 new_reg = uap->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
705 if (new_reg != uap->curregs[R15]) {
706 uap->curregs[R15] = new_reg;
707
708 if (ZS_IS_ASLEEP(uap))
709 return;
710 /* NOTE: Not subject to 'transmitter active' rule. */
711 write_zsreg(uap, R15, uap->curregs[R15]);
712 }
713 }
714
715 /*
716 * Control break state emission
717 * The port lock is not held.
718 */
719 static void pmz_break_ctl(struct uart_port *port, int break_state)
720 {
721 struct uart_pmac_port *uap = to_pmz(port);
722 unsigned char set_bits, clear_bits, new_reg;
723 unsigned long flags;
724
725 if (uap->node == NULL)
726 return;
727 set_bits = clear_bits = 0;
728
729 if (break_state)
730 set_bits |= SND_BRK;
731 else
732 clear_bits |= SND_BRK;
733
734 spin_lock_irqsave(&port->lock, flags);
735
736 new_reg = (uap->curregs[R5] | set_bits) & ~clear_bits;
737 if (new_reg != uap->curregs[R5]) {
738 uap->curregs[R5] = new_reg;
739
740 /* NOTE: Not subject to 'transmitter active' rule. */
741 if (ZS_IS_ASLEEP(uap))
742 return;
743 write_zsreg(uap, R5, uap->curregs[R5]);
744 }
745
746 spin_unlock_irqrestore(&port->lock, flags);
747 }
748
749 /*
750 * Turn power on or off to the SCC and associated stuff
751 * (port drivers, modem, IR port, etc.)
752 * Returns the number of milliseconds we should wait before
753 * trying to use the port.
754 */
755 static int pmz_set_scc_power(struct uart_pmac_port *uap, int state)
756 {
757 int delay = 0;
758 int rc;
759
760 if (state) {
761 rc = pmac_call_feature(
762 PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 1);
763 pmz_debug("port power on result: %d\n", rc);
764 if (ZS_IS_INTMODEM(uap)) {
765 rc = pmac_call_feature(
766 PMAC_FTR_MODEM_ENABLE, uap->node, 0, 1);
767 delay = 2500; /* wait for 2.5s before using */
768 pmz_debug("modem power result: %d\n", rc);
769 }
770 } else {
771 /* TODO: Make that depend on a timer, don't power down
772 * immediately
773 */
774 if (ZS_IS_INTMODEM(uap)) {
775 rc = pmac_call_feature(
776 PMAC_FTR_MODEM_ENABLE, uap->node, 0, 0);
777 pmz_debug("port power off result: %d\n", rc);
778 }
779 pmac_call_feature(PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 0);
780 }
781 return delay;
782 }
783
784 /*
785 * FixZeroBug....Works around a bug in the SCC receving channel.
786 * Inspired from Darwin code, 15 Sept. 2000 -DanM
787 *
788 * The following sequence prevents a problem that is seen with O'Hare ASICs
789 * (most versions -- also with some Heathrow and Hydra ASICs) where a zero
790 * at the input to the receiver becomes 'stuck' and locks up the receiver.
791 * This problem can occur as a result of a zero bit at the receiver input
792 * coincident with any of the following events:
793 *
794 * The SCC is initialized (hardware or software).
795 * A framing error is detected.
796 * The clocking option changes from synchronous or X1 asynchronous
797 * clocking to X16, X32, or X64 asynchronous clocking.
798 * The decoding mode is changed among NRZ, NRZI, FM0, or FM1.
799 *
800 * This workaround attempts to recover from the lockup condition by placing
801 * the SCC in synchronous loopback mode with a fast clock before programming
802 * any of the asynchronous modes.
803 */
804 static void pmz_fix_zero_bug_scc(struct uart_pmac_port *uap)
805 {
806 write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB);
807 zssync(uap);
808 udelay(10);
809 write_zsreg(uap, 9, (ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB) | NV);
810 zssync(uap);
811
812 write_zsreg(uap, 4, X1CLK | MONSYNC);
813 write_zsreg(uap, 3, Rx8);
814 write_zsreg(uap, 5, Tx8 | RTS);
815 write_zsreg(uap, 9, NV); /* Didn't we already do this? */
816 write_zsreg(uap, 11, RCBR | TCBR);
817 write_zsreg(uap, 12, 0);
818 write_zsreg(uap, 13, 0);
819 write_zsreg(uap, 14, (LOOPBAK | BRSRC));
820 write_zsreg(uap, 14, (LOOPBAK | BRSRC | BRENAB));
821 write_zsreg(uap, 3, Rx8 | RxENABLE);
822 write_zsreg(uap, 0, RES_EXT_INT);
823 write_zsreg(uap, 0, RES_EXT_INT);
824 write_zsreg(uap, 0, RES_EXT_INT); /* to kill some time */
825
826 /* The channel should be OK now, but it is probably receiving
827 * loopback garbage.
828 * Switch to asynchronous mode, disable the receiver,
829 * and discard everything in the receive buffer.
830 */
831 write_zsreg(uap, 9, NV);
832 write_zsreg(uap, 4, X16CLK | SB_MASK);
833 write_zsreg(uap, 3, Rx8);
834
835 while (read_zsreg(uap, 0) & Rx_CH_AV) {
836 (void)read_zsreg(uap, 8);
837 write_zsreg(uap, 0, RES_EXT_INT);
838 write_zsreg(uap, 0, ERR_RES);
839 }
840 }
841
842 /*
843 * Real startup routine, powers up the hardware and sets up
844 * the SCC. Returns a delay in ms where you need to wait before
845 * actually using the port, this is typically the internal modem
846 * powerup delay. This routine expect the lock to be taken.
847 */
848 static int __pmz_startup(struct uart_pmac_port *uap)
849 {
850 int pwr_delay = 0;
851
852 memset(&uap->curregs, 0, sizeof(uap->curregs));
853
854 /* Power up the SCC & underlying hardware (modem/irda) */
855 pwr_delay = pmz_set_scc_power(uap, 1);
856
857 /* Nice buggy HW ... */
858 pmz_fix_zero_bug_scc(uap);
859
860 /* Reset the channel */
861 uap->curregs[R9] = 0;
862 write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB);
863 zssync(uap);
864 udelay(10);
865 write_zsreg(uap, 9, 0);
866 zssync(uap);
867
868 /* Clear the interrupt registers */
869 write_zsreg(uap, R1, 0);
870 write_zsreg(uap, R0, ERR_RES);
871 write_zsreg(uap, R0, ERR_RES);
872 write_zsreg(uap, R0, RES_H_IUS);
873 write_zsreg(uap, R0, RES_H_IUS);
874
875 /* Setup some valid baud rate */
876 uap->curregs[R4] = X16CLK | SB1;
877 uap->curregs[R3] = Rx8;
878 uap->curregs[R5] = Tx8 | RTS;
879 if (!ZS_IS_IRDA(uap))
880 uap->curregs[R5] |= DTR;
881 uap->curregs[R12] = 0;
882 uap->curregs[R13] = 0;
883 uap->curregs[R14] = BRENAB;
884
885 /* Clear handshaking, enable BREAK interrupts */
886 uap->curregs[R15] = BRKIE;
887
888 /* Master interrupt enable */
889 uap->curregs[R9] |= NV | MIE;
890
891 pmz_load_zsregs(uap, uap->curregs);
892
893 /* Enable receiver and transmitter. */
894 write_zsreg(uap, R3, uap->curregs[R3] |= RxENABLE);
895 write_zsreg(uap, R5, uap->curregs[R5] |= TxENABLE);
896
897 /* Remember status for DCD/CTS changes */
898 uap->prev_status = read_zsreg(uap, R0);
899
900
901 return pwr_delay;
902 }
903
904 static void pmz_irda_reset(struct uart_pmac_port *uap)
905 {
906 uap->curregs[R5] |= DTR;
907 write_zsreg(uap, R5, uap->curregs[R5]);
908 zssync(uap);
909 mdelay(110);
910 uap->curregs[R5] &= ~DTR;
911 write_zsreg(uap, R5, uap->curregs[R5]);
912 zssync(uap);
913 mdelay(10);
914 }
915
916 /*
917 * This is the "normal" startup routine, using the above one
918 * wrapped with the lock and doing a schedule delay
919 */
920 static int pmz_startup(struct uart_port *port)
921 {
922 struct uart_pmac_port *uap = to_pmz(port);
923 unsigned long flags;
924 int pwr_delay = 0;
925
926 pmz_debug("pmz: startup()\n");
927
928 if (ZS_IS_ASLEEP(uap))
929 return -EAGAIN;
930 if (uap->node == NULL)
931 return -ENODEV;
932
933 mutex_lock(&pmz_irq_mutex);
934
935 uap->flags |= PMACZILOG_FLAG_IS_OPEN;
936
937 /* A console is never powered down. Else, power up and
938 * initialize the chip
939 */
940 if (!ZS_IS_CONS(uap)) {
941 spin_lock_irqsave(&port->lock, flags);
942 pwr_delay = __pmz_startup(uap);
943 spin_unlock_irqrestore(&port->lock, flags);
944 }
945
946 pmz_get_port_A(uap)->flags |= PMACZILOG_FLAG_IS_IRQ_ON;
947 if (request_irq(uap->port.irq, pmz_interrupt, IRQF_SHARED, "PowerMac Zilog", uap)) {
948 dev_err(&uap->dev->ofdev.dev,
949 "Unable to register zs interrupt handler.\n");
950 pmz_set_scc_power(uap, 0);
951 mutex_unlock(&pmz_irq_mutex);
952 return -ENXIO;
953 }
954
955 mutex_unlock(&pmz_irq_mutex);
956
957 /* Right now, we deal with delay by blocking here, I'll be
958 * smarter later on
959 */
960 if (pwr_delay != 0) {
961 pmz_debug("pmz: delaying %d ms\n", pwr_delay);
962 msleep(pwr_delay);
963 }
964
965 /* IrDA reset is done now */
966 if (ZS_IS_IRDA(uap))
967 pmz_irda_reset(uap);
968
969 /* Enable interrupts emission from the chip */
970 spin_lock_irqsave(&port->lock, flags);
971 uap->curregs[R1] |= INT_ALL_Rx | TxINT_ENAB;
972 if (!ZS_IS_EXTCLK(uap))
973 uap->curregs[R1] |= EXT_INT_ENAB;
974 write_zsreg(uap, R1, uap->curregs[R1]);
975 spin_unlock_irqrestore(&port->lock, flags);
976
977 pmz_debug("pmz: startup() done.\n");
978
979 return 0;
980 }
981
982 static void pmz_shutdown(struct uart_port *port)
983 {
984 struct uart_pmac_port *uap = to_pmz(port);
985 unsigned long flags;
986
987 pmz_debug("pmz: shutdown()\n");
988
989 if (uap->node == NULL)
990 return;
991
992 mutex_lock(&pmz_irq_mutex);
993
994 /* Release interrupt handler */
995 free_irq(uap->port.irq, uap);
996
997 spin_lock_irqsave(&port->lock, flags);
998
999 uap->flags &= ~PMACZILOG_FLAG_IS_OPEN;
1000
1001 if (!ZS_IS_OPEN(uap->mate))
1002 pmz_get_port_A(uap)->flags &= ~PMACZILOG_FLAG_IS_IRQ_ON;
1003
1004 /* Disable interrupts */
1005 if (!ZS_IS_ASLEEP(uap)) {
1006 uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
1007 write_zsreg(uap, R1, uap->curregs[R1]);
1008 zssync(uap);
1009 }
1010
1011 if (ZS_IS_CONS(uap) || ZS_IS_ASLEEP(uap)) {
1012 spin_unlock_irqrestore(&port->lock, flags);
1013 mutex_unlock(&pmz_irq_mutex);
1014 return;
1015 }
1016
1017 /* Disable receiver and transmitter. */
1018 uap->curregs[R3] &= ~RxENABLE;
1019 uap->curregs[R5] &= ~TxENABLE;
1020
1021 /* Disable all interrupts and BRK assertion. */
1022 uap->curregs[R5] &= ~SND_BRK;
1023 pmz_maybe_update_regs(uap);
1024
1025 /* Shut the chip down */
1026 pmz_set_scc_power(uap, 0);
1027
1028 spin_unlock_irqrestore(&port->lock, flags);
1029
1030 mutex_unlock(&pmz_irq_mutex);
1031
1032 pmz_debug("pmz: shutdown() done.\n");
1033 }
1034
1035 /* Shared by TTY driver and serial console setup. The port lock is held
1036 * and local interrupts are disabled.
1037 */
1038 static void pmz_convert_to_zs(struct uart_pmac_port *uap, unsigned int cflag,
1039 unsigned int iflag, unsigned long baud)
1040 {
1041 int brg;
1042
1043
1044 /* Switch to external clocking for IrDA high clock rates. That
1045 * code could be re-used for Midi interfaces with different
1046 * multipliers
1047 */
1048 if (baud >= 115200 && ZS_IS_IRDA(uap)) {
1049 uap->curregs[R4] = X1CLK;
1050 uap->curregs[R11] = RCTRxCP | TCTRxCP;
1051 uap->curregs[R14] = 0; /* BRG off */
1052 uap->curregs[R12] = 0;
1053 uap->curregs[R13] = 0;
1054 uap->flags |= PMACZILOG_FLAG_IS_EXTCLK;
1055 } else {
1056 switch (baud) {
1057 case ZS_CLOCK/16: /* 230400 */
1058 uap->curregs[R4] = X16CLK;
1059 uap->curregs[R11] = 0;
1060 uap->curregs[R14] = 0;
1061 break;
1062 case ZS_CLOCK/32: /* 115200 */
1063 uap->curregs[R4] = X32CLK;
1064 uap->curregs[R11] = 0;
1065 uap->curregs[R14] = 0;
1066 break;
1067 default:
1068 uap->curregs[R4] = X16CLK;
1069 uap->curregs[R11] = TCBR | RCBR;
1070 brg = BPS_TO_BRG(baud, ZS_CLOCK / 16);
1071 uap->curregs[R12] = (brg & 255);
1072 uap->curregs[R13] = ((brg >> 8) & 255);
1073 uap->curregs[R14] = BRENAB;
1074 }
1075 uap->flags &= ~PMACZILOG_FLAG_IS_EXTCLK;
1076 }
1077
1078 /* Character size, stop bits, and parity. */
1079 uap->curregs[3] &= ~RxN_MASK;
1080 uap->curregs[5] &= ~TxN_MASK;
1081
1082 switch (cflag & CSIZE) {
1083 case CS5:
1084 uap->curregs[3] |= Rx5;
1085 uap->curregs[5] |= Tx5;
1086 uap->parity_mask = 0x1f;
1087 break;
1088 case CS6:
1089 uap->curregs[3] |= Rx6;
1090 uap->curregs[5] |= Tx6;
1091 uap->parity_mask = 0x3f;
1092 break;
1093 case CS7:
1094 uap->curregs[3] |= Rx7;
1095 uap->curregs[5] |= Tx7;
1096 uap->parity_mask = 0x7f;
1097 break;
1098 case CS8:
1099 default:
1100 uap->curregs[3] |= Rx8;
1101 uap->curregs[5] |= Tx8;
1102 uap->parity_mask = 0xff;
1103 break;
1104 };
1105 uap->curregs[4] &= ~(SB_MASK);
1106 if (cflag & CSTOPB)
1107 uap->curregs[4] |= SB2;
1108 else
1109 uap->curregs[4] |= SB1;
1110 if (cflag & PARENB)
1111 uap->curregs[4] |= PAR_ENAB;
1112 else
1113 uap->curregs[4] &= ~PAR_ENAB;
1114 if (!(cflag & PARODD))
1115 uap->curregs[4] |= PAR_EVEN;
1116 else
1117 uap->curregs[4] &= ~PAR_EVEN;
1118
1119 uap->port.read_status_mask = Rx_OVR;
1120 if (iflag & INPCK)
1121 uap->port.read_status_mask |= CRC_ERR | PAR_ERR;
1122 if (iflag & (BRKINT | PARMRK))
1123 uap->port.read_status_mask |= BRK_ABRT;
1124
1125 uap->port.ignore_status_mask = 0;
1126 if (iflag & IGNPAR)
1127 uap->port.ignore_status_mask |= CRC_ERR | PAR_ERR;
1128 if (iflag & IGNBRK) {
1129 uap->port.ignore_status_mask |= BRK_ABRT;
1130 if (iflag & IGNPAR)
1131 uap->port.ignore_status_mask |= Rx_OVR;
1132 }
1133
1134 if ((cflag & CREAD) == 0)
1135 uap->port.ignore_status_mask = 0xff;
1136 }
1137
1138
1139 /*
1140 * Set the irda codec on the imac to the specified baud rate.
1141 */
1142 static void pmz_irda_setup(struct uart_pmac_port *uap, unsigned long *baud)
1143 {
1144 u8 cmdbyte;
1145 int t, version;
1146
1147 switch (*baud) {
1148 /* SIR modes */
1149 case 2400:
1150 cmdbyte = 0x53;
1151 break;
1152 case 4800:
1153 cmdbyte = 0x52;
1154 break;
1155 case 9600:
1156 cmdbyte = 0x51;
1157 break;
1158 case 19200:
1159 cmdbyte = 0x50;
1160 break;
1161 case 38400:
1162 cmdbyte = 0x4f;
1163 break;
1164 case 57600:
1165 cmdbyte = 0x4e;
1166 break;
1167 case 115200:
1168 cmdbyte = 0x4d;
1169 break;
1170 /* The FIR modes aren't really supported at this point, how
1171 * do we select the speed ? via the FCR on KeyLargo ?
1172 */
1173 case 1152000:
1174 cmdbyte = 0;
1175 break;
1176 case 4000000:
1177 cmdbyte = 0;
1178 break;
1179 default: /* 9600 */
1180 cmdbyte = 0x51;
1181 *baud = 9600;
1182 break;
1183 }
1184
1185 /* Wait for transmitter to drain */
1186 t = 10000;
1187 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0
1188 || (read_zsreg(uap, R1) & ALL_SNT) == 0) {
1189 if (--t <= 0) {
1190 dev_err(&uap->dev->ofdev.dev, "transmitter didn't drain\n");
1191 return;
1192 }
1193 udelay(10);
1194 }
1195
1196 /* Drain the receiver too */
1197 t = 100;
1198 (void)read_zsdata(uap);
1199 (void)read_zsdata(uap);
1200 (void)read_zsdata(uap);
1201 mdelay(10);
1202 while (read_zsreg(uap, R0) & Rx_CH_AV) {
1203 read_zsdata(uap);
1204 mdelay(10);
1205 if (--t <= 0) {
1206 dev_err(&uap->dev->ofdev.dev, "receiver didn't drain\n");
1207 return;
1208 }
1209 }
1210
1211 /* Switch to command mode */
1212 uap->curregs[R5] |= DTR;
1213 write_zsreg(uap, R5, uap->curregs[R5]);
1214 zssync(uap);
1215 mdelay(1);
1216
1217 /* Switch SCC to 19200 */
1218 pmz_convert_to_zs(uap, CS8, 0, 19200);
1219 pmz_load_zsregs(uap, uap->curregs);
1220 mdelay(1);
1221
1222 /* Write get_version command byte */
1223 write_zsdata(uap, 1);
1224 t = 5000;
1225 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) {
1226 if (--t <= 0) {
1227 dev_err(&uap->dev->ofdev.dev,
1228 "irda_setup timed out on get_version byte\n");
1229 goto out;
1230 }
1231 udelay(10);
1232 }
1233 version = read_zsdata(uap);
1234
1235 if (version < 4) {
1236 dev_info(&uap->dev->ofdev.dev, "IrDA: dongle version %d not supported\n",
1237 version);
1238 goto out;
1239 }
1240
1241 /* Send speed mode */
1242 write_zsdata(uap, cmdbyte);
1243 t = 5000;
1244 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) {
1245 if (--t <= 0) {
1246 dev_err(&uap->dev->ofdev.dev,
1247 "irda_setup timed out on speed mode byte\n");
1248 goto out;
1249 }
1250 udelay(10);
1251 }
1252 t = read_zsdata(uap);
1253 if (t != cmdbyte)
1254 dev_err(&uap->dev->ofdev.dev,
1255 "irda_setup speed mode byte = %x (%x)\n", t, cmdbyte);
1256
1257 dev_info(&uap->dev->ofdev.dev, "IrDA setup for %ld bps, dongle version: %d\n",
1258 *baud, version);
1259
1260 (void)read_zsdata(uap);
1261 (void)read_zsdata(uap);
1262 (void)read_zsdata(uap);
1263
1264 out:
1265 /* Switch back to data mode */
1266 uap->curregs[R5] &= ~DTR;
1267 write_zsreg(uap, R5, uap->curregs[R5]);
1268 zssync(uap);
1269
1270 (void)read_zsdata(uap);
1271 (void)read_zsdata(uap);
1272 (void)read_zsdata(uap);
1273 }
1274
1275
1276 static void __pmz_set_termios(struct uart_port *port, struct ktermios *termios,
1277 struct ktermios *old)
1278 {
1279 struct uart_pmac_port *uap = to_pmz(port);
1280 unsigned long baud;
1281
1282 pmz_debug("pmz: set_termios()\n");
1283
1284 if (ZS_IS_ASLEEP(uap))
1285 return;
1286
1287 memcpy(&uap->termios_cache, termios, sizeof(struct ktermios));
1288
1289 /* XXX Check which revs of machines actually allow 1 and 4Mb speeds
1290 * on the IR dongle. Note that the IRTTY driver currently doesn't know
1291 * about the FIR mode and high speed modes. So these are unused. For
1292 * implementing proper support for these, we should probably add some
1293 * DMA as well, at least on the Rx side, which isn't a simple thing
1294 * at this point.
1295 */
1296 if (ZS_IS_IRDA(uap)) {
1297 /* Calc baud rate */
1298 baud = uart_get_baud_rate(port, termios, old, 1200, 4000000);
1299 pmz_debug("pmz: switch IRDA to %ld bauds\n", baud);
1300 /* Cet the irda codec to the right rate */
1301 pmz_irda_setup(uap, &baud);
1302 /* Set final baud rate */
1303 pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud);
1304 pmz_load_zsregs(uap, uap->curregs);
1305 zssync(uap);
1306 } else {
1307 baud = uart_get_baud_rate(port, termios, old, 1200, 230400);
1308 pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud);
1309 /* Make sure modem status interrupts are correctly configured */
1310 if (UART_ENABLE_MS(&uap->port, termios->c_cflag)) {
1311 uap->curregs[R15] |= DCDIE | SYNCIE | CTSIE;
1312 uap->flags |= PMACZILOG_FLAG_MODEM_STATUS;
1313 } else {
1314 uap->curregs[R15] &= ~(DCDIE | SYNCIE | CTSIE);
1315 uap->flags &= ~PMACZILOG_FLAG_MODEM_STATUS;
1316 }
1317
1318 /* Load registers to the chip */
1319 pmz_maybe_update_regs(uap);
1320 }
1321 uart_update_timeout(port, termios->c_cflag, baud);
1322
1323 pmz_debug("pmz: set_termios() done.\n");
1324 }
1325
1326 /* The port lock is not held. */
1327 static void pmz_set_termios(struct uart_port *port, struct ktermios *termios,
1328 struct ktermios *old)
1329 {
1330 struct uart_pmac_port *uap = to_pmz(port);
1331 unsigned long flags;
1332
1333 spin_lock_irqsave(&port->lock, flags);
1334
1335 /* Disable IRQs on the port */
1336 uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
1337 write_zsreg(uap, R1, uap->curregs[R1]);
1338
1339 /* Setup new port configuration */
1340 __pmz_set_termios(port, termios, old);
1341
1342 /* Re-enable IRQs on the port */
1343 if (ZS_IS_OPEN(uap)) {
1344 uap->curregs[R1] |= INT_ALL_Rx | TxINT_ENAB;
1345 if (!ZS_IS_EXTCLK(uap))
1346 uap->curregs[R1] |= EXT_INT_ENAB;
1347 write_zsreg(uap, R1, uap->curregs[R1]);
1348 }
1349 spin_unlock_irqrestore(&port->lock, flags);
1350 }
1351
1352 static const char *pmz_type(struct uart_port *port)
1353 {
1354 struct uart_pmac_port *uap = to_pmz(port);
1355
1356 if (ZS_IS_IRDA(uap))
1357 return "Z85c30 ESCC - Infrared port";
1358 else if (ZS_IS_INTMODEM(uap))
1359 return "Z85c30 ESCC - Internal modem";
1360 return "Z85c30 ESCC - Serial port";
1361 }
1362
1363 /* We do not request/release mappings of the registers here, this
1364 * happens at early serial probe time.
1365 */
1366 static void pmz_release_port(struct uart_port *port)
1367 {
1368 }
1369
1370 static int pmz_request_port(struct uart_port *port)
1371 {
1372 return 0;
1373 }
1374
1375 /* These do not need to do anything interesting either. */
1376 static void pmz_config_port(struct uart_port *port, int flags)
1377 {
1378 }
1379
1380 /* We do not support letting the user mess with the divisor, IRQ, etc. */
1381 static int pmz_verify_port(struct uart_port *port, struct serial_struct *ser)
1382 {
1383 return -EINVAL;
1384 }
1385
1386 static struct uart_ops pmz_pops = {
1387 .tx_empty = pmz_tx_empty,
1388 .set_mctrl = pmz_set_mctrl,
1389 .get_mctrl = pmz_get_mctrl,
1390 .stop_tx = pmz_stop_tx,
1391 .start_tx = pmz_start_tx,
1392 .stop_rx = pmz_stop_rx,
1393 .enable_ms = pmz_enable_ms,
1394 .break_ctl = pmz_break_ctl,
1395 .startup = pmz_startup,
1396 .shutdown = pmz_shutdown,
1397 .set_termios = pmz_set_termios,
1398 .type = pmz_type,
1399 .release_port = pmz_release_port,
1400 .request_port = pmz_request_port,
1401 .config_port = pmz_config_port,
1402 .verify_port = pmz_verify_port,
1403 };
1404
1405 /*
1406 * Setup one port structure after probing, HW is down at this point,
1407 * Unlike sunzilog, we don't need to pre-init the spinlock as we don't
1408 * register our console before uart_add_one_port() is called
1409 */
1410 static int __init pmz_init_port(struct uart_pmac_port *uap)
1411 {
1412 struct device_node *np = uap->node;
1413 const char *conn;
1414 const struct slot_names_prop {
1415 int count;
1416 char name[1];
1417 } *slots;
1418 int len;
1419 struct resource r_ports, r_rxdma, r_txdma;
1420
1421 /*
1422 * Request & map chip registers
1423 */
1424 if (of_address_to_resource(np, 0, &r_ports))
1425 return -ENODEV;
1426 uap->port.mapbase = r_ports.start;
1427 uap->port.membase = ioremap(uap->port.mapbase, 0x1000);
1428
1429 uap->control_reg = uap->port.membase;
1430 uap->data_reg = uap->control_reg + 0x10;
1431
1432 /*
1433 * Request & map DBDMA registers
1434 */
1435 #ifdef HAS_DBDMA
1436 if (of_address_to_resource(np, 1, &r_txdma) == 0 &&
1437 of_address_to_resource(np, 2, &r_rxdma) == 0)
1438 uap->flags |= PMACZILOG_FLAG_HAS_DMA;
1439 #else
1440 memset(&r_txdma, 0, sizeof(struct resource));
1441 memset(&r_rxdma, 0, sizeof(struct resource));
1442 #endif
1443 if (ZS_HAS_DMA(uap)) {
1444 uap->tx_dma_regs = ioremap(r_txdma.start, 0x100);
1445 if (uap->tx_dma_regs == NULL) {
1446 uap->flags &= ~PMACZILOG_FLAG_HAS_DMA;
1447 goto no_dma;
1448 }
1449 uap->rx_dma_regs = ioremap(r_rxdma.start, 0x100);
1450 if (uap->rx_dma_regs == NULL) {
1451 iounmap(uap->tx_dma_regs);
1452 uap->tx_dma_regs = NULL;
1453 uap->flags &= ~PMACZILOG_FLAG_HAS_DMA;
1454 goto no_dma;
1455 }
1456 uap->tx_dma_irq = irq_of_parse_and_map(np, 1);
1457 uap->rx_dma_irq = irq_of_parse_and_map(np, 2);
1458 }
1459 no_dma:
1460
1461 /*
1462 * Detect port type
1463 */
1464 if (of_device_is_compatible(np, "cobalt"))
1465 uap->flags |= PMACZILOG_FLAG_IS_INTMODEM;
1466 conn = of_get_property(np, "AAPL,connector", &len);
1467 if (conn && (strcmp(conn, "infrared") == 0))
1468 uap->flags |= PMACZILOG_FLAG_IS_IRDA;
1469 uap->port_type = PMAC_SCC_ASYNC;
1470 /* 1999 Powerbook G3 has slot-names property instead */
1471 slots = of_get_property(np, "slot-names", &len);
1472 if (slots && slots->count > 0) {
1473 if (strcmp(slots->name, "IrDA") == 0)
1474 uap->flags |= PMACZILOG_FLAG_IS_IRDA;
1475 else if (strcmp(slots->name, "Modem") == 0)
1476 uap->flags |= PMACZILOG_FLAG_IS_INTMODEM;
1477 }
1478 if (ZS_IS_IRDA(uap))
1479 uap->port_type = PMAC_SCC_IRDA;
1480 if (ZS_IS_INTMODEM(uap)) {
1481 struct device_node* i2c_modem =
1482 of_find_node_by_name(NULL, "i2c-modem");
1483 if (i2c_modem) {
1484 const char* mid =
1485 of_get_property(i2c_modem, "modem-id", NULL);
1486 if (mid) switch(*mid) {
1487 case 0x04 :
1488 case 0x05 :
1489 case 0x07 :
1490 case 0x08 :
1491 case 0x0b :
1492 case 0x0c :
1493 uap->port_type = PMAC_SCC_I2S1;
1494 }
1495 printk(KERN_INFO "pmac_zilog: i2c-modem detected, id: %d\n",
1496 mid ? (*mid) : 0);
1497 of_node_put(i2c_modem);
1498 } else {
1499 printk(KERN_INFO "pmac_zilog: serial modem detected\n");
1500 }
1501 }
1502
1503 /*
1504 * Init remaining bits of "port" structure
1505 */
1506 uap->port.iotype = UPIO_MEM;
1507 uap->port.irq = irq_of_parse_and_map(np, 0);
1508 uap->port.uartclk = ZS_CLOCK;
1509 uap->port.fifosize = 1;
1510 uap->port.ops = &pmz_pops;
1511 uap->port.type = PORT_PMAC_ZILOG;
1512 uap->port.flags = 0;
1513
1514 /* Setup some valid baud rate information in the register
1515 * shadows so we don't write crap there before baud rate is
1516 * first initialized.
1517 */
1518 pmz_convert_to_zs(uap, CS8, 0, 9600);
1519
1520 return 0;
1521 }
1522
1523 /*
1524 * Get rid of a port on module removal
1525 */
1526 static void pmz_dispose_port(struct uart_pmac_port *uap)
1527 {
1528 struct device_node *np;
1529
1530 np = uap->node;
1531 iounmap(uap->rx_dma_regs);
1532 iounmap(uap->tx_dma_regs);
1533 iounmap(uap->control_reg);
1534 uap->node = NULL;
1535 of_node_put(np);
1536 memset(uap, 0, sizeof(struct uart_pmac_port));
1537 }
1538
1539 /*
1540 * Called upon match with an escc node in the devive-tree.
1541 */
1542 static int pmz_attach(struct macio_dev *mdev, const struct of_device_id *match)
1543 {
1544 int i;
1545
1546 /* Iterate the pmz_ports array to find a matching entry
1547 */
1548 for (i = 0; i < MAX_ZS_PORTS; i++)
1549 if (pmz_ports[i].node == mdev->ofdev.node) {
1550 struct uart_pmac_port *uap = &pmz_ports[i];
1551
1552 uap->dev = mdev;
1553 dev_set_drvdata(&mdev->ofdev.dev, uap);
1554 if (macio_request_resources(uap->dev, "pmac_zilog"))
1555 printk(KERN_WARNING "%s: Failed to request resource"
1556 ", port still active\n",
1557 uap->node->name);
1558 else
1559 uap->flags |= PMACZILOG_FLAG_RSRC_REQUESTED;
1560 return 0;
1561 }
1562 return -ENODEV;
1563 }
1564
1565 /*
1566 * That one should not be called, macio isn't really a hotswap device,
1567 * we don't expect one of those serial ports to go away...
1568 */
1569 static int pmz_detach(struct macio_dev *mdev)
1570 {
1571 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1572
1573 if (!uap)
1574 return -ENODEV;
1575
1576 if (uap->flags & PMACZILOG_FLAG_RSRC_REQUESTED) {
1577 macio_release_resources(uap->dev);
1578 uap->flags &= ~PMACZILOG_FLAG_RSRC_REQUESTED;
1579 }
1580 dev_set_drvdata(&mdev->ofdev.dev, NULL);
1581 uap->dev = NULL;
1582
1583 return 0;
1584 }
1585
1586
1587 static int pmz_suspend(struct macio_dev *mdev, pm_message_t pm_state)
1588 {
1589 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1590 struct uart_state *state;
1591 unsigned long flags;
1592
1593 if (uap == NULL) {
1594 printk("HRM... pmz_suspend with NULL uap\n");
1595 return 0;
1596 }
1597
1598 if (pm_state.event == mdev->ofdev.dev.power.power_state.event)
1599 return 0;
1600
1601 pmz_debug("suspend, switching to state %d\n", pm_state.event);
1602
1603 state = pmz_uart_reg.state + uap->port.line;
1604
1605 mutex_lock(&pmz_irq_mutex);
1606 mutex_lock(&state->mutex);
1607
1608 spin_lock_irqsave(&uap->port.lock, flags);
1609
1610 if (ZS_IS_OPEN(uap) || ZS_IS_CONS(uap)) {
1611 /* Disable receiver and transmitter. */
1612 uap->curregs[R3] &= ~RxENABLE;
1613 uap->curregs[R5] &= ~TxENABLE;
1614
1615 /* Disable all interrupts and BRK assertion. */
1616 uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
1617 uap->curregs[R5] &= ~SND_BRK;
1618 pmz_load_zsregs(uap, uap->curregs);
1619 uap->flags |= PMACZILOG_FLAG_IS_ASLEEP;
1620 mb();
1621 }
1622
1623 spin_unlock_irqrestore(&uap->port.lock, flags);
1624
1625 if (ZS_IS_OPEN(uap) || ZS_IS_OPEN(uap->mate))
1626 if (ZS_IS_ASLEEP(uap->mate) && ZS_IS_IRQ_ON(pmz_get_port_A(uap))) {
1627 pmz_get_port_A(uap)->flags &= ~PMACZILOG_FLAG_IS_IRQ_ON;
1628 disable_irq(uap->port.irq);
1629 }
1630
1631 if (ZS_IS_CONS(uap))
1632 uap->port.cons->flags &= ~CON_ENABLED;
1633
1634 /* Shut the chip down */
1635 pmz_set_scc_power(uap, 0);
1636
1637 mutex_unlock(&state->mutex);
1638 mutex_unlock(&pmz_irq_mutex);
1639
1640 pmz_debug("suspend, switching complete\n");
1641
1642 mdev->ofdev.dev.power.power_state = pm_state;
1643
1644 return 0;
1645 }
1646
1647
1648 static int pmz_resume(struct macio_dev *mdev)
1649 {
1650 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1651 struct uart_state *state;
1652 unsigned long flags;
1653 int pwr_delay = 0;
1654
1655 if (uap == NULL)
1656 return 0;
1657
1658 if (mdev->ofdev.dev.power.power_state.event == PM_EVENT_ON)
1659 return 0;
1660
1661 pmz_debug("resume, switching to state 0\n");
1662
1663 state = pmz_uart_reg.state + uap->port.line;
1664
1665 mutex_lock(&pmz_irq_mutex);
1666 mutex_lock(&state->mutex);
1667
1668 spin_lock_irqsave(&uap->port.lock, flags);
1669 if (!ZS_IS_OPEN(uap) && !ZS_IS_CONS(uap)) {
1670 spin_unlock_irqrestore(&uap->port.lock, flags);
1671 goto bail;
1672 }
1673 pwr_delay = __pmz_startup(uap);
1674
1675 /* Take care of config that may have changed while asleep */
1676 __pmz_set_termios(&uap->port, &uap->termios_cache, NULL);
1677
1678 if (ZS_IS_OPEN(uap)) {
1679 /* Enable interrupts */
1680 uap->curregs[R1] |= INT_ALL_Rx | TxINT_ENAB;
1681 if (!ZS_IS_EXTCLK(uap))
1682 uap->curregs[R1] |= EXT_INT_ENAB;
1683 write_zsreg(uap, R1, uap->curregs[R1]);
1684 }
1685
1686 spin_unlock_irqrestore(&uap->port.lock, flags);
1687
1688 if (ZS_IS_CONS(uap))
1689 uap->port.cons->flags |= CON_ENABLED;
1690
1691 /* Re-enable IRQ on the controller */
1692 if (ZS_IS_OPEN(uap) && !ZS_IS_IRQ_ON(pmz_get_port_A(uap))) {
1693 pmz_get_port_A(uap)->flags |= PMACZILOG_FLAG_IS_IRQ_ON;
1694 enable_irq(uap->port.irq);
1695 }
1696
1697 bail:
1698 mutex_unlock(&state->mutex);
1699 mutex_unlock(&pmz_irq_mutex);
1700
1701 /* Right now, we deal with delay by blocking here, I'll be
1702 * smarter later on
1703 */
1704 if (pwr_delay != 0) {
1705 pmz_debug("pmz: delaying %d ms\n", pwr_delay);
1706 msleep(pwr_delay);
1707 }
1708
1709 pmz_debug("resume, switching complete\n");
1710
1711 mdev->ofdev.dev.power.power_state.event = PM_EVENT_ON;
1712
1713 return 0;
1714 }
1715
1716 /*
1717 * Probe all ports in the system and build the ports array, we register
1718 * with the serial layer at this point, the macio-type probing is only
1719 * used later to "attach" to the sysfs tree so we get power management
1720 * events
1721 */
1722 static int __init pmz_probe(void)
1723 {
1724 struct device_node *node_p, *node_a, *node_b, *np;
1725 int count = 0;
1726 int rc;
1727
1728 /*
1729 * Find all escc chips in the system
1730 */
1731 node_p = of_find_node_by_name(NULL, "escc");
1732 while (node_p) {
1733 /*
1734 * First get channel A/B node pointers
1735 *
1736 * TODO: Add routines with proper locking to do that...
1737 */
1738 node_a = node_b = NULL;
1739 for (np = NULL; (np = of_get_next_child(node_p, np)) != NULL;) {
1740 if (strncmp(np->name, "ch-a", 4) == 0)
1741 node_a = of_node_get(np);
1742 else if (strncmp(np->name, "ch-b", 4) == 0)
1743 node_b = of_node_get(np);
1744 }
1745 if (!node_a && !node_b) {
1746 of_node_put(node_a);
1747 of_node_put(node_b);
1748 printk(KERN_ERR "pmac_zilog: missing node %c for escc %s\n",
1749 (!node_a) ? 'a' : 'b', node_p->full_name);
1750 goto next;
1751 }
1752
1753 /*
1754 * Fill basic fields in the port structures
1755 */
1756 pmz_ports[count].mate = &pmz_ports[count+1];
1757 pmz_ports[count+1].mate = &pmz_ports[count];
1758 pmz_ports[count].flags = PMACZILOG_FLAG_IS_CHANNEL_A;
1759 pmz_ports[count].node = node_a;
1760 pmz_ports[count+1].node = node_b;
1761 pmz_ports[count].port.line = count;
1762 pmz_ports[count+1].port.line = count+1;
1763
1764 /*
1765 * Setup the ports for real
1766 */
1767 rc = pmz_init_port(&pmz_ports[count]);
1768 if (rc == 0 && node_b != NULL)
1769 rc = pmz_init_port(&pmz_ports[count+1]);
1770 if (rc != 0) {
1771 of_node_put(node_a);
1772 of_node_put(node_b);
1773 memset(&pmz_ports[count], 0, sizeof(struct uart_pmac_port));
1774 memset(&pmz_ports[count+1], 0, sizeof(struct uart_pmac_port));
1775 goto next;
1776 }
1777 count += 2;
1778 next:
1779 node_p = of_find_node_by_name(node_p, "escc");
1780 }
1781 pmz_ports_count = count;
1782
1783 return 0;
1784 }
1785
1786 #ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE
1787
1788 static void pmz_console_write(struct console *con, const char *s, unsigned int count);
1789 static int __init pmz_console_setup(struct console *co, char *options);
1790
1791 static struct console pmz_console = {
1792 .name = PMACZILOG_NAME,
1793 .write = pmz_console_write,
1794 .device = uart_console_device,
1795 .setup = pmz_console_setup,
1796 .flags = CON_PRINTBUFFER,
1797 .index = -1,
1798 .data = &pmz_uart_reg,
1799 };
1800
1801 #define PMACZILOG_CONSOLE &pmz_console
1802 #else /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
1803 #define PMACZILOG_CONSOLE (NULL)
1804 #endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
1805
1806 /*
1807 * Register the driver, console driver and ports with the serial
1808 * core
1809 */
1810 static int __init pmz_register(void)
1811 {
1812 int i, rc;
1813
1814 pmz_uart_reg.nr = pmz_ports_count;
1815 pmz_uart_reg.cons = PMACZILOG_CONSOLE;
1816
1817 /*
1818 * Register this driver with the serial core
1819 */
1820 rc = uart_register_driver(&pmz_uart_reg);
1821 if (rc)
1822 return rc;
1823
1824 /*
1825 * Register each port with the serial core
1826 */
1827 for (i = 0; i < pmz_ports_count; i++) {
1828 struct uart_pmac_port *uport = &pmz_ports[i];
1829 /* NULL node may happen on wallstreet */
1830 if (uport->node != NULL)
1831 rc = uart_add_one_port(&pmz_uart_reg, &uport->port);
1832 if (rc)
1833 goto err_out;
1834 }
1835
1836 return 0;
1837 err_out:
1838 while (i-- > 0) {
1839 struct uart_pmac_port *uport = &pmz_ports[i];
1840 uart_remove_one_port(&pmz_uart_reg, &uport->port);
1841 }
1842 uart_unregister_driver(&pmz_uart_reg);
1843 return rc;
1844 }
1845
1846 static struct of_device_id pmz_match[] =
1847 {
1848 {
1849 .name = "ch-a",
1850 },
1851 {
1852 .name = "ch-b",
1853 },
1854 {},
1855 };
1856 MODULE_DEVICE_TABLE (of, pmz_match);
1857
1858 static struct macio_driver pmz_driver =
1859 {
1860 .name = "pmac_zilog",
1861 .match_table = pmz_match,
1862 .probe = pmz_attach,
1863 .remove = pmz_detach,
1864 .suspend = pmz_suspend,
1865 .resume = pmz_resume,
1866 };
1867
1868 static int __init init_pmz(void)
1869 {
1870 int rc, i;
1871 printk(KERN_INFO "%s\n", version);
1872
1873 /*
1874 * First, we need to do a direct OF-based probe pass. We
1875 * do that because we want serial console up before the
1876 * macio stuffs calls us back, and since that makes it
1877 * easier to pass the proper number of channels to
1878 * uart_register_driver()
1879 */
1880 if (pmz_ports_count == 0)
1881 pmz_probe();
1882
1883 /*
1884 * Bail early if no port found
1885 */
1886 if (pmz_ports_count == 0)
1887 return -ENODEV;
1888
1889 /*
1890 * Now we register with the serial layer
1891 */
1892 rc = pmz_register();
1893 if (rc) {
1894 printk(KERN_ERR
1895 "pmac_zilog: Error registering serial device, disabling pmac_zilog.\n"
1896 "pmac_zilog: Did another serial driver already claim the minors?\n");
1897 /* effectively "pmz_unprobe()" */
1898 for (i=0; i < pmz_ports_count; i++)
1899 pmz_dispose_port(&pmz_ports[i]);
1900 return rc;
1901 }
1902
1903 /*
1904 * Then we register the macio driver itself
1905 */
1906 return macio_register_driver(&pmz_driver);
1907 }
1908
1909 static void __exit exit_pmz(void)
1910 {
1911 int i;
1912
1913 /* Get rid of macio-driver (detach from macio) */
1914 macio_unregister_driver(&pmz_driver);
1915
1916 for (i = 0; i < pmz_ports_count; i++) {
1917 struct uart_pmac_port *uport = &pmz_ports[i];
1918 if (uport->node != NULL) {
1919 uart_remove_one_port(&pmz_uart_reg, &uport->port);
1920 pmz_dispose_port(uport);
1921 }
1922 }
1923 /* Unregister UART driver */
1924 uart_unregister_driver(&pmz_uart_reg);
1925 }
1926
1927 #ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE
1928
1929 static void pmz_console_putchar(struct uart_port *port, int ch)
1930 {
1931 struct uart_pmac_port *uap = (struct uart_pmac_port *)port;
1932
1933 /* Wait for the transmit buffer to empty. */
1934 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0)
1935 udelay(5);
1936 write_zsdata(uap, ch);
1937 }
1938
1939 /*
1940 * Print a string to the serial port trying not to disturb
1941 * any possible real use of the port...
1942 */
1943 static void pmz_console_write(struct console *con, const char *s, unsigned int count)
1944 {
1945 struct uart_pmac_port *uap = &pmz_ports[con->index];
1946 unsigned long flags;
1947
1948 if (ZS_IS_ASLEEP(uap))
1949 return;
1950 spin_lock_irqsave(&uap->port.lock, flags);
1951
1952 /* Turn of interrupts and enable the transmitter. */
1953 write_zsreg(uap, R1, uap->curregs[1] & ~TxINT_ENAB);
1954 write_zsreg(uap, R5, uap->curregs[5] | TxENABLE | RTS | DTR);
1955
1956 uart_console_write(&uap->port, s, count, pmz_console_putchar);
1957
1958 /* Restore the values in the registers. */
1959 write_zsreg(uap, R1, uap->curregs[1]);
1960 /* Don't disable the transmitter. */
1961
1962 spin_unlock_irqrestore(&uap->port.lock, flags);
1963 }
1964
1965 /*
1966 * Setup the serial console
1967 */
1968 static int __init pmz_console_setup(struct console *co, char *options)
1969 {
1970 struct uart_pmac_port *uap;
1971 struct uart_port *port;
1972 int baud = 38400;
1973 int bits = 8;
1974 int parity = 'n';
1975 int flow = 'n';
1976 unsigned long pwr_delay;
1977
1978 /*
1979 * XServe's default to 57600 bps
1980 */
1981 if (machine_is_compatible("RackMac1,1")
1982 || machine_is_compatible("RackMac1,2")
1983 || machine_is_compatible("MacRISC4"))
1984 baud = 57600;
1985
1986 /*
1987 * Check whether an invalid uart number has been specified, and
1988 * if so, search for the first available port that does have
1989 * console support.
1990 */
1991 if (co->index >= pmz_ports_count)
1992 co->index = 0;
1993 uap = &pmz_ports[co->index];
1994 if (uap->node == NULL)
1995 return -ENODEV;
1996 port = &uap->port;
1997
1998 /*
1999 * Mark port as beeing a console
2000 */
2001 uap->flags |= PMACZILOG_FLAG_IS_CONS;
2002
2003 /*
2004 * Temporary fix for uart layer who didn't setup the spinlock yet
2005 */
2006 spin_lock_init(&port->lock);
2007
2008 /*
2009 * Enable the hardware
2010 */
2011 pwr_delay = __pmz_startup(uap);
2012 if (pwr_delay)
2013 mdelay(pwr_delay);
2014
2015 if (options)
2016 uart_parse_options(options, &baud, &parity, &bits, &flow);
2017
2018 return uart_set_options(port, co, baud, parity, bits, flow);
2019 }
2020
2021 static int __init pmz_console_init(void)
2022 {
2023 /* Probe ports */
2024 pmz_probe();
2025
2026 /* TODO: Autoprobe console based on OF */
2027 /* pmz_console.index = i; */
2028 register_console(&pmz_console);
2029
2030 return 0;
2031
2032 }
2033 console_initcall(pmz_console_init);
2034 #endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
2035
2036 module_init(init_pmz);
2037 module_exit(exit_pmz);
WRT350N Kernel Patches