drivers/serial/sh-sci.h

   1 /* $Id: sh-sci.h,v 1.4 2004/02/19 16:43:56 lethal Exp $
   2  *
   3  *  linux/drivers/serial/sh-sci.h
   4  *
   5  *  SuperH on-chip serial module support.  (SCI with no FIFO / with FIFO)
   6  *  Copyright (C) 1999, 2000  Niibe Yutaka
   7  *  Copyright (C) 2000  Greg Banks
   8  *  Copyright (C) 2002, 2003  Paul Mundt
   9  *  Modified to support multiple serial ports. Stuart Menefy (May 2000).
  10  *  Modified to support SH7300(SH-Mobile) SCIF. Takashi Kusuda (Jun 2003).
  11  *  Modified to support H8/300 Series Yoshinori Sato (Feb 2004).
  12  *  Removed SH7300 support (Jul 2007).
  13  *  Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Aug 2007).
  14  */
  15 #include <linux/serial_core.h>
  16 #include <asm/io.h>
  17
  18 #include <asm/gpio.h>
  19
  20 #if defined(CONFIG_H83007) || defined(CONFIG_H83068)
  21 #include <asm/regs306x.h>
  22 #endif
  23 #if defined(CONFIG_H8S2678)
  24 #include <asm/regs267x.h>
  25 #endif
  26
  27 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
  28     defined(CONFIG_CPU_SUBTYPE_SH7707) || \
  29     defined(CONFIG_CPU_SUBTYPE_SH7708) || \
  30     defined(CONFIG_CPU_SUBTYPE_SH7709)
  31 # define SCPCR  0xA4000116 /* 16 bit SCI and SCIF */
  32 # define SCPDR  0xA4000136 /* 8  bit SCI and SCIF */
  33 # define SCSCR_INIT(port)          0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
  34 # define SCI_AND_SCIF
  35 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
  36 # define SCIF0          0xA4400000
  37 # define SCIF2          0xA4410000
  38 # define SCSMR_Ir       0xA44A0000
  39 # define IRDA_SCIF      SCIF0
  40 # define SCPCR 0xA4000116
  41 # define SCPDR 0xA4000136
  42
  43 /* Set the clock source,
  44  * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input
  45  * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
  46  */
  47 # define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
  48 # define SCIF_ONLY
  49 #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
  50       defined(CONFIG_CPU_SUBTYPE_SH7721)
  51 # define SCSCR_INIT(port)  0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
  52 # define SCIF_ONLY
  53 #define SCIF_ORER    0x0200   /* overrun error bit */
  54 #elif defined(CONFIG_SH_RTS7751R2D)
  55 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
  56 # define SCIF_ORER 0x0001   /* overrun error bit */
  57 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
  58 # define SCIF_ONLY
  59 #elif defined(CONFIG_CPU_SUBTYPE_SH7750)  || \
  60       defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
  61       defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
  62       defined(CONFIG_CPU_SUBTYPE_SH7091)  || \
  63       defined(CONFIG_CPU_SUBTYPE_SH7751)  || \
  64       defined(CONFIG_CPU_SUBTYPE_SH7751R)
  65 # define SCSPTR1 0xffe0001c /* 8  bit SCI */
  66 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
  67 # define SCIF_ORER 0x0001   /* overrun error bit */
  68 # define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
  69         0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
  70         0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ )
  71 # define SCI_AND_SCIF
  72 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
  73 # define SCSPTR0 0xfe600024 /* 16 bit SCIF */
  74 # define SCSPTR1 0xfe610024 /* 16 bit SCIF */
  75 # define SCSPTR2 0xfe620024 /* 16 bit SCIF */
  76 # define SCIF_ORER 0x0001  /* overrun error bit */
  77 # define SCSCR_INIT(port)          0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
  78 # define SCIF_ONLY
  79 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
  80 # define SCSPTR0 0xA4400000       /* 16 bit SCIF */
  81 # define SCIF_ORER 0x0001   /* overrun error bit */
  82 # define PACR 0xa4050100
  83 # define PBCR 0xa4050102
  84 # define SCSCR_INIT(port)          0x3B
  85 # define SCIF_ONLY
  86 #elif defined(CONFIG_CPU_SUBTYPE_SH7343)
  87 # define SCSPTR0 0xffe00010     /* 16 bit SCIF */
  88 # define SCSPTR1 0xffe10010     /* 16 bit SCIF */
  89 # define SCSPTR2 0xffe20010     /* 16 bit SCIF */
  90 # define SCSPTR3 0xffe30010     /* 16 bit SCIF */
  91 # define SCSCR_INIT(port) 0x32  /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */
  92 # define SCIF_ONLY
  93 #elif defined(CONFIG_CPU_SUBTYPE_SH7722)
  94 # define SCPDR0                 0xA405013E      /* 16 bit SCIF0 PSDR */
  95 # define SCSPTR0                SCPDR0
  96 # define SCIF_ORER              0x0001  /* overrun error bit */
  97 # define SCSCR_INIT(port)       0x0038  /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
  98 # define SCIF_ONLY
  99 # define PORT_PSCR              0xA405011E
 100 #elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
 101 # define SCSPTR2 0xffe80020 /* 16 bit SCIF */
 102 # define SCIF_ORER 0x0001   /* overrun error bit */
 103 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 104 # define SCIF_ONLY
 105 #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
 106 # include <asm/hardware.h>
 107 # define SCIF_BASE_ADDR    0x01030000
 108 # define SCIF_ADDR_SH5     PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR
 109 # define SCIF_PTR2_OFFS    0x0000020
 110 # define SCIF_LSR2_OFFS    0x0000024
 111 # define SCSPTR2           ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
 112 # define SCLSR2            ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
 113 # define SCSCR_INIT(port)  0x38         /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */
 114 # define SCIF_ONLY
 115 #elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
 116 # define SCSCR_INIT(port)          0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
 117 # define SCI_ONLY
 118 # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
 119 #elif defined(CONFIG_H8S2678)
 120 # define SCSCR_INIT(port)          0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
 121 # define SCI_ONLY
 122 # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
 123 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
 124 # define SCSPTR0 0xffe00024 /* 16 bit SCIF */
 125 # define SCSPTR1 0xffe08024 /* 16 bit SCIF */
 126 # define SCIF_ORER 0x0001  /* overrun error bit */
 127 # define SCSCR_INIT(port)       0x3a    /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 128 # define SCIF_ONLY
 129 #elif defined(CONFIG_CPU_SUBTYPE_SH7770)
 130 # define SCSPTR0 0xff923020 /* 16 bit SCIF */
 131 # define SCSPTR1 0xff924020 /* 16 bit SCIF */
 132 # define SCSPTR2 0xff925020 /* 16 bit SCIF */
 133 # define SCIF_ORER 0x0001  /* overrun error bit */
 134 # define SCSCR_INIT(port)       0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */
 135 # define SCIF_ONLY
 136 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
 137 # define SCSPTR0        0xffe00024      /* 16 bit SCIF */
 138 # define SCSPTR1        0xffe10024      /* 16 bit SCIF */
 139 # define SCIF_ORER      0x0001          /* Overrun error bit */
 140 # define SCSCR_INIT(port)       0x3a    /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 141 # define SCIF_ONLY
 142 #elif defined(CONFIG_CPU_SUBTYPE_SH7785)
 143 # define SCSPTR0        0xffea0024      /* 16 bit SCIF */
 144 # define SCSPTR1        0xffeb0024      /* 16 bit SCIF */
 145 # define SCSPTR2        0xffec0024      /* 16 bit SCIF */
 146 # define SCSPTR3        0xffed0024      /* 16 bit SCIF */
 147 # define SCSPTR4        0xffee0024      /* 16 bit SCIF */
 148 # define SCSPTR5        0xffef0024      /* 16 bit SCIF */
 149 # define SCIF_OPER      0x0001          /* Overrun error bit */
 150 # define SCSCR_INIT(port)       0x3a    /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 151 # define SCIF_ONLY
 152 #elif defined(CONFIG_CPU_SUBTYPE_SH7203) || \
 153       defined(CONFIG_CPU_SUBTYPE_SH7206) || \
 154       defined(CONFIG_CPU_SUBTYPE_SH7263)
 155 # define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
 156 # define SCSPTR1 0xfffe8820 /* 16 bit SCIF */
 157 # define SCSPTR2 0xfffe9020 /* 16 bit SCIF */
 158 # define SCSPTR3 0xfffe9820 /* 16 bit SCIF */
 159 # define SCSCR_INIT(port)       0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 160 # define SCIF_ONLY
 161 #elif defined(CONFIG_CPU_SUBTYPE_SH7619)
 162 # define SCSPTR0 0xf8400020 /* 16 bit SCIF */
 163 # define SCSPTR1 0xf8410020 /* 16 bit SCIF */
 164 # define SCSPTR2 0xf8420020 /* 16 bit SCIF */
 165 # define SCIF_ORER 0x0001  /* overrun error bit */
 166 # define SCSCR_INIT(port)       0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 167 # define SCIF_ONLY
 168 #elif defined(CONFIG_CPU_SUBTYPE_SHX3)
 169 # define SCSPTR0 0xffc30020             /* 16 bit SCIF */
 170 # define SCSPTR1 0xffc40020             /* 16 bit SCIF */
 171 # define SCSPTR2 0xffc50020             /* 16 bit SCIF */
 172 # define SCSPTR3 0xffc60020             /* 16 bit SCIF */
 173 # define SCIF_ORER 0x0001               /* Overrun error bit */
 174 # define SCSCR_INIT(port)       0x38    /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 175 # define SCIF_ONLY
 176 #else
 177 # error CPU subtype not defined
 178 #endif
 179
 180 /* SCSCR */
 181 #define SCI_CTRL_FLAGS_TIE  0x80 /* all */
 182 #define SCI_CTRL_FLAGS_RIE  0x40 /* all */
 183 #define SCI_CTRL_FLAGS_TE   0x20 /* all */
 184 #define SCI_CTRL_FLAGS_RE   0x10 /* all */
 185 #if defined(CONFIG_CPU_SUBTYPE_SH7750)  || \
 186     defined(CONFIG_CPU_SUBTYPE_SH7091)  || \
 187     defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
 188     defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
 189     defined(CONFIG_CPU_SUBTYPE_SH7751)  || \
 190     defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
 191     defined(CONFIG_CPU_SUBTYPE_SH7780)  || \
 192     defined(CONFIG_CPU_SUBTYPE_SH7785)  || \
 193     defined(CONFIG_CPU_SUBTYPE_SHX3)
 194 #define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
 195 #else
 196 #define SCI_CTRL_FLAGS_REIE 0
 197 #endif
 198 /*      SCI_CTRL_FLAGS_MPIE 0x08  * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 199 /*      SCI_CTRL_FLAGS_TEIE 0x04  * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 200 /*      SCI_CTRL_FLAGS_CKE1 0x02  * all */
 201 /*      SCI_CTRL_FLAGS_CKE0 0x01  * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */
 202
 203 /* SCxSR SCI */
 204 #define SCI_TDRE  0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 205 #define SCI_RDRF  0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 206 #define SCI_ORER  0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 207 #define SCI_FER   0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 208 #define SCI_PER   0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 209 #define SCI_TEND  0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 210 /*      SCI_MPB   0x02  * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 211 /*      SCI_MPBT  0x01  * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 212
 213 #define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER)
 214
 215 /* SCxSR SCIF */
 216 #define SCIF_ER    0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 217 #define SCIF_TEND  0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 218 #define SCIF_TDFE  0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 219 #define SCIF_BRK   0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 220 #define SCIF_FER   0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 221 #define SCIF_PER   0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 222 #define SCIF_RDF   0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 223 #define SCIF_DR    0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 224
 225 #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
 226     defined(CONFIG_CPU_SUBTYPE_SH7720) || \
 227     defined(CONFIG_CPU_SUBTYPE_SH7721)
 228 #define SCIF_ORER    0x0200
 229 #define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
 230 #define SCIF_RFDC_MASK 0x007f
 231 #define SCIF_TXROOM_MAX 64
 232 #else
 233 #define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
 234 #define SCIF_RFDC_MASK 0x001f
 235 #define SCIF_TXROOM_MAX 16
 236 #endif
 237
 238 #if defined(SCI_ONLY)
 239 # define SCxSR_TEND(port)               SCI_TEND
 240 # define SCxSR_ERRORS(port)             SCI_ERRORS
 241 # define SCxSR_RDxF(port)               SCI_RDRF
 242 # define SCxSR_TDxE(port)               SCI_TDRE
 243 # define SCxSR_ORER(port)               SCI_ORER
 244 # define SCxSR_FER(port)                SCI_FER
 245 # define SCxSR_PER(port)                SCI_PER
 246 # define SCxSR_BRK(port)                0x00
 247 # define SCxSR_RDxF_CLEAR(port)         0xbc
 248 # define SCxSR_ERROR_CLEAR(port)        0xc4
 249 # define SCxSR_TDxE_CLEAR(port)         0x78
 250 # define SCxSR_BREAK_CLEAR(port)        0xc4
 251 #elif defined(SCIF_ONLY)
 252 # define SCxSR_TEND(port)               SCIF_TEND
 253 # define SCxSR_ERRORS(port)             SCIF_ERRORS
 254 # define SCxSR_RDxF(port)               SCIF_RDF
 255 # define SCxSR_TDxE(port)               SCIF_TDFE
 256 #if defined(CONFIG_CPU_SUBTYPE_SH7705)
 257 # define SCxSR_ORER(port)               SCIF_ORER
 258 #else
 259 # define SCxSR_ORER(port)               0x0000
 260 #endif
 261 # define SCxSR_FER(port)                SCIF_FER
 262 # define SCxSR_PER(port)                SCIF_PER
 263 # define SCxSR_BRK(port)                SCIF_BRK
 264 #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
 265     defined(CONFIG_CPU_SUBTYPE_SH7720) || \
 266     defined(CONFIG_CPU_SUBTYPE_SH7721)
 267 # define SCxSR_RDxF_CLEAR(port)         (sci_in(port,SCxSR)&0xfffc)
 268 # define SCxSR_ERROR_CLEAR(port)        (sci_in(port,SCxSR)&0xfd73)
 269 # define SCxSR_TDxE_CLEAR(port)         (sci_in(port,SCxSR)&0xffdf)
 270 # define SCxSR_BREAK_CLEAR(port)        (sci_in(port,SCxSR)&0xffe3)
 271 #else
 272 /* SH7705 can also use this, clearing is same between 7705 and 7709 */
 273 # define SCxSR_RDxF_CLEAR(port)         0x00fc
 274 # define SCxSR_ERROR_CLEAR(port)        0x0073
 275 # define SCxSR_TDxE_CLEAR(port)         0x00df
 276 # define SCxSR_BREAK_CLEAR(port)        0x00e3
 277 #endif
 278 #else
 279 # define SCxSR_TEND(port)        (((port)->type == PORT_SCI) ? SCI_TEND   : SCIF_TEND)
 280 # define SCxSR_ERRORS(port)      (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
 281 # define SCxSR_RDxF(port)        (((port)->type == PORT_SCI) ? SCI_RDRF   : SCIF_RDF)
 282 # define SCxSR_TDxE(port)        (((port)->type == PORT_SCI) ? SCI_TDRE   : SCIF_TDFE)
 283 # define SCxSR_ORER(port)        (((port)->type == PORT_SCI) ? SCI_ORER   : 0x0000)
 284 # define SCxSR_FER(port)         (((port)->type == PORT_SCI) ? SCI_FER    : SCIF_FER)
 285 # define SCxSR_PER(port)         (((port)->type == PORT_SCI) ? SCI_PER    : SCIF_PER)
 286 # define SCxSR_BRK(port)         (((port)->type == PORT_SCI) ? 0x00       : SCIF_BRK)
 287 # define SCxSR_RDxF_CLEAR(port)  (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
 288 # define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
 289 # define SCxSR_TDxE_CLEAR(port)  (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
 290 # define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3)
 291 #endif
 292
 293 /* SCFCR */
 294 #define SCFCR_RFRST 0x0002
 295 #define SCFCR_TFRST 0x0004
 296 #define SCFCR_TCRST 0x4000
 297 #define SCFCR_MCE   0x0008
 298
 299 #define SCI_MAJOR               204
 300 #define SCI_MINOR_START         8
 301
 302 /* Generic serial flags */
 303 #define SCI_RX_THROTTLE         0x0000001
 304
 305 #define SCI_MAGIC 0xbabeface
 306
 307 /*
 308  * Events are used to schedule things to happen at timer-interrupt
 309  * time, instead of at rs interrupt time.
 310  */
 311 #define SCI_EVENT_WRITE_WAKEUP  0
 312
 313 #define SCI_IN(size, offset)                                    \
 314   unsigned int addr = port->mapbase + (offset);                 \
 315   if ((size) == 8) {                                            \
 316     return ctrl_inb(addr);                                      \
 317   } else {                                                      \
 318     return ctrl_inw(addr);                                      \
 319   }
 320 #define SCI_OUT(size, offset, value)                            \
 321   unsigned int addr = port->mapbase + (offset);                 \
 322   if ((size) == 8) {                                            \
 323     ctrl_outb(value, addr);                                     \
 324   } else {                                                      \
 325     ctrl_outw(value, addr);                                     \
 326   }
 327
 328 #define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
 329   static inline unsigned int sci_##name##_in(struct uart_port *port)    \
 330   {                                                                     \
 331     if (port->type == PORT_SCI) {                                       \
 332       SCI_IN(sci_size, sci_offset)                                      \
 333     } else {                                                            \
 334       SCI_IN(scif_size, scif_offset);                                   \
 335     }                                                                   \
 336   }                                                                     \
 337   static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
 338   {                                                                     \
 339     if (port->type == PORT_SCI) {                                       \
 340       SCI_OUT(sci_size, sci_offset, value)                              \
 341     } else {                                                            \
 342       SCI_OUT(scif_size, scif_offset, value);                           \
 343     }                                                                   \
 344   }
 345
 346 #define CPU_SCIF_FNS(name, scif_offset, scif_size)                              \
 347   static inline unsigned int sci_##name##_in(struct uart_port *port)    \
 348   {                                                                     \
 349     SCI_IN(scif_size, scif_offset);                                     \
 350   }                                                                     \
 351   static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
 352   {                                                                     \
 353     SCI_OUT(scif_size, scif_offset, value);                             \
 354   }
 355
 356 #define CPU_SCI_FNS(name, sci_offset, sci_size)                         \
 357   static inline unsigned int sci_##name##_in(struct uart_port* port)    \
 358   {                                                                     \
 359     SCI_IN(sci_size, sci_offset);                                       \
 360   }                                                                     \
 361   static inline void sci_##name##_out(struct uart_port* port, unsigned int value) \
 362   {                                                                     \
 363     SCI_OUT(sci_size, sci_offset, value);                               \
 364   }
 365
 366 #ifdef CONFIG_CPU_SH3
 367 #if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
 368 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
 369                                 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
 370                                  h8_sci_offset, h8_sci_size) \
 371   CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
 372 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
 373           CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
 374 #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
 375       defined(CONFIG_CPU_SUBTYPE_SH7720) || \
 376       defined(CONFIG_CPU_SUBTYPE_SH7721)
 377 #define SCIF_FNS(name, scif_offset, scif_size) \
 378   CPU_SCIF_FNS(name, scif_offset, scif_size)
 379 #else
 380 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
 381                  sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
 382                  h8_sci_offset, h8_sci_size) \
 383   CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh3_scif_offset, sh3_scif_size)
 384 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
 385   CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
 386 #endif
 387 #elif defined(__H8300H__) || defined(__H8300S__)
 388 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
 389                  sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
 390                  h8_sci_offset, h8_sci_size) \
 391   CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
 392 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size)
 393 #else
 394 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
 395                  sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
 396                  h8_sci_offset, h8_sci_size) \
 397   CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
 398 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
 399   CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
 400 #endif
 401
 402 #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
 403     defined(CONFIG_CPU_SUBTYPE_SH7720) || \
 404     defined(CONFIG_CPU_SUBTYPE_SH7721)
 405
 406 SCIF_FNS(SCSMR,  0x00, 16)
 407 SCIF_FNS(SCBRR,  0x04,  8)
 408 SCIF_FNS(SCSCR,  0x08, 16)
 409 SCIF_FNS(SCTDSR, 0x0c,  8)
 410 SCIF_FNS(SCFER,  0x10, 16)
 411 SCIF_FNS(SCxSR,  0x14, 16)
 412 SCIF_FNS(SCFCR,  0x18, 16)
 413 SCIF_FNS(SCFDR,  0x1c, 16)
 414 SCIF_FNS(SCxTDR, 0x20,  8)
 415 SCIF_FNS(SCxRDR, 0x24,  8)
 416 SCIF_FNS(SCLSR,  0x24, 16)
 417 #else
 418 /*      reg      SCI/SH3   SCI/SH4  SCIF/SH3   SCIF/SH4  SCI/H8*/
 419 /*      name     off  sz   off  sz   off  sz   off  sz   off  sz*/
 420 SCIx_FNS(SCSMR,  0x00,  8, 0x00,  8, 0x00,  8, 0x00, 16, 0x00,  8)
 421 SCIx_FNS(SCBRR,  0x02,  8, 0x04,  8, 0x02,  8, 0x04,  8, 0x01,  8)
 422 SCIx_FNS(SCSCR,  0x04,  8, 0x08,  8, 0x04,  8, 0x08, 16, 0x02,  8)
 423 SCIx_FNS(SCxTDR, 0x06,  8, 0x0c,  8, 0x06,  8, 0x0C,  8, 0x03,  8)
 424 SCIx_FNS(SCxSR,  0x08,  8, 0x10,  8, 0x08, 16, 0x10, 16, 0x04,  8)
 425 SCIx_FNS(SCxRDR, 0x0a,  8, 0x14,  8, 0x0A,  8, 0x14,  8, 0x05,  8)
 426 SCIF_FNS(SCFCR,                      0x0c,  8, 0x18, 16)
 427 #if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
 428     defined(CONFIG_CPU_SUBTYPE_SH7763) || \
 429     defined(CONFIG_CPU_SUBTYPE_SH7780) || \
 430     defined(CONFIG_CPU_SUBTYPE_SH7785)
 431 SCIF_FNS(SCFDR,                      0x0e, 16, 0x1C, 16)
 432 SCIF_FNS(SCTFDR,                     0x0e, 16, 0x1C, 16)
 433 SCIF_FNS(SCRFDR,                     0x0e, 16, 0x20, 16)
 434 SCIF_FNS(SCSPTR,                        0,  0, 0x24, 16)
 435 SCIF_FNS(SCLSR,                         0,  0, 0x28, 16)
 436 #else
 437 SCIF_FNS(SCFDR,                      0x0e, 16, 0x1C, 16)
 438 SCIF_FNS(SCSPTR,                        0,  0, 0x20, 16)
 439 SCIF_FNS(SCLSR,                         0,  0, 0x24, 16)
 440 #endif
 441 #endif
 442 #define sci_in(port, reg) sci_##reg##_in(port)
 443 #define sci_out(port, reg, value) sci_##reg##_out(port, value)
 444
 445 /* H8/300 series SCI pins assignment */
 446 #if defined(__H8300H__) || defined(__H8300S__)
 447 static const struct __attribute__((packed)) {
 448         int port;             /* GPIO port no */
 449         unsigned short rx,tx; /* GPIO bit no */
 450 } h8300_sci_pins[] = {
 451 #if defined(CONFIG_H83007) || defined(CONFIG_H83068)
 452         {    /* SCI0 */
 453                 .port = H8300_GPIO_P9,
 454                 .rx   = H8300_GPIO_B2,
 455                 .tx   = H8300_GPIO_B0,
 456         },
 457         {    /* SCI1 */
 458                 .port = H8300_GPIO_P9,
 459                 .rx   = H8300_GPIO_B3,
 460                 .tx   = H8300_GPIO_B1,
 461         },
 462         {    /* SCI2 */
 463                 .port = H8300_GPIO_PB,
 464                 .rx   = H8300_GPIO_B7,
 465                 .tx   = H8300_GPIO_B6,
 466         }
 467 #elif defined(CONFIG_H8S2678)
 468         {    /* SCI0 */
 469                 .port = H8300_GPIO_P3,
 470                 .rx   = H8300_GPIO_B2,
 471                 .tx   = H8300_GPIO_B0,
 472         },
 473         {    /* SCI1 */
 474                 .port = H8300_GPIO_P3,
 475                 .rx   = H8300_GPIO_B3,
 476                 .tx   = H8300_GPIO_B1,
 477         },
 478         {    /* SCI2 */
 479                 .port = H8300_GPIO_P5,
 480                 .rx   = H8300_GPIO_B1,
 481                 .tx   = H8300_GPIO_B0,
 482         }
 483 #endif
 484 };
 485 #endif
 486
 487 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
 488     defined(CONFIG_CPU_SUBTYPE_SH7707) || \
 489     defined(CONFIG_CPU_SUBTYPE_SH7708) || \
 490     defined(CONFIG_CPU_SUBTYPE_SH7709)
 491 static inline int sci_rxd_in(struct uart_port *port)
 492 {
 493         if (port->mapbase == 0xfffffe80)
 494                 return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCI */
 495         if (port->mapbase == 0xa4000150)
 496                 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
 497         if (port->mapbase == 0xa4000140)
 498                 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
 499         return 1;
 500 }
 501 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
 502 static inline int sci_rxd_in(struct uart_port *port)
 503 {
 504         if (port->mapbase == SCIF0)
 505                 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
 506         if (port->mapbase == SCIF2)
 507                 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
 508         return 1;
 509 }
 510 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
 511 static inline int sci_rxd_in(struct uart_port *port)
 512 {
 513           return sci_in(port,SCxSR)&0x0010 ? 1 : 0;
 514 }
 515 static inline void set_sh771x_scif_pfc(struct uart_port *port)
 516 {
 517         if (port->mapbase == 0xA4400000){
 518                 ctrl_outw(ctrl_inw(PACR)&0xffc0,PACR);
 519                 ctrl_outw(ctrl_inw(PBCR)&0x0fff,PBCR);
 520                 return;
 521         }
 522         if (port->mapbase == 0xA4410000){
 523                 ctrl_outw(ctrl_inw(PBCR)&0xf003,PBCR);
 524                 return;
 525         }
 526 }
 527 #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
 528       defined(CONFIG_CPU_SUBTYPE_SH7721)
 529 static inline int sci_rxd_in(struct uart_port *port)
 530 {
 531         if (port->mapbase == 0xa4430000)
 532                 return sci_in(port, SCxSR) & 0x0003 ? 1 : 0;
 533         else if (port->mapbase == 0xa4438000)
 534                 return sci_in(port, SCxSR) & 0x0003 ? 1 : 0;
 535         return 1;
 536 }
 537 #elif defined(CONFIG_CPU_SUBTYPE_SH7750)  || \
 538       defined(CONFIG_CPU_SUBTYPE_SH7751)  || \
 539       defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
 540       defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
 541       defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
 542       defined(CONFIG_CPU_SUBTYPE_SH7091)  || \
 543       defined(CONFIG_CPU_SUBTYPE_SH4_202)
 544 static inline int sci_rxd_in(struct uart_port *port)
 545 {
 546 #ifndef SCIF_ONLY
 547         if (port->mapbase == 0xffe00000)
 548                 return ctrl_inb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
 549 #endif
 550 #ifndef SCI_ONLY
 551         if (port->mapbase == 0xffe80000)
 552                 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
 553 #endif
 554         return 1;
 555 }
 556 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
 557 static inline int sci_rxd_in(struct uart_port *port)
 558 {
 559         if (port->mapbase == 0xfe600000)
 560                 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
 561         if (port->mapbase == 0xfe610000)
 562                 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
 563         if (port->mapbase == 0xfe620000)
 564                 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
 565         return 1;
 566 }
 567 #elif defined(CONFIG_CPU_SUBTYPE_SH7343)
 568 static inline int sci_rxd_in(struct uart_port *port)
 569 {
 570         if (port->mapbase == 0xffe00000)
 571                 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
 572         if (port->mapbase == 0xffe10000)
 573                 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
 574         if (port->mapbase == 0xffe20000)
 575                 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
 576         if (port->mapbase == 0xffe30000)
 577                 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
 578         return 1;
 579 }
 580 #elif defined(CONFIG_CPU_SUBTYPE_SH7722)
 581 static inline int sci_rxd_in(struct uart_port *port)
 582 {
 583         if (port->mapbase == 0xffe00000)
 584                 return ctrl_inb(SCPDR0) & 0x0001 ? 1 : 0; /* SCIF0 */
 585         return 1;
 586 }
 587 #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
 588 static inline int sci_rxd_in(struct uart_port *port)
 589 {
 590          return sci_in(port, SCSPTR)&0x0001 ? 1 : 0; /* SCIF */
 591 }
 592 #elif defined(__H8300H__) || defined(__H8300S__)
 593 static inline int sci_rxd_in(struct uart_port *port)
 594 {
 595         int ch = (port->mapbase - SMR0) >> 3;
 596         return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0;
 597 }
 598 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
 599 static inline int sci_rxd_in(struct uart_port *port)
 600 {
 601         if (port->mapbase == 0xffe00000)
 602                 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
 603         if (port->mapbase == 0xffe08000)
 604                 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
 605         return 1;
 606 }
 607 #elif defined(CONFIG_CPU_SUBTYPE_SH7770)
 608 static inline int sci_rxd_in(struct uart_port *port)
 609 {
 610         if (port->mapbase == 0xff923000)
 611                 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
 612         if (port->mapbase == 0xff924000)
 613                 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
 614         if (port->mapbase == 0xff925000)
 615                 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
 616         return 1;
 617 }
 618 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
 619 static inline int sci_rxd_in(struct uart_port *port)
 620 {
 621         if (port->mapbase == 0xffe00000)
 622                 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
 623         if (port->mapbase == 0xffe10000)
 624                 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
 625         return 1;
 626 }
 627 #elif defined(CONFIG_CPU_SUBTYPE_SH7785)
 628 static inline int sci_rxd_in(struct uart_port *port)
 629 {
 630         if (port->mapbase == 0xffea0000)
 631                 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
 632         if (port->mapbase == 0xffeb0000)
 633                 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
 634         if (port->mapbase == 0xffec0000)
 635                 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
 636         if (port->mapbase == 0xffed0000)
 637                 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
 638         if (port->mapbase == 0xffee0000)
 639                 return ctrl_inw(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF */
 640         if (port->mapbase == 0xffef0000)
 641                 return ctrl_inw(SCSPTR5) & 0x0001 ? 1 : 0; /* SCIF */
 642         return 1;
 643 }
 644 #elif defined(CONFIG_CPU_SUBTYPE_SH7203) || \
 645       defined(CONFIG_CPU_SUBTYPE_SH7206) || \
 646       defined(CONFIG_CPU_SUBTYPE_SH7263)
 647 static inline int sci_rxd_in(struct uart_port *port)
 648 {
 649         if (port->mapbase == 0xfffe8000)
 650                 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
 651         if (port->mapbase == 0xfffe8800)
 652                 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
 653         if (port->mapbase == 0xfffe9000)
 654                 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
 655         if (port->mapbase == 0xfffe9800)
 656                 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
 657         return 1;
 658 }
 659 #elif defined(CONFIG_CPU_SUBTYPE_SH7619)
 660 static inline int sci_rxd_in(struct uart_port *port)
 661 {
 662         if (port->mapbase == 0xf8400000)
 663                 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
 664         if (port->mapbase == 0xf8410000)
 665                 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
 666         if (port->mapbase == 0xf8420000)
 667                 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
 668         return 1;
 669 }
 670 #elif defined(CONFIG_CPU_SUBTYPE_SHX3)
 671 static inline int sci_rxd_in(struct uart_port *port)
 672 {
 673         if (port->mapbase == 0xffc30000)
 674                 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
 675         if (port->mapbase == 0xffc40000)
 676                 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
 677         if (port->mapbase == 0xffc50000)
 678                 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
 679         if (port->mapbase == 0xffc60000)
 680                 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
 681         return 1;
 682 }
 683 #endif
 684
 685 /*
 686  * Values for the BitRate Register (SCBRR)
 687  *
 688  * The values are actually divisors for a frequency which can
 689  * be internal to the SH3 (14.7456MHz) or derived from an external
 690  * clock source.  This driver assumes the internal clock is used;
 691  * to support using an external clock source, config options or
 692  * possibly command-line options would need to be added.
 693  *
 694  * Also, to support speeds below 2400 (why?) the lower 2 bits of
 695  * the SCSMR register would also need to be set to non-zero values.
 696  *
 697  * -- Greg Banks 27Feb2000
 698  *
 699  * Answer: The SCBRR register is only eight bits, and the value in
 700  * it gets larger with lower baud rates. At around 2400 (depending on
 701  * the peripherial module clock) you run out of bits. However the
 702  * lower two bits of SCSMR allow the module clock to be divided down,
 703  * scaling the value which is needed in SCBRR.
 704  *
 705  * -- Stuart Menefy - 23 May 2000
 706  *
 707  * I meant, why would anyone bother with bitrates below 2400.
 708  *
 709  * -- Greg Banks - 7Jul2000
 710  *
 711  * You "speedist"!  How will I use my 110bps ASR-33 teletype with paper
 712  * tape reader as a console!
 713  *
 714  * -- Mitch Davis - 15 Jul 2000
 715  */
 716
 717 #if defined(CONFIG_CPU_SUBTYPE_SH7763) || \
 718     defined(CONFIG_CPU_SUBTYPE_SH7780) || \
 719     defined(CONFIG_CPU_SUBTYPE_SH7785)
 720 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
 721 #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
 722       defined(CONFIG_CPU_SUBTYPE_SH7720) || \
 723       defined(CONFIG_CPU_SUBTYPE_SH7721)
 724 #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
 725 #elif defined(__H8300H__) || defined(__H8300S__)
 726 #define SCBRR_VALUE(bps) (((CONFIG_CPU_CLOCK*1000/32)/bps)-1)
 727 #elif defined(CONFIG_SUPERH64)
 728 #define SCBRR_VALUE(bps) ((current_cpu_data.module_clock+16*bps)/(32*bps)-1)
 729 #else /* Generic SH */
 730 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
 731 #endif