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[wrt350n-kernel.git] / drivers / ata / pata_hpt3x3.c
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1 /*
2 * pata_hpt3x3 - HPT3x3 driver
3 * (c) Copyright 2005-2006 Red Hat
5 * Was pata_hpt34x but the naming was confusing as it supported the
6 * 343 and 363 so it has been renamed.
8 * Based on:
9 * linux/drivers/ide/pci/hpt34x.c Version 0.40 Sept 10, 2002
10 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
12 * May be copied or modified under the terms of the GNU General Public
13 * License
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/pci.h>
19 #include <linux/init.h>
20 #include <linux/blkdev.h>
21 #include <linux/delay.h>
22 #include <scsi/scsi_host.h>
23 #include <linux/libata.h>
25 #define DRV_NAME "pata_hpt3x3"
26 #define DRV_VERSION "0.4.2"
28 /**
29 * hpt3x3_set_piomode - PIO setup
30 * @ap: ATA interface
31 * @adev: device on the interface
33 * Set our PIO requirements. This is fairly simple on the HPT3x3 as
34 * all we have to do is clear the MWDMA and UDMA bits then load the
35 * mode number.
38 static void hpt3x3_set_piomode(struct ata_port *ap, struct ata_device *adev)
40 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
41 u32 r1, r2;
42 int dn = 2 * ap->port_no + adev->devno;
44 pci_read_config_dword(pdev, 0x44, &r1);
45 pci_read_config_dword(pdev, 0x48, &r2);
46 /* Load the PIO timing number */
47 r1 &= ~(7 << (3 * dn));
48 r1 |= (adev->pio_mode - XFER_PIO_0) << (3 * dn);
49 r2 &= ~(0x11 << dn); /* Clear MWDMA and UDMA bits */
51 pci_write_config_dword(pdev, 0x44, r1);
52 pci_write_config_dword(pdev, 0x48, r2);
55 /**
56 * hpt3x3_set_dmamode - DMA timing setup
57 * @ap: ATA interface
58 * @adev: Device being configured
60 * Set up the channel for MWDMA or UDMA modes. Much the same as with
61 * PIO, load the mode number and then set MWDMA or UDMA flag.
64 static void hpt3x3_set_dmamode(struct ata_port *ap, struct ata_device *adev)
66 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
67 u32 r1, r2;
68 int dn = 2 * ap->port_no + adev->devno;
69 int mode_num = adev->dma_mode & 0x0F;
71 pci_read_config_dword(pdev, 0x44, &r1);
72 pci_read_config_dword(pdev, 0x48, &r2);
73 /* Load the timing number */
74 r1 &= ~(7 << (3 * dn));
75 r1 |= (mode_num << (3 * dn));
76 r2 &= ~(0x11 << dn); /* Clear MWDMA and UDMA bits */
78 if (adev->dma_mode >= XFER_UDMA_0)
79 r2 |= 0x01 << dn; /* Ultra mode */
80 else
81 r2 |= 0x10 << dn; /* MWDMA */
83 pci_write_config_dword(pdev, 0x44, r1);
84 pci_write_config_dword(pdev, 0x48, r2);
87 static struct scsi_host_template hpt3x3_sht = {
88 .module = THIS_MODULE,
89 .name = DRV_NAME,
90 .ioctl = ata_scsi_ioctl,
91 .queuecommand = ata_scsi_queuecmd,
92 .can_queue = ATA_DEF_QUEUE,
93 .this_id = ATA_SHT_THIS_ID,
94 .sg_tablesize = LIBATA_MAX_PRD,
95 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
96 .emulated = ATA_SHT_EMULATED,
97 .use_clustering = ATA_SHT_USE_CLUSTERING,
98 .proc_name = DRV_NAME,
99 .dma_boundary = ATA_DMA_BOUNDARY,
100 .slave_configure = ata_scsi_slave_config,
101 .slave_destroy = ata_scsi_slave_destroy,
102 .bios_param = ata_std_bios_param,
103 #ifdef CONFIG_PM
104 .resume = ata_scsi_device_resume,
105 .suspend = ata_scsi_device_suspend,
106 #endif
109 static struct ata_port_operations hpt3x3_port_ops = {
110 .port_disable = ata_port_disable,
111 .set_piomode = hpt3x3_set_piomode,
112 .set_dmamode = hpt3x3_set_dmamode,
113 .mode_filter = ata_pci_default_filter,
115 .tf_load = ata_tf_load,
116 .tf_read = ata_tf_read,
117 .check_status = ata_check_status,
118 .exec_command = ata_exec_command,
119 .dev_select = ata_std_dev_select,
121 .freeze = ata_bmdma_freeze,
122 .thaw = ata_bmdma_thaw,
123 .error_handler = ata_bmdma_error_handler,
124 .post_internal_cmd = ata_bmdma_post_internal_cmd,
125 .cable_detect = ata_cable_40wire,
127 .bmdma_setup = ata_bmdma_setup,
128 .bmdma_start = ata_bmdma_start,
129 .bmdma_stop = ata_bmdma_stop,
130 .bmdma_status = ata_bmdma_status,
132 .qc_prep = ata_qc_prep,
133 .qc_issue = ata_qc_issue_prot,
135 .data_xfer = ata_data_xfer,
137 .irq_handler = ata_interrupt,
138 .irq_clear = ata_bmdma_irq_clear,
139 .irq_on = ata_irq_on,
140 .irq_ack = ata_irq_ack,
142 .port_start = ata_port_start,
146 * hpt3x3_init_chipset - chip setup
147 * @dev: PCI device
149 * Perform the setup required at boot and on resume.
152 static void hpt3x3_init_chipset(struct pci_dev *dev)
154 u16 cmd;
155 /* Initialize the board */
156 pci_write_config_word(dev, 0x80, 0x00);
157 /* Check if it is a 343 or a 363. 363 has COMMAND_MEMORY set */
158 pci_read_config_word(dev, PCI_COMMAND, &cmd);
159 if (cmd & PCI_COMMAND_MEMORY)
160 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xF0);
161 else
162 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20);
167 * hpt3x3_init_one - Initialise an HPT343/363
168 * @dev: PCI device
169 * @id: Entry in match table
171 * Perform basic initialisation. The chip has a quirk that it won't
172 * function unless it is at XX00. The old ATA driver touched this up
173 * but we leave it for pci quirks to do properly.
176 static int hpt3x3_init_one(struct pci_dev *dev, const struct pci_device_id *id)
178 static struct ata_port_info info = {
179 .sht = &hpt3x3_sht,
180 .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
181 .pio_mask = 0x1f,
182 .mwdma_mask = 0x07,
183 .udma_mask = 0x07,
184 .port_ops = &hpt3x3_port_ops
186 static struct ata_port_info *port_info[2] = { &info, &info };
188 hpt3x3_init_chipset(dev);
189 /* Now kick off ATA set up */
190 return ata_pci_init_one(dev, port_info, 2);
193 #ifdef CONFIG_PM
194 static int hpt3x3_reinit_one(struct pci_dev *dev)
196 hpt3x3_init_chipset(dev);
197 return ata_pci_device_resume(dev);
199 #endif
201 static const struct pci_device_id hpt3x3[] = {
202 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT343), },
204 { },
207 static struct pci_driver hpt3x3_pci_driver = {
208 .name = DRV_NAME,
209 .id_table = hpt3x3,
210 .probe = hpt3x3_init_one,
211 .remove = ata_pci_remove_one,
212 #ifdef CONFIG_PM
213 .suspend = ata_pci_device_suspend,
214 .resume = hpt3x3_reinit_one,
215 #endif
218 static int __init hpt3x3_init(void)
220 return pci_register_driver(&hpt3x3_pci_driver);
224 static void __exit hpt3x3_exit(void)
226 pci_unregister_driver(&hpt3x3_pci_driver);
230 MODULE_AUTHOR("Alan Cox");
231 MODULE_DESCRIPTION("low-level driver for the Highpoint HPT343/363");
232 MODULE_LICENSE("GPL");
233 MODULE_DEVICE_TABLE(pci, hpt3x3);
234 MODULE_VERSION(DRV_VERSION);
236 module_init(hpt3x3_init);
237 module_exit(hpt3x3_exit);