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[POWERPC] Use menuconfig objects II - Macintosh
[wrt350n-kernel.git] / drivers / ata / pata_pdc202xx_old.c
blobee636beb05e132f7da4ca127d569702c5eb4d6fc
1 /*
2 * pata_pdc202xx_old.c - Promise PDC202xx PATA for new ATA layer
3 * (C) 2005 Red Hat Inc
4 * Alan Cox <alan@redhat.com>
5 * (C) 2007 Bartlomiej Zolnierkiewicz
6 *
7 * Based in part on linux/drivers/ide/pci/pdc202xx_old.c
8 *
9 * First cut with LBA48/ATAPI
10 *
11 * TODO:
12 * Channel interlock/reset on both required
13 */
14
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/pci.h>
18 #include <linux/init.h>
19 #include <linux/blkdev.h>
20 #include <linux/delay.h>
21 #include <scsi/scsi_host.h>
22 #include <linux/libata.h>
23
24 #define DRV_NAME "pata_pdc202xx_old"
25 #define DRV_VERSION "0.4.2"
26
27 static int pdc2026x_cable_detect(struct ata_port *ap)
28 {
29 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
30 u16 cis;
31
32 pci_read_config_word(pdev, 0x50, &cis);
33 if (cis & (1 << (10 + ap->port_no)))
34 return ATA_CBL_PATA80;
35 return ATA_CBL_PATA40;
36 }
37
38 /**
39 * pdc202xx_configure_piomode - set chip PIO timing
40 * @ap: ATA interface
41 * @adev: ATA device
42 * @pio: PIO mode
43 *
44 * Called to do the PIO mode setup. Our timing registers are shared
45 * so a configure_dmamode call will undo any work we do here and vice
46 * versa
47 */
48
49 static void pdc202xx_configure_piomode(struct ata_port *ap, struct ata_device *adev, int pio)
50 {
51 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
52 int port = 0x60 + 8 * ap->port_no + 4 * adev->devno;
53 static u16 pio_timing[5] = {
54 0x0913, 0x050C , 0x0308, 0x0206, 0x0104
55 };
56 u8 r_ap, r_bp;
57
58 pci_read_config_byte(pdev, port, &r_ap);
59 pci_read_config_byte(pdev, port + 1, &r_bp);
60 r_ap &= ~0x3F; /* Preserve ERRDY_EN, SYNC_IN */
61 r_bp &= ~0x1F;
62 r_ap |= (pio_timing[pio] >> 8);
63 r_bp |= (pio_timing[pio] & 0xFF);
64
65 if (ata_pio_need_iordy(adev))
66 r_ap |= 0x20; /* IORDY enable */
67 if (adev->class == ATA_DEV_ATA)
68 r_ap |= 0x10; /* FIFO enable */
69 pci_write_config_byte(pdev, port, r_ap);
70 pci_write_config_byte(pdev, port + 1, r_bp);
71 }
72
73 /**
74 * pdc202xx_set_piomode - set initial PIO mode data
75 * @ap: ATA interface
76 * @adev: ATA device
77 *
78 * Called to do the PIO mode setup. Our timing registers are shared
79 * but we want to set the PIO timing by default.
80 */
81
82 static void pdc202xx_set_piomode(struct ata_port *ap, struct ata_device *adev)
83 {
84 pdc202xx_configure_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
85 }
86
87 /**
88 * pdc202xx_configure_dmamode - set DMA mode in chip
89 * @ap: ATA interface
90 * @adev: ATA device
91 *
92 * Load DMA cycle times into the chip ready for a DMA transfer
93 * to occur.
94 */
95
96 static void pdc202xx_set_dmamode(struct ata_port *ap, struct ata_device *adev)
97 {
98 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
99 int port = 0x60 + 8 * ap->port_no + 4 * adev->devno;
100 static u8 udma_timing[6][2] = {
101 { 0x60, 0x03 }, /* 33 Mhz Clock */
102 { 0x40, 0x02 },
103 { 0x20, 0x01 },
104 { 0x40, 0x02 }, /* 66 Mhz Clock */
105 { 0x20, 0x01 },
106 { 0x20, 0x01 }
107 };
108 static u8 mdma_timing[3][2] = {
109 { 0x60, 0x03 },
110 { 0x60, 0x04 },
111 { 0xe0, 0x0f },
112 };
113 u8 r_bp, r_cp;
114
115 pci_read_config_byte(pdev, port + 1, &r_bp);
116 pci_read_config_byte(pdev, port + 2, &r_cp);
117
118 r_bp &= ~0xE0;
119 r_cp &= ~0x0F;
120
121 if (adev->dma_mode >= XFER_UDMA_0) {
122 int speed = adev->dma_mode - XFER_UDMA_0;
123 r_bp |= udma_timing[speed][0];
124 r_cp |= udma_timing[speed][1];
125
126 } else {
127 int speed = adev->dma_mode - XFER_MW_DMA_0;
128 r_bp |= mdma_timing[speed][0];
129 r_cp |= mdma_timing[speed][1];
130 }
131 pci_write_config_byte(pdev, port + 1, r_bp);
132 pci_write_config_byte(pdev, port + 2, r_cp);
133
134 }
135
136 /**
137 * pdc2026x_bmdma_start - DMA engine begin
138 * @qc: ATA command
139 *
140 * In UDMA3 or higher we have to clock switch for the duration of the
141 * DMA transfer sequence.
142 */
143
144 static void pdc2026x_bmdma_start(struct ata_queued_cmd *qc)
145 {
146 struct ata_port *ap = qc->ap;
147 struct ata_device *adev = qc->dev;
148 struct ata_taskfile *tf = &qc->tf;
149 int sel66 = ap->port_no ? 0x08: 0x02;
150
151 void __iomem *master = ap->host->ports[0]->ioaddr.bmdma_addr;
152 void __iomem *clock = master + 0x11;
153 void __iomem *atapi_reg = master + 0x20 + (4 * ap->port_no);
154
155 u32 len;
156
157 /* Check we keep host level locking here */
158 if (adev->dma_mode >= XFER_UDMA_2)
159 iowrite8(ioread8(clock) | sel66, clock);
160 else
161 iowrite8(ioread8(clock) & ~sel66, clock);
162
163 /* The DMA clocks may have been trashed by a reset. FIXME: make conditional
164 and move to qc_issue ? */
165 pdc202xx_set_dmamode(ap, qc->dev);
166
167 /* Cases the state machine will not complete correctly without help */
168 if ((tf->flags & ATA_TFLAG_LBA48) || tf->protocol == ATA_PROT_ATAPI_DMA)
169 {
170 len = qc->nbytes / 2;
171
172 if (tf->flags & ATA_TFLAG_WRITE)
173 len |= 0x06000000;
174 else
175 len |= 0x05000000;
176
177 iowrite32(len, atapi_reg);
178 }
179
180 /* Activate DMA */
181 ata_bmdma_start(qc);
182 }
183
184 /**
185 * pdc2026x_bmdma_end - DMA engine stop
186 * @qc: ATA command
187 *
188 * After a DMA completes we need to put the clock back to 33MHz for
189 * PIO timings.
190 */
191
192 static void pdc2026x_bmdma_stop(struct ata_queued_cmd *qc)
193 {
194 struct ata_port *ap = qc->ap;
195 struct ata_device *adev = qc->dev;
196 struct ata_taskfile *tf = &qc->tf;
197
198 int sel66 = ap->port_no ? 0x08: 0x02;
199 /* The clock bits are in the same register for both channels */
200 void __iomem *master = ap->host->ports[0]->ioaddr.bmdma_addr;
201 void __iomem *clock = master + 0x11;
202 void __iomem *atapi_reg = master + 0x20 + (4 * ap->port_no);
203
204 /* Cases the state machine will not complete correctly */
205 if (tf->protocol == ATA_PROT_ATAPI_DMA || ( tf->flags & ATA_TFLAG_LBA48)) {
206 iowrite32(0, atapi_reg);
207 iowrite8(ioread8(clock) & ~sel66, clock);
208 }
209 /* Check we keep host level locking here */
210 /* Flip back to 33Mhz for PIO */
211 if (adev->dma_mode >= XFER_UDMA_2)
212 iowrite8(ioread8(clock) & ~sel66, clock);
213
214 ata_bmdma_stop(qc);
215 }
216
217 /**
218 * pdc2026x_dev_config - device setup hook
219 * @adev: newly found device
220 *
221 * Perform chip specific early setup. We need to lock the transfer
222 * sizes to 8bit to avoid making the state engine on the 2026x cards
223 * barf.
224 */
225
226 static void pdc2026x_dev_config(struct ata_device *adev)
227 {
228 adev->max_sectors = 256;
229 }
230
231 static struct scsi_host_template pdc202xx_sht = {
232 .module = THIS_MODULE,
233 .name = DRV_NAME,
234 .ioctl = ata_scsi_ioctl,
235 .queuecommand = ata_scsi_queuecmd,
236 .can_queue = ATA_DEF_QUEUE,
237 .this_id = ATA_SHT_THIS_ID,
238 .sg_tablesize = LIBATA_MAX_PRD,
239 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
240 .emulated = ATA_SHT_EMULATED,
241 .use_clustering = ATA_SHT_USE_CLUSTERING,
242 .proc_name = DRV_NAME,
243 .dma_boundary = ATA_DMA_BOUNDARY,
244 .slave_configure = ata_scsi_slave_config,
245 .slave_destroy = ata_scsi_slave_destroy,
246 .bios_param = ata_std_bios_param,
247 #ifdef CONFIG_PM
248 .resume = ata_scsi_device_resume,
249 .suspend = ata_scsi_device_suspend,
250 #endif
251 };
252
253 static struct ata_port_operations pdc2024x_port_ops = {
254 .port_disable = ata_port_disable,
255 .set_piomode = pdc202xx_set_piomode,
256 .set_dmamode = pdc202xx_set_dmamode,
257 .mode_filter = ata_pci_default_filter,
258 .tf_load = ata_tf_load,
259 .tf_read = ata_tf_read,
260 .check_status = ata_check_status,
261 .exec_command = ata_exec_command,
262 .dev_select = ata_std_dev_select,
263
264 .freeze = ata_bmdma_freeze,
265 .thaw = ata_bmdma_thaw,
266 .error_handler = ata_bmdma_error_handler,
267 .post_internal_cmd = ata_bmdma_post_internal_cmd,
268 .cable_detect = ata_cable_40wire,
269
270 .bmdma_setup = ata_bmdma_setup,
271 .bmdma_start = ata_bmdma_start,
272 .bmdma_stop = ata_bmdma_stop,
273 .bmdma_status = ata_bmdma_status,
274
275 .qc_prep = ata_qc_prep,
276 .qc_issue = ata_qc_issue_prot,
277 .data_xfer = ata_data_xfer,
278
279 .irq_handler = ata_interrupt,
280 .irq_clear = ata_bmdma_irq_clear,
281 .irq_on = ata_irq_on,
282 .irq_ack = ata_irq_ack,
283
284 .port_start = ata_port_start,
285 };
286
287 static struct ata_port_operations pdc2026x_port_ops = {
288 .port_disable = ata_port_disable,
289 .set_piomode = pdc202xx_set_piomode,
290 .set_dmamode = pdc202xx_set_dmamode,
291 .mode_filter = ata_pci_default_filter,
292 .tf_load = ata_tf_load,
293 .tf_read = ata_tf_read,
294 .check_status = ata_check_status,
295 .exec_command = ata_exec_command,
296 .dev_select = ata_std_dev_select,
297 .dev_config = pdc2026x_dev_config,
298
299 .freeze = ata_bmdma_freeze,
300 .thaw = ata_bmdma_thaw,
301 .error_handler = ata_bmdma_error_handler,
302 .post_internal_cmd = ata_bmdma_post_internal_cmd,
303 .cable_detect = pdc2026x_cable_detect,
304
305 .bmdma_setup = ata_bmdma_setup,
306 .bmdma_start = pdc2026x_bmdma_start,
307 .bmdma_stop = pdc2026x_bmdma_stop,
308 .bmdma_status = ata_bmdma_status,
309
310 .qc_prep = ata_qc_prep,
311 .qc_issue = ata_qc_issue_prot,
312 .data_xfer = ata_data_xfer,
313
314 .irq_handler = ata_interrupt,
315 .irq_clear = ata_bmdma_irq_clear,
316 .irq_on = ata_irq_on,
317 .irq_ack = ata_irq_ack,
318
319 .port_start = ata_port_start,
320 };
321
322 static int pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
323 {
324 static struct ata_port_info info[3] = {
325 {
326 .sht = &pdc202xx_sht,
327 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
328 .pio_mask = 0x1f,
329 .mwdma_mask = 0x07,
330 .udma_mask = ATA_UDMA2,
331 .port_ops = &pdc2024x_port_ops
332 },
333 {
334 .sht = &pdc202xx_sht,
335 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
336 .pio_mask = 0x1f,
337 .mwdma_mask = 0x07,
338 .udma_mask = ATA_UDMA4,
339 .port_ops = &pdc2026x_port_ops
340 },
341 {
342 .sht = &pdc202xx_sht,
343 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
344 .pio_mask = 0x1f,
345 .mwdma_mask = 0x07,
346 .udma_mask = ATA_UDMA5,
347 .port_ops = &pdc2026x_port_ops
348 }
349
350 };
351 static struct ata_port_info *port_info[2];
352
353 port_info[0] = port_info[1] = &info[id->driver_data];
354
355 if (dev->device == PCI_DEVICE_ID_PROMISE_20265) {
356 struct pci_dev *bridge = dev->bus->self;
357 /* Don't grab anything behind a Promise I2O RAID */
358 if (bridge && bridge->vendor == PCI_VENDOR_ID_INTEL) {
359 if( bridge->device == PCI_DEVICE_ID_INTEL_I960)
360 return -ENODEV;
361 if( bridge->device == PCI_DEVICE_ID_INTEL_I960RM)
362 return -ENODEV;
363 }
364 }
365 return ata_pci_init_one(dev, port_info, 2);
366 }
367
368 static const struct pci_device_id pdc202xx[] = {
369 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 },
370 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 },
371 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 1 },
372 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 2 },
373 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 2 },
374
375 { },
376 };
377
378 static struct pci_driver pdc202xx_pci_driver = {
379 .name = DRV_NAME,
380 .id_table = pdc202xx,
381 .probe = pdc202xx_init_one,
382 .remove = ata_pci_remove_one,
383 #ifdef CONFIG_PM
384 .suspend = ata_pci_device_suspend,
385 .resume = ata_pci_device_resume,
386 #endif
387 };
388
389 static int __init pdc202xx_init(void)
390 {
391 return pci_register_driver(&pdc202xx_pci_driver);
392 }
393
394 static void __exit pdc202xx_exit(void)
395 {
396 pci_unregister_driver(&pdc202xx_pci_driver);
397 }
398
399 MODULE_AUTHOR("Alan Cox");
400 MODULE_DESCRIPTION("low-level driver for Promise 2024x and 20262-20267");
401 MODULE_LICENSE("GPL");
402 MODULE_DEVICE_TABLE(pci, pdc202xx);
403 MODULE_VERSION(DRV_VERSION);
404
405 module_init(pdc202xx_init);
406 module_exit(pdc202xx_exit);
WRT350N Kernel Patches