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[POWERPC] Use menuconfig objects II - Macintosh
[wrt350n-kernel.git] / drivers / ata / sata_sil24.c
blobe6223ba667daca271a19e1c541470d80463c2a9a
1 /*
2 * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers
3 *
4 * Copyright 2005 Tejun Heo
5 *
6 * Based on preview driver from Silicon Image.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2, or (at your option) any
11 * later version.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 */
19
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/pci.h>
23 #include <linux/blkdev.h>
24 #include <linux/delay.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/device.h>
28 #include <scsi/scsi_host.h>
29 #include <scsi/scsi_cmnd.h>
30 #include <linux/libata.h>
31
32 #define DRV_NAME "sata_sil24"
33 #define DRV_VERSION "0.8"
34
35 /*
36 * Port request block (PRB) 32 bytes
37 */
38 struct sil24_prb {
39 __le16 ctrl;
40 __le16 prot;
41 __le32 rx_cnt;
42 u8 fis[6 * 4];
43 };
44
45 /*
46 * Scatter gather entry (SGE) 16 bytes
47 */
48 struct sil24_sge {
49 __le64 addr;
50 __le32 cnt;
51 __le32 flags;
52 };
53
54 /*
55 * Port multiplier
56 */
57 struct sil24_port_multiplier {
58 __le32 diag;
59 __le32 sactive;
60 };
61
62 enum {
63 SIL24_HOST_BAR = 0,
64 SIL24_PORT_BAR = 2,
65
66 /*
67 * Global controller registers (128 bytes @ BAR0)
68 */
69 /* 32 bit regs */
70 HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */
71 HOST_CTRL = 0x40,
72 HOST_IRQ_STAT = 0x44,
73 HOST_PHY_CFG = 0x48,
74 HOST_BIST_CTRL = 0x50,
75 HOST_BIST_PTRN = 0x54,
76 HOST_BIST_STAT = 0x58,
77 HOST_MEM_BIST_STAT = 0x5c,
78 HOST_FLASH_CMD = 0x70,
79 /* 8 bit regs */
80 HOST_FLASH_DATA = 0x74,
81 HOST_TRANSITION_DETECT = 0x75,
82 HOST_GPIO_CTRL = 0x76,
83 HOST_I2C_ADDR = 0x78, /* 32 bit */
84 HOST_I2C_DATA = 0x7c,
85 HOST_I2C_XFER_CNT = 0x7e,
86 HOST_I2C_CTRL = 0x7f,
87
88 /* HOST_SLOT_STAT bits */
89 HOST_SSTAT_ATTN = (1 << 31),
90
91 /* HOST_CTRL bits */
92 HOST_CTRL_M66EN = (1 << 16), /* M66EN PCI bus signal */
93 HOST_CTRL_TRDY = (1 << 17), /* latched PCI TRDY */
94 HOST_CTRL_STOP = (1 << 18), /* latched PCI STOP */
95 HOST_CTRL_DEVSEL = (1 << 19), /* latched PCI DEVSEL */
96 HOST_CTRL_REQ64 = (1 << 20), /* latched PCI REQ64 */
97 HOST_CTRL_GLOBAL_RST = (1 << 31), /* global reset */
98
99 /*
100 * Port registers
101 * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
102 */
103 PORT_REGS_SIZE = 0x2000,
104
105 PORT_LRAM = 0x0000, /* 31 LRAM slots and PMP regs */
106 PORT_LRAM_SLOT_SZ = 0x0080, /* 32 bytes PRB + 2 SGE, ACT... */
107
108 PORT_PMP = 0x0f80, /* 8 bytes PMP * 16 (128 bytes) */
109 PORT_PMP_STATUS = 0x0000, /* port device status offset */
110 PORT_PMP_QACTIVE = 0x0004, /* port device QActive offset */
111 PORT_PMP_SIZE = 0x0008, /* 8 bytes per PMP */
112
113 /* 32 bit regs */
114 PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */
115 PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */
116 PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */
117 PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */
118 PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */
119 PORT_ACTIVATE_UPPER_ADDR= 0x101c,
120 PORT_EXEC_FIFO = 0x1020, /* command execution fifo */
121 PORT_CMD_ERR = 0x1024, /* command error number */
122 PORT_FIS_CFG = 0x1028,
123 PORT_FIFO_THRES = 0x102c,
124 /* 16 bit regs */
125 PORT_DECODE_ERR_CNT = 0x1040,
126 PORT_DECODE_ERR_THRESH = 0x1042,
127 PORT_CRC_ERR_CNT = 0x1044,
128 PORT_CRC_ERR_THRESH = 0x1046,
129 PORT_HSHK_ERR_CNT = 0x1048,
130 PORT_HSHK_ERR_THRESH = 0x104a,
131 /* 32 bit regs */
132 PORT_PHY_CFG = 0x1050,
133 PORT_SLOT_STAT = 0x1800,
134 PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */
135 PORT_CONTEXT = 0x1e04,
136 PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */
137 PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */
138 PORT_SCONTROL = 0x1f00,
139 PORT_SSTATUS = 0x1f04,
140 PORT_SERROR = 0x1f08,
141 PORT_SACTIVE = 0x1f0c,
142
143 /* PORT_CTRL_STAT bits */
144 PORT_CS_PORT_RST = (1 << 0), /* port reset */
145 PORT_CS_DEV_RST = (1 << 1), /* device reset */
146 PORT_CS_INIT = (1 << 2), /* port initialize */
147 PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */
148 PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */
149 PORT_CS_PMP_RESUME = (1 << 6), /* PMP resume */
150 PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */
151 PORT_CS_PMP_EN = (1 << 13), /* port multiplier enable */
152 PORT_CS_RDY = (1 << 31), /* port ready to accept commands */
153
154 /* PORT_IRQ_STAT/ENABLE_SET/CLR */
155 /* bits[11:0] are masked */
156 PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */
157 PORT_IRQ_ERROR = (1 << 1), /* command execution error */
158 PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */
159 PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */
160 PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */
161 PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */
162 PORT_IRQ_UNK_FIS = (1 << 6), /* unknown FIS received */
163 PORT_IRQ_DEV_XCHG = (1 << 7), /* device exchanged */
164 PORT_IRQ_8B10B = (1 << 8), /* 8b/10b decode error threshold */
165 PORT_IRQ_CRC = (1 << 9), /* CRC error threshold */
166 PORT_IRQ_HANDSHAKE = (1 << 10), /* handshake error threshold */
167 PORT_IRQ_SDB_NOTIFY = (1 << 11), /* SDB notify received */
168
169 DEF_PORT_IRQ = PORT_IRQ_COMPLETE | PORT_IRQ_ERROR |
170 PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG |
171 PORT_IRQ_UNK_FIS,
172
173 /* bits[27:16] are unmasked (raw) */
174 PORT_IRQ_RAW_SHIFT = 16,
175 PORT_IRQ_MASKED_MASK = 0x7ff,
176 PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT),
177
178 /* ENABLE_SET/CLR specific, intr steering - 2 bit field */
179 PORT_IRQ_STEER_SHIFT = 30,
180 PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT),
181
182 /* PORT_CMD_ERR constants */
183 PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */
184 PORT_CERR_SDB = 2, /* Error bit in SDB FIS */
185 PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */
186 PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */
187 PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */
188 PORT_CERR_DIRECTION = 6, /* Data direction mismatch */
189 PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */
190 PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */
191 PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */
192 PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */
193 PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */
194 PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */
195 PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */
196 PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */
197 PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */
198 PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */
199 PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */
200 PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */
201 PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */
202 PORT_CERR_XFR_MSTABRT = 34, /* PSD ecode 10 - master abort */
203 PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */
204 PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */
205
206 /* bits of PRB control field */
207 PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */
208 PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */
209 PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */
210 PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */
211 PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */
212
213 /* PRB protocol field */
214 PRB_PROT_PACKET = (1 << 0),
215 PRB_PROT_TCQ = (1 << 1),
216 PRB_PROT_NCQ = (1 << 2),
217 PRB_PROT_READ = (1 << 3),
218 PRB_PROT_WRITE = (1 << 4),
219 PRB_PROT_TRANSPARENT = (1 << 5),
220
221 /*
222 * Other constants
223 */
224 SGE_TRM = (1 << 31), /* Last SGE in chain */
225 SGE_LNK = (1 << 30), /* linked list
226 Points to SGT, not SGE */
227 SGE_DRD = (1 << 29), /* discard data read (/dev/null)
228 data address ignored */
229
230 SIL24_MAX_CMDS = 31,
231
232 /* board id */
233 BID_SIL3124 = 0,
234 BID_SIL3132 = 1,
235 BID_SIL3131 = 2,
236
237 /* host flags */
238 SIL24_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
239 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
240 ATA_FLAG_NCQ | ATA_FLAG_SKIP_D2H_BSY,
241 SIL24_FLAG_PCIX_IRQ_WOC = (1 << 24), /* IRQ loss errata on PCI-X */
242
243 IRQ_STAT_4PORTS = 0xf,
244 };
245
246 struct sil24_ata_block {
247 struct sil24_prb prb;
248 struct sil24_sge sge[LIBATA_MAX_PRD];
249 };
250
251 struct sil24_atapi_block {
252 struct sil24_prb prb;
253 u8 cdb[16];
254 struct sil24_sge sge[LIBATA_MAX_PRD - 1];
255 };
256
257 union sil24_cmd_block {
258 struct sil24_ata_block ata;
259 struct sil24_atapi_block atapi;
260 };
261
262 static struct sil24_cerr_info {
263 unsigned int err_mask, action;
264 const char *desc;
265 } sil24_cerr_db[] = {
266 [0] = { AC_ERR_DEV, ATA_EH_REVALIDATE,
267 "device error" },
268 [PORT_CERR_DEV] = { AC_ERR_DEV, ATA_EH_REVALIDATE,
269 "device error via D2H FIS" },
270 [PORT_CERR_SDB] = { AC_ERR_DEV, ATA_EH_REVALIDATE,
271 "device error via SDB FIS" },
272 [PORT_CERR_DATA] = { AC_ERR_ATA_BUS, ATA_EH_SOFTRESET,
273 "error in data FIS" },
274 [PORT_CERR_SEND] = { AC_ERR_ATA_BUS, ATA_EH_SOFTRESET,
275 "failed to transmit command FIS" },
276 [PORT_CERR_INCONSISTENT] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
277 "protocol mismatch" },
278 [PORT_CERR_DIRECTION] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
279 "data directon mismatch" },
280 [PORT_CERR_UNDERRUN] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
281 "ran out of SGEs while writing" },
282 [PORT_CERR_OVERRUN] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
283 "ran out of SGEs while reading" },
284 [PORT_CERR_PKT_PROT] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
285 "invalid data directon for ATAPI CDB" },
286 [PORT_CERR_SGT_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_SOFTRESET,
287 "SGT no on qword boundary" },
288 [PORT_CERR_SGT_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
289 "PCI target abort while fetching SGT" },
290 [PORT_CERR_SGT_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
291 "PCI master abort while fetching SGT" },
292 [PORT_CERR_SGT_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
293 "PCI parity error while fetching SGT" },
294 [PORT_CERR_CMD_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_SOFTRESET,
295 "PRB not on qword boundary" },
296 [PORT_CERR_CMD_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
297 "PCI target abort while fetching PRB" },
298 [PORT_CERR_CMD_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
299 "PCI master abort while fetching PRB" },
300 [PORT_CERR_CMD_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
301 "PCI parity error while fetching PRB" },
302 [PORT_CERR_XFR_UNDEF] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
303 "undefined error while transferring data" },
304 [PORT_CERR_XFR_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
305 "PCI target abort while transferring data" },
306 [PORT_CERR_XFR_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
307 "PCI master abort while transferring data" },
308 [PORT_CERR_XFR_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
309 "PCI parity error while transferring data" },
310 [PORT_CERR_SENDSERVICE] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
311 "FIS received while sending service FIS" },
312 };
313
314 /*
315 * ap->private_data
316 *
317 * The preview driver always returned 0 for status. We emulate it
318 * here from the previous interrupt.
319 */
320 struct sil24_port_priv {
321 union sil24_cmd_block *cmd_block; /* 32 cmd blocks */
322 dma_addr_t cmd_block_dma; /* DMA base addr for them */
323 struct ata_taskfile tf; /* Cached taskfile registers */
324 };
325
326 static void sil24_dev_config(struct ata_device *dev);
327 static u8 sil24_check_status(struct ata_port *ap);
328 static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg);
329 static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val);
330 static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
331 static void sil24_qc_prep(struct ata_queued_cmd *qc);
332 static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc);
333 static void sil24_irq_clear(struct ata_port *ap);
334 static void sil24_freeze(struct ata_port *ap);
335 static void sil24_thaw(struct ata_port *ap);
336 static void sil24_error_handler(struct ata_port *ap);
337 static void sil24_post_internal_cmd(struct ata_queued_cmd *qc);
338 static int sil24_port_start(struct ata_port *ap);
339 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
340 #ifdef CONFIG_PM
341 static int sil24_pci_device_resume(struct pci_dev *pdev);
342 #endif
343
344 static const struct pci_device_id sil24_pci_tbl[] = {
345 { PCI_VDEVICE(CMD, 0x3124), BID_SIL3124 },
346 { PCI_VDEVICE(INTEL, 0x3124), BID_SIL3124 },
347 { PCI_VDEVICE(CMD, 0x3132), BID_SIL3132 },
348 { PCI_VDEVICE(CMD, 0x0242), BID_SIL3132 },
349 { PCI_VDEVICE(CMD, 0x3131), BID_SIL3131 },
350 { PCI_VDEVICE(CMD, 0x3531), BID_SIL3131 },
351
352 { } /* terminate list */
353 };
354
355 static struct pci_driver sil24_pci_driver = {
356 .name = DRV_NAME,
357 .id_table = sil24_pci_tbl,
358 .probe = sil24_init_one,
359 .remove = ata_pci_remove_one,
360 #ifdef CONFIG_PM
361 .suspend = ata_pci_device_suspend,
362 .resume = sil24_pci_device_resume,
363 #endif
364 };
365
366 static struct scsi_host_template sil24_sht = {
367 .module = THIS_MODULE,
368 .name = DRV_NAME,
369 .ioctl = ata_scsi_ioctl,
370 .queuecommand = ata_scsi_queuecmd,
371 .change_queue_depth = ata_scsi_change_queue_depth,
372 .can_queue = SIL24_MAX_CMDS,
373 .this_id = ATA_SHT_THIS_ID,
374 .sg_tablesize = LIBATA_MAX_PRD,
375 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
376 .emulated = ATA_SHT_EMULATED,
377 .use_clustering = ATA_SHT_USE_CLUSTERING,
378 .proc_name = DRV_NAME,
379 .dma_boundary = ATA_DMA_BOUNDARY,
380 .slave_configure = ata_scsi_slave_config,
381 .slave_destroy = ata_scsi_slave_destroy,
382 .bios_param = ata_std_bios_param,
383 #ifdef CONFIG_PM
384 .suspend = ata_scsi_device_suspend,
385 .resume = ata_scsi_device_resume,
386 #endif
387 };
388
389 static const struct ata_port_operations sil24_ops = {
390 .port_disable = ata_port_disable,
391
392 .dev_config = sil24_dev_config,
393
394 .check_status = sil24_check_status,
395 .check_altstatus = sil24_check_status,
396 .dev_select = ata_noop_dev_select,
397
398 .tf_read = sil24_tf_read,
399
400 .qc_prep = sil24_qc_prep,
401 .qc_issue = sil24_qc_issue,
402
403 .irq_clear = sil24_irq_clear,
404 .irq_on = ata_dummy_irq_on,
405 .irq_ack = ata_dummy_irq_ack,
406
407 .scr_read = sil24_scr_read,
408 .scr_write = sil24_scr_write,
409
410 .freeze = sil24_freeze,
411 .thaw = sil24_thaw,
412 .error_handler = sil24_error_handler,
413 .post_internal_cmd = sil24_post_internal_cmd,
414
415 .port_start = sil24_port_start,
416 };
417
418 /*
419 * Use bits 30-31 of port_flags to encode available port numbers.
420 * Current maxium is 4.
421 */
422 #define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30)
423 #define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1)
424
425 static const struct ata_port_info sil24_port_info[] = {
426 /* sil_3124 */
427 {
428 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(4) |
429 SIL24_FLAG_PCIX_IRQ_WOC,
430 .pio_mask = 0x1f, /* pio0-4 */
431 .mwdma_mask = 0x07, /* mwdma0-2 */
432 .udma_mask = 0x3f, /* udma0-5 */
433 .port_ops = &sil24_ops,
434 },
435 /* sil_3132 */
436 {
437 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(2),
438 .pio_mask = 0x1f, /* pio0-4 */
439 .mwdma_mask = 0x07, /* mwdma0-2 */
440 .udma_mask = 0x3f, /* udma0-5 */
441 .port_ops = &sil24_ops,
442 },
443 /* sil_3131/sil_3531 */
444 {
445 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(1),
446 .pio_mask = 0x1f, /* pio0-4 */
447 .mwdma_mask = 0x07, /* mwdma0-2 */
448 .udma_mask = 0x3f, /* udma0-5 */
449 .port_ops = &sil24_ops,
450 },
451 };
452
453 static int sil24_tag(int tag)
454 {
455 if (unlikely(ata_tag_internal(tag)))
456 return 0;
457 return tag;
458 }
459
460 static void sil24_dev_config(struct ata_device *dev)
461 {
462 void __iomem *port = dev->ap->ioaddr.cmd_addr;
463
464 if (dev->cdb_len == 16)
465 writel(PORT_CS_CDB16, port + PORT_CTRL_STAT);
466 else
467 writel(PORT_CS_CDB16, port + PORT_CTRL_CLR);
468 }
469
470 static inline void sil24_update_tf(struct ata_port *ap)
471 {
472 struct sil24_port_priv *pp = ap->private_data;
473 void __iomem *port = ap->ioaddr.cmd_addr;
474 struct sil24_prb __iomem *prb = port;
475 u8 fis[6 * 4];
476
477 memcpy_fromio(fis, prb->fis, 6 * 4);
478 ata_tf_from_fis(fis, &pp->tf);
479 }
480
481 static u8 sil24_check_status(struct ata_port *ap)
482 {
483 struct sil24_port_priv *pp = ap->private_data;
484 return pp->tf.command;
485 }
486
487 static int sil24_scr_map[] = {
488 [SCR_CONTROL] = 0,
489 [SCR_STATUS] = 1,
490 [SCR_ERROR] = 2,
491 [SCR_ACTIVE] = 3,
492 };
493
494 static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg)
495 {
496 void __iomem *scr_addr = ap->ioaddr.scr_addr;
497 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
498 void __iomem *addr;
499 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
500 return readl(scr_addr + sil24_scr_map[sc_reg] * 4);
501 }
502 return 0xffffffffU;
503 }
504
505 static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val)
506 {
507 void __iomem *scr_addr = ap->ioaddr.scr_addr;
508 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
509 void __iomem *addr;
510 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
511 writel(val, scr_addr + sil24_scr_map[sc_reg] * 4);
512 }
513 }
514
515 static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
516 {
517 struct sil24_port_priv *pp = ap->private_data;
518 *tf = pp->tf;
519 }
520
521 static int sil24_init_port(struct ata_port *ap)
522 {
523 void __iomem *port = ap->ioaddr.cmd_addr;
524 u32 tmp;
525
526 writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
527 ata_wait_register(port + PORT_CTRL_STAT,
528 PORT_CS_INIT, PORT_CS_INIT, 10, 100);
529 tmp = ata_wait_register(port + PORT_CTRL_STAT,
530 PORT_CS_RDY, 0, 10, 100);
531
532 if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY)
533 return -EIO;
534 return 0;
535 }
536
537 static int sil24_softreset(struct ata_port *ap, unsigned int *class)
538 {
539 void __iomem *port = ap->ioaddr.cmd_addr;
540 struct sil24_port_priv *pp = ap->private_data;
541 struct sil24_prb *prb = &pp->cmd_block[0].ata.prb;
542 dma_addr_t paddr = pp->cmd_block_dma;
543 u32 mask, irq_stat;
544 const char *reason;
545
546 DPRINTK("ENTER\n");
547
548 if (ata_port_offline(ap)) {
549 DPRINTK("PHY reports no device\n");
550 *class = ATA_DEV_NONE;
551 goto out;
552 }
553
554 /* put the port into known state */
555 if (sil24_init_port(ap)) {
556 reason ="port not ready";
557 goto err;
558 }
559
560 /* do SRST */
561 prb->ctrl = cpu_to_le16(PRB_CTRL_SRST);
562 prb->fis[1] = 0; /* no PMP yet */
563
564 writel((u32)paddr, port + PORT_CMD_ACTIVATE);
565 writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4);
566
567 mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT;
568 irq_stat = ata_wait_register(port + PORT_IRQ_STAT, mask, 0x0,
569 100, ATA_TMOUT_BOOT / HZ * 1000);
570
571 writel(irq_stat, port + PORT_IRQ_STAT); /* clear IRQs */
572 irq_stat >>= PORT_IRQ_RAW_SHIFT;
573
574 if (!(irq_stat & PORT_IRQ_COMPLETE)) {
575 if (irq_stat & PORT_IRQ_ERROR)
576 reason = "SRST command error";
577 else
578 reason = "timeout";
579 goto err;
580 }
581
582 sil24_update_tf(ap);
583 *class = ata_dev_classify(&pp->tf);
584
585 if (*class == ATA_DEV_UNKNOWN)
586 *class = ATA_DEV_NONE;
587
588 out:
589 DPRINTK("EXIT, class=%u\n", *class);
590 return 0;
591
592 err:
593 ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason);
594 return -EIO;
595 }
596
597 static int sil24_hardreset(struct ata_port *ap, unsigned int *class)
598 {
599 void __iomem *port = ap->ioaddr.cmd_addr;
600 const char *reason;
601 int tout_msec, rc;
602 u32 tmp;
603
604 /* sil24 does the right thing(tm) without any protection */
605 sata_set_spd(ap);
606
607 tout_msec = 100;
608 if (ata_port_online(ap))
609 tout_msec = 5000;
610
611 writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
612 tmp = ata_wait_register(port + PORT_CTRL_STAT,
613 PORT_CS_DEV_RST, PORT_CS_DEV_RST, 10, tout_msec);
614
615 /* SStatus oscillates between zero and valid status after
616 * DEV_RST, debounce it.
617 */
618 rc = sata_phy_debounce(ap, sata_deb_timing_long);
619 if (rc) {
620 reason = "PHY debouncing failed";
621 goto err;
622 }
623
624 if (tmp & PORT_CS_DEV_RST) {
625 if (ata_port_offline(ap))
626 return 0;
627 reason = "link not ready";
628 goto err;
629 }
630
631 /* Sil24 doesn't store signature FIS after hardreset, so we
632 * can't wait for BSY to clear. Some devices take a long time
633 * to get ready and those devices will choke if we don't wait
634 * for BSY clearance here. Tell libata to perform follow-up
635 * softreset.
636 */
637 return -EAGAIN;
638
639 err:
640 ata_port_printk(ap, KERN_ERR, "hardreset failed (%s)\n", reason);
641 return -EIO;
642 }
643
644 static inline void sil24_fill_sg(struct ata_queued_cmd *qc,
645 struct sil24_sge *sge)
646 {
647 struct scatterlist *sg;
648
649 ata_for_each_sg(sg, qc) {
650 sge->addr = cpu_to_le64(sg_dma_address(sg));
651 sge->cnt = cpu_to_le32(sg_dma_len(sg));
652 if (ata_sg_is_last(sg, qc))
653 sge->flags = cpu_to_le32(SGE_TRM);
654 else
655 sge->flags = 0;
656 sge++;
657 }
658 }
659
660 static void sil24_qc_prep(struct ata_queued_cmd *qc)
661 {
662 struct ata_port *ap = qc->ap;
663 struct sil24_port_priv *pp = ap->private_data;
664 union sil24_cmd_block *cb;
665 struct sil24_prb *prb;
666 struct sil24_sge *sge;
667 u16 ctrl = 0;
668
669 cb = &pp->cmd_block[sil24_tag(qc->tag)];
670
671 switch (qc->tf.protocol) {
672 case ATA_PROT_PIO:
673 case ATA_PROT_DMA:
674 case ATA_PROT_NCQ:
675 case ATA_PROT_NODATA:
676 prb = &cb->ata.prb;
677 sge = cb->ata.sge;
678 break;
679
680 case ATA_PROT_ATAPI:
681 case ATA_PROT_ATAPI_DMA:
682 case ATA_PROT_ATAPI_NODATA:
683 prb = &cb->atapi.prb;
684 sge = cb->atapi.sge;
685 memset(cb->atapi.cdb, 0, 32);
686 memcpy(cb->atapi.cdb, qc->cdb, qc->dev->cdb_len);
687
688 if (qc->tf.protocol != ATA_PROT_ATAPI_NODATA) {
689 if (qc->tf.flags & ATA_TFLAG_WRITE)
690 ctrl = PRB_CTRL_PACKET_WRITE;
691 else
692 ctrl = PRB_CTRL_PACKET_READ;
693 }
694 break;
695
696 default:
697 prb = NULL; /* shut up, gcc */
698 sge = NULL;
699 BUG();
700 }
701
702 prb->ctrl = cpu_to_le16(ctrl);
703 ata_tf_to_fis(&qc->tf, prb->fis, 0);
704
705 if (qc->flags & ATA_QCFLAG_DMAMAP)
706 sil24_fill_sg(qc, sge);
707 }
708
709 static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc)
710 {
711 struct ata_port *ap = qc->ap;
712 struct sil24_port_priv *pp = ap->private_data;
713 void __iomem *port = ap->ioaddr.cmd_addr;
714 unsigned int tag = sil24_tag(qc->tag);
715 dma_addr_t paddr;
716 void __iomem *activate;
717
718 paddr = pp->cmd_block_dma + tag * sizeof(*pp->cmd_block);
719 activate = port + PORT_CMD_ACTIVATE + tag * 8;
720
721 writel((u32)paddr, activate);
722 writel((u64)paddr >> 32, activate + 4);
723
724 return 0;
725 }
726
727 static void sil24_irq_clear(struct ata_port *ap)
728 {
729 /* unused */
730 }
731
732 static void sil24_freeze(struct ata_port *ap)
733 {
734 void __iomem *port = ap->ioaddr.cmd_addr;
735
736 /* Port-wide IRQ mask in HOST_CTRL doesn't really work, clear
737 * PORT_IRQ_ENABLE instead.
738 */
739 writel(0xffff, port + PORT_IRQ_ENABLE_CLR);
740 }
741
742 static void sil24_thaw(struct ata_port *ap)
743 {
744 void __iomem *port = ap->ioaddr.cmd_addr;
745 u32 tmp;
746
747 /* clear IRQ */
748 tmp = readl(port + PORT_IRQ_STAT);
749 writel(tmp, port + PORT_IRQ_STAT);
750
751 /* turn IRQ back on */
752 writel(DEF_PORT_IRQ, port + PORT_IRQ_ENABLE_SET);
753 }
754
755 static void sil24_error_intr(struct ata_port *ap)
756 {
757 void __iomem *port = ap->ioaddr.cmd_addr;
758 struct ata_eh_info *ehi = &ap->eh_info;
759 int freeze = 0;
760 u32 irq_stat;
761
762 /* on error, we need to clear IRQ explicitly */
763 irq_stat = readl(port + PORT_IRQ_STAT);
764 writel(irq_stat, port + PORT_IRQ_STAT);
765
766 /* first, analyze and record host port events */
767 ata_ehi_clear_desc(ehi);
768
769 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
770
771 if (irq_stat & (PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG)) {
772 ata_ehi_hotplugged(ehi);
773 ata_ehi_push_desc(ehi, ", %s",
774 irq_stat & PORT_IRQ_PHYRDY_CHG ?
775 "PHY RDY changed" : "device exchanged");
776 freeze = 1;
777 }
778
779 if (irq_stat & PORT_IRQ_UNK_FIS) {
780 ehi->err_mask |= AC_ERR_HSM;
781 ehi->action |= ATA_EH_SOFTRESET;
782 ata_ehi_push_desc(ehi , ", unknown FIS");
783 freeze = 1;
784 }
785
786 /* deal with command error */
787 if (irq_stat & PORT_IRQ_ERROR) {
788 struct sil24_cerr_info *ci = NULL;
789 unsigned int err_mask = 0, action = 0;
790 struct ata_queued_cmd *qc;
791 u32 cerr;
792
793 /* analyze CMD_ERR */
794 cerr = readl(port + PORT_CMD_ERR);
795 if (cerr < ARRAY_SIZE(sil24_cerr_db))
796 ci = &sil24_cerr_db[cerr];
797
798 if (ci && ci->desc) {
799 err_mask |= ci->err_mask;
800 action |= ci->action;
801 ata_ehi_push_desc(ehi, ", %s", ci->desc);
802 } else {
803 err_mask |= AC_ERR_OTHER;
804 action |= ATA_EH_SOFTRESET;
805 ata_ehi_push_desc(ehi, ", unknown command error %d",
806 cerr);
807 }
808
809 /* record error info */
810 qc = ata_qc_from_tag(ap, ap->active_tag);
811 if (qc) {
812 sil24_update_tf(ap);
813 qc->err_mask |= err_mask;
814 } else
815 ehi->err_mask |= err_mask;
816
817 ehi->action |= action;
818 }
819
820 /* freeze or abort */
821 if (freeze)
822 ata_port_freeze(ap);
823 else
824 ata_port_abort(ap);
825 }
826
827 static void sil24_finish_qc(struct ata_queued_cmd *qc)
828 {
829 if (qc->flags & ATA_QCFLAG_RESULT_TF)
830 sil24_update_tf(qc->ap);
831 }
832
833 static inline void sil24_host_intr(struct ata_port *ap)
834 {
835 void __iomem *port = ap->ioaddr.cmd_addr;
836 u32 slot_stat, qc_active;
837 int rc;
838
839 slot_stat = readl(port + PORT_SLOT_STAT);
840
841 if (unlikely(slot_stat & HOST_SSTAT_ATTN)) {
842 sil24_error_intr(ap);
843 return;
844 }
845
846 if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC)
847 writel(PORT_IRQ_COMPLETE, port + PORT_IRQ_STAT);
848
849 qc_active = slot_stat & ~HOST_SSTAT_ATTN;
850 rc = ata_qc_complete_multiple(ap, qc_active, sil24_finish_qc);
851 if (rc > 0)
852 return;
853 if (rc < 0) {
854 struct ata_eh_info *ehi = &ap->eh_info;
855 ehi->err_mask |= AC_ERR_HSM;
856 ehi->action |= ATA_EH_SOFTRESET;
857 ata_port_freeze(ap);
858 return;
859 }
860
861 if (ata_ratelimit())
862 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
863 "(slot_stat 0x%x active_tag %d sactive 0x%x)\n",
864 slot_stat, ap->active_tag, ap->sactive);
865 }
866
867 static irqreturn_t sil24_interrupt(int irq, void *dev_instance)
868 {
869 struct ata_host *host = dev_instance;
870 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
871 unsigned handled = 0;
872 u32 status;
873 int i;
874
875 status = readl(host_base + HOST_IRQ_STAT);
876
877 if (status == 0xffffffff) {
878 printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, "
879 "PCI fault or device removal?\n");
880 goto out;
881 }
882
883 if (!(status & IRQ_STAT_4PORTS))
884 goto out;
885
886 spin_lock(&host->lock);
887
888 for (i = 0; i < host->n_ports; i++)
889 if (status & (1 << i)) {
890 struct ata_port *ap = host->ports[i];
891 if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
892 sil24_host_intr(host->ports[i]);
893 handled++;
894 } else
895 printk(KERN_ERR DRV_NAME
896 ": interrupt from disabled port %d\n", i);
897 }
898
899 spin_unlock(&host->lock);
900 out:
901 return IRQ_RETVAL(handled);
902 }
903
904 static void sil24_error_handler(struct ata_port *ap)
905 {
906 struct ata_eh_context *ehc = &ap->eh_context;
907
908 if (sil24_init_port(ap)) {
909 ata_eh_freeze_port(ap);
910 ehc->i.action |= ATA_EH_HARDRESET;
911 }
912
913 /* perform recovery */
914 ata_do_eh(ap, ata_std_prereset, sil24_softreset, sil24_hardreset,
915 ata_std_postreset);
916 }
917
918 static void sil24_post_internal_cmd(struct ata_queued_cmd *qc)
919 {
920 struct ata_port *ap = qc->ap;
921
922 /* make DMA engine forget about the failed command */
923 if (qc->flags & ATA_QCFLAG_FAILED)
924 sil24_init_port(ap);
925 }
926
927 static int sil24_port_start(struct ata_port *ap)
928 {
929 struct device *dev = ap->host->dev;
930 struct sil24_port_priv *pp;
931 union sil24_cmd_block *cb;
932 size_t cb_size = sizeof(*cb) * SIL24_MAX_CMDS;
933 dma_addr_t cb_dma;
934 int rc;
935
936 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
937 if (!pp)
938 return -ENOMEM;
939
940 pp->tf.command = ATA_DRDY;
941
942 cb = dmam_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL);
943 if (!cb)
944 return -ENOMEM;
945 memset(cb, 0, cb_size);
946
947 rc = ata_pad_alloc(ap, dev);
948 if (rc)
949 return rc;
950
951 pp->cmd_block = cb;
952 pp->cmd_block_dma = cb_dma;
953
954 ap->private_data = pp;
955
956 return 0;
957 }
958
959 static void sil24_init_controller(struct ata_host *host)
960 {
961 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
962 void __iomem *port_base = host->iomap[SIL24_PORT_BAR];
963 u32 tmp;
964 int i;
965
966 /* GPIO off */
967 writel(0, host_base + HOST_FLASH_CMD);
968
969 /* clear global reset & mask interrupts during initialization */
970 writel(0, host_base + HOST_CTRL);
971
972 /* init ports */
973 for (i = 0; i < host->n_ports; i++) {
974 void __iomem *port = port_base + i * PORT_REGS_SIZE;
975
976 /* Initial PHY setting */
977 writel(0x20c, port + PORT_PHY_CFG);
978
979 /* Clear port RST */
980 tmp = readl(port + PORT_CTRL_STAT);
981 if (tmp & PORT_CS_PORT_RST) {
982 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
983 tmp = ata_wait_register(port + PORT_CTRL_STAT,
984 PORT_CS_PORT_RST,
985 PORT_CS_PORT_RST, 10, 100);
986 if (tmp & PORT_CS_PORT_RST)
987 dev_printk(KERN_ERR, host->dev,
988 "failed to clear port RST\n");
989 }
990
991 /* Configure IRQ WoC */
992 if (host->ports[0]->flags & SIL24_FLAG_PCIX_IRQ_WOC)
993 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_STAT);
994 else
995 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
996
997 /* Zero error counters. */
998 writel(0x8000, port + PORT_DECODE_ERR_THRESH);
999 writel(0x8000, port + PORT_CRC_ERR_THRESH);
1000 writel(0x8000, port + PORT_HSHK_ERR_THRESH);
1001 writel(0x0000, port + PORT_DECODE_ERR_CNT);
1002 writel(0x0000, port + PORT_CRC_ERR_CNT);
1003 writel(0x0000, port + PORT_HSHK_ERR_CNT);
1004
1005 /* Always use 64bit activation */
1006 writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);
1007
1008 /* Clear port multiplier enable and resume bits */
1009 writel(PORT_CS_PMP_EN | PORT_CS_PMP_RESUME,
1010 port + PORT_CTRL_CLR);
1011 }
1012
1013 /* Turn on interrupts */
1014 writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL);
1015 }
1016
1017 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1018 {
1019 static int printed_version = 0;
1020 struct ata_port_info pi = sil24_port_info[ent->driver_data];
1021 const struct ata_port_info *ppi[] = { &pi, NULL };
1022 void __iomem * const *iomap;
1023 struct ata_host *host;
1024 int i, rc;
1025 u32 tmp;
1026
1027 if (!printed_version++)
1028 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1029
1030 /* acquire resources */
1031 rc = pcim_enable_device(pdev);
1032 if (rc)
1033 return rc;
1034
1035 rc = pcim_iomap_regions(pdev,
1036 (1 << SIL24_HOST_BAR) | (1 << SIL24_PORT_BAR),
1037 DRV_NAME);
1038 if (rc)
1039 return rc;
1040 iomap = pcim_iomap_table(pdev);
1041
1042 /* apply workaround for completion IRQ loss on PCI-X errata */
1043 if (pi.flags & SIL24_FLAG_PCIX_IRQ_WOC) {
1044 tmp = readl(iomap[SIL24_HOST_BAR] + HOST_CTRL);
1045 if (tmp & (HOST_CTRL_TRDY | HOST_CTRL_STOP | HOST_CTRL_DEVSEL))
1046 dev_printk(KERN_INFO, &pdev->dev,
1047 "Applying completion IRQ loss on PCI-X "
1048 "errata fix\n");
1049 else
1050 pi.flags &= ~SIL24_FLAG_PCIX_IRQ_WOC;
1051 }
1052
1053 /* allocate and fill host */
1054 host = ata_host_alloc_pinfo(&pdev->dev, ppi,
1055 SIL24_FLAG2NPORTS(ppi[0]->flags));
1056 if (!host)
1057 return -ENOMEM;
1058 host->iomap = iomap;
1059
1060 for (i = 0; i < host->n_ports; i++) {
1061 void __iomem *port = iomap[SIL24_PORT_BAR] + i * PORT_REGS_SIZE;
1062
1063 host->ports[i]->ioaddr.cmd_addr = port;
1064 host->ports[i]->ioaddr.scr_addr = port + PORT_SCONTROL;
1065
1066 ata_std_ports(&host->ports[i]->ioaddr);
1067 }
1068
1069 /* configure and activate the device */
1070 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1071 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1072 if (rc) {
1073 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1074 if (rc) {
1075 dev_printk(KERN_ERR, &pdev->dev,
1076 "64-bit DMA enable failed\n");
1077 return rc;
1078 }
1079 }
1080 } else {
1081 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1082 if (rc) {
1083 dev_printk(KERN_ERR, &pdev->dev,
1084 "32-bit DMA enable failed\n");
1085 return rc;
1086 }
1087 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1088 if (rc) {
1089 dev_printk(KERN_ERR, &pdev->dev,
1090 "32-bit consistent DMA enable failed\n");
1091 return rc;
1092 }
1093 }
1094
1095 sil24_init_controller(host);
1096
1097 pci_set_master(pdev);
1098 return ata_host_activate(host, pdev->irq, sil24_interrupt, IRQF_SHARED,
1099 &sil24_sht);
1100 }
1101
1102 #ifdef CONFIG_PM
1103 static int sil24_pci_device_resume(struct pci_dev *pdev)
1104 {
1105 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1106 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
1107 int rc;
1108
1109 rc = ata_pci_device_do_resume(pdev);
1110 if (rc)
1111 return rc;
1112
1113 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND)
1114 writel(HOST_CTRL_GLOBAL_RST, host_base + HOST_CTRL);
1115
1116 sil24_init_controller(host);
1117
1118 ata_host_resume(host);
1119
1120 return 0;
1121 }
1122 #endif
1123
1124 static int __init sil24_init(void)
1125 {
1126 return pci_register_driver(&sil24_pci_driver);
1127 }
1128
1129 static void __exit sil24_exit(void)
1130 {
1131 pci_unregister_driver(&sil24_pci_driver);
1132 }
1133
1134 MODULE_AUTHOR("Tejun Heo");
1135 MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver");
1136 MODULE_LICENSE("GPL");
1137 MODULE_DEVICE_TABLE(pci, sil24_pci_tbl);
1138
1139 module_init(sil24_init);
1140 module_exit(sil24_exit);
WRT350N Kernel Patches