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[POWERPC] Use menuconfig objects II - Macintosh
[wrt350n-kernel.git] / drivers / char / drm / i810_dma.c
blob603d17fd2d6912e556250a758b7e3336b96bb3b4
1 /* i810_dma.c -- DMA support for the i810 -*- linux-c -*-
2 * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
3 *
4 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 *
27 * Authors: Rickard E. (Rik) Faith <faith@valinux.com>
28 * Jeff Hartmann <jhartmann@valinux.com>
29 * Keith Whitwell <keith@tungstengraphics.com>
30 *
31 */
32
33 #include "drmP.h"
34 #include "drm.h"
35 #include "i810_drm.h"
36 #include "i810_drv.h"
37 #include <linux/interrupt.h> /* For task queue support */
38 #include <linux/delay.h>
39 #include <linux/pagemap.h>
40
41 #define I810_BUF_FREE 2
42 #define I810_BUF_CLIENT 1
43 #define I810_BUF_HARDWARE 0
44
45 #define I810_BUF_UNMAPPED 0
46 #define I810_BUF_MAPPED 1
47
48 static drm_buf_t *i810_freelist_get(drm_device_t * dev)
49 {
50 drm_device_dma_t *dma = dev->dma;
51 int i;
52 int used;
53
54 /* Linear search might not be the best solution */
55
56 for (i = 0; i < dma->buf_count; i++) {
57 drm_buf_t *buf = dma->buflist[i];
58 drm_i810_buf_priv_t *buf_priv = buf->dev_private;
59 /* In use is already a pointer */
60 used = cmpxchg(buf_priv->in_use, I810_BUF_FREE,
61 I810_BUF_CLIENT);
62 if (used == I810_BUF_FREE) {
63 return buf;
64 }
65 }
66 return NULL;
67 }
68
69 /* This should only be called if the buffer is not sent to the hardware
70 * yet, the hardware updates in use for us once its on the ring buffer.
71 */
72
73 static int i810_freelist_put(drm_device_t * dev, drm_buf_t * buf)
74 {
75 drm_i810_buf_priv_t *buf_priv = buf->dev_private;
76 int used;
77
78 /* In use is already a pointer */
79 used = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, I810_BUF_FREE);
80 if (used != I810_BUF_CLIENT) {
81 DRM_ERROR("Freeing buffer thats not in use : %d\n", buf->idx);
82 return -EINVAL;
83 }
84
85 return 0;
86 }
87
88 static int i810_mmap_buffers(struct file *filp, struct vm_area_struct *vma)
89 {
90 drm_file_t *priv = filp->private_data;
91 drm_device_t *dev;
92 drm_i810_private_t *dev_priv;
93 drm_buf_t *buf;
94 drm_i810_buf_priv_t *buf_priv;
95
96 lock_kernel();
97 dev = priv->head->dev;
98 dev_priv = dev->dev_private;
99 buf = dev_priv->mmap_buffer;
100 buf_priv = buf->dev_private;
101
102 vma->vm_flags |= (VM_IO | VM_DONTCOPY);
103 vma->vm_file = filp;
104
105 buf_priv->currently_mapped = I810_BUF_MAPPED;
106 unlock_kernel();
107
108 if (io_remap_pfn_range(vma, vma->vm_start,
109 vma->vm_pgoff,
110 vma->vm_end - vma->vm_start, vma->vm_page_prot))
111 return -EAGAIN;
112 return 0;
113 }
114
115 static const struct file_operations i810_buffer_fops = {
116 .open = drm_open,
117 .release = drm_release,
118 .ioctl = drm_ioctl,
119 .mmap = i810_mmap_buffers,
120 .fasync = drm_fasync,
121 };
122
123 static int i810_map_buffer(drm_buf_t * buf, struct file *filp)
124 {
125 drm_file_t *priv = filp->private_data;
126 drm_device_t *dev = priv->head->dev;
127 drm_i810_buf_priv_t *buf_priv = buf->dev_private;
128 drm_i810_private_t *dev_priv = dev->dev_private;
129 const struct file_operations *old_fops;
130 int retcode = 0;
131
132 if (buf_priv->currently_mapped == I810_BUF_MAPPED)
133 return -EINVAL;
134
135 down_write(&current->mm->mmap_sem);
136 old_fops = filp->f_op;
137 filp->f_op = &i810_buffer_fops;
138 dev_priv->mmap_buffer = buf;
139 buf_priv->virtual = (void *)do_mmap(filp, 0, buf->total,
140 PROT_READ | PROT_WRITE,
141 MAP_SHARED, buf->bus_address);
142 dev_priv->mmap_buffer = NULL;
143 filp->f_op = old_fops;
144 if (IS_ERR(buf_priv->virtual)) {
145 /* Real error */
146 DRM_ERROR("mmap error\n");
147 retcode = PTR_ERR(buf_priv->virtual);
148 buf_priv->virtual = NULL;
149 }
150 up_write(&current->mm->mmap_sem);
151
152 return retcode;
153 }
154
155 static int i810_unmap_buffer(drm_buf_t * buf)
156 {
157 drm_i810_buf_priv_t *buf_priv = buf->dev_private;
158 int retcode = 0;
159
160 if (buf_priv->currently_mapped != I810_BUF_MAPPED)
161 return -EINVAL;
162
163 down_write(&current->mm->mmap_sem);
164 retcode = do_munmap(current->mm,
165 (unsigned long)buf_priv->virtual,
166 (size_t) buf->total);
167 up_write(&current->mm->mmap_sem);
168
169 buf_priv->currently_mapped = I810_BUF_UNMAPPED;
170 buf_priv->virtual = NULL;
171
172 return retcode;
173 }
174
175 static int i810_dma_get_buffer(drm_device_t * dev, drm_i810_dma_t * d,
176 struct file *filp)
177 {
178 drm_buf_t *buf;
179 drm_i810_buf_priv_t *buf_priv;
180 int retcode = 0;
181
182 buf = i810_freelist_get(dev);
183 if (!buf) {
184 retcode = -ENOMEM;
185 DRM_DEBUG("retcode=%d\n", retcode);
186 return retcode;
187 }
188
189 retcode = i810_map_buffer(buf, filp);
190 if (retcode) {
191 i810_freelist_put(dev, buf);
192 DRM_ERROR("mapbuf failed, retcode %d\n", retcode);
193 return retcode;
194 }
195 buf->filp = filp;
196 buf_priv = buf->dev_private;
197 d->granted = 1;
198 d->request_idx = buf->idx;
199 d->request_size = buf->total;
200 d->virtual = buf_priv->virtual;
201
202 return retcode;
203 }
204
205 static int i810_dma_cleanup(drm_device_t * dev)
206 {
207 drm_device_dma_t *dma = dev->dma;
208
209 /* Make sure interrupts are disabled here because the uninstall ioctl
210 * may not have been called from userspace and after dev_private
211 * is freed, it's too late.
212 */
213 if (drm_core_check_feature(dev, DRIVER_HAVE_IRQ) && dev->irq_enabled)
214 drm_irq_uninstall(dev);
215
216 if (dev->dev_private) {
217 int i;
218 drm_i810_private_t *dev_priv =
219 (drm_i810_private_t *) dev->dev_private;
220
221 if (dev_priv->ring.virtual_start) {
222 drm_core_ioremapfree(&dev_priv->ring.map, dev);
223 }
224 if (dev_priv->hw_status_page) {
225 pci_free_consistent(dev->pdev, PAGE_SIZE,
226 dev_priv->hw_status_page,
227 dev_priv->dma_status_page);
228 /* Need to rewrite hardware status page */
229 I810_WRITE(0x02080, 0x1ffff000);
230 }
231 drm_free(dev->dev_private, sizeof(drm_i810_private_t),
232 DRM_MEM_DRIVER);
233 dev->dev_private = NULL;
234
235 for (i = 0; i < dma->buf_count; i++) {
236 drm_buf_t *buf = dma->buflist[i];
237 drm_i810_buf_priv_t *buf_priv = buf->dev_private;
238
239 if (buf_priv->kernel_virtual && buf->total)
240 drm_core_ioremapfree(&buf_priv->map, dev);
241 }
242 }
243 return 0;
244 }
245
246 static int i810_wait_ring(drm_device_t * dev, int n)
247 {
248 drm_i810_private_t *dev_priv = dev->dev_private;
249 drm_i810_ring_buffer_t *ring = &(dev_priv->ring);
250 int iters = 0;
251 unsigned long end;
252 unsigned int last_head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
253
254 end = jiffies + (HZ * 3);
255 while (ring->space < n) {
256 ring->head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
257 ring->space = ring->head - (ring->tail + 8);
258 if (ring->space < 0)
259 ring->space += ring->Size;
260
261 if (ring->head != last_head) {
262 end = jiffies + (HZ * 3);
263 last_head = ring->head;
264 }
265
266 iters++;
267 if (time_before(end, jiffies)) {
268 DRM_ERROR("space: %d wanted %d\n", ring->space, n);
269 DRM_ERROR("lockup\n");
270 goto out_wait_ring;
271 }
272 udelay(1);
273 }
274
275 out_wait_ring:
276 return iters;
277 }
278
279 static void i810_kernel_lost_context(drm_device_t * dev)
280 {
281 drm_i810_private_t *dev_priv = dev->dev_private;
282 drm_i810_ring_buffer_t *ring = &(dev_priv->ring);
283
284 ring->head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
285 ring->tail = I810_READ(LP_RING + RING_TAIL);
286 ring->space = ring->head - (ring->tail + 8);
287 if (ring->space < 0)
288 ring->space += ring->Size;
289 }
290
291 static int i810_freelist_init(drm_device_t * dev, drm_i810_private_t * dev_priv)
292 {
293 drm_device_dma_t *dma = dev->dma;
294 int my_idx = 24;
295 u32 *hw_status = (u32 *) (dev_priv->hw_status_page + my_idx);
296 int i;
297
298 if (dma->buf_count > 1019) {
299 /* Not enough space in the status page for the freelist */
300 return -EINVAL;
301 }
302
303 for (i = 0; i < dma->buf_count; i++) {
304 drm_buf_t *buf = dma->buflist[i];
305 drm_i810_buf_priv_t *buf_priv = buf->dev_private;
306
307 buf_priv->in_use = hw_status++;
308 buf_priv->my_use_idx = my_idx;
309 my_idx += 4;
310
311 *buf_priv->in_use = I810_BUF_FREE;
312
313 buf_priv->map.offset = buf->bus_address;
314 buf_priv->map.size = buf->total;
315 buf_priv->map.type = _DRM_AGP;
316 buf_priv->map.flags = 0;
317 buf_priv->map.mtrr = 0;
318
319 drm_core_ioremap(&buf_priv->map, dev);
320 buf_priv->kernel_virtual = buf_priv->map.handle;
321
322 }
323 return 0;
324 }
325
326 static int i810_dma_initialize(drm_device_t * dev,
327 drm_i810_private_t * dev_priv,
328 drm_i810_init_t * init)
329 {
330 struct list_head *list;
331
332 memset(dev_priv, 0, sizeof(drm_i810_private_t));
333
334 list_for_each(list, &dev->maplist->head) {
335 drm_map_list_t *r_list = list_entry(list, drm_map_list_t, head);
336 if (r_list->map &&
337 r_list->map->type == _DRM_SHM &&
338 r_list->map->flags & _DRM_CONTAINS_LOCK) {
339 dev_priv->sarea_map = r_list->map;
340 break;
341 }
342 }
343 if (!dev_priv->sarea_map) {
344 dev->dev_private = (void *)dev_priv;
345 i810_dma_cleanup(dev);
346 DRM_ERROR("can not find sarea!\n");
347 return -EINVAL;
348 }
349 dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset);
350 if (!dev_priv->mmio_map) {
351 dev->dev_private = (void *)dev_priv;
352 i810_dma_cleanup(dev);
353 DRM_ERROR("can not find mmio map!\n");
354 return -EINVAL;
355 }
356 dev->agp_buffer_token = init->buffers_offset;
357 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
358 if (!dev->agp_buffer_map) {
359 dev->dev_private = (void *)dev_priv;
360 i810_dma_cleanup(dev);
361 DRM_ERROR("can not find dma buffer map!\n");
362 return -EINVAL;
363 }
364
365 dev_priv->sarea_priv = (drm_i810_sarea_t *)
366 ((u8 *) dev_priv->sarea_map->handle + init->sarea_priv_offset);
367
368 dev_priv->ring.Start = init->ring_start;
369 dev_priv->ring.End = init->ring_end;
370 dev_priv->ring.Size = init->ring_size;
371
372 dev_priv->ring.map.offset = dev->agp->base + init->ring_start;
373 dev_priv->ring.map.size = init->ring_size;
374 dev_priv->ring.map.type = _DRM_AGP;
375 dev_priv->ring.map.flags = 0;
376 dev_priv->ring.map.mtrr = 0;
377
378 drm_core_ioremap(&dev_priv->ring.map, dev);
379
380 if (dev_priv->ring.map.handle == NULL) {
381 dev->dev_private = (void *)dev_priv;
382 i810_dma_cleanup(dev);
383 DRM_ERROR("can not ioremap virtual address for"
384 " ring buffer\n");
385 return DRM_ERR(ENOMEM);
386 }
387
388 dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
389
390 dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
391
392 dev_priv->w = init->w;
393 dev_priv->h = init->h;
394 dev_priv->pitch = init->pitch;
395 dev_priv->back_offset = init->back_offset;
396 dev_priv->depth_offset = init->depth_offset;
397 dev_priv->front_offset = init->front_offset;
398
399 dev_priv->overlay_offset = init->overlay_offset;
400 dev_priv->overlay_physical = init->overlay_physical;
401
402 dev_priv->front_di1 = init->front_offset | init->pitch_bits;
403 dev_priv->back_di1 = init->back_offset | init->pitch_bits;
404 dev_priv->zi1 = init->depth_offset | init->pitch_bits;
405
406 /* Program Hardware Status Page */
407 dev_priv->hw_status_page =
408 pci_alloc_consistent(dev->pdev, PAGE_SIZE,
409 &dev_priv->dma_status_page);
410 if (!dev_priv->hw_status_page) {
411 dev->dev_private = (void *)dev_priv;
412 i810_dma_cleanup(dev);
413 DRM_ERROR("Can not allocate hardware status page\n");
414 return -ENOMEM;
415 }
416 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
417 DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
418
419 I810_WRITE(0x02080, dev_priv->dma_status_page);
420 DRM_DEBUG("Enabled hardware status page\n");
421
422 /* Now we need to init our freelist */
423 if (i810_freelist_init(dev, dev_priv) != 0) {
424 dev->dev_private = (void *)dev_priv;
425 i810_dma_cleanup(dev);
426 DRM_ERROR("Not enough space in the status page for"
427 " the freelist\n");
428 return -ENOMEM;
429 }
430 dev->dev_private = (void *)dev_priv;
431
432 return 0;
433 }
434
435 /* i810 DRM version 1.1 used a smaller init structure with different
436 * ordering of values than is currently used (drm >= 1.2). There is
437 * no defined way to detect the XFree version to correct this problem,
438 * however by checking using this procedure we can detect the correct
439 * thing to do.
440 *
441 * #1 Read the Smaller init structure from user-space
442 * #2 Verify the overlay_physical is a valid physical address, or NULL
443 * If it isn't then we have a v1.1 client. Fix up params.
444 * If it is, then we have a 1.2 client... get the rest of the data.
445 */
446 static int i810_dma_init_compat(drm_i810_init_t * init, unsigned long arg)
447 {
448
449 /* Get v1.1 init data */
450 if (copy_from_user(init, (drm_i810_pre12_init_t __user *) arg,
451 sizeof(drm_i810_pre12_init_t))) {
452 return -EFAULT;
453 }
454
455 if ((!init->overlay_physical) || (init->overlay_physical > 4096)) {
456
457 /* This is a v1.2 client, just get the v1.2 init data */
458 DRM_INFO("Using POST v1.2 init.\n");
459 if (copy_from_user(init, (drm_i810_init_t __user *) arg,
460 sizeof(drm_i810_init_t))) {
461 return -EFAULT;
462 }
463 } else {
464
465 /* This is a v1.1 client, fix the params */
466 DRM_INFO("Using PRE v1.2 init.\n");
467 init->pitch_bits = init->h;
468 init->pitch = init->w;
469 init->h = init->overlay_physical;
470 init->w = init->overlay_offset;
471 init->overlay_physical = 0;
472 init->overlay_offset = 0;
473 }
474
475 return 0;
476 }
477
478 static int i810_dma_init(struct inode *inode, struct file *filp,
479 unsigned int cmd, unsigned long arg)
480 {
481 drm_file_t *priv = filp->private_data;
482 drm_device_t *dev = priv->head->dev;
483 drm_i810_private_t *dev_priv;
484 drm_i810_init_t init;
485 int retcode = 0;
486
487 /* Get only the init func */
488 if (copy_from_user
489 (&init, (void __user *)arg, sizeof(drm_i810_init_func_t)))
490 return -EFAULT;
491
492 switch (init.func) {
493 case I810_INIT_DMA:
494 /* This case is for backward compatibility. It
495 * handles XFree 4.1.0 and 4.2.0, and has to
496 * do some parameter checking as described below.
497 * It will someday go away.
498 */
499 retcode = i810_dma_init_compat(&init, arg);
500 if (retcode)
501 return retcode;
502
503 dev_priv = drm_alloc(sizeof(drm_i810_private_t),
504 DRM_MEM_DRIVER);
505 if (dev_priv == NULL)
506 return -ENOMEM;
507 retcode = i810_dma_initialize(dev, dev_priv, &init);
508 break;
509
510 default:
511 case I810_INIT_DMA_1_4:
512 DRM_INFO("Using v1.4 init.\n");
513 if (copy_from_user(&init, (drm_i810_init_t __user *) arg,
514 sizeof(drm_i810_init_t))) {
515 return -EFAULT;
516 }
517 dev_priv = drm_alloc(sizeof(drm_i810_private_t),
518 DRM_MEM_DRIVER);
519 if (dev_priv == NULL)
520 return -ENOMEM;
521 retcode = i810_dma_initialize(dev, dev_priv, &init);
522 break;
523
524 case I810_CLEANUP_DMA:
525 DRM_INFO("DMA Cleanup\n");
526 retcode = i810_dma_cleanup(dev);
527 break;
528 }
529
530 return retcode;
531 }
532
533 /* Most efficient way to verify state for the i810 is as it is
534 * emitted. Non-conformant state is silently dropped.
535 *
536 * Use 'volatile' & local var tmp to force the emitted values to be
537 * identical to the verified ones.
538 */
539 static void i810EmitContextVerified(drm_device_t * dev,
540 volatile unsigned int *code)
541 {
542 drm_i810_private_t *dev_priv = dev->dev_private;
543 int i, j = 0;
544 unsigned int tmp;
545 RING_LOCALS;
546
547 BEGIN_LP_RING(I810_CTX_SETUP_SIZE);
548
549 OUT_RING(GFX_OP_COLOR_FACTOR);
550 OUT_RING(code[I810_CTXREG_CF1]);
551
552 OUT_RING(GFX_OP_STIPPLE);
553 OUT_RING(code[I810_CTXREG_ST1]);
554
555 for (i = 4; i < I810_CTX_SETUP_SIZE; i++) {
556 tmp = code[i];
557
558 if ((tmp & (7 << 29)) == (3 << 29) &&
559 (tmp & (0x1f << 24)) < (0x1d << 24)) {
560 OUT_RING(tmp);
561 j++;
562 } else
563 printk("constext state dropped!!!\n");
564 }
565
566 if (j & 1)
567 OUT_RING(0);
568
569 ADVANCE_LP_RING();
570 }
571
572 static void i810EmitTexVerified(drm_device_t * dev, volatile unsigned int *code)
573 {
574 drm_i810_private_t *dev_priv = dev->dev_private;
575 int i, j = 0;
576 unsigned int tmp;
577 RING_LOCALS;
578
579 BEGIN_LP_RING(I810_TEX_SETUP_SIZE);
580
581 OUT_RING(GFX_OP_MAP_INFO);
582 OUT_RING(code[I810_TEXREG_MI1]);
583 OUT_RING(code[I810_TEXREG_MI2]);
584 OUT_RING(code[I810_TEXREG_MI3]);
585
586 for (i = 4; i < I810_TEX_SETUP_SIZE; i++) {
587 tmp = code[i];
588
589 if ((tmp & (7 << 29)) == (3 << 29) &&
590 (tmp & (0x1f << 24)) < (0x1d << 24)) {
591 OUT_RING(tmp);
592 j++;
593 } else
594 printk("texture state dropped!!!\n");
595 }
596
597 if (j & 1)
598 OUT_RING(0);
599
600 ADVANCE_LP_RING();
601 }
602
603 /* Need to do some additional checking when setting the dest buffer.
604 */
605 static void i810EmitDestVerified(drm_device_t * dev,
606 volatile unsigned int *code)
607 {
608 drm_i810_private_t *dev_priv = dev->dev_private;
609 unsigned int tmp;
610 RING_LOCALS;
611
612 BEGIN_LP_RING(I810_DEST_SETUP_SIZE + 2);
613
614 tmp = code[I810_DESTREG_DI1];
615 if (tmp == dev_priv->front_di1 || tmp == dev_priv->back_di1) {
616 OUT_RING(CMD_OP_DESTBUFFER_INFO);
617 OUT_RING(tmp);
618 } else
619 DRM_DEBUG("bad di1 %x (allow %x or %x)\n",
620 tmp, dev_priv->front_di1, dev_priv->back_di1);
621
622 /* invarient:
623 */
624 OUT_RING(CMD_OP_Z_BUFFER_INFO);
625 OUT_RING(dev_priv->zi1);
626
627 OUT_RING(GFX_OP_DESTBUFFER_VARS);
628 OUT_RING(code[I810_DESTREG_DV1]);
629
630 OUT_RING(GFX_OP_DRAWRECT_INFO);
631 OUT_RING(code[I810_DESTREG_DR1]);
632 OUT_RING(code[I810_DESTREG_DR2]);
633 OUT_RING(code[I810_DESTREG_DR3]);
634 OUT_RING(code[I810_DESTREG_DR4]);
635 OUT_RING(0);
636
637 ADVANCE_LP_RING();
638 }
639
640 static void i810EmitState(drm_device_t * dev)
641 {
642 drm_i810_private_t *dev_priv = dev->dev_private;
643 drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
644 unsigned int dirty = sarea_priv->dirty;
645
646 DRM_DEBUG("%s %x\n", __FUNCTION__, dirty);
647
648 if (dirty & I810_UPLOAD_BUFFERS) {
649 i810EmitDestVerified(dev, sarea_priv->BufferState);
650 sarea_priv->dirty &= ~I810_UPLOAD_BUFFERS;
651 }
652
653 if (dirty & I810_UPLOAD_CTX) {
654 i810EmitContextVerified(dev, sarea_priv->ContextState);
655 sarea_priv->dirty &= ~I810_UPLOAD_CTX;
656 }
657
658 if (dirty & I810_UPLOAD_TEX0) {
659 i810EmitTexVerified(dev, sarea_priv->TexState[0]);
660 sarea_priv->dirty &= ~I810_UPLOAD_TEX0;
661 }
662
663 if (dirty & I810_UPLOAD_TEX1) {
664 i810EmitTexVerified(dev, sarea_priv->TexState[1]);
665 sarea_priv->dirty &= ~I810_UPLOAD_TEX1;
666 }
667 }
668
669 /* need to verify
670 */
671 static void i810_dma_dispatch_clear(drm_device_t * dev, int flags,
672 unsigned int clear_color,
673 unsigned int clear_zval)
674 {
675 drm_i810_private_t *dev_priv = dev->dev_private;
676 drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
677 int nbox = sarea_priv->nbox;
678 drm_clip_rect_t *pbox = sarea_priv->boxes;
679 int pitch = dev_priv->pitch;
680 int cpp = 2;
681 int i;
682 RING_LOCALS;
683
684 if (dev_priv->current_page == 1) {
685 unsigned int tmp = flags;
686
687 flags &= ~(I810_FRONT | I810_BACK);
688 if (tmp & I810_FRONT)
689 flags |= I810_BACK;
690 if (tmp & I810_BACK)
691 flags |= I810_FRONT;
692 }
693
694 i810_kernel_lost_context(dev);
695
696 if (nbox > I810_NR_SAREA_CLIPRECTS)
697 nbox = I810_NR_SAREA_CLIPRECTS;
698
699 for (i = 0; i < nbox; i++, pbox++) {
700 unsigned int x = pbox->x1;
701 unsigned int y = pbox->y1;
702 unsigned int width = (pbox->x2 - x) * cpp;
703 unsigned int height = pbox->y2 - y;
704 unsigned int start = y * pitch + x * cpp;
705
706 if (pbox->x1 > pbox->x2 ||
707 pbox->y1 > pbox->y2 ||
708 pbox->x2 > dev_priv->w || pbox->y2 > dev_priv->h)
709 continue;
710
711 if (flags & I810_FRONT) {
712 BEGIN_LP_RING(6);
713 OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3);
714 OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch);
715 OUT_RING((height << 16) | width);
716 OUT_RING(start);
717 OUT_RING(clear_color);
718 OUT_RING(0);
719 ADVANCE_LP_RING();
720 }
721
722 if (flags & I810_BACK) {
723 BEGIN_LP_RING(6);
724 OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3);
725 OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch);
726 OUT_RING((height << 16) | width);
727 OUT_RING(dev_priv->back_offset + start);
728 OUT_RING(clear_color);
729 OUT_RING(0);
730 ADVANCE_LP_RING();
731 }
732
733 if (flags & I810_DEPTH) {
734 BEGIN_LP_RING(6);
735 OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3);
736 OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch);
737 OUT_RING((height << 16) | width);
738 OUT_RING(dev_priv->depth_offset + start);
739 OUT_RING(clear_zval);
740 OUT_RING(0);
741 ADVANCE_LP_RING();
742 }
743 }
744 }
745
746 static void i810_dma_dispatch_swap(drm_device_t * dev)
747 {
748 drm_i810_private_t *dev_priv = dev->dev_private;
749 drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
750 int nbox = sarea_priv->nbox;
751 drm_clip_rect_t *pbox = sarea_priv->boxes;
752 int pitch = dev_priv->pitch;
753 int cpp = 2;
754 int i;
755 RING_LOCALS;
756
757 DRM_DEBUG("swapbuffers\n");
758
759 i810_kernel_lost_context(dev);
760
761 if (nbox > I810_NR_SAREA_CLIPRECTS)
762 nbox = I810_NR_SAREA_CLIPRECTS;
763
764 for (i = 0; i < nbox; i++, pbox++) {
765 unsigned int w = pbox->x2 - pbox->x1;
766 unsigned int h = pbox->y2 - pbox->y1;
767 unsigned int dst = pbox->x1 * cpp + pbox->y1 * pitch;
768 unsigned int start = dst;
769
770 if (pbox->x1 > pbox->x2 ||
771 pbox->y1 > pbox->y2 ||
772 pbox->x2 > dev_priv->w || pbox->y2 > dev_priv->h)
773 continue;
774
775 BEGIN_LP_RING(6);
776 OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_SRC_COPY_BLT | 0x4);
777 OUT_RING(pitch | (0xCC << 16));
778 OUT_RING((h << 16) | (w * cpp));
779 if (dev_priv->current_page == 0)
780 OUT_RING(dev_priv->front_offset + start);
781 else
782 OUT_RING(dev_priv->back_offset + start);
783 OUT_RING(pitch);
784 if (dev_priv->current_page == 0)
785 OUT_RING(dev_priv->back_offset + start);
786 else
787 OUT_RING(dev_priv->front_offset + start);
788 ADVANCE_LP_RING();
789 }
790 }
791
792 static void i810_dma_dispatch_vertex(drm_device_t * dev,
793 drm_buf_t * buf, int discard, int used)
794 {
795 drm_i810_private_t *dev_priv = dev->dev_private;
796 drm_i810_buf_priv_t *buf_priv = buf->dev_private;
797 drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
798 drm_clip_rect_t *box = sarea_priv->boxes;
799 int nbox = sarea_priv->nbox;
800 unsigned long address = (unsigned long)buf->bus_address;
801 unsigned long start = address - dev->agp->base;
802 int i = 0;
803 RING_LOCALS;
804
805 i810_kernel_lost_context(dev);
806
807 if (nbox > I810_NR_SAREA_CLIPRECTS)
808 nbox = I810_NR_SAREA_CLIPRECTS;
809
810 if (used > 4 * 1024)
811 used = 0;
812
813 if (sarea_priv->dirty)
814 i810EmitState(dev);
815
816 if (buf_priv->currently_mapped == I810_BUF_MAPPED) {
817 unsigned int prim = (sarea_priv->vertex_prim & PR_MASK);
818
819 *(u32 *) buf_priv->kernel_virtual =
820 ((GFX_OP_PRIMITIVE | prim | ((used / 4) - 2)));
821
822 if (used & 4) {
823 *(u32 *) ((char *) buf_priv->kernel_virtual + used) = 0;
824 used += 4;
825 }
826
827 i810_unmap_buffer(buf);
828 }
829
830 if (used) {
831 do {
832 if (i < nbox) {
833 BEGIN_LP_RING(4);
834 OUT_RING(GFX_OP_SCISSOR | SC_UPDATE_SCISSOR |
835 SC_ENABLE);
836 OUT_RING(GFX_OP_SCISSOR_INFO);
837 OUT_RING(box[i].x1 | (box[i].y1 << 16));
838 OUT_RING((box[i].x2 -
839 1) | ((box[i].y2 - 1) << 16));
840 ADVANCE_LP_RING();
841 }
842
843 BEGIN_LP_RING(4);
844 OUT_RING(CMD_OP_BATCH_BUFFER);
845 OUT_RING(start | BB1_PROTECTED);
846 OUT_RING(start + used - 4);
847 OUT_RING(0);
848 ADVANCE_LP_RING();
849
850 } while (++i < nbox);
851 }
852
853 if (discard) {
854 dev_priv->counter++;
855
856 (void)cmpxchg(buf_priv->in_use, I810_BUF_CLIENT,
857 I810_BUF_HARDWARE);
858
859 BEGIN_LP_RING(8);
860 OUT_RING(CMD_STORE_DWORD_IDX);
861 OUT_RING(20);
862 OUT_RING(dev_priv->counter);
863 OUT_RING(CMD_STORE_DWORD_IDX);
864 OUT_RING(buf_priv->my_use_idx);
865 OUT_RING(I810_BUF_FREE);
866 OUT_RING(CMD_REPORT_HEAD);
867 OUT_RING(0);
868 ADVANCE_LP_RING();
869 }
870 }
871
872 static void i810_dma_dispatch_flip(drm_device_t * dev)
873 {
874 drm_i810_private_t *dev_priv = dev->dev_private;
875 int pitch = dev_priv->pitch;
876 RING_LOCALS;
877
878 DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
879 __FUNCTION__,
880 dev_priv->current_page,
881 dev_priv->sarea_priv->pf_current_page);
882
883 i810_kernel_lost_context(dev);
884
885 BEGIN_LP_RING(2);
886 OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);
887 OUT_RING(0);
888 ADVANCE_LP_RING();
889
890 BEGIN_LP_RING(I810_DEST_SETUP_SIZE + 2);
891 /* On i815 at least ASYNC is buggy */
892 /* pitch<<5 is from 11.2.8 p158,
893 its the pitch / 8 then left shifted 8,
894 so (pitch >> 3) << 8 */
895 OUT_RING(CMD_OP_FRONTBUFFER_INFO | (pitch << 5) /*| ASYNC_FLIP */ );
896 if (dev_priv->current_page == 0) {
897 OUT_RING(dev_priv->back_offset);
898 dev_priv->current_page = 1;
899 } else {
900 OUT_RING(dev_priv->front_offset);
901 dev_priv->current_page = 0;
902 }
903 OUT_RING(0);
904 ADVANCE_LP_RING();
905
906 BEGIN_LP_RING(2);
907 OUT_RING(CMD_OP_WAIT_FOR_EVENT | WAIT_FOR_PLANE_A_FLIP);
908 OUT_RING(0);
909 ADVANCE_LP_RING();
910
911 /* Increment the frame counter. The client-side 3D driver must
912 * throttle the framerate by waiting for this value before
913 * performing the swapbuffer ioctl.
914 */
915 dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
916
917 }
918
919 static void i810_dma_quiescent(drm_device_t * dev)
920 {
921 drm_i810_private_t *dev_priv = dev->dev_private;
922 RING_LOCALS;
923
924 /* printk("%s\n", __FUNCTION__); */
925
926 i810_kernel_lost_context(dev);
927
928 BEGIN_LP_RING(4);
929 OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);
930 OUT_RING(CMD_REPORT_HEAD);
931 OUT_RING(0);
932 OUT_RING(0);
933 ADVANCE_LP_RING();
934
935 i810_wait_ring(dev, dev_priv->ring.Size - 8);
936 }
937
938 static int i810_flush_queue(drm_device_t * dev)
939 {
940 drm_i810_private_t *dev_priv = dev->dev_private;
941 drm_device_dma_t *dma = dev->dma;
942 int i, ret = 0;
943 RING_LOCALS;
944
945 /* printk("%s\n", __FUNCTION__); */
946
947 i810_kernel_lost_context(dev);
948
949 BEGIN_LP_RING(2);
950 OUT_RING(CMD_REPORT_HEAD);
951 OUT_RING(0);
952 ADVANCE_LP_RING();
953
954 i810_wait_ring(dev, dev_priv->ring.Size - 8);
955
956 for (i = 0; i < dma->buf_count; i++) {
957 drm_buf_t *buf = dma->buflist[i];
958 drm_i810_buf_priv_t *buf_priv = buf->dev_private;
959
960 int used = cmpxchg(buf_priv->in_use, I810_BUF_HARDWARE,
961 I810_BUF_FREE);
962
963 if (used == I810_BUF_HARDWARE)
964 DRM_DEBUG("reclaimed from HARDWARE\n");
965 if (used == I810_BUF_CLIENT)
966 DRM_DEBUG("still on client\n");
967 }
968
969 return ret;
970 }
971
972 /* Must be called with the lock held */
973 static void i810_reclaim_buffers(drm_device_t * dev, struct file *filp)
974 {
975 drm_device_dma_t *dma = dev->dma;
976 int i;
977
978 if (!dma)
979 return;
980 if (!dev->dev_private)
981 return;
982 if (!dma->buflist)
983 return;
984
985 i810_flush_queue(dev);
986
987 for (i = 0; i < dma->buf_count; i++) {
988 drm_buf_t *buf = dma->buflist[i];
989 drm_i810_buf_priv_t *buf_priv = buf->dev_private;
990
991 if (buf->filp == filp && buf_priv) {
992 int used = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT,
993 I810_BUF_FREE);
994
995 if (used == I810_BUF_CLIENT)
996 DRM_DEBUG("reclaimed from client\n");
997 if (buf_priv->currently_mapped == I810_BUF_MAPPED)
998 buf_priv->currently_mapped = I810_BUF_UNMAPPED;
999 }
1000 }
1001 }
1002
1003 static int i810_flush_ioctl(struct inode *inode, struct file *filp,
1004 unsigned int cmd, unsigned long arg)
1005 {
1006 drm_file_t *priv = filp->private_data;
1007 drm_device_t *dev = priv->head->dev;
1008
1009 LOCK_TEST_WITH_RETURN(dev, filp);
1010
1011 i810_flush_queue(dev);
1012 return 0;
1013 }
1014
1015 static int i810_dma_vertex(struct inode *inode, struct file *filp,
1016 unsigned int cmd, unsigned long arg)
1017 {
1018 drm_file_t *priv = filp->private_data;
1019 drm_device_t *dev = priv->head->dev;
1020 drm_device_dma_t *dma = dev->dma;
1021 drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
1022 u32 *hw_status = dev_priv->hw_status_page;
1023 drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
1024 dev_priv->sarea_priv;
1025 drm_i810_vertex_t vertex;
1026
1027 if (copy_from_user
1028 (&vertex, (drm_i810_vertex_t __user *) arg, sizeof(vertex)))
1029 return -EFAULT;
1030
1031 LOCK_TEST_WITH_RETURN(dev, filp);
1032
1033 DRM_DEBUG("i810 dma vertex, idx %d used %d discard %d\n",
1034 vertex.idx, vertex.used, vertex.discard);
1035
1036 if (vertex.idx < 0 || vertex.idx > dma->buf_count)
1037 return -EINVAL;
1038
1039 i810_dma_dispatch_vertex(dev,
1040 dma->buflist[vertex.idx],
1041 vertex.discard, vertex.used);
1042
1043 atomic_add(vertex.used, &dev->counts[_DRM_STAT_SECONDARY]);
1044 atomic_inc(&dev->counts[_DRM_STAT_DMA]);
1045 sarea_priv->last_enqueue = dev_priv->counter - 1;
1046 sarea_priv->last_dispatch = (int)hw_status[5];
1047
1048 return 0;
1049 }
1050
1051 static int i810_clear_bufs(struct inode *inode, struct file *filp,
1052 unsigned int cmd, unsigned long arg)
1053 {
1054 drm_file_t *priv = filp->private_data;
1055 drm_device_t *dev = priv->head->dev;
1056 drm_i810_clear_t clear;
1057
1058 if (copy_from_user
1059 (&clear, (drm_i810_clear_t __user *) arg, sizeof(clear)))
1060 return -EFAULT;
1061
1062 LOCK_TEST_WITH_RETURN(dev, filp);
1063
1064 /* GH: Someone's doing nasty things... */
1065 if (!dev->dev_private) {
1066 return -EINVAL;
1067 }
1068
1069 i810_dma_dispatch_clear(dev, clear.flags,
1070 clear.clear_color, clear.clear_depth);
1071 return 0;
1072 }
1073
1074 static int i810_swap_bufs(struct inode *inode, struct file *filp,
1075 unsigned int cmd, unsigned long arg)
1076 {
1077 drm_file_t *priv = filp->private_data;
1078 drm_device_t *dev = priv->head->dev;
1079
1080 DRM_DEBUG("i810_swap_bufs\n");
1081
1082 LOCK_TEST_WITH_RETURN(dev, filp);
1083
1084 i810_dma_dispatch_swap(dev);
1085 return 0;
1086 }
1087
1088 static int i810_getage(struct inode *inode, struct file *filp, unsigned int cmd,
1089 unsigned long arg)
1090 {
1091 drm_file_t *priv = filp->private_data;
1092 drm_device_t *dev = priv->head->dev;
1093 drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
1094 u32 *hw_status = dev_priv->hw_status_page;
1095 drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
1096 dev_priv->sarea_priv;
1097
1098 sarea_priv->last_dispatch = (int)hw_status[5];
1099 return 0;
1100 }
1101
1102 static int i810_getbuf(struct inode *inode, struct file *filp, unsigned int cmd,
1103 unsigned long arg)
1104 {
1105 drm_file_t *priv = filp->private_data;
1106 drm_device_t *dev = priv->head->dev;
1107 int retcode = 0;
1108 drm_i810_dma_t d;
1109 drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
1110 u32 *hw_status = dev_priv->hw_status_page;
1111 drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
1112 dev_priv->sarea_priv;
1113
1114 if (copy_from_user(&d, (drm_i810_dma_t __user *) arg, sizeof(d)))
1115 return -EFAULT;
1116
1117 LOCK_TEST_WITH_RETURN(dev, filp);
1118
1119 d.granted = 0;
1120
1121 retcode = i810_dma_get_buffer(dev, &d, filp);
1122
1123 DRM_DEBUG("i810_dma: %d returning %d, granted = %d\n",
1124 current->pid, retcode, d.granted);
1125
1126 if (copy_to_user((drm_dma_t __user *) arg, &d, sizeof(d)))
1127 return -EFAULT;
1128 sarea_priv->last_dispatch = (int)hw_status[5];
1129
1130 return retcode;
1131 }
1132
1133 static int i810_copybuf(struct inode *inode,
1134 struct file *filp, unsigned int cmd, unsigned long arg)
1135 {
1136 /* Never copy - 2.4.x doesn't need it */
1137 return 0;
1138 }
1139
1140 static int i810_docopy(struct inode *inode, struct file *filp, unsigned int cmd,
1141 unsigned long arg)
1142 {
1143 /* Never copy - 2.4.x doesn't need it */
1144 return 0;
1145 }
1146
1147 static void i810_dma_dispatch_mc(drm_device_t * dev, drm_buf_t * buf, int used,
1148 unsigned int last_render)
1149 {
1150 drm_i810_private_t *dev_priv = dev->dev_private;
1151 drm_i810_buf_priv_t *buf_priv = buf->dev_private;
1152 drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
1153 unsigned long address = (unsigned long)buf->bus_address;
1154 unsigned long start = address - dev->agp->base;
1155 int u;
1156 RING_LOCALS;
1157
1158 i810_kernel_lost_context(dev);
1159
1160 u = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, I810_BUF_HARDWARE);
1161 if (u != I810_BUF_CLIENT) {
1162 DRM_DEBUG("MC found buffer that isn't mine!\n");
1163 }
1164
1165 if (used > 4 * 1024)
1166 used = 0;
1167
1168 sarea_priv->dirty = 0x7f;
1169
1170 DRM_DEBUG("dispatch mc addr 0x%lx, used 0x%x\n", address, used);
1171
1172 dev_priv->counter++;
1173 DRM_DEBUG("dispatch counter : %ld\n", dev_priv->counter);
1174 DRM_DEBUG("i810_dma_dispatch_mc\n");
1175 DRM_DEBUG("start : %lx\n", start);
1176 DRM_DEBUG("used : %d\n", used);
1177 DRM_DEBUG("start + used - 4 : %ld\n", start + used - 4);
1178
1179 if (buf_priv->currently_mapped == I810_BUF_MAPPED) {
1180 if (used & 4) {
1181 *(u32 *) ((char *) buf_priv->virtual + used) = 0;
1182 used += 4;
1183 }
1184
1185 i810_unmap_buffer(buf);
1186 }
1187 BEGIN_LP_RING(4);
1188 OUT_RING(CMD_OP_BATCH_BUFFER);
1189 OUT_RING(start | BB1_PROTECTED);
1190 OUT_RING(start + used - 4);
1191 OUT_RING(0);
1192 ADVANCE_LP_RING();
1193
1194 BEGIN_LP_RING(8);
1195 OUT_RING(CMD_STORE_DWORD_IDX);
1196 OUT_RING(buf_priv->my_use_idx);
1197 OUT_RING(I810_BUF_FREE);
1198 OUT_RING(0);
1199
1200 OUT_RING(CMD_STORE_DWORD_IDX);
1201 OUT_RING(16);
1202 OUT_RING(last_render);
1203 OUT_RING(0);
1204 ADVANCE_LP_RING();
1205 }
1206
1207 static int i810_dma_mc(struct inode *inode, struct file *filp,
1208 unsigned int cmd, unsigned long arg)
1209 {
1210 drm_file_t *priv = filp->private_data;
1211 drm_device_t *dev = priv->head->dev;
1212 drm_device_dma_t *dma = dev->dma;
1213 drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
1214 u32 *hw_status = dev_priv->hw_status_page;
1215 drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
1216 dev_priv->sarea_priv;
1217 drm_i810_mc_t mc;
1218
1219 if (copy_from_user(&mc, (drm_i810_mc_t __user *) arg, sizeof(mc)))
1220 return -EFAULT;
1221
1222 LOCK_TEST_WITH_RETURN(dev, filp);
1223
1224 if (mc.idx >= dma->buf_count || mc.idx < 0)
1225 return -EINVAL;
1226
1227 i810_dma_dispatch_mc(dev, dma->buflist[mc.idx], mc.used,
1228 mc.last_render);
1229
1230 atomic_add(mc.used, &dev->counts[_DRM_STAT_SECONDARY]);
1231 atomic_inc(&dev->counts[_DRM_STAT_DMA]);
1232 sarea_priv->last_enqueue = dev_priv->counter - 1;
1233 sarea_priv->last_dispatch = (int)hw_status[5];
1234
1235 return 0;
1236 }
1237
1238 static int i810_rstatus(struct inode *inode, struct file *filp,
1239 unsigned int cmd, unsigned long arg)
1240 {
1241 drm_file_t *priv = filp->private_data;
1242 drm_device_t *dev = priv->head->dev;
1243 drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
1244
1245 return (int)(((u32 *) (dev_priv->hw_status_page))[4]);
1246 }
1247
1248 static int i810_ov0_info(struct inode *inode, struct file *filp,
1249 unsigned int cmd, unsigned long arg)
1250 {
1251 drm_file_t *priv = filp->private_data;
1252 drm_device_t *dev = priv->head->dev;
1253 drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
1254 drm_i810_overlay_t data;
1255
1256 data.offset = dev_priv->overlay_offset;
1257 data.physical = dev_priv->overlay_physical;
1258 if (copy_to_user
1259 ((drm_i810_overlay_t __user *) arg, &data, sizeof(data)))
1260 return -EFAULT;
1261 return 0;
1262 }
1263
1264 static int i810_fstatus(struct inode *inode, struct file *filp,
1265 unsigned int cmd, unsigned long arg)
1266 {
1267 drm_file_t *priv = filp->private_data;
1268 drm_device_t *dev = priv->head->dev;
1269 drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
1270
1271 LOCK_TEST_WITH_RETURN(dev, filp);
1272
1273 return I810_READ(0x30008);
1274 }
1275
1276 static int i810_ov0_flip(struct inode *inode, struct file *filp,
1277 unsigned int cmd, unsigned long arg)
1278 {
1279 drm_file_t *priv = filp->private_data;
1280 drm_device_t *dev = priv->head->dev;
1281 drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
1282
1283 LOCK_TEST_WITH_RETURN(dev, filp);
1284
1285 //Tell the overlay to update
1286 I810_WRITE(0x30000, dev_priv->overlay_physical | 0x80000000);
1287
1288 return 0;
1289 }
1290
1291 /* Not sure why this isn't set all the time:
1292 */
1293 static void i810_do_init_pageflip(drm_device_t * dev)
1294 {
1295 drm_i810_private_t *dev_priv = dev->dev_private;
1296
1297 DRM_DEBUG("%s\n", __FUNCTION__);
1298 dev_priv->page_flipping = 1;
1299 dev_priv->current_page = 0;
1300 dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
1301 }
1302
1303 static int i810_do_cleanup_pageflip(drm_device_t * dev)
1304 {
1305 drm_i810_private_t *dev_priv = dev->dev_private;
1306
1307 DRM_DEBUG("%s\n", __FUNCTION__);
1308 if (dev_priv->current_page != 0)
1309 i810_dma_dispatch_flip(dev);
1310
1311 dev_priv->page_flipping = 0;
1312 return 0;
1313 }
1314
1315 static int i810_flip_bufs(struct inode *inode, struct file *filp,
1316 unsigned int cmd, unsigned long arg)
1317 {
1318 drm_file_t *priv = filp->private_data;
1319 drm_device_t *dev = priv->head->dev;
1320 drm_i810_private_t *dev_priv = dev->dev_private;
1321
1322 DRM_DEBUG("%s\n", __FUNCTION__);
1323
1324 LOCK_TEST_WITH_RETURN(dev, filp);
1325
1326 if (!dev_priv->page_flipping)
1327 i810_do_init_pageflip(dev);
1328
1329 i810_dma_dispatch_flip(dev);
1330 return 0;
1331 }
1332
1333 int i810_driver_load(drm_device_t *dev, unsigned long flags)
1334 {
1335 /* i810 has 4 more counters */
1336 dev->counters += 4;
1337 dev->types[6] = _DRM_STAT_IRQ;
1338 dev->types[7] = _DRM_STAT_PRIMARY;
1339 dev->types[8] = _DRM_STAT_SECONDARY;
1340 dev->types[9] = _DRM_STAT_DMA;
1341
1342 return 0;
1343 }
1344
1345 void i810_driver_lastclose(drm_device_t * dev)
1346 {
1347 i810_dma_cleanup(dev);
1348 }
1349
1350 void i810_driver_preclose(drm_device_t * dev, DRMFILE filp)
1351 {
1352 if (dev->dev_private) {
1353 drm_i810_private_t *dev_priv = dev->dev_private;
1354 if (dev_priv->page_flipping) {
1355 i810_do_cleanup_pageflip(dev);
1356 }
1357 }
1358 }
1359
1360 void i810_driver_reclaim_buffers_locked(drm_device_t * dev, struct file *filp)
1361 {
1362 i810_reclaim_buffers(dev, filp);
1363 }
1364
1365 int i810_driver_dma_quiescent(drm_device_t * dev)
1366 {
1367 i810_dma_quiescent(dev);
1368 return 0;
1369 }
1370
1371 drm_ioctl_desc_t i810_ioctls[] = {
1372 [DRM_IOCTL_NR(DRM_I810_INIT)] = {i810_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
1373 [DRM_IOCTL_NR(DRM_I810_VERTEX)] = {i810_dma_vertex, DRM_AUTH},
1374 [DRM_IOCTL_NR(DRM_I810_CLEAR)] = {i810_clear_bufs, DRM_AUTH},
1375 [DRM_IOCTL_NR(DRM_I810_FLUSH)] = {i810_flush_ioctl, DRM_AUTH},
1376 [DRM_IOCTL_NR(DRM_I810_GETAGE)] = {i810_getage, DRM_AUTH},
1377 [DRM_IOCTL_NR(DRM_I810_GETBUF)] = {i810_getbuf, DRM_AUTH},
1378 [DRM_IOCTL_NR(DRM_I810_SWAP)] = {i810_swap_bufs, DRM_AUTH},
1379 [DRM_IOCTL_NR(DRM_I810_COPY)] = {i810_copybuf, DRM_AUTH},
1380 [DRM_IOCTL_NR(DRM_I810_DOCOPY)] = {i810_docopy, DRM_AUTH},
1381 [DRM_IOCTL_NR(DRM_I810_OV0INFO)] = {i810_ov0_info, DRM_AUTH},
1382 [DRM_IOCTL_NR(DRM_I810_FSTATUS)] = {i810_fstatus, DRM_AUTH},
1383 [DRM_IOCTL_NR(DRM_I810_OV0FLIP)] = {i810_ov0_flip, DRM_AUTH},
1384 [DRM_IOCTL_NR(DRM_I810_MC)] = {i810_dma_mc, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
1385 [DRM_IOCTL_NR(DRM_I810_RSTATUS)] = {i810_rstatus, DRM_AUTH},
1386 [DRM_IOCTL_NR(DRM_I810_FLIP)] = {i810_flip_bufs, DRM_AUTH}
1387 };
1388
1389 int i810_max_ioctl = DRM_ARRAY_SIZE(i810_ioctls);
1390
1391 /**
1392 * Determine if the device really is AGP or not.
1393 *
1394 * All Intel graphics chipsets are treated as AGP, even if they are really
1395 * PCI-e.
1396 *
1397 * \param dev The device to be tested.
1398 *
1399 * \returns
1400 * A value of 1 is always retured to indictate every i810 is AGP.
1401 */
1402 int i810_driver_device_is_agp(drm_device_t * dev)
1403 {
1404 return 1;
1405 }
WRT350N Kernel Patches