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[POWERPC] Use menuconfig objects II - Macintosh
[wrt350n-kernel.git] / drivers / kvm / svm.c
blob3d8ea7ac2ecc308cded7d2b5f78473ff64f29a0f
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
16
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/vmalloc.h>
20 #include <linux/highmem.h>
21 #include <linux/profile.h>
22 #include <asm/desc.h>
23
24 #include "kvm_svm.h"
25 #include "x86_emulate.h"
26
27 MODULE_AUTHOR("Qumranet");
28 MODULE_LICENSE("GPL");
29
30 #define IOPM_ALLOC_ORDER 2
31 #define MSRPM_ALLOC_ORDER 1
32
33 #define DB_VECTOR 1
34 #define UD_VECTOR 6
35 #define GP_VECTOR 13
36
37 #define DR7_GD_MASK (1 << 13)
38 #define DR6_BD_MASK (1 << 13)
39 #define CR4_DE_MASK (1UL << 3)
40
41 #define SEG_TYPE_LDT 2
42 #define SEG_TYPE_BUSY_TSS16 3
43
44 #define KVM_EFER_LMA (1 << 10)
45 #define KVM_EFER_LME (1 << 8)
46
47 unsigned long iopm_base;
48 unsigned long msrpm_base;
49
50 struct kvm_ldttss_desc {
51 u16 limit0;
52 u16 base0;
53 unsigned base1 : 8, type : 5, dpl : 2, p : 1;
54 unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
55 u32 base3;
56 u32 zero1;
57 } __attribute__((packed));
58
59 struct svm_cpu_data {
60 int cpu;
61
62 uint64_t asid_generation;
63 uint32_t max_asid;
64 uint32_t next_asid;
65 struct kvm_ldttss_desc *tss_desc;
66
67 struct page *save_area;
68 };
69
70 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
71
72 struct svm_init_data {
73 int cpu;
74 int r;
75 };
76
77 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
78
79 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
80 #define MSRS_RANGE_SIZE 2048
81 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
82
83 #define MAX_INST_SIZE 15
84
85 static unsigned get_addr_size(struct kvm_vcpu *vcpu)
86 {
87 struct vmcb_save_area *sa = &vcpu->svm->vmcb->save;
88 u16 cs_attrib;
89
90 if (!(sa->cr0 & CR0_PE_MASK) || (sa->rflags & X86_EFLAGS_VM))
91 return 2;
92
93 cs_attrib = sa->cs.attrib;
94
95 return (cs_attrib & SVM_SELECTOR_L_MASK) ? 8 :
96 (cs_attrib & SVM_SELECTOR_DB_MASK) ? 4 : 2;
97 }
98
99 static inline u8 pop_irq(struct kvm_vcpu *vcpu)
100 {
101 int word_index = __ffs(vcpu->irq_summary);
102 int bit_index = __ffs(vcpu->irq_pending[word_index]);
103 int irq = word_index * BITS_PER_LONG + bit_index;
104
105 clear_bit(bit_index, &vcpu->irq_pending[word_index]);
106 if (!vcpu->irq_pending[word_index])
107 clear_bit(word_index, &vcpu->irq_summary);
108 return irq;
109 }
110
111 static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq)
112 {
113 set_bit(irq, vcpu->irq_pending);
114 set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary);
115 }
116
117 static inline void clgi(void)
118 {
119 asm volatile (SVM_CLGI);
120 }
121
122 static inline void stgi(void)
123 {
124 asm volatile (SVM_STGI);
125 }
126
127 static inline void invlpga(unsigned long addr, u32 asid)
128 {
129 asm volatile (SVM_INVLPGA :: "a"(addr), "c"(asid));
130 }
131
132 static inline unsigned long kvm_read_cr2(void)
133 {
134 unsigned long cr2;
135
136 asm volatile ("mov %%cr2, %0" : "=r" (cr2));
137 return cr2;
138 }
139
140 static inline void kvm_write_cr2(unsigned long val)
141 {
142 asm volatile ("mov %0, %%cr2" :: "r" (val));
143 }
144
145 static inline unsigned long read_dr6(void)
146 {
147 unsigned long dr6;
148
149 asm volatile ("mov %%dr6, %0" : "=r" (dr6));
150 return dr6;
151 }
152
153 static inline void write_dr6(unsigned long val)
154 {
155 asm volatile ("mov %0, %%dr6" :: "r" (val));
156 }
157
158 static inline unsigned long read_dr7(void)
159 {
160 unsigned long dr7;
161
162 asm volatile ("mov %%dr7, %0" : "=r" (dr7));
163 return dr7;
164 }
165
166 static inline void write_dr7(unsigned long val)
167 {
168 asm volatile ("mov %0, %%dr7" :: "r" (val));
169 }
170
171 static inline void force_new_asid(struct kvm_vcpu *vcpu)
172 {
173 vcpu->svm->asid_generation--;
174 }
175
176 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
177 {
178 force_new_asid(vcpu);
179 }
180
181 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
182 {
183 if (!(efer & KVM_EFER_LMA))
184 efer &= ~KVM_EFER_LME;
185
186 vcpu->svm->vmcb->save.efer = efer | MSR_EFER_SVME_MASK;
187 vcpu->shadow_efer = efer;
188 }
189
190 static void svm_inject_gp(struct kvm_vcpu *vcpu, unsigned error_code)
191 {
192 vcpu->svm->vmcb->control.event_inj = SVM_EVTINJ_VALID |
193 SVM_EVTINJ_VALID_ERR |
194 SVM_EVTINJ_TYPE_EXEPT |
195 GP_VECTOR;
196 vcpu->svm->vmcb->control.event_inj_err = error_code;
197 }
198
199 static void inject_ud(struct kvm_vcpu *vcpu)
200 {
201 vcpu->svm->vmcb->control.event_inj = SVM_EVTINJ_VALID |
202 SVM_EVTINJ_TYPE_EXEPT |
203 UD_VECTOR;
204 }
205
206 static void inject_db(struct kvm_vcpu *vcpu)
207 {
208 vcpu->svm->vmcb->control.event_inj = SVM_EVTINJ_VALID |
209 SVM_EVTINJ_TYPE_EXEPT |
210 DB_VECTOR;
211 }
212
213 static int is_page_fault(uint32_t info)
214 {
215 info &= SVM_EVTINJ_VEC_MASK | SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
216 return info == (PF_VECTOR | SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_EXEPT);
217 }
218
219 static int is_external_interrupt(u32 info)
220 {
221 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
222 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
223 }
224
225 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
226 {
227 if (!vcpu->svm->next_rip) {
228 printk(KERN_DEBUG "%s: NOP\n", __FUNCTION__);
229 return;
230 }
231 if (vcpu->svm->next_rip - vcpu->svm->vmcb->save.rip > 15) {
232 printk(KERN_ERR "%s: ip 0x%llx next 0x%llx\n",
233 __FUNCTION__,
234 vcpu->svm->vmcb->save.rip,
235 vcpu->svm->next_rip);
236 }
237
238 vcpu->rip = vcpu->svm->vmcb->save.rip = vcpu->svm->next_rip;
239 vcpu->svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
240
241 vcpu->interrupt_window_open = 1;
242 }
243
244 static int has_svm(void)
245 {
246 uint32_t eax, ebx, ecx, edx;
247
248 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
249 printk(KERN_INFO "has_svm: not amd\n");
250 return 0;
251 }
252
253 cpuid(0x80000000, &eax, &ebx, &ecx, &edx);
254 if (eax < SVM_CPUID_FUNC) {
255 printk(KERN_INFO "has_svm: can't execute cpuid_8000000a\n");
256 return 0;
257 }
258
259 cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
260 if (!(ecx & (1 << SVM_CPUID_FEATURE_SHIFT))) {
261 printk(KERN_DEBUG "has_svm: svm not available\n");
262 return 0;
263 }
264 return 1;
265 }
266
267 static void svm_hardware_disable(void *garbage)
268 {
269 struct svm_cpu_data *svm_data
270 = per_cpu(svm_data, raw_smp_processor_id());
271
272 if (svm_data) {
273 uint64_t efer;
274
275 wrmsrl(MSR_VM_HSAVE_PA, 0);
276 rdmsrl(MSR_EFER, efer);
277 wrmsrl(MSR_EFER, efer & ~MSR_EFER_SVME_MASK);
278 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
279 __free_page(svm_data->save_area);
280 kfree(svm_data);
281 }
282 }
283
284 static void svm_hardware_enable(void *garbage)
285 {
286
287 struct svm_cpu_data *svm_data;
288 uint64_t efer;
289 #ifdef CONFIG_X86_64
290 struct desc_ptr gdt_descr;
291 #else
292 struct Xgt_desc_struct gdt_descr;
293 #endif
294 struct desc_struct *gdt;
295 int me = raw_smp_processor_id();
296
297 if (!has_svm()) {
298 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
299 return;
300 }
301 svm_data = per_cpu(svm_data, me);
302
303 if (!svm_data) {
304 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
305 me);
306 return;
307 }
308
309 svm_data->asid_generation = 1;
310 svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
311 svm_data->next_asid = svm_data->max_asid + 1;
312
313 asm volatile ( "sgdt %0" : "=m"(gdt_descr) );
314 gdt = (struct desc_struct *)gdt_descr.address;
315 svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
316
317 rdmsrl(MSR_EFER, efer);
318 wrmsrl(MSR_EFER, efer | MSR_EFER_SVME_MASK);
319
320 wrmsrl(MSR_VM_HSAVE_PA,
321 page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
322 }
323
324 static int svm_cpu_init(int cpu)
325 {
326 struct svm_cpu_data *svm_data;
327 int r;
328
329 svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
330 if (!svm_data)
331 return -ENOMEM;
332 svm_data->cpu = cpu;
333 svm_data->save_area = alloc_page(GFP_KERNEL);
334 r = -ENOMEM;
335 if (!svm_data->save_area)
336 goto err_1;
337
338 per_cpu(svm_data, cpu) = svm_data;
339
340 return 0;
341
342 err_1:
343 kfree(svm_data);
344 return r;
345
346 }
347
348 static int set_msr_interception(u32 *msrpm, unsigned msr,
349 int read, int write)
350 {
351 int i;
352
353 for (i = 0; i < NUM_MSR_MAPS; i++) {
354 if (msr >= msrpm_ranges[i] &&
355 msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
356 u32 msr_offset = (i * MSRS_IN_RANGE + msr -
357 msrpm_ranges[i]) * 2;
358
359 u32 *base = msrpm + (msr_offset / 32);
360 u32 msr_shift = msr_offset % 32;
361 u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
362 *base = (*base & ~(0x3 << msr_shift)) |
363 (mask << msr_shift);
364 return 1;
365 }
366 }
367 printk(KERN_DEBUG "%s: not found 0x%x\n", __FUNCTION__, msr);
368 return 0;
369 }
370
371 static __init int svm_hardware_setup(void)
372 {
373 int cpu;
374 struct page *iopm_pages;
375 struct page *msrpm_pages;
376 void *msrpm_va;
377 int r;
378
379 kvm_emulator_want_group7_invlpg();
380
381 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
382
383 if (!iopm_pages)
384 return -ENOMEM;
385 memset(page_address(iopm_pages), 0xff,
386 PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
387 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
388
389
390 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
391
392 r = -ENOMEM;
393 if (!msrpm_pages)
394 goto err_1;
395
396 msrpm_va = page_address(msrpm_pages);
397 memset(msrpm_va, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
398 msrpm_base = page_to_pfn(msrpm_pages) << PAGE_SHIFT;
399
400 #ifdef CONFIG_X86_64
401 set_msr_interception(msrpm_va, MSR_GS_BASE, 1, 1);
402 set_msr_interception(msrpm_va, MSR_FS_BASE, 1, 1);
403 set_msr_interception(msrpm_va, MSR_KERNEL_GS_BASE, 1, 1);
404 set_msr_interception(msrpm_va, MSR_LSTAR, 1, 1);
405 set_msr_interception(msrpm_va, MSR_CSTAR, 1, 1);
406 set_msr_interception(msrpm_va, MSR_SYSCALL_MASK, 1, 1);
407 #endif
408 set_msr_interception(msrpm_va, MSR_K6_STAR, 1, 1);
409 set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_CS, 1, 1);
410 set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_ESP, 1, 1);
411 set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_EIP, 1, 1);
412
413 for_each_online_cpu(cpu) {
414 r = svm_cpu_init(cpu);
415 if (r)
416 goto err_2;
417 }
418 return 0;
419
420 err_2:
421 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
422 msrpm_base = 0;
423 err_1:
424 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
425 iopm_base = 0;
426 return r;
427 }
428
429 static __exit void svm_hardware_unsetup(void)
430 {
431 __free_pages(pfn_to_page(msrpm_base >> PAGE_SHIFT), MSRPM_ALLOC_ORDER);
432 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
433 iopm_base = msrpm_base = 0;
434 }
435
436 static void init_seg(struct vmcb_seg *seg)
437 {
438 seg->selector = 0;
439 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
440 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
441 seg->limit = 0xffff;
442 seg->base = 0;
443 }
444
445 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
446 {
447 seg->selector = 0;
448 seg->attrib = SVM_SELECTOR_P_MASK | type;
449 seg->limit = 0xffff;
450 seg->base = 0;
451 }
452
453 static int svm_vcpu_setup(struct kvm_vcpu *vcpu)
454 {
455 return 0;
456 }
457
458 static void init_vmcb(struct vmcb *vmcb)
459 {
460 struct vmcb_control_area *control = &vmcb->control;
461 struct vmcb_save_area *save = &vmcb->save;
462 u64 tsc;
463
464 control->intercept_cr_read = INTERCEPT_CR0_MASK |
465 INTERCEPT_CR3_MASK |
466 INTERCEPT_CR4_MASK;
467
468 control->intercept_cr_write = INTERCEPT_CR0_MASK |
469 INTERCEPT_CR3_MASK |
470 INTERCEPT_CR4_MASK;
471
472 control->intercept_dr_read = INTERCEPT_DR0_MASK |
473 INTERCEPT_DR1_MASK |
474 INTERCEPT_DR2_MASK |
475 INTERCEPT_DR3_MASK;
476
477 control->intercept_dr_write = INTERCEPT_DR0_MASK |
478 INTERCEPT_DR1_MASK |
479 INTERCEPT_DR2_MASK |
480 INTERCEPT_DR3_MASK |
481 INTERCEPT_DR5_MASK |
482 INTERCEPT_DR7_MASK;
483
484 control->intercept_exceptions = 1 << PF_VECTOR;
485
486
487 control->intercept = (1ULL << INTERCEPT_INTR) |
488 (1ULL << INTERCEPT_NMI) |
489 (1ULL << INTERCEPT_SMI) |
490 /*
491 * selective cr0 intercept bug?
492 * 0: 0f 22 d8 mov %eax,%cr3
493 * 3: 0f 20 c0 mov %cr0,%eax
494 * 6: 0d 00 00 00 80 or $0x80000000,%eax
495 * b: 0f 22 c0 mov %eax,%cr0
496 * set cr3 ->interception
497 * get cr0 ->interception
498 * set cr0 -> no interception
499 */
500 /* (1ULL << INTERCEPT_SELECTIVE_CR0) | */
501 (1ULL << INTERCEPT_CPUID) |
502 (1ULL << INTERCEPT_HLT) |
503 (1ULL << INTERCEPT_INVLPGA) |
504 (1ULL << INTERCEPT_IOIO_PROT) |
505 (1ULL << INTERCEPT_MSR_PROT) |
506 (1ULL << INTERCEPT_TASK_SWITCH) |
507 (1ULL << INTERCEPT_SHUTDOWN) |
508 (1ULL << INTERCEPT_VMRUN) |
509 (1ULL << INTERCEPT_VMMCALL) |
510 (1ULL << INTERCEPT_VMLOAD) |
511 (1ULL << INTERCEPT_VMSAVE) |
512 (1ULL << INTERCEPT_STGI) |
513 (1ULL << INTERCEPT_CLGI) |
514 (1ULL << INTERCEPT_SKINIT);
515
516 control->iopm_base_pa = iopm_base;
517 control->msrpm_base_pa = msrpm_base;
518 rdtscll(tsc);
519 control->tsc_offset = -tsc;
520 control->int_ctl = V_INTR_MASKING_MASK;
521
522 init_seg(&save->es);
523 init_seg(&save->ss);
524 init_seg(&save->ds);
525 init_seg(&save->fs);
526 init_seg(&save->gs);
527
528 save->cs.selector = 0xf000;
529 /* Executable/Readable Code Segment */
530 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
531 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
532 save->cs.limit = 0xffff;
533 /*
534 * cs.base should really be 0xffff0000, but vmx can't handle that, so
535 * be consistent with it.
536 *
537 * Replace when we have real mode working for vmx.
538 */
539 save->cs.base = 0xf0000;
540
541 save->gdtr.limit = 0xffff;
542 save->idtr.limit = 0xffff;
543
544 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
545 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
546
547 save->efer = MSR_EFER_SVME_MASK;
548
549 save->dr6 = 0xffff0ff0;
550 save->dr7 = 0x400;
551 save->rflags = 2;
552 save->rip = 0x0000fff0;
553
554 /*
555 * cr0 val on cpu init should be 0x60000010, we enable cpu
556 * cache by default. the orderly way is to enable cache in bios.
557 */
558 save->cr0 = 0x00000010 | CR0_PG_MASK | CR0_WP_MASK;
559 save->cr4 = CR4_PAE_MASK;
560 /* rdx = ?? */
561 }
562
563 static int svm_create_vcpu(struct kvm_vcpu *vcpu)
564 {
565 struct page *page;
566 int r;
567
568 r = -ENOMEM;
569 vcpu->svm = kzalloc(sizeof *vcpu->svm, GFP_KERNEL);
570 if (!vcpu->svm)
571 goto out1;
572 page = alloc_page(GFP_KERNEL);
573 if (!page)
574 goto out2;
575
576 vcpu->svm->vmcb = page_address(page);
577 memset(vcpu->svm->vmcb, 0, PAGE_SIZE);
578 vcpu->svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
579 vcpu->svm->cr0 = 0x00000010;
580 vcpu->svm->asid_generation = 0;
581 memset(vcpu->svm->db_regs, 0, sizeof(vcpu->svm->db_regs));
582 init_vmcb(vcpu->svm->vmcb);
583
584 fx_init(vcpu);
585
586 return 0;
587
588 out2:
589 kfree(vcpu->svm);
590 out1:
591 return r;
592 }
593
594 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
595 {
596 if (!vcpu->svm)
597 return;
598 if (vcpu->svm->vmcb)
599 __free_page(pfn_to_page(vcpu->svm->vmcb_pa >> PAGE_SHIFT));
600 kfree(vcpu->svm);
601 }
602
603 static void svm_vcpu_load(struct kvm_vcpu *vcpu)
604 {
605 get_cpu();
606 }
607
608 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
609 {
610 put_cpu();
611 }
612
613 static void svm_vcpu_decache(struct kvm_vcpu *vcpu)
614 {
615 }
616
617 static void svm_cache_regs(struct kvm_vcpu *vcpu)
618 {
619 vcpu->regs[VCPU_REGS_RAX] = vcpu->svm->vmcb->save.rax;
620 vcpu->regs[VCPU_REGS_RSP] = vcpu->svm->vmcb->save.rsp;
621 vcpu->rip = vcpu->svm->vmcb->save.rip;
622 }
623
624 static void svm_decache_regs(struct kvm_vcpu *vcpu)
625 {
626 vcpu->svm->vmcb->save.rax = vcpu->regs[VCPU_REGS_RAX];
627 vcpu->svm->vmcb->save.rsp = vcpu->regs[VCPU_REGS_RSP];
628 vcpu->svm->vmcb->save.rip = vcpu->rip;
629 }
630
631 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
632 {
633 return vcpu->svm->vmcb->save.rflags;
634 }
635
636 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
637 {
638 vcpu->svm->vmcb->save.rflags = rflags;
639 }
640
641 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
642 {
643 struct vmcb_save_area *save = &vcpu->svm->vmcb->save;
644
645 switch (seg) {
646 case VCPU_SREG_CS: return &save->cs;
647 case VCPU_SREG_DS: return &save->ds;
648 case VCPU_SREG_ES: return &save->es;
649 case VCPU_SREG_FS: return &save->fs;
650 case VCPU_SREG_GS: return &save->gs;
651 case VCPU_SREG_SS: return &save->ss;
652 case VCPU_SREG_TR: return &save->tr;
653 case VCPU_SREG_LDTR: return &save->ldtr;
654 }
655 BUG();
656 return NULL;
657 }
658
659 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
660 {
661 struct vmcb_seg *s = svm_seg(vcpu, seg);
662
663 return s->base;
664 }
665
666 static void svm_get_segment(struct kvm_vcpu *vcpu,
667 struct kvm_segment *var, int seg)
668 {
669 struct vmcb_seg *s = svm_seg(vcpu, seg);
670
671 var->base = s->base;
672 var->limit = s->limit;
673 var->selector = s->selector;
674 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
675 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
676 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
677 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
678 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
679 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
680 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
681 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
682 var->unusable = !var->present;
683 }
684
685 static void svm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
686 {
687 struct vmcb_seg *s = svm_seg(vcpu, VCPU_SREG_CS);
688
689 *db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
690 *l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
691 }
692
693 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
694 {
695 dt->limit = vcpu->svm->vmcb->save.idtr.limit;
696 dt->base = vcpu->svm->vmcb->save.idtr.base;
697 }
698
699 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
700 {
701 vcpu->svm->vmcb->save.idtr.limit = dt->limit;
702 vcpu->svm->vmcb->save.idtr.base = dt->base ;
703 }
704
705 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
706 {
707 dt->limit = vcpu->svm->vmcb->save.gdtr.limit;
708 dt->base = vcpu->svm->vmcb->save.gdtr.base;
709 }
710
711 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
712 {
713 vcpu->svm->vmcb->save.gdtr.limit = dt->limit;
714 vcpu->svm->vmcb->save.gdtr.base = dt->base ;
715 }
716
717 static void svm_decache_cr0_cr4_guest_bits(struct kvm_vcpu *vcpu)
718 {
719 }
720
721 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
722 {
723 #ifdef CONFIG_X86_64
724 if (vcpu->shadow_efer & KVM_EFER_LME) {
725 if (!is_paging(vcpu) && (cr0 & CR0_PG_MASK)) {
726 vcpu->shadow_efer |= KVM_EFER_LMA;
727 vcpu->svm->vmcb->save.efer |= KVM_EFER_LMA | KVM_EFER_LME;
728 }
729
730 if (is_paging(vcpu) && !(cr0 & CR0_PG_MASK) ) {
731 vcpu->shadow_efer &= ~KVM_EFER_LMA;
732 vcpu->svm->vmcb->save.efer &= ~(KVM_EFER_LMA | KVM_EFER_LME);
733 }
734 }
735 #endif
736 vcpu->svm->cr0 = cr0;
737 vcpu->svm->vmcb->save.cr0 = cr0 | CR0_PG_MASK | CR0_WP_MASK;
738 vcpu->cr0 = cr0;
739 }
740
741 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
742 {
743 vcpu->cr4 = cr4;
744 vcpu->svm->vmcb->save.cr4 = cr4 | CR4_PAE_MASK;
745 }
746
747 static void svm_set_segment(struct kvm_vcpu *vcpu,
748 struct kvm_segment *var, int seg)
749 {
750 struct vmcb_seg *s = svm_seg(vcpu, seg);
751
752 s->base = var->base;
753 s->limit = var->limit;
754 s->selector = var->selector;
755 if (var->unusable)
756 s->attrib = 0;
757 else {
758 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
759 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
760 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
761 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
762 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
763 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
764 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
765 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
766 }
767 if (seg == VCPU_SREG_CS)
768 vcpu->svm->vmcb->save.cpl
769 = (vcpu->svm->vmcb->save.cs.attrib
770 >> SVM_SELECTOR_DPL_SHIFT) & 3;
771
772 }
773
774 /* FIXME:
775
776 vcpu->svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
777 vcpu->svm->vmcb->control.int_ctl |= (sregs->cr8 & V_TPR_MASK);
778
779 */
780
781 static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
782 {
783 return -EOPNOTSUPP;
784 }
785
786 static void load_host_msrs(struct kvm_vcpu *vcpu)
787 {
788 int i;
789
790 for ( i = 0; i < NR_HOST_SAVE_MSRS; i++)
791 wrmsrl(host_save_msrs[i], vcpu->svm->host_msrs[i]);
792 }
793
794 static void save_host_msrs(struct kvm_vcpu *vcpu)
795 {
796 int i;
797
798 for ( i = 0; i < NR_HOST_SAVE_MSRS; i++)
799 rdmsrl(host_save_msrs[i], vcpu->svm->host_msrs[i]);
800 }
801
802 static void new_asid(struct kvm_vcpu *vcpu, struct svm_cpu_data *svm_data)
803 {
804 if (svm_data->next_asid > svm_data->max_asid) {
805 ++svm_data->asid_generation;
806 svm_data->next_asid = 1;
807 vcpu->svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
808 }
809
810 vcpu->cpu = svm_data->cpu;
811 vcpu->svm->asid_generation = svm_data->asid_generation;
812 vcpu->svm->vmcb->control.asid = svm_data->next_asid++;
813 }
814
815 static void svm_invlpg(struct kvm_vcpu *vcpu, gva_t address)
816 {
817 invlpga(address, vcpu->svm->vmcb->control.asid); // is needed?
818 }
819
820 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
821 {
822 return vcpu->svm->db_regs[dr];
823 }
824
825 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
826 int *exception)
827 {
828 *exception = 0;
829
830 if (vcpu->svm->vmcb->save.dr7 & DR7_GD_MASK) {
831 vcpu->svm->vmcb->save.dr7 &= ~DR7_GD_MASK;
832 vcpu->svm->vmcb->save.dr6 |= DR6_BD_MASK;
833 *exception = DB_VECTOR;
834 return;
835 }
836
837 switch (dr) {
838 case 0 ... 3:
839 vcpu->svm->db_regs[dr] = value;
840 return;
841 case 4 ... 5:
842 if (vcpu->cr4 & CR4_DE_MASK) {
843 *exception = UD_VECTOR;
844 return;
845 }
846 case 7: {
847 if (value & ~((1ULL << 32) - 1)) {
848 *exception = GP_VECTOR;
849 return;
850 }
851 vcpu->svm->vmcb->save.dr7 = value;
852 return;
853 }
854 default:
855 printk(KERN_DEBUG "%s: unexpected dr %u\n",
856 __FUNCTION__, dr);
857 *exception = UD_VECTOR;
858 return;
859 }
860 }
861
862 static int pf_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
863 {
864 u32 exit_int_info = vcpu->svm->vmcb->control.exit_int_info;
865 u64 fault_address;
866 u32 error_code;
867 enum emulation_result er;
868 int r;
869
870 if (is_external_interrupt(exit_int_info))
871 push_irq(vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK);
872
873 spin_lock(&vcpu->kvm->lock);
874
875 fault_address = vcpu->svm->vmcb->control.exit_info_2;
876 error_code = vcpu->svm->vmcb->control.exit_info_1;
877 r = kvm_mmu_page_fault(vcpu, fault_address, error_code);
878 if (r < 0) {
879 spin_unlock(&vcpu->kvm->lock);
880 return r;
881 }
882 if (!r) {
883 spin_unlock(&vcpu->kvm->lock);
884 return 1;
885 }
886 er = emulate_instruction(vcpu, kvm_run, fault_address, error_code);
887 spin_unlock(&vcpu->kvm->lock);
888
889 switch (er) {
890 case EMULATE_DONE:
891 return 1;
892 case EMULATE_DO_MMIO:
893 ++kvm_stat.mmio_exits;
894 kvm_run->exit_reason = KVM_EXIT_MMIO;
895 return 0;
896 case EMULATE_FAIL:
897 vcpu_printf(vcpu, "%s: emulate fail\n", __FUNCTION__);
898 break;
899 default:
900 BUG();
901 }
902
903 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
904 return 0;
905 }
906
907 static int shutdown_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
908 {
909 /*
910 * VMCB is undefined after a SHUTDOWN intercept
911 * so reinitialize it.
912 */
913 memset(vcpu->svm->vmcb, 0, PAGE_SIZE);
914 init_vmcb(vcpu->svm->vmcb);
915
916 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
917 return 0;
918 }
919
920 static int io_get_override(struct kvm_vcpu *vcpu,
921 struct vmcb_seg **seg,
922 int *addr_override)
923 {
924 u8 inst[MAX_INST_SIZE];
925 unsigned ins_length;
926 gva_t rip;
927 int i;
928
929 rip = vcpu->svm->vmcb->save.rip;
930 ins_length = vcpu->svm->next_rip - rip;
931 rip += vcpu->svm->vmcb->save.cs.base;
932
933 if (ins_length > MAX_INST_SIZE)
934 printk(KERN_DEBUG
935 "%s: inst length err, cs base 0x%llx rip 0x%llx "
936 "next rip 0x%llx ins_length %u\n",
937 __FUNCTION__,
938 vcpu->svm->vmcb->save.cs.base,
939 vcpu->svm->vmcb->save.rip,
940 vcpu->svm->vmcb->control.exit_info_2,
941 ins_length);
942
943 if (kvm_read_guest(vcpu, rip, ins_length, inst) != ins_length)
944 /* #PF */
945 return 0;
946
947 *addr_override = 0;
948 *seg = NULL;
949 for (i = 0; i < ins_length; i++)
950 switch (inst[i]) {
951 case 0xf0:
952 case 0xf2:
953 case 0xf3:
954 case 0x66:
955 continue;
956 case 0x67:
957 *addr_override = 1;
958 continue;
959 case 0x2e:
960 *seg = &vcpu->svm->vmcb->save.cs;
961 continue;
962 case 0x36:
963 *seg = &vcpu->svm->vmcb->save.ss;
964 continue;
965 case 0x3e:
966 *seg = &vcpu->svm->vmcb->save.ds;
967 continue;
968 case 0x26:
969 *seg = &vcpu->svm->vmcb->save.es;
970 continue;
971 case 0x64:
972 *seg = &vcpu->svm->vmcb->save.fs;
973 continue;
974 case 0x65:
975 *seg = &vcpu->svm->vmcb->save.gs;
976 continue;
977 default:
978 return 1;
979 }
980 printk(KERN_DEBUG "%s: unexpected\n", __FUNCTION__);
981 return 0;
982 }
983
984 static unsigned long io_adress(struct kvm_vcpu *vcpu, int ins, u64 *address)
985 {
986 unsigned long addr_mask;
987 unsigned long *reg;
988 struct vmcb_seg *seg;
989 int addr_override;
990 struct vmcb_save_area *save_area = &vcpu->svm->vmcb->save;
991 u16 cs_attrib = save_area->cs.attrib;
992 unsigned addr_size = get_addr_size(vcpu);
993
994 if (!io_get_override(vcpu, &seg, &addr_override))
995 return 0;
996
997 if (addr_override)
998 addr_size = (addr_size == 2) ? 4: (addr_size >> 1);
999
1000 if (ins) {
1001 reg = &vcpu->regs[VCPU_REGS_RDI];
1002 seg = &vcpu->svm->vmcb->save.es;
1003 } else {
1004 reg = &vcpu->regs[VCPU_REGS_RSI];
1005 seg = (seg) ? seg : &vcpu->svm->vmcb->save.ds;
1006 }
1007
1008 addr_mask = ~0ULL >> (64 - (addr_size * 8));
1009
1010 if ((cs_attrib & SVM_SELECTOR_L_MASK) &&
1011 !(vcpu->svm->vmcb->save.rflags & X86_EFLAGS_VM)) {
1012 *address = (*reg & addr_mask);
1013 return addr_mask;
1014 }
1015
1016 if (!(seg->attrib & SVM_SELECTOR_P_SHIFT)) {
1017 svm_inject_gp(vcpu, 0);
1018 return 0;
1019 }
1020
1021 *address = (*reg & addr_mask) + seg->base;
1022 return addr_mask;
1023 }
1024
1025 static int io_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1026 {
1027 u32 io_info = vcpu->svm->vmcb->control.exit_info_1; //address size bug?
1028 int _in = io_info & SVM_IOIO_TYPE_MASK;
1029
1030 ++kvm_stat.io_exits;
1031
1032 vcpu->svm->next_rip = vcpu->svm->vmcb->control.exit_info_2;
1033
1034 kvm_run->exit_reason = KVM_EXIT_IO;
1035 kvm_run->io.port = io_info >> 16;
1036 kvm_run->io.direction = (_in) ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
1037 kvm_run->io.size = ((io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT);
1038 kvm_run->io.string = (io_info & SVM_IOIO_STR_MASK) != 0;
1039 kvm_run->io.rep = (io_info & SVM_IOIO_REP_MASK) != 0;
1040
1041 if (kvm_run->io.string) {
1042 unsigned addr_mask;
1043
1044 addr_mask = io_adress(vcpu, _in, &kvm_run->io.address);
1045 if (!addr_mask) {
1046 printk(KERN_DEBUG "%s: get io address failed\n",
1047 __FUNCTION__);
1048 return 1;
1049 }
1050
1051 if (kvm_run->io.rep) {
1052 kvm_run->io.count
1053 = vcpu->regs[VCPU_REGS_RCX] & addr_mask;
1054 kvm_run->io.string_down = (vcpu->svm->vmcb->save.rflags
1055 & X86_EFLAGS_DF) != 0;
1056 }
1057 } else
1058 kvm_run->io.value = vcpu->svm->vmcb->save.rax;
1059 return 0;
1060 }
1061
1062 static int nop_on_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1063 {
1064 return 1;
1065 }
1066
1067 static int halt_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1068 {
1069 vcpu->svm->next_rip = vcpu->svm->vmcb->save.rip + 1;
1070 skip_emulated_instruction(vcpu);
1071 if (vcpu->irq_summary)
1072 return 1;
1073
1074 kvm_run->exit_reason = KVM_EXIT_HLT;
1075 ++kvm_stat.halt_exits;
1076 return 0;
1077 }
1078
1079 static int vmmcall_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1080 {
1081 vcpu->svm->vmcb->save.rip += 3;
1082 return kvm_hypercall(vcpu, kvm_run);
1083 }
1084
1085 static int invalid_op_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1086 {
1087 inject_ud(vcpu);
1088 return 1;
1089 }
1090
1091 static int task_switch_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1092 {
1093 printk(KERN_DEBUG "%s: task swiche is unsupported\n", __FUNCTION__);
1094 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1095 return 0;
1096 }
1097
1098 static int cpuid_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1099 {
1100 vcpu->svm->next_rip = vcpu->svm->vmcb->save.rip + 2;
1101 kvm_run->exit_reason = KVM_EXIT_CPUID;
1102 return 0;
1103 }
1104
1105 static int emulate_on_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1106 {
1107 if (emulate_instruction(vcpu, NULL, 0, 0) != EMULATE_DONE)
1108 printk(KERN_ERR "%s: failed\n", __FUNCTION__);
1109 return 1;
1110 }
1111
1112 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
1113 {
1114 switch (ecx) {
1115 case MSR_IA32_TIME_STAMP_COUNTER: {
1116 u64 tsc;
1117
1118 rdtscll(tsc);
1119 *data = vcpu->svm->vmcb->control.tsc_offset + tsc;
1120 break;
1121 }
1122 case MSR_K6_STAR:
1123 *data = vcpu->svm->vmcb->save.star;
1124 break;
1125 #ifdef CONFIG_X86_64
1126 case MSR_LSTAR:
1127 *data = vcpu->svm->vmcb->save.lstar;
1128 break;
1129 case MSR_CSTAR:
1130 *data = vcpu->svm->vmcb->save.cstar;
1131 break;
1132 case MSR_KERNEL_GS_BASE:
1133 *data = vcpu->svm->vmcb->save.kernel_gs_base;
1134 break;
1135 case MSR_SYSCALL_MASK:
1136 *data = vcpu->svm->vmcb->save.sfmask;
1137 break;
1138 #endif
1139 case MSR_IA32_SYSENTER_CS:
1140 *data = vcpu->svm->vmcb->save.sysenter_cs;
1141 break;
1142 case MSR_IA32_SYSENTER_EIP:
1143 *data = vcpu->svm->vmcb->save.sysenter_eip;
1144 break;
1145 case MSR_IA32_SYSENTER_ESP:
1146 *data = vcpu->svm->vmcb->save.sysenter_esp;
1147 break;
1148 default:
1149 return kvm_get_msr_common(vcpu, ecx, data);
1150 }
1151 return 0;
1152 }
1153
1154 static int rdmsr_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1155 {
1156 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
1157 u64 data;
1158
1159 if (svm_get_msr(vcpu, ecx, &data))
1160 svm_inject_gp(vcpu, 0);
1161 else {
1162 vcpu->svm->vmcb->save.rax = data & 0xffffffff;
1163 vcpu->regs[VCPU_REGS_RDX] = data >> 32;
1164 vcpu->svm->next_rip = vcpu->svm->vmcb->save.rip + 2;
1165 skip_emulated_instruction(vcpu);
1166 }
1167 return 1;
1168 }
1169
1170 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
1171 {
1172 switch (ecx) {
1173 case MSR_IA32_TIME_STAMP_COUNTER: {
1174 u64 tsc;
1175
1176 rdtscll(tsc);
1177 vcpu->svm->vmcb->control.tsc_offset = data - tsc;
1178 break;
1179 }
1180 case MSR_K6_STAR:
1181 vcpu->svm->vmcb->save.star = data;
1182 break;
1183 #ifdef CONFIG_X86_64
1184 case MSR_LSTAR:
1185 vcpu->svm->vmcb->save.lstar = data;
1186 break;
1187 case MSR_CSTAR:
1188 vcpu->svm->vmcb->save.cstar = data;
1189 break;
1190 case MSR_KERNEL_GS_BASE:
1191 vcpu->svm->vmcb->save.kernel_gs_base = data;
1192 break;
1193 case MSR_SYSCALL_MASK:
1194 vcpu->svm->vmcb->save.sfmask = data;
1195 break;
1196 #endif
1197 case MSR_IA32_SYSENTER_CS:
1198 vcpu->svm->vmcb->save.sysenter_cs = data;
1199 break;
1200 case MSR_IA32_SYSENTER_EIP:
1201 vcpu->svm->vmcb->save.sysenter_eip = data;
1202 break;
1203 case MSR_IA32_SYSENTER_ESP:
1204 vcpu->svm->vmcb->save.sysenter_esp = data;
1205 break;
1206 default:
1207 return kvm_set_msr_common(vcpu, ecx, data);
1208 }
1209 return 0;
1210 }
1211
1212 static int wrmsr_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1213 {
1214 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
1215 u64 data = (vcpu->svm->vmcb->save.rax & -1u)
1216 | ((u64)(vcpu->regs[VCPU_REGS_RDX] & -1u) << 32);
1217 vcpu->svm->next_rip = vcpu->svm->vmcb->save.rip + 2;
1218 if (svm_set_msr(vcpu, ecx, data))
1219 svm_inject_gp(vcpu, 0);
1220 else
1221 skip_emulated_instruction(vcpu);
1222 return 1;
1223 }
1224
1225 static int msr_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1226 {
1227 if (vcpu->svm->vmcb->control.exit_info_1)
1228 return wrmsr_interception(vcpu, kvm_run);
1229 else
1230 return rdmsr_interception(vcpu, kvm_run);
1231 }
1232
1233 static int interrupt_window_interception(struct kvm_vcpu *vcpu,
1234 struct kvm_run *kvm_run)
1235 {
1236 /*
1237 * If the user space waits to inject interrupts, exit as soon as
1238 * possible
1239 */
1240 if (kvm_run->request_interrupt_window &&
1241 !vcpu->irq_summary) {
1242 ++kvm_stat.irq_window_exits;
1243 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1244 return 0;
1245 }
1246
1247 return 1;
1248 }
1249
1250 static int (*svm_exit_handlers[])(struct kvm_vcpu *vcpu,
1251 struct kvm_run *kvm_run) = {
1252 [SVM_EXIT_READ_CR0] = emulate_on_interception,
1253 [SVM_EXIT_READ_CR3] = emulate_on_interception,
1254 [SVM_EXIT_READ_CR4] = emulate_on_interception,
1255 /* for now: */
1256 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
1257 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
1258 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
1259 [SVM_EXIT_READ_DR0] = emulate_on_interception,
1260 [SVM_EXIT_READ_DR1] = emulate_on_interception,
1261 [SVM_EXIT_READ_DR2] = emulate_on_interception,
1262 [SVM_EXIT_READ_DR3] = emulate_on_interception,
1263 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
1264 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
1265 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
1266 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
1267 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
1268 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
1269 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
1270 [SVM_EXIT_INTR] = nop_on_interception,
1271 [SVM_EXIT_NMI] = nop_on_interception,
1272 [SVM_EXIT_SMI] = nop_on_interception,
1273 [SVM_EXIT_INIT] = nop_on_interception,
1274 [SVM_EXIT_VINTR] = interrupt_window_interception,
1275 /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */
1276 [SVM_EXIT_CPUID] = cpuid_interception,
1277 [SVM_EXIT_HLT] = halt_interception,
1278 [SVM_EXIT_INVLPG] = emulate_on_interception,
1279 [SVM_EXIT_INVLPGA] = invalid_op_interception,
1280 [SVM_EXIT_IOIO] = io_interception,
1281 [SVM_EXIT_MSR] = msr_interception,
1282 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
1283 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
1284 [SVM_EXIT_VMRUN] = invalid_op_interception,
1285 [SVM_EXIT_VMMCALL] = vmmcall_interception,
1286 [SVM_EXIT_VMLOAD] = invalid_op_interception,
1287 [SVM_EXIT_VMSAVE] = invalid_op_interception,
1288 [SVM_EXIT_STGI] = invalid_op_interception,
1289 [SVM_EXIT_CLGI] = invalid_op_interception,
1290 [SVM_EXIT_SKINIT] = invalid_op_interception,
1291 };
1292
1293
1294 static int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1295 {
1296 u32 exit_code = vcpu->svm->vmcb->control.exit_code;
1297
1298 kvm_run->exit_type = KVM_EXIT_TYPE_VM_EXIT;
1299
1300 if (is_external_interrupt(vcpu->svm->vmcb->control.exit_int_info) &&
1301 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR)
1302 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
1303 "exit_code 0x%x\n",
1304 __FUNCTION__, vcpu->svm->vmcb->control.exit_int_info,
1305 exit_code);
1306
1307 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
1308 || svm_exit_handlers[exit_code] == 0) {
1309 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1310 printk(KERN_ERR "%s: 0x%x @ 0x%llx cr0 0x%lx rflags 0x%llx\n",
1311 __FUNCTION__,
1312 exit_code,
1313 vcpu->svm->vmcb->save.rip,
1314 vcpu->cr0,
1315 vcpu->svm->vmcb->save.rflags);
1316 return 0;
1317 }
1318
1319 return svm_exit_handlers[exit_code](vcpu, kvm_run);
1320 }
1321
1322 static void reload_tss(struct kvm_vcpu *vcpu)
1323 {
1324 int cpu = raw_smp_processor_id();
1325
1326 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1327 svm_data->tss_desc->type = 9; //available 32/64-bit TSS
1328 load_TR_desc();
1329 }
1330
1331 static void pre_svm_run(struct kvm_vcpu *vcpu)
1332 {
1333 int cpu = raw_smp_processor_id();
1334
1335 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1336
1337 vcpu->svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
1338 if (vcpu->cpu != cpu ||
1339 vcpu->svm->asid_generation != svm_data->asid_generation)
1340 new_asid(vcpu, svm_data);
1341 }
1342
1343
1344 static inline void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
1345 {
1346 struct vmcb_control_area *control;
1347
1348 control = &vcpu->svm->vmcb->control;
1349 control->int_vector = pop_irq(vcpu);
1350 control->int_ctl &= ~V_INTR_PRIO_MASK;
1351 control->int_ctl |= V_IRQ_MASK |
1352 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1353 }
1354
1355 static void kvm_reput_irq(struct kvm_vcpu *vcpu)
1356 {
1357 struct vmcb_control_area *control = &vcpu->svm->vmcb->control;
1358
1359 if (control->int_ctl & V_IRQ_MASK) {
1360 control->int_ctl &= ~V_IRQ_MASK;
1361 push_irq(vcpu, control->int_vector);
1362 }
1363
1364 vcpu->interrupt_window_open =
1365 !(control->int_state & SVM_INTERRUPT_SHADOW_MASK);
1366 }
1367
1368 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1369 struct kvm_run *kvm_run)
1370 {
1371 struct vmcb_control_area *control = &vcpu->svm->vmcb->control;
1372
1373 vcpu->interrupt_window_open =
1374 (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) &&
1375 (vcpu->svm->vmcb->save.rflags & X86_EFLAGS_IF));
1376
1377 if (vcpu->interrupt_window_open && vcpu->irq_summary)
1378 /*
1379 * If interrupts enabled, and not blocked by sti or mov ss. Good.
1380 */
1381 kvm_do_inject_irq(vcpu);
1382
1383 /*
1384 * Interrupts blocked. Wait for unblock.
1385 */
1386 if (!vcpu->interrupt_window_open &&
1387 (vcpu->irq_summary || kvm_run->request_interrupt_window)) {
1388 control->intercept |= 1ULL << INTERCEPT_VINTR;
1389 } else
1390 control->intercept &= ~(1ULL << INTERCEPT_VINTR);
1391 }
1392
1393 static void post_kvm_run_save(struct kvm_vcpu *vcpu,
1394 struct kvm_run *kvm_run)
1395 {
1396 kvm_run->ready_for_interrupt_injection = (vcpu->interrupt_window_open &&
1397 vcpu->irq_summary == 0);
1398 kvm_run->if_flag = (vcpu->svm->vmcb->save.rflags & X86_EFLAGS_IF) != 0;
1399 kvm_run->cr8 = vcpu->cr8;
1400 kvm_run->apic_base = vcpu->apic_base;
1401 }
1402
1403 /*
1404 * Check if userspace requested an interrupt window, and that the
1405 * interrupt window is open.
1406 *
1407 * No need to exit to userspace if we already have an interrupt queued.
1408 */
1409 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu,
1410 struct kvm_run *kvm_run)
1411 {
1412 return (!vcpu->irq_summary &&
1413 kvm_run->request_interrupt_window &&
1414 vcpu->interrupt_window_open &&
1415 (vcpu->svm->vmcb->save.rflags & X86_EFLAGS_IF));
1416 }
1417
1418 static void save_db_regs(unsigned long *db_regs)
1419 {
1420 asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0]));
1421 asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1]));
1422 asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2]));
1423 asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3]));
1424 }
1425
1426 static void load_db_regs(unsigned long *db_regs)
1427 {
1428 asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0]));
1429 asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1]));
1430 asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2]));
1431 asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3]));
1432 }
1433
1434 static int svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1435 {
1436 u16 fs_selector;
1437 u16 gs_selector;
1438 u16 ldt_selector;
1439 int r;
1440
1441 again:
1442 if (!vcpu->mmio_read_completed)
1443 do_interrupt_requests(vcpu, kvm_run);
1444
1445 clgi();
1446
1447 pre_svm_run(vcpu);
1448
1449 save_host_msrs(vcpu);
1450 fs_selector = read_fs();
1451 gs_selector = read_gs();
1452 ldt_selector = read_ldt();
1453 vcpu->svm->host_cr2 = kvm_read_cr2();
1454 vcpu->svm->host_dr6 = read_dr6();
1455 vcpu->svm->host_dr7 = read_dr7();
1456 vcpu->svm->vmcb->save.cr2 = vcpu->cr2;
1457
1458 if (vcpu->svm->vmcb->save.dr7 & 0xff) {
1459 write_dr7(0);
1460 save_db_regs(vcpu->svm->host_db_regs);
1461 load_db_regs(vcpu->svm->db_regs);
1462 }
1463
1464 fx_save(vcpu->host_fx_image);
1465 fx_restore(vcpu->guest_fx_image);
1466
1467 asm volatile (
1468 #ifdef CONFIG_X86_64
1469 "push %%rbx; push %%rcx; push %%rdx;"
1470 "push %%rsi; push %%rdi; push %%rbp;"
1471 "push %%r8; push %%r9; push %%r10; push %%r11;"
1472 "push %%r12; push %%r13; push %%r14; push %%r15;"
1473 #else
1474 "push %%ebx; push %%ecx; push %%edx;"
1475 "push %%esi; push %%edi; push %%ebp;"
1476 #endif
1477
1478 #ifdef CONFIG_X86_64
1479 "mov %c[rbx](%[vcpu]), %%rbx \n\t"
1480 "mov %c[rcx](%[vcpu]), %%rcx \n\t"
1481 "mov %c[rdx](%[vcpu]), %%rdx \n\t"
1482 "mov %c[rsi](%[vcpu]), %%rsi \n\t"
1483 "mov %c[rdi](%[vcpu]), %%rdi \n\t"
1484 "mov %c[rbp](%[vcpu]), %%rbp \n\t"
1485 "mov %c[r8](%[vcpu]), %%r8 \n\t"
1486 "mov %c[r9](%[vcpu]), %%r9 \n\t"
1487 "mov %c[r10](%[vcpu]), %%r10 \n\t"
1488 "mov %c[r11](%[vcpu]), %%r11 \n\t"
1489 "mov %c[r12](%[vcpu]), %%r12 \n\t"
1490 "mov %c[r13](%[vcpu]), %%r13 \n\t"
1491 "mov %c[r14](%[vcpu]), %%r14 \n\t"
1492 "mov %c[r15](%[vcpu]), %%r15 \n\t"
1493 #else
1494 "mov %c[rbx](%[vcpu]), %%ebx \n\t"
1495 "mov %c[rcx](%[vcpu]), %%ecx \n\t"
1496 "mov %c[rdx](%[vcpu]), %%edx \n\t"
1497 "mov %c[rsi](%[vcpu]), %%esi \n\t"
1498 "mov %c[rdi](%[vcpu]), %%edi \n\t"
1499 "mov %c[rbp](%[vcpu]), %%ebp \n\t"
1500 #endif
1501
1502 #ifdef CONFIG_X86_64
1503 /* Enter guest mode */
1504 "push %%rax \n\t"
1505 "mov %c[svm](%[vcpu]), %%rax \n\t"
1506 "mov %c[vmcb](%%rax), %%rax \n\t"
1507 SVM_VMLOAD "\n\t"
1508 SVM_VMRUN "\n\t"
1509 SVM_VMSAVE "\n\t"
1510 "pop %%rax \n\t"
1511 #else
1512 /* Enter guest mode */
1513 "push %%eax \n\t"
1514 "mov %c[svm](%[vcpu]), %%eax \n\t"
1515 "mov %c[vmcb](%%eax), %%eax \n\t"
1516 SVM_VMLOAD "\n\t"
1517 SVM_VMRUN "\n\t"
1518 SVM_VMSAVE "\n\t"
1519 "pop %%eax \n\t"
1520 #endif
1521
1522 /* Save guest registers, load host registers */
1523 #ifdef CONFIG_X86_64
1524 "mov %%rbx, %c[rbx](%[vcpu]) \n\t"
1525 "mov %%rcx, %c[rcx](%[vcpu]) \n\t"
1526 "mov %%rdx, %c[rdx](%[vcpu]) \n\t"
1527 "mov %%rsi, %c[rsi](%[vcpu]) \n\t"
1528 "mov %%rdi, %c[rdi](%[vcpu]) \n\t"
1529 "mov %%rbp, %c[rbp](%[vcpu]) \n\t"
1530 "mov %%r8, %c[r8](%[vcpu]) \n\t"
1531 "mov %%r9, %c[r9](%[vcpu]) \n\t"
1532 "mov %%r10, %c[r10](%[vcpu]) \n\t"
1533 "mov %%r11, %c[r11](%[vcpu]) \n\t"
1534 "mov %%r12, %c[r12](%[vcpu]) \n\t"
1535 "mov %%r13, %c[r13](%[vcpu]) \n\t"
1536 "mov %%r14, %c[r14](%[vcpu]) \n\t"
1537 "mov %%r15, %c[r15](%[vcpu]) \n\t"
1538
1539 "pop %%r15; pop %%r14; pop %%r13; pop %%r12;"
1540 "pop %%r11; pop %%r10; pop %%r9; pop %%r8;"
1541 "pop %%rbp; pop %%rdi; pop %%rsi;"
1542 "pop %%rdx; pop %%rcx; pop %%rbx; \n\t"
1543 #else
1544 "mov %%ebx, %c[rbx](%[vcpu]) \n\t"
1545 "mov %%ecx, %c[rcx](%[vcpu]) \n\t"
1546 "mov %%edx, %c[rdx](%[vcpu]) \n\t"
1547 "mov %%esi, %c[rsi](%[vcpu]) \n\t"
1548 "mov %%edi, %c[rdi](%[vcpu]) \n\t"
1549 "mov %%ebp, %c[rbp](%[vcpu]) \n\t"
1550
1551 "pop %%ebp; pop %%edi; pop %%esi;"
1552 "pop %%edx; pop %%ecx; pop %%ebx; \n\t"
1553 #endif
1554 :
1555 : [vcpu]"a"(vcpu),
1556 [svm]"i"(offsetof(struct kvm_vcpu, svm)),
1557 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
1558 [rbx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBX])),
1559 [rcx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RCX])),
1560 [rdx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDX])),
1561 [rsi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RSI])),
1562 [rdi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDI])),
1563 [rbp]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBP]))
1564 #ifdef CONFIG_X86_64
1565 ,[r8 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R8 ])),
1566 [r9 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R9 ])),
1567 [r10]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R10])),
1568 [r11]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R11])),
1569 [r12]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R12])),
1570 [r13]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R13])),
1571 [r14]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R14])),
1572 [r15]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R15]))
1573 #endif
1574 : "cc", "memory" );
1575
1576 fx_save(vcpu->guest_fx_image);
1577 fx_restore(vcpu->host_fx_image);
1578
1579 if ((vcpu->svm->vmcb->save.dr7 & 0xff))
1580 load_db_regs(vcpu->svm->host_db_regs);
1581
1582 vcpu->cr2 = vcpu->svm->vmcb->save.cr2;
1583
1584 write_dr6(vcpu->svm->host_dr6);
1585 write_dr7(vcpu->svm->host_dr7);
1586 kvm_write_cr2(vcpu->svm->host_cr2);
1587
1588 load_fs(fs_selector);
1589 load_gs(gs_selector);
1590 load_ldt(ldt_selector);
1591 load_host_msrs(vcpu);
1592
1593 reload_tss(vcpu);
1594
1595 /*
1596 * Profile KVM exit RIPs:
1597 */
1598 if (unlikely(prof_on == KVM_PROFILING))
1599 profile_hit(KVM_PROFILING,
1600 (void *)(unsigned long)vcpu->svm->vmcb->save.rip);
1601
1602 stgi();
1603
1604 kvm_reput_irq(vcpu);
1605
1606 vcpu->svm->next_rip = 0;
1607
1608 if (vcpu->svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
1609 kvm_run->exit_type = KVM_EXIT_TYPE_FAIL_ENTRY;
1610 kvm_run->exit_reason = vcpu->svm->vmcb->control.exit_code;
1611 post_kvm_run_save(vcpu, kvm_run);
1612 return 0;
1613 }
1614
1615 r = handle_exit(vcpu, kvm_run);
1616 if (r > 0) {
1617 if (signal_pending(current)) {
1618 ++kvm_stat.signal_exits;
1619 post_kvm_run_save(vcpu, kvm_run);
1620 return -EINTR;
1621 }
1622
1623 if (dm_request_for_irq_injection(vcpu, kvm_run)) {
1624 ++kvm_stat.request_irq_exits;
1625 post_kvm_run_save(vcpu, kvm_run);
1626 return -EINTR;
1627 }
1628 kvm_resched(vcpu);
1629 goto again;
1630 }
1631 post_kvm_run_save(vcpu, kvm_run);
1632 return r;
1633 }
1634
1635 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
1636 {
1637 force_new_asid(vcpu);
1638 }
1639
1640 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
1641 {
1642 vcpu->svm->vmcb->save.cr3 = root;
1643 force_new_asid(vcpu);
1644 }
1645
1646 static void svm_inject_page_fault(struct kvm_vcpu *vcpu,
1647 unsigned long addr,
1648 uint32_t err_code)
1649 {
1650 uint32_t exit_int_info = vcpu->svm->vmcb->control.exit_int_info;
1651
1652 ++kvm_stat.pf_guest;
1653
1654 if (is_page_fault(exit_int_info)) {
1655
1656 vcpu->svm->vmcb->control.event_inj_err = 0;
1657 vcpu->svm->vmcb->control.event_inj = SVM_EVTINJ_VALID |
1658 SVM_EVTINJ_VALID_ERR |
1659 SVM_EVTINJ_TYPE_EXEPT |
1660 DF_VECTOR;
1661 return;
1662 }
1663 vcpu->cr2 = addr;
1664 vcpu->svm->vmcb->save.cr2 = addr;
1665 vcpu->svm->vmcb->control.event_inj = SVM_EVTINJ_VALID |
1666 SVM_EVTINJ_VALID_ERR |
1667 SVM_EVTINJ_TYPE_EXEPT |
1668 PF_VECTOR;
1669 vcpu->svm->vmcb->control.event_inj_err = err_code;
1670 }
1671
1672
1673 static int is_disabled(void)
1674 {
1675 return 0;
1676 }
1677
1678 static void
1679 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1680 {
1681 /*
1682 * Patch in the VMMCALL instruction:
1683 */
1684 hypercall[0] = 0x0f;
1685 hypercall[1] = 0x01;
1686 hypercall[2] = 0xd9;
1687 hypercall[3] = 0xc3;
1688 }
1689
1690 static struct kvm_arch_ops svm_arch_ops = {
1691 .cpu_has_kvm_support = has_svm,
1692 .disabled_by_bios = is_disabled,
1693 .hardware_setup = svm_hardware_setup,
1694 .hardware_unsetup = svm_hardware_unsetup,
1695 .hardware_enable = svm_hardware_enable,
1696 .hardware_disable = svm_hardware_disable,
1697
1698 .vcpu_create = svm_create_vcpu,
1699 .vcpu_free = svm_free_vcpu,
1700
1701 .vcpu_load = svm_vcpu_load,
1702 .vcpu_put = svm_vcpu_put,
1703 .vcpu_decache = svm_vcpu_decache,
1704
1705 .set_guest_debug = svm_guest_debug,
1706 .get_msr = svm_get_msr,
1707 .set_msr = svm_set_msr,
1708 .get_segment_base = svm_get_segment_base,
1709 .get_segment = svm_get_segment,
1710 .set_segment = svm_set_segment,
1711 .get_cs_db_l_bits = svm_get_cs_db_l_bits,
1712 .decache_cr0_cr4_guest_bits = svm_decache_cr0_cr4_guest_bits,
1713 .set_cr0 = svm_set_cr0,
1714 .set_cr0_no_modeswitch = svm_set_cr0,
1715 .set_cr3 = svm_set_cr3,
1716 .set_cr4 = svm_set_cr4,
1717 .set_efer = svm_set_efer,
1718 .get_idt = svm_get_idt,
1719 .set_idt = svm_set_idt,
1720 .get_gdt = svm_get_gdt,
1721 .set_gdt = svm_set_gdt,
1722 .get_dr = svm_get_dr,
1723 .set_dr = svm_set_dr,
1724 .cache_regs = svm_cache_regs,
1725 .decache_regs = svm_decache_regs,
1726 .get_rflags = svm_get_rflags,
1727 .set_rflags = svm_set_rflags,
1728
1729 .invlpg = svm_invlpg,
1730 .tlb_flush = svm_flush_tlb,
1731 .inject_page_fault = svm_inject_page_fault,
1732
1733 .inject_gp = svm_inject_gp,
1734
1735 .run = svm_vcpu_run,
1736 .skip_emulated_instruction = skip_emulated_instruction,
1737 .vcpu_setup = svm_vcpu_setup,
1738 .patch_hypercall = svm_patch_hypercall,
1739 };
1740
1741 static int __init svm_init(void)
1742 {
1743 return kvm_init_arch(&svm_arch_ops, THIS_MODULE);
1744 }
1745
1746 static void __exit svm_exit(void)
1747 {
1748 kvm_exit_arch();
1749 }
1750
1751 module_init(svm_init)
1752 module_exit(svm_exit)
WRT350N Kernel Patches