drivers/video/matrox/matroxfb_base.h

   1 /*
   2  *
   3  * Hardware accelerated Matrox Millennium I, II, Mystique, G100, G200, G400 and G450
   4  *
   5  * (c) 1998-2002 Petr Vandrovec <vandrove@vc.cvut.cz>
   6  *
   7  */
   8 #ifndef __MATROXFB_H__
   9 #define __MATROXFB_H__
  10
  11 /* general, but fairly heavy, debugging */
  12 #undef MATROXFB_DEBUG
  13
  14 /* heavy debugging: */
  15 /* -- logs putc[s], so everytime a char is displayed, it's logged */
  16 #undef MATROXFB_DEBUG_HEAVY
  17
  18 /* This one _could_ cause infinite loops */
  19 /* It _does_ cause lots and lots of messages during idle loops */
  20 #undef MATROXFB_DEBUG_LOOP
  21
  22 /* Debug register calls, too? */
  23 #undef MATROXFB_DEBUG_REG
  24
  25 /* Guard accelerator accesses with spin_lock_irqsave... */
  26 #undef MATROXFB_USE_SPINLOCKS
  27
  28 #include <linux/module.h>
  29 #include <linux/kernel.h>
  30 #include <linux/errno.h>
  31 #include <linux/string.h>
  32 #include <linux/mm.h>
  33 #include <linux/slab.h>
  34 #include <linux/delay.h>
  35 #include <linux/fb.h>
  36 #include <linux/console.h>
  37 #include <linux/selection.h>
  38 #include <linux/ioport.h>
  39 #include <linux/init.h>
  40 #include <linux/timer.h>
  41 #include <linux/pci.h>
  42 #include <linux/spinlock.h>
  43 #include <linux/kd.h>
  44
  45 #include <asm/io.h>
  46 #include <asm/unaligned.h>
  47 #ifdef CONFIG_MTRR
  48 #include <asm/mtrr.h>
  49 #endif
  50
  51 #if defined(CONFIG_PPC_PMAC)
  52 #include <asm/prom.h>
  53 #include <asm/pci-bridge.h>
  54 #include "../macmodes.h"
  55 #endif
  56
  57 /* always compile support for 32MB... It cost almost nothing */
  58 #define CONFIG_FB_MATROX_32MB
  59
  60 #ifdef MATROXFB_DEBUG
  61
  62 #define DEBUG
  63 #define DBG(x)          printk(KERN_DEBUG "matroxfb: %s\n", (x));
  64
  65 #ifdef MATROXFB_DEBUG_HEAVY
  66 #define DBG_HEAVY(x)    DBG(x)
  67 #else /* MATROXFB_DEBUG_HEAVY */
  68 #define DBG_HEAVY(x)    /* DBG_HEAVY */
  69 #endif /* MATROXFB_DEBUG_HEAVY */
  70
  71 #ifdef MATROXFB_DEBUG_LOOP
  72 #define DBG_LOOP(x)     DBG(x)
  73 #else /* MATROXFB_DEBUG_LOOP */
  74 #define DBG_LOOP(x)     /* DBG_LOOP */
  75 #endif /* MATROXFB_DEBUG_LOOP */
  76
  77 #ifdef MATROXFB_DEBUG_REG
  78 #define DBG_REG(x)      DBG(x)
  79 #else /* MATROXFB_DEBUG_REG */
  80 #define DBG_REG(x)      /* DBG_REG */
  81 #endif /* MATROXFB_DEBUG_REG */
  82
  83 #else /* MATROXFB_DEBUG */
  84
  85 #define DBG(x)          /* DBG */
  86 #define DBG_HEAVY(x)    /* DBG_HEAVY */
  87 #define DBG_REG(x)      /* DBG_REG */
  88 #define DBG_LOOP(x)     /* DBG_LOOP */
  89
  90 #endif /* MATROXFB_DEBUG */
  91
  92 #ifdef DEBUG
  93 #define dprintk(X...)   printk(X)
  94 #else
  95 #define dprintk(X...)
  96 #endif
  97
  98 #ifndef PCI_SS_VENDOR_ID_SIEMENS_NIXDORF
  99 #define PCI_SS_VENDOR_ID_SIEMENS_NIXDORF        0x110A
 100 #endif
 101 #ifndef PCI_SS_VENDOR_ID_MATROX
 102 #define PCI_SS_VENDOR_ID_MATROX         PCI_VENDOR_ID_MATROX
 103 #endif
 104
 105 #ifndef PCI_SS_ID_MATROX_PRODUCTIVA_G100_AGP
 106 #define PCI_SS_ID_MATROX_GENERIC                0xFF00
 107 #define PCI_SS_ID_MATROX_PRODUCTIVA_G100_AGP    0xFF01
 108 #define PCI_SS_ID_MATROX_MYSTIQUE_G200_AGP      0xFF02
 109 #define PCI_SS_ID_MATROX_MILLENIUM_G200_AGP     0xFF03
 110 #define PCI_SS_ID_MATROX_MARVEL_G200_AGP        0xFF04
 111 #define PCI_SS_ID_MATROX_MGA_G100_PCI           0xFF05
 112 #define PCI_SS_ID_MATROX_MGA_G100_AGP           0x1001
 113 #define PCI_SS_ID_MATROX_MILLENNIUM_G400_MAX_AGP        0x2179
 114 #define PCI_SS_ID_SIEMENS_MGA_G100_AGP          0x001E /* 30 */
 115 #define PCI_SS_ID_SIEMENS_MGA_G200_AGP          0x0032 /* 50 */
 116 #endif
 117
 118 #define MX_VISUAL_TRUECOLOR     FB_VISUAL_DIRECTCOLOR
 119 #define MX_VISUAL_DIRECTCOLOR   FB_VISUAL_TRUECOLOR
 120 #define MX_VISUAL_PSEUDOCOLOR   FB_VISUAL_PSEUDOCOLOR
 121
 122 #define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16)
 123
 124 /* G-series and Mystique have (almost) same DAC */
 125 #undef NEED_DAC1064
 126 #if defined(CONFIG_FB_MATROX_MYSTIQUE) || defined(CONFIG_FB_MATROX_G)
 127 #define NEED_DAC1064 1
 128 #endif
 129
 130 typedef struct {
 131         void __iomem*   vaddr;
 132 } vaddr_t;
 133
 134 static inline unsigned int mga_readb(vaddr_t va, unsigned int offs) {
 135         return readb(va.vaddr + offs);
 136 }
 137
 138 static inline void mga_writeb(vaddr_t va, unsigned int offs, u_int8_t value) {
 139         writeb(value, va.vaddr + offs);
 140 }
 141
 142 static inline void mga_writew(vaddr_t va, unsigned int offs, u_int16_t value) {
 143         writew(value, va.vaddr + offs);
 144 }
 145
 146 static inline u_int32_t mga_readl(vaddr_t va, unsigned int offs) {
 147         return readl(va.vaddr + offs);
 148 }
 149
 150 static inline void mga_writel(vaddr_t va, unsigned int offs, u_int32_t value) {
 151         writel(value, va.vaddr + offs);
 152 }
 153
 154 static inline void mga_memcpy_toio(vaddr_t va, const void* src, int len) {
 155 #if defined(__alpha__) || defined(__i386__) || defined(__x86_64__)
 156         /*
 157          * memcpy_toio works for us if:
 158          *  (1) Copies data as 32bit quantities, not byte after byte,
 159          *  (2) Performs LE ordered stores, and
 160          *  (3) It copes with unaligned source (destination is guaranteed to be page
 161          *      aligned and length is guaranteed to be multiple of 4).
 162          */
 163         memcpy_toio(va.vaddr, src, len);
 164 #else
 165         u_int32_t __iomem* addr = va.vaddr;
 166
 167         if ((unsigned long)src & 3) {
 168                 while (len >= 4) {
 169                         fb_writel(get_unaligned((u32 *)src), addr);
 170                         addr++;
 171                         len -= 4;
 172                         src += 4;
 173                 }
 174         } else {
 175                 while (len >= 4) {
 176                         fb_writel(*(u32 *)src, addr);
 177                         addr++;
 178                         len -= 4;
 179                         src += 4;
 180                 }
 181         }
 182 #endif
 183 }
 184
 185 static inline void vaddr_add(vaddr_t* va, unsigned long offs) {
 186         va->vaddr += offs;
 187 }
 188
 189 static inline void __iomem* vaddr_va(vaddr_t va) {
 190         return va.vaddr;
 191 }
 192
 193 #define MGA_IOREMAP_NORMAL      0
 194 #define MGA_IOREMAP_NOCACHE     1
 195
 196 #define MGA_IOREMAP_FB          MGA_IOREMAP_NOCACHE
 197 #define MGA_IOREMAP_MMIO        MGA_IOREMAP_NOCACHE
 198 static inline int mga_ioremap(unsigned long phys, unsigned long size, int flags, vaddr_t* virt) {
 199         if (flags & MGA_IOREMAP_NOCACHE)
 200                 virt->vaddr = ioremap_nocache(phys, size);
 201         else
 202                 virt->vaddr = ioremap(phys, size);
 203         return (virt->vaddr == 0); /* 0, !0... 0, error_code in future */
 204 }
 205
 206 static inline void mga_iounmap(vaddr_t va) {
 207         iounmap(va.vaddr);
 208 }
 209
 210 struct my_timming {
 211         unsigned int pixclock;
 212         int mnp;
 213         unsigned int crtc;
 214         unsigned int HDisplay;
 215         unsigned int HSyncStart;
 216         unsigned int HSyncEnd;
 217         unsigned int HTotal;
 218         unsigned int VDisplay;
 219         unsigned int VSyncStart;
 220         unsigned int VSyncEnd;
 221         unsigned int VTotal;
 222         unsigned int sync;
 223         int          dblscan;
 224         int          interlaced;
 225         unsigned int delay;     /* CRTC delay */
 226 };
 227
 228 enum { M_SYSTEM_PLL, M_PIXEL_PLL_A, M_PIXEL_PLL_B, M_PIXEL_PLL_C, M_VIDEO_PLL };
 229
 230 struct matrox_pll_cache {
 231         unsigned int    valid;
 232         struct {
 233                 unsigned int    mnp_key;
 234                 unsigned int    mnp_value;
 235                       } data[4];
 236 };
 237
 238 struct matrox_pll_limits {
 239         unsigned int    vcomin;
 240         unsigned int    vcomax;
 241 };
 242
 243 struct matrox_pll_features {
 244         unsigned int    vco_freq_min;
 245         unsigned int    ref_freq;
 246         unsigned int    feed_div_min;
 247         unsigned int    feed_div_max;
 248         unsigned int    in_div_min;
 249         unsigned int    in_div_max;
 250         unsigned int    post_shift_max;
 251 };
 252
 253 struct matroxfb_par
 254 {
 255         unsigned int    final_bppShift;
 256         unsigned int    cmap_len;
 257         struct {
 258                 unsigned int bytes;
 259                 unsigned int pixels;
 260                 unsigned int chunks;
 261                       } ydstorg;
 262 };
 263
 264 struct matrox_fb_info;
 265
 266 struct matrox_DAC1064_features {
 267         u_int8_t        xvrefctrl;
 268         u_int8_t        xmiscctrl;
 269 };
 270
 271 /* current hardware status */
 272 struct mavenregs {
 273         u_int8_t regs[256];
 274         int      mode;
 275         int      vlines;
 276         int      xtal;
 277         int      fv;
 278
 279         u_int16_t htotal;
 280         u_int16_t hcorr;
 281 };
 282
 283 struct matrox_crtc2 {
 284         u_int32_t ctl;
 285 };
 286
 287 struct matrox_hw_state {
 288         u_int32_t       MXoptionReg;
 289         unsigned char   DACclk[6];
 290         unsigned char   DACreg[80];
 291         unsigned char   MiscOutReg;
 292         unsigned char   DACpal[768];
 293         unsigned char   CRTC[25];
 294         unsigned char   CRTCEXT[9];
 295         unsigned char   SEQ[5];
 296         /* unused for MGA mode, but who knows... */
 297         unsigned char   GCTL[9];
 298         /* unused for MGA mode, but who knows... */
 299         unsigned char   ATTR[21];
 300
 301         /* TVOut only */
 302         struct mavenregs        maven;
 303
 304         struct matrox_crtc2     crtc2;
 305 };
 306
 307 struct matrox_accel_data {
 308 #ifdef CONFIG_FB_MATROX_MILLENIUM
 309         unsigned char   ramdac_rev;
 310 #endif
 311         u_int32_t       m_dwg_rect;
 312         u_int32_t       m_opmode;
 313 };
 314
 315 struct v4l2_queryctrl;
 316 struct v4l2_control;
 317
 318 struct matrox_altout {
 319         const char      *name;
 320         int             (*compute)(void* altout_dev, struct my_timming* input);
 321         int             (*program)(void* altout_dev);
 322         int             (*start)(void* altout_dev);
 323         int             (*verifymode)(void* altout_dev, u_int32_t mode);
 324         int             (*getqueryctrl)(void* altout_dev,
 325                                         struct v4l2_queryctrl* ctrl);
 326         int             (*getctrl)(void* altout_dev,
 327                                    struct v4l2_control* ctrl);
 328         int             (*setctrl)(void* altout_dev,
 329                                    struct v4l2_control* ctrl);
 330 };
 331
 332 #define MATROXFB_SRC_NONE       0
 333 #define MATROXFB_SRC_CRTC1      1
 334 #define MATROXFB_SRC_CRTC2      2
 335
 336 enum mga_chip { MGA_2064, MGA_2164, MGA_1064, MGA_1164, MGA_G100, MGA_G200, MGA_G400, MGA_G450, MGA_G550 };
 337
 338 struct matrox_bios {
 339         unsigned int    bios_valid : 1;
 340         unsigned int    pins_len;
 341         unsigned char   pins[128];
 342         struct {
 343                 unsigned char vMaj, vMin, vRev;
 344                       } version;
 345         struct {
 346                 unsigned char state, tvout;
 347                       } output;
 348 };
 349
 350 struct matrox_switch;
 351 struct matroxfb_driver;
 352 struct matroxfb_dh_fb_info;
 353
 354 struct matrox_vsync {
 355         wait_queue_head_t       wait;
 356         unsigned int            cnt;
 357 };
 358
 359 struct matrox_fb_info {
 360         struct fb_info          fbcon;
 361
 362         struct list_head        next_fb;
 363
 364         int                     dead;
 365         int                     initialized;
 366         unsigned int            usecount;
 367
 368         unsigned int            userusecount;
 369         unsigned long           irq_flags;
 370
 371         struct matroxfb_par     curr;
 372         struct matrox_hw_state  hw;
 373
 374         struct matrox_accel_data accel;
 375
 376         struct pci_dev*         pcidev;
 377
 378         struct {
 379                 struct matrox_vsync     vsync;
 380                 unsigned int    pixclock;
 381                 int             mnp;
 382                 int             panpos;
 383                               } crtc1;
 384         struct {
 385                 struct matrox_vsync     vsync;
 386                 unsigned int    pixclock;
 387                 int             mnp;
 388         struct matroxfb_dh_fb_info*     info;
 389         struct rw_semaphore     lock;
 390                               } crtc2;
 391         struct {
 392         struct rw_semaphore     lock;
 393         struct {
 394                 int brightness, contrast, saturation, hue, gamma;
 395                 int testout, deflicker;
 396                                 } tvo_params;
 397                               } altout;
 398 #define MATROXFB_MAX_OUTPUTS            3
 399         struct {
 400         unsigned int            src;
 401         struct matrox_altout*   output;
 402         void*                   data;
 403         unsigned int            mode;
 404         unsigned int            default_src;
 405                               } outputs[MATROXFB_MAX_OUTPUTS];
 406
 407 #define MATROXFB_MAX_FB_DRIVERS         5
 408         struct matroxfb_driver* (drivers[MATROXFB_MAX_FB_DRIVERS]);
 409         void*                   (drivers_data[MATROXFB_MAX_FB_DRIVERS]);
 410         unsigned int            drivers_count;
 411
 412         struct {
 413         unsigned long   base;   /* physical */
 414         vaddr_t         vbase;  /* CPU view */
 415         unsigned int    len;
 416         unsigned int    len_usable;
 417         unsigned int    len_maximum;
 418                       } video;
 419
 420         struct {
 421         unsigned long   base;   /* physical */
 422         vaddr_t         vbase;  /* CPU view */
 423         unsigned int    len;
 424                       } mmio;
 425
 426         unsigned int    max_pixel_clock;
 427
 428         struct matrox_switch*   hw_switch;
 429
 430         struct {
 431                 struct matrox_pll_features pll;
 432                 struct matrox_DAC1064_features DAC1064;
 433                               } features;
 434         struct {
 435                 spinlock_t      DAC;
 436                 spinlock_t      accel;
 437                               } lock;
 438
 439         enum mga_chip           chip;
 440
 441         int                     interleave;
 442         int                     millenium;
 443         int                     milleniumII;
 444         struct {
 445                 int             cfb4;
 446                 const int*      vxres;
 447                 int             cross4MB;
 448                 int             text;
 449                 int             plnwt;
 450                 int             srcorg;
 451                               } capable;
 452 #ifdef CONFIG_MTRR
 453         struct {
 454                 int             vram;
 455                 int             vram_valid;
 456                               } mtrr;
 457 #endif
 458         struct {
 459                 int             precise_width;
 460                 int             mga_24bpp_fix;
 461                 int             novga;
 462                 int             nobios;
 463                 int             nopciretry;
 464                 int             noinit;
 465                 int             sgram;
 466 #ifdef CONFIG_FB_MATROX_32MB
 467                 int             support32MB;
 468 #endif
 469
 470                 int             accelerator;
 471                 int             text_type_aux;
 472                 int             video64bits;
 473                 int             crtc2;
 474                 int             maven_capable;
 475                 unsigned int    vgastep;
 476                 unsigned int    textmode;
 477                 unsigned int    textstep;
 478                 unsigned int    textvram;       /* character cells */
 479                 unsigned int    ydstorg;        /* offset in bytes from video start to usable memory */
 480                                                 /* 0 except for 6MB Millenium */
 481                 int             memtype;
 482                 int             g450dac;
 483                 int             dfp_type;
 484                 int             panellink;      /* G400 DFP possible (not G450/G550) */
 485                 int             dualhead;
 486                 unsigned int    fbResource;
 487                               } devflags;
 488         struct fb_ops           fbops;
 489         struct matrox_bios      bios;
 490         struct {
 491                 struct matrox_pll_limits        pixel;
 492                 struct matrox_pll_limits        system;
 493                 struct matrox_pll_limits        video;
 494                               } limits;
 495         struct {
 496                 struct matrox_pll_cache pixel;
 497                 struct matrox_pll_cache system;
 498                 struct matrox_pll_cache video;
 499                                       } cache;
 500         struct {
 501                 struct {
 502                         unsigned int    video;
 503                         unsigned int    system;
 504                                       } pll;
 505                 struct {
 506                         u_int32_t       opt;
 507                         u_int32_t       opt2;
 508                         u_int32_t       opt3;
 509                         u_int32_t       mctlwtst;
 510                         u_int32_t       mctlwtst_core;
 511                         u_int32_t       memmisc;
 512                         u_int32_t       memrdbk;
 513                         u_int32_t       maccess;
 514                                       } reg;
 515                 struct {
 516                         unsigned int    ddr:1,
 517                                         emrswen:1,
 518                                         dll:1;
 519                                       } memory;
 520                               } values;
 521         u_int32_t cmap[17];
 522 };
 523
 524 #define info2minfo(info) container_of(info, struct matrox_fb_info, fbcon)
 525
 526 #ifdef CONFIG_FB_MATROX_MULTIHEAD
 527 #define ACCESS_FBINFO2(info, x) (info->x)
 528 #define ACCESS_FBINFO(x) ACCESS_FBINFO2(minfo,x)
 529
 530 #define MINFO minfo
 531
 532 #define WPMINFO2 struct matrox_fb_info* minfo
 533 #define WPMINFO  WPMINFO2 ,
 534 #define CPMINFO2 const struct matrox_fb_info* minfo
 535 #define CPMINFO  CPMINFO2 ,
 536 #define PMINFO2  minfo
 537 #define PMINFO   PMINFO2 ,
 538
 539 #define MINFO_FROM(x)      struct matrox_fb_info* minfo = x
 540 #else
 541
 542 extern struct matrox_fb_info matroxfb_global_mxinfo;
 543
 544 #define ACCESS_FBINFO(x) (matroxfb_global_mxinfo.x)
 545 #define ACCESS_FBINFO2(info, x) (matroxfb_global_mxinfo.x)
 546
 547 #define MINFO (&matroxfb_global_mxinfo)
 548
 549 #define WPMINFO2 void
 550 #define WPMINFO
 551 #define CPMINFO2 void
 552 #define CPMINFO
 553 #define PMINFO2
 554 #define PMINFO
 555
 556 #define MINFO_FROM(x)
 557
 558 #endif
 559
 560 #define MINFO_FROM_INFO(x) MINFO_FROM(info2minfo(x))
 561
 562 struct matrox_switch {
 563         int     (*preinit)(WPMINFO2);
 564         void    (*reset)(WPMINFO2);
 565         int     (*init)(WPMINFO struct my_timming*);
 566         void    (*restore)(WPMINFO2);
 567 };
 568
 569 struct matroxfb_driver {
 570         struct list_head        node;
 571         char*                   name;
 572         void*                   (*probe)(struct matrox_fb_info* info);
 573         void                    (*remove)(struct matrox_fb_info* info, void* data);
 574 };
 575
 576 int matroxfb_register_driver(struct matroxfb_driver* drv);
 577 void matroxfb_unregister_driver(struct matroxfb_driver* drv);
 578
 579 #define PCI_OPTION_REG  0x40
 580 #define   PCI_OPTION_ENABLE_ROM         0x40000000
 581
 582 #define PCI_MGA_INDEX   0x44
 583 #define PCI_MGA_DATA    0x48
 584 #define PCI_OPTION2_REG 0x50
 585 #define PCI_OPTION3_REG 0x54
 586 #define PCI_MEMMISC_REG 0x58
 587
 588 #define M_DWGCTL        0x1C00
 589 #define M_MACCESS       0x1C04
 590 #define M_CTLWTST       0x1C08
 591
 592 #define M_PLNWT         0x1C1C
 593
 594 #define M_BCOL          0x1C20
 595 #define M_FCOL          0x1C24
 596
 597 #define M_SGN           0x1C58
 598 #define M_LEN           0x1C5C
 599 #define M_AR0           0x1C60
 600 #define M_AR1           0x1C64
 601 #define M_AR2           0x1C68
 602 #define M_AR3           0x1C6C
 603 #define M_AR4           0x1C70
 604 #define M_AR5           0x1C74
 605 #define M_AR6           0x1C78
 606
 607 #define M_CXBNDRY       0x1C80
 608 #define M_FXBNDRY       0x1C84
 609 #define M_YDSTLEN       0x1C88
 610 #define M_PITCH         0x1C8C
 611 #define M_YDST          0x1C90
 612 #define M_YDSTORG       0x1C94
 613 #define M_YTOP          0x1C98
 614 #define M_YBOT          0x1C9C
 615
 616 /* mystique only */
 617 #define M_CACHEFLUSH    0x1FFF
 618
 619 #define M_EXEC          0x0100
 620
 621 #define M_DWG_TRAP      0x04
 622 #define M_DWG_BITBLT    0x08
 623 #define M_DWG_ILOAD     0x09
 624
 625 #define M_DWG_LINEAR    0x0080
 626 #define M_DWG_SOLID     0x0800
 627 #define M_DWG_ARZERO    0x1000
 628 #define M_DWG_SGNZERO   0x2000
 629 #define M_DWG_SHIFTZERO 0x4000
 630
 631 #define M_DWG_REPLACE   0x000C0000
 632 #define M_DWG_REPLACE2  (M_DWG_REPLACE | 0x40)
 633 #define M_DWG_XOR       0x00060010
 634
 635 #define M_DWG_BFCOL     0x04000000
 636 #define M_DWG_BMONOWF   0x08000000
 637
 638 #define M_DWG_TRANSC    0x40000000
 639
 640 #define M_FIFOSTATUS    0x1E10
 641 #define M_STATUS        0x1E14
 642 #define M_ICLEAR        0x1E18
 643 #define M_IEN           0x1E1C
 644
 645 #define M_VCOUNT        0x1E20
 646
 647 #define M_RESET         0x1E40
 648 #define M_MEMRDBK       0x1E44
 649
 650 #define M_AGP2PLL       0x1E4C
 651
 652 #define M_OPMODE        0x1E54
 653 #define     M_OPMODE_DMA_GEN_WRITE      0x00
 654 #define     M_OPMODE_DMA_BLIT           0x04
 655 #define     M_OPMODE_DMA_VECTOR_WRITE   0x08
 656 #define     M_OPMODE_DMA_LE             0x0000          /* little endian - no transformation */
 657 #define     M_OPMODE_DMA_BE_8BPP        0x0000
 658 #define     M_OPMODE_DMA_BE_16BPP       0x0100
 659 #define     M_OPMODE_DMA_BE_32BPP       0x0200
 660 #define     M_OPMODE_DIR_LE             0x000000        /* little endian - no transformation */
 661 #define     M_OPMODE_DIR_BE_8BPP        0x000000
 662 #define     M_OPMODE_DIR_BE_16BPP       0x010000
 663 #define     M_OPMODE_DIR_BE_32BPP       0x020000
 664
 665 #define M_ATTR_INDEX    0x1FC0
 666 #define M_ATTR_DATA     0x1FC1
 667
 668 #define M_MISC_REG      0x1FC2
 669 #define M_3C2_RD        0x1FC2
 670
 671 #define M_SEQ_INDEX     0x1FC4
 672 #define M_SEQ_DATA      0x1FC5
 673 #define     M_SEQ1              0x01
 674 #define        M_SEQ1_SCROFF            0x20
 675
 676 #define M_MISC_REG_READ 0x1FCC
 677
 678 #define M_GRAPHICS_INDEX 0x1FCE
 679 #define M_GRAPHICS_DATA 0x1FCF
 680
 681 #define M_CRTC_INDEX    0x1FD4
 682
 683 #define M_ATTR_RESET    0x1FDA
 684 #define M_3DA_WR        0x1FDA
 685 #define M_INSTS1        0x1FDA
 686
 687 #define M_EXTVGA_INDEX  0x1FDE
 688 #define M_EXTVGA_DATA   0x1FDF
 689
 690 /* G200 only */
 691 #define M_SRCORG        0x2CB4
 692 #define M_DSTORG        0x2CB8
 693
 694 #define M_RAMDAC_BASE   0x3C00
 695
 696 /* fortunately, same on TVP3026 and MGA1064 */
 697 #define M_DAC_REG       (M_RAMDAC_BASE+0)
 698 #define M_DAC_VAL       (M_RAMDAC_BASE+1)
 699 #define M_PALETTE_MASK  (M_RAMDAC_BASE+2)
 700
 701 #define M_X_INDEX       0x00
 702 #define M_X_DATAREG     0x0A
 703
 704 #define DAC_XGENIOCTRL          0x2A
 705 #define DAC_XGENIODATA          0x2B
 706
 707 #define M_C2CTL         0x3C10
 708
 709 #define MX_OPTION_BSWAP         0x00000000
 710
 711 #ifdef __LITTLE_ENDIAN
 712 #define M_OPMODE_4BPP   (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
 713 #define M_OPMODE_8BPP   (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
 714 #define M_OPMODE_16BPP  (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
 715 #define M_OPMODE_24BPP  (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
 716 #define M_OPMODE_32BPP  (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
 717 #else
 718 #ifdef __BIG_ENDIAN
 719 #define M_OPMODE_4BPP   (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE       | M_OPMODE_DMA_BLIT)   /* TODO */
 720 #define M_OPMODE_8BPP   (M_OPMODE_DMA_LE | M_OPMODE_DIR_BE_8BPP  | M_OPMODE_DMA_BLIT)
 721 #define M_OPMODE_16BPP  (M_OPMODE_DMA_LE | M_OPMODE_DIR_BE_16BPP | M_OPMODE_DMA_BLIT)
 722 #define M_OPMODE_24BPP  (M_OPMODE_DMA_LE | M_OPMODE_DIR_BE_8BPP  | M_OPMODE_DMA_BLIT)   /* TODO, ?32 */
 723 #define M_OPMODE_32BPP  (M_OPMODE_DMA_LE | M_OPMODE_DIR_BE_32BPP | M_OPMODE_DMA_BLIT)
 724 #else
 725 #error "Byte ordering have to be defined. Cannot continue."
 726 #endif
 727 #endif
 728
 729 #define mga_inb(addr)           mga_readb(ACCESS_FBINFO(mmio.vbase), (addr))
 730 #define mga_inl(addr)           mga_readl(ACCESS_FBINFO(mmio.vbase), (addr))
 731 #define mga_outb(addr,val)      mga_writeb(ACCESS_FBINFO(mmio.vbase), (addr), (val))
 732 #define mga_outw(addr,val)      mga_writew(ACCESS_FBINFO(mmio.vbase), (addr), (val))
 733 #define mga_outl(addr,val)      mga_writel(ACCESS_FBINFO(mmio.vbase), (addr), (val))
 734 #define mga_readr(port,idx)     (mga_outb((port),(idx)), mga_inb((port)+1))
 735 #define mga_setr(addr,port,val) mga_outw(addr, ((val)<<8) | (port))
 736
 737 #define mga_fifo(n)     do {} while ((mga_inl(M_FIFOSTATUS) & 0xFF) < (n))
 738
 739 #define WaitTillIdle()  do {} while (mga_inl(M_STATUS) & 0x10000)
 740
 741 /* code speedup */
 742 #ifdef CONFIG_FB_MATROX_MILLENIUM
 743 #define isInterleave(x)  (x->interleave)
 744 #define isMillenium(x)   (x->millenium)
 745 #define isMilleniumII(x) (x->milleniumII)
 746 #else
 747 #define isInterleave(x)  (0)
 748 #define isMillenium(x)   (0)
 749 #define isMilleniumII(x) (0)
 750 #endif
 751
 752 #define matroxfb_DAC_lock()                   spin_lock(&ACCESS_FBINFO(lock.DAC))
 753 #define matroxfb_DAC_unlock()                 spin_unlock(&ACCESS_FBINFO(lock.DAC))
 754 #define matroxfb_DAC_lock_irqsave(flags)      spin_lock_irqsave(&ACCESS_FBINFO(lock.DAC),flags)
 755 #define matroxfb_DAC_unlock_irqrestore(flags) spin_unlock_irqrestore(&ACCESS_FBINFO(lock.DAC),flags)
 756 extern void matroxfb_DAC_out(CPMINFO int reg, int val);
 757 extern int matroxfb_DAC_in(CPMINFO int reg);
 758 extern void matroxfb_var2my(struct fb_var_screeninfo* fvsi, struct my_timming* mt);
 759 extern int matroxfb_wait_for_sync(WPMINFO u_int32_t crtc);
 760 extern int matroxfb_enable_irq(WPMINFO int reenable);
 761
 762 #ifdef MATROXFB_USE_SPINLOCKS
 763 #define CRITBEGIN  spin_lock_irqsave(&ACCESS_FBINFO(lock.accel), critflags);
 764 #define CRITEND    spin_unlock_irqrestore(&ACCESS_FBINFO(lock.accel), critflags);
 765 #define CRITFLAGS  unsigned long critflags;
 766 #else
 767 #define CRITBEGIN
 768 #define CRITEND
 769 #define CRITFLAGS
 770 #endif
 771
 772 #endif  /* __MATROXFB_H__ */