1 #include <linux/serial.h>
3 #include <asm/portmux.h>
7 #define OFFSET_THR 0x00 /* Transmit Holding register */
8 #define OFFSET_RBR 0x00 /* Receive Buffer register */
9 #define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
10 #define OFFSET_IER 0x04 /* Interrupt Enable Register */
11 #define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
12 #define OFFSET_IIR 0x08 /* Interrupt Identification Register */
13 #define OFFSET_LCR 0x0C /* Line Control Register */
14 #define OFFSET_MCR 0x10 /* Modem Control Register */
15 #define OFFSET_LSR 0x14 /* Line Status Register */
16 #define OFFSET_MSR 0x18 /* Modem Status Register */
17 #define OFFSET_SCR 0x1C /* SCR Scratch Register */
18 #define OFFSET_GCTL 0x24 /* Global Control Register */
20 #define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
21 #define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
22 #define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
23 #define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
24 #define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
25 #define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
26 #define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
28 #define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
29 #define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
30 #define UART_PUT_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER),v)
31 #define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
32 #define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
33 #define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
35 #ifdef CONFIG_BFIN_UART0_CTSRTS
36 # define CONFIG_SERIAL_BFIN_CTSRTS
37 # ifndef CONFIG_UART0_CTS_PIN
38 # define CONFIG_UART0_CTS_PIN -1
40 # ifndef CONFIG_UART0_RTS_PIN
41 # define CONFIG_UART0_RTS_PIN -1
45 struct bfin_serial_port
{
46 struct uart_port port
;
47 unsigned int old_status
;
49 #ifdef CONFIG_SERIAL_BFIN_DMA
52 struct circ_buf rx_dma_buf
;
53 struct timer_list rx_dma_timer
;
55 unsigned int tx_dma_channel
;
56 unsigned int rx_dma_channel
;
57 struct work_struct tx_dma_workqueue
;
60 unsigned int anomaly_threshold
;
63 #ifdef CONFIG_SERIAL_BFIN_CTSRTS
64 struct work_struct cts_workqueue
;
70 /* The hardware clears the LSR bits upon read, so we need to cache
71 * some of the more fun bits in software so they don't get lost
72 * when checking the LSR in other code paths (TX).
74 static inline unsigned int UART_GET_LSR(struct bfin_serial_port
*uart
)
76 unsigned int lsr
= bfin_read16(uart
->port
.membase
+ OFFSET_LSR
);
77 uart
->lsr
|= (lsr
& (BI
|FE
|PE
|OE
));
78 return lsr
| uart
->lsr
;
81 static inline void UART_CLEAR_LSR(struct bfin_serial_port
*uart
)
84 bfin_write16(uart
->port
.membase
+ OFFSET_LSR
, -1);
87 struct bfin_serial_port bfin_serial_ports
[NR_PORTS
];
88 struct bfin_serial_res
{
89 unsigned long uart_base_addr
;
91 #ifdef CONFIG_SERIAL_BFIN_DMA
92 unsigned int uart_tx_dma_channel
;
93 unsigned int uart_rx_dma_channel
;
95 #ifdef CONFIG_SERIAL_BFIN_CTSRTS
101 struct bfin_serial_res bfin_serial_resource
[] = {
105 #ifdef CONFIG_SERIAL_BFIN_DMA
109 #ifdef CONFIG_BFIN_UART0_CTSRTS
110 CONFIG_UART0_CTS_PIN
,
111 CONFIG_UART0_RTS_PIN
,
116 #define DRIVER_NAME "bfin-uart"
118 int nr_ports
= NR_PORTS
;
119 static void bfin_serial_hw_init(struct bfin_serial_port
*uart
)
122 #ifdef CONFIG_SERIAL_BFIN_UART0
123 peripheral_request(P_UART0_TX
, DRIVER_NAME
);
124 peripheral_request(P_UART0_RX
, DRIVER_NAME
);
127 #ifdef CONFIG_SERIAL_BFIN_CTSRTS
128 if (uart
->cts_pin
>= 0) {
129 gpio_request(uart
->cts_pin
, DRIVER_NAME
);
130 gpio_direction_input(uart
->cts_pin
);
132 if (uart
->rts_pin
>= 0) {
133 gpio_request(uart
->rts_pin
, DRIVER_NAME
);
134 gpio_direction_input(uart
->rts_pin
, 0);