1 /************************************************************************
3 * This file is subject to the terms and conditions of the GNU Public
4 * License. See the file "COPYING" in the main directory of this archive
7 * Non-GPL License also available as part of VisualDSP++
8 * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
10 * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
12 * This file under source code control, please send bugs or changes to:
13 * dsptools.support@analog.com
15 ************************************************************************/
17 * File: include/asm-blackfin/mach-bf533/defBF532.h
28 * Bugs: Enter bugs at http://blackfin.uclinux.org/
30 * This program is free software; you can redistribute it and/or modify
31 * it under the terms of the GNU General Public License as published by
32 * the Free Software Foundation; either version 2, or (at your option)
35 * This program is distributed in the hope that it will be useful,
36 * but WITHOUT ANY WARRANTY; without even the implied warranty of
37 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
38 * GNU General Public License for more details.
40 * You should have received a copy of the GNU General Public License
41 * along with this program; see the file COPYING.
42 * If not, write to the Free Software Foundation,
43 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
45 /* SYSTEM & MM REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF532 */
50 /* include all Core registers and bit definitions */
51 #include <asm/mach-common/def_LPBlackfin.h>
53 /*********************************************************************************** */
54 /* System MMR Register Map */
55 /*********************************************************************************** */
56 /* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
58 #define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */
59 #define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */
60 #define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */
61 #define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */
62 #define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */
63 #define CHIPID 0xFFC00014 /* Chip ID Register */
65 /* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
66 #define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */
67 #define SYSCR 0xFFC00104 /* System Configuration registe */
68 #define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
69 #define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */
70 #define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
71 #define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
72 #define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
73 #define SIC_ISR 0xFFC00120 /* Interrupt Status Register */
74 #define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */
76 /* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
77 #define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
78 #define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
79 #define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
81 /* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
82 #define RTC_STAT 0xFFC00300 /* RTC Status Register */
83 #define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
84 #define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
85 #define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
86 #define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
87 #define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */
88 #define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register (alternate macro) */
90 /* UART Controller (0xFFC00400 - 0xFFC004FF) */
91 #define UART_THR 0xFFC00400 /* Transmit Holding register */
92 #define UART_RBR 0xFFC00400 /* Receive Buffer register */
93 #define UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
94 #define UART_IER 0xFFC00404 /* Interrupt Enable Register */
95 #define UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
96 #define UART_IIR 0xFFC00408 /* Interrupt Identification Register */
97 #define UART_LCR 0xFFC0040C /* Line Control Register */
98 #define UART_MCR 0xFFC00410 /* Modem Control Register */
99 #define UART_LSR 0xFFC00414 /* Line Status Register */
101 #define UART_MSR 0xFFC00418 /* Modem Status Register (UNUSED in ADSP-BF532) */
103 #define UART_SCR 0xFFC0041C /* SCR Scratch Register */
104 #define UART_GCTL 0xFFC00424 /* Global Control Register */
106 /* SPI Controller (0xFFC00500 - 0xFFC005FF) */
107 #define SPI0_REGBASE 0xFFC00500
108 #define SPI_CTL 0xFFC00500 /* SPI Control Register */
109 #define SPI_FLG 0xFFC00504 /* SPI Flag register */
110 #define SPI_STAT 0xFFC00508 /* SPI Status register */
111 #define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
112 #define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
113 #define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */
114 #define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
116 /* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */
118 #define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
119 #define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
120 #define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
121 #define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
123 #define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
124 #define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
125 #define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
126 #define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
128 #define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
129 #define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
130 #define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
131 #define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
133 #define TIMER_ENABLE 0xFFC00640 /* Timer Enable Register */
134 #define TIMER_DISABLE 0xFFC00644 /* Timer Disable Register */
135 #define TIMER_STATUS 0xFFC00648 /* Timer Status Register */
137 /* General Purpose IO (0xFFC00700 - 0xFFC007FF) */
139 #define FIO_FLAG_D 0xFFC00700 /* Flag Mask to directly specify state of pins */
140 #define FIO_FLAG_C 0xFFC00704 /* Peripheral Interrupt Flag Register (clear) */
141 #define FIO_FLAG_S 0xFFC00708 /* Peripheral Interrupt Flag Register (set) */
142 #define FIO_FLAG_T 0xFFC0070C /* Flag Mask to directly toggle state of pins */
143 #define FIO_MASKA_D 0xFFC00710 /* Flag Mask Interrupt A Register (set directly) */
144 #define FIO_MASKA_C 0xFFC00714 /* Flag Mask Interrupt A Register (clear) */
145 #define FIO_MASKA_S 0xFFC00718 /* Flag Mask Interrupt A Register (set) */
146 #define FIO_MASKA_T 0xFFC0071C /* Flag Mask Interrupt A Register (toggle) */
147 #define FIO_MASKB_D 0xFFC00720 /* Flag Mask Interrupt B Register (set directly) */
148 #define FIO_MASKB_C 0xFFC00724 /* Flag Mask Interrupt B Register (clear) */
149 #define FIO_MASKB_S 0xFFC00728 /* Flag Mask Interrupt B Register (set) */
150 #define FIO_MASKB_T 0xFFC0072C /* Flag Mask Interrupt B Register (toggle) */
151 #define FIO_DIR 0xFFC00730 /* Peripheral Flag Direction Register */
152 #define FIO_POLAR 0xFFC00734 /* Flag Source Polarity Register */
153 #define FIO_EDGE 0xFFC00738 /* Flag Source Sensitivity Register */
154 #define FIO_BOTH 0xFFC0073C /* Flag Set on BOTH Edges Register */
155 #define FIO_INEN 0xFFC00740 /* Flag Input Enable Register */
157 /* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
158 #define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
159 #define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
160 #define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
161 #define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
162 #define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
163 #define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
164 #define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
165 #define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
166 #define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
167 #define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
168 #define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
169 #define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
170 #define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
171 #define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
172 #define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
173 #define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
174 #define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
175 #define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
176 #define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
177 #define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
178 #define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
179 #define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
181 /* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
182 #define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
183 #define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
184 #define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
185 #define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
186 #define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
187 #define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
188 #define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
189 #define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
190 #define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
191 #define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
192 #define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
193 #define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
194 #define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
195 #define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
196 #define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
197 #define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
198 #define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
199 #define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
200 #define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
201 #define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
202 #define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
203 #define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
205 /* Asynchronous Memory Controller - External Bus Interface Unit */
206 #define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
207 #define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
208 #define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
210 /* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
212 #define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
213 #define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
214 #define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
215 #define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
217 /* DMA Traffic controls */
218 #define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
219 #define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
221 /* Alternate deprecated register names (below) provided for backwards code compatibility */
222 #define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */
223 #define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */
225 /* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
226 #define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
227 #define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
228 #define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
229 #define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
230 #define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
231 #define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
232 #define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
233 #define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
234 #define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
235 #define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
236 #define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
237 #define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
238 #define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
240 #define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
241 #define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
242 #define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
243 #define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
244 #define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
245 #define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
246 #define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
247 #define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
248 #define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
249 #define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
250 #define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
251 #define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
252 #define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
254 #define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
255 #define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
256 #define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
257 #define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
258 #define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
259 #define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
260 #define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
261 #define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
262 #define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
263 #define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
264 #define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
265 #define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
266 #define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
268 #define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
269 #define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
270 #define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
271 #define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
272 #define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
273 #define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
274 #define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
275 #define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
276 #define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
277 #define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
278 #define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
279 #define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
280 #define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
282 #define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
283 #define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
284 #define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
285 #define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
286 #define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
287 #define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
288 #define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
289 #define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
290 #define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
291 #define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
292 #define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
293 #define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
294 #define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
296 #define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
297 #define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
298 #define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
299 #define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
300 #define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
301 #define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
302 #define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
303 #define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
304 #define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
305 #define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
306 #define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
307 #define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
308 #define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
310 #define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
311 #define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
312 #define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
313 #define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
314 #define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
315 #define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
316 #define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
317 #define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
318 #define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
319 #define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
320 #define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
321 #define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
322 #define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
324 #define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
325 #define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
326 #define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
327 #define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
328 #define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
329 #define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
330 #define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
331 #define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
332 #define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
333 #define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
334 #define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
335 #define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
336 #define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
338 #define MDMA_D1_CONFIG 0xFFC00E88 /* MemDMA Stream 1 Destination Configuration Register */
339 #define MDMA_D1_NEXT_DESC_PTR 0xFFC00E80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
340 #define MDMA_D1_START_ADDR 0xFFC00E84 /* MemDMA Stream 1 Destination Start Address Register */
341 #define MDMA_D1_X_COUNT 0xFFC00E90 /* MemDMA Stream 1 Destination X Count Register */
342 #define MDMA_D1_Y_COUNT 0xFFC00E98 /* MemDMA Stream 1 Destination Y Count Register */
343 #define MDMA_D1_X_MODIFY 0xFFC00E94 /* MemDMA Stream 1 Destination X Modify Register */
344 #define MDMA_D1_Y_MODIFY 0xFFC00E9C /* MemDMA Stream 1 Destination Y Modify Register */
345 #define MDMA_D1_CURR_DESC_PTR 0xFFC00EA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
346 #define MDMA_D1_CURR_ADDR 0xFFC00EA4 /* MemDMA Stream 1 Destination Current Address Register */
347 #define MDMA_D1_CURR_X_COUNT 0xFFC00EB0 /* MemDMA Stream 1 Destination Current X Count Register */
348 #define MDMA_D1_CURR_Y_COUNT 0xFFC00EB8 /* MemDMA Stream 1 Destination Current Y Count Register */
349 #define MDMA_D1_IRQ_STATUS 0xFFC00EA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
350 #define MDMA_D1_PERIPHERAL_MAP 0xFFC00EAC /* MemDMA Stream 1 Destination Peripheral Map Register */
352 #define MDMA_S1_CONFIG 0xFFC00EC8 /* MemDMA Stream 1 Source Configuration Register */
353 #define MDMA_S1_NEXT_DESC_PTR 0xFFC00EC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
354 #define MDMA_S1_START_ADDR 0xFFC00EC4 /* MemDMA Stream 1 Source Start Address Register */
355 #define MDMA_S1_X_COUNT 0xFFC00ED0 /* MemDMA Stream 1 Source X Count Register */
356 #define MDMA_S1_Y_COUNT 0xFFC00ED8 /* MemDMA Stream 1 Source Y Count Register */
357 #define MDMA_S1_X_MODIFY 0xFFC00ED4 /* MemDMA Stream 1 Source X Modify Register */
358 #define MDMA_S1_Y_MODIFY 0xFFC00EDC /* MemDMA Stream 1 Source Y Modify Register */
359 #define MDMA_S1_CURR_DESC_PTR 0xFFC00EE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
360 #define MDMA_S1_CURR_ADDR 0xFFC00EE4 /* MemDMA Stream 1 Source Current Address Register */
361 #define MDMA_S1_CURR_X_COUNT 0xFFC00EF0 /* MemDMA Stream 1 Source Current X Count Register */
362 #define MDMA_S1_CURR_Y_COUNT 0xFFC00EF8 /* MemDMA Stream 1 Source Current Y Count Register */
363 #define MDMA_S1_IRQ_STATUS 0xFFC00EE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
364 #define MDMA_S1_PERIPHERAL_MAP 0xFFC00EEC /* MemDMA Stream 1 Source Peripheral Map Register */
366 #define MDMA_D0_CONFIG 0xFFC00E08 /* MemDMA Stream 0 Destination Configuration Register */
367 #define MDMA_D0_NEXT_DESC_PTR 0xFFC00E00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
368 #define MDMA_D0_START_ADDR 0xFFC00E04 /* MemDMA Stream 0 Destination Start Address Register */
369 #define MDMA_D0_X_COUNT 0xFFC00E10 /* MemDMA Stream 0 Destination X Count Register */
370 #define MDMA_D0_Y_COUNT 0xFFC00E18 /* MemDMA Stream 0 Destination Y Count Register */
371 #define MDMA_D0_X_MODIFY 0xFFC00E14 /* MemDMA Stream 0 Destination X Modify Register */
372 #define MDMA_D0_Y_MODIFY 0xFFC00E1C /* MemDMA Stream 0 Destination Y Modify Register */
373 #define MDMA_D0_CURR_DESC_PTR 0xFFC00E20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
374 #define MDMA_D0_CURR_ADDR 0xFFC00E24 /* MemDMA Stream 0 Destination Current Address Register */
375 #define MDMA_D0_CURR_X_COUNT 0xFFC00E30 /* MemDMA Stream 0 Destination Current X Count Register */
376 #define MDMA_D0_CURR_Y_COUNT 0xFFC00E38 /* MemDMA Stream 0 Destination Current Y Count Register */
377 #define MDMA_D0_IRQ_STATUS 0xFFC00E28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
378 #define MDMA_D0_PERIPHERAL_MAP 0xFFC00E2C /* MemDMA Stream 0 Destination Peripheral Map Register */
380 #define MDMA_S0_CONFIG 0xFFC00E48 /* MemDMA Stream 0 Source Configuration Register */
381 #define MDMA_S0_NEXT_DESC_PTR 0xFFC00E40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
382 #define MDMA_S0_START_ADDR 0xFFC00E44 /* MemDMA Stream 0 Source Start Address Register */
383 #define MDMA_S0_X_COUNT 0xFFC00E50 /* MemDMA Stream 0 Source X Count Register */
384 #define MDMA_S0_Y_COUNT 0xFFC00E58 /* MemDMA Stream 0 Source Y Count Register */
385 #define MDMA_S0_X_MODIFY 0xFFC00E54 /* MemDMA Stream 0 Source X Modify Register */
386 #define MDMA_S0_Y_MODIFY 0xFFC00E5C /* MemDMA Stream 0 Source Y Modify Register */
387 #define MDMA_S0_CURR_DESC_PTR 0xFFC00E60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
388 #define MDMA_S0_CURR_ADDR 0xFFC00E64 /* MemDMA Stream 0 Source Current Address Register */
389 #define MDMA_S0_CURR_X_COUNT 0xFFC00E70 /* MemDMA Stream 0 Source Current X Count Register */
390 #define MDMA_S0_CURR_Y_COUNT 0xFFC00E78 /* MemDMA Stream 0 Source Current Y Count Register */
391 #define MDMA_S0_IRQ_STATUS 0xFFC00E68 /* MemDMA Stream 0 Source Interrupt/Status Register */
392 #define MDMA_S0_PERIPHERAL_MAP 0xFFC00E6C /* MemDMA Stream 0 Source Peripheral Map Register */
394 /* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */
396 #define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
397 #define PPI_STATUS 0xFFC01004 /* PPI Status Register */
398 #define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
399 #define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
400 #define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
402 /*********************************************************************************** */
403 /* System MMR Register Bits */
404 /******************************************************************************* */
406 /* ********************* PLL AND RESET MASKS ************************ */
409 #define PLL_CLKIN 0x0000 /* Pass CLKIN to PLL */
410 #define PLL_CLKIN_DIV2 0x0001 /* Pass CLKIN/2 to PLL */
411 #define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
412 #define PLL_OFF 0x0002 /* Shut off PLL clocks */
413 #define STOPCK_OFF 0x0008 /* Core clock off */
414 #define STOPCK 0x0008 /* Core Clock Off */
415 #define PDWN 0x0020 /* Put the PLL in a Deep Sleep state */
416 #if !defined(__ADSPBF538__)
417 /* this file is included in defBF538.h but IN_DELAY/OUT_DELAY are different */
418 # define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */
419 # define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */
421 #define BYPASS 0x0100 /* Bypass the PLL */
422 /* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */
423 #define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
426 #define SSEL 0x000F /* System Select */
427 #define CSEL 0x0030 /* Core Select */
429 #define SCLK_DIV(x) (x) /* SCLK = VCO / x */
431 #define CCLK_DIV1 0x00000000 /* CCLK = VCO / 1 */
432 #define CCLK_DIV2 0x00000010 /* CCLK = VCO / 2 */
433 #define CCLK_DIV4 0x00000020 /* CCLK = VCO / 4 */
434 #define CCLK_DIV8 0x00000030 /* CCLK = VCO / 8 */
436 #define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
439 #define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
440 #define FULL_ON 0x0002 /* Processor In Full On Mode */
441 #define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
442 #define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
445 #define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */
446 #define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
447 #define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
448 #define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
449 #define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
451 #define GAIN 0x000C /* Voltage Level Gain */
452 #define GAIN_5 0x0000 /* GAIN = 5 */
453 #define GAIN_10 0x0004 /* GAIN = 10 */
454 #define GAIN_20 0x0008 /* GAIN = 20 */
455 #define GAIN_50 0x000C /* GAIN = 50 */
457 #define VLEV 0x00F0 /* Internal Voltage Level */
458 #define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
459 #define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
460 #define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
461 #define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
462 #define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
463 #define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
464 #define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
465 #define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
467 #define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
468 #define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */
471 #define CHIPID_VERSION 0xF0000000
472 #define CHIPID_FAMILY 0x0FFFF000
473 #define CHIPID_MANUFACTURE 0x00000FFE
476 #define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
477 #define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
478 #define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
479 #define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
480 #define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
483 #define BMODE 0x0006 /* Boot Mode - Latched During HW Reset From Mode Pins */
484 #define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
486 /* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
490 #define P0_IVG(x) ((x)-7) /* Peripheral #0 assigned IVG #x */
491 #define P1_IVG(x) ((x)-7) << 0x4 /* Peripheral #1 assigned IVG #x */
492 #define P2_IVG(x) ((x)-7) << 0x8 /* Peripheral #2 assigned IVG #x */
493 #define P3_IVG(x) ((x)-7) << 0xC /* Peripheral #3 assigned IVG #x */
494 #define P4_IVG(x) ((x)-7) << 0x10 /* Peripheral #4 assigned IVG #x */
495 #define P5_IVG(x) ((x)-7) << 0x14 /* Peripheral #5 assigned IVG #x */
496 #define P6_IVG(x) ((x)-7) << 0x18 /* Peripheral #6 assigned IVG #x */
497 #define P7_IVG(x) ((x)-7) << 0x1C /* Peripheral #7 assigned IVG #x */
501 #define P8_IVG(x) ((x)-7) /* Peripheral #8 assigned IVG #x */
502 #define P9_IVG(x) ((x)-7) << 0x4 /* Peripheral #9 assigned IVG #x */
503 #define P10_IVG(x) ((x)-7) << 0x8 /* Peripheral #10 assigned IVG #x */
504 #define P11_IVG(x) ((x)-7) << 0xC /* Peripheral #11 assigned IVG #x */
505 #define P12_IVG(x) ((x)-7) << 0x10 /* Peripheral #12 assigned IVG #x */
506 #define P13_IVG(x) ((x)-7) << 0x14 /* Peripheral #13 assigned IVG #x */
507 #define P14_IVG(x) ((x)-7) << 0x18 /* Peripheral #14 assigned IVG #x */
508 #define P15_IVG(x) ((x)-7) << 0x1C /* Peripheral #15 assigned IVG #x */
511 #define P16_IVG(x) ((x)-7) /* Peripheral #16 assigned IVG #x */
512 #define P17_IVG(x) ((x)-7) << 0x4 /* Peripheral #17 assigned IVG #x */
513 #define P18_IVG(x) ((x)-7) << 0x8 /* Peripheral #18 assigned IVG #x */
514 #define P19_IVG(x) ((x)-7) << 0xC /* Peripheral #19 assigned IVG #x */
515 #define P20_IVG(x) ((x)-7) << 0x10 /* Peripheral #20 assigned IVG #x */
516 #define P21_IVG(x) ((x)-7) << 0x14 /* Peripheral #21 assigned IVG #x */
517 #define P22_IVG(x) ((x)-7) << 0x18 /* Peripheral #22 assigned IVG #x */
518 #define P23_IVG(x) ((x)-7) << 0x1C /* Peripheral #23 assigned IVG #x */
520 /* SIC_IMASK Masks */
521 #define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
522 #define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
523 #define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */
524 #define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */
527 #define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
528 #define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
529 #define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */
530 #define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */
532 /* ***************************** UART CONTROLLER MASKS ********************** */
534 /* UART_LCR Register */
542 #define WLS(x) ((x-5) & 0x03)
553 /* UART_MCR Register */
554 #define LOOP_ENA 0x10
555 #define LOOP_ENA_P 0x04
557 /* UART_LSR Register */
574 /* UART_IER Register */
583 /* UART_IIR Register */
584 #define STATUS(x) ((x << 1) & 0x06)
586 #define STATUS_P1 0x02
587 #define STATUS_P0 0x01
589 #define IIR_TX_READY 0x02 /* UART_THR empty */
590 #define IIR_RX_READY 0x04 /* Receive data ready */
591 #define IIR_LINE_CHANGE 0x06 /* Receive line status */
592 #define IIR_STATUS 0x06
594 /* UART_GCTL Register */
609 /* ********** SERIAL PORT MASKS ********************** */
611 /* SPORTx_TCR1 Masks */
612 #define TSPEN 0x0001 /* TX enable */
613 #define ITCLK 0x0002 /* Internal TX Clock Select */
614 #define TDTYPE 0x000C /* TX Data Formatting Select */
615 #define DTYPE_NORM 0x0000 /* Data Format Normal */
616 #define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
617 #define DTYPE_ALAW 0x000C /* Compand Using A-Law */
618 #define TLSBIT 0x0010 /* TX Bit Order */
619 #define ITFS 0x0200 /* Internal TX Frame Sync Select */
620 #define TFSR 0x0400 /* TX Frame Sync Required Select */
621 #define DITFS 0x0800 /* Data Independent TX Frame Sync Select */
622 #define LTFS 0x1000 /* Low TX Frame Sync Select */
623 #define LATFS 0x2000 /* Late TX Frame Sync Select */
624 #define TCKFE 0x4000 /* TX Clock Falling Edge Select */
626 /* SPORTx_TCR2 Masks */
627 #if defined(__ADSPBF531__) || defined(__ADSPBF532__) || \
628 defined(__ADSPBF533__)
629 # define SLEN 0x001F /*TX Word Length */
631 # define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */
633 #define TXSE 0x0100 /*TX Secondary Enable */
634 #define TSFSE 0x0200 /*TX Stereo Frame Sync Enable */
635 #define TRFST 0x0400 /*TX Right-First Data Order */
637 /* SPORTx_RCR1 Masks */
638 #define RSPEN 0x0001 /* RX enable */
639 #define IRCLK 0x0002 /* Internal RX Clock Select */
640 #define RDTYPE 0x000C /* RX Data Formatting Select */
641 #define DTYPE_NORM 0x0000 /* no companding */
642 #define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
643 #define DTYPE_ALAW 0x000C /* Compand Using A-Law */
644 #define RLSBIT 0x0010 /* RX Bit Order */
645 #define IRFS 0x0200 /* Internal RX Frame Sync Select */
646 #define RFSR 0x0400 /* RX Frame Sync Required Select */
647 #define LRFS 0x1000 /* Low RX Frame Sync Select */
648 #define LARFS 0x2000 /* Late RX Frame Sync Select */
649 #define RCKFE 0x4000 /* RX Clock Falling Edge Select */
651 /* SPORTx_RCR2 Masks */
652 /* SLEN defined above */
653 #define RXSE 0x0100 /*RX Secondary Enable */
654 #define RSFSE 0x0200 /*RX Stereo Frame Sync Enable */
655 #define RRFST 0x0400 /*Right-First Data Order */
657 /*SPORTx_STAT Masks */
658 #define RXNE 0x0001 /*RX FIFO Not Empty Status */
659 #define RUVF 0x0002 /*RX Underflow Status */
660 #define ROVF 0x0004 /*RX Overflow Status */
661 #define TXF 0x0008 /*TX FIFO Full Status */
662 #define TUVF 0x0010 /*TX Underflow Status */
663 #define TOVF 0x0020 /*TX Overflow Status */
664 #define TXHRE 0x0040 /*TX Hold Register Empty */
666 /*SPORTx_MCMC1 Masks */
667 #define SP_WSIZE 0x0000F000 /*Multichannel Window Size Field */
668 #define SP_WOFF 0x000003FF /*Multichannel Window Offset Field */
669 /* SPORTx_MCMC1 Macros */
670 #define SET_SP_WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */
671 /* Only use SET_WSIZE Macro With Logic OR While Setting Lower Order Bits */
672 #define SET_SP_WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */
674 /*SPORTx_MCMC2 Masks */
675 #define MCCRM 0x00000003 /*Multichannel Clock Recovery Mode */
676 #define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
677 #define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
678 #define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
679 #define MCDTXPE 0x00000004 /*Multichannel DMA Transmit Packing */
680 #define MCDRXPE 0x00000008 /*Multichannel DMA Receive Packing */
681 #define MCMEN 0x00000010 /*Multichannel Frame Mode Enable */
682 #define FSDR 0x00000080 /*Multichannel Frame Sync to Data Relationship */
683 #define MFD 0x0000F000 /*Multichannel Frame Delay */
684 #define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */
685 #define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */
686 #define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */
687 #define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */
688 #define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */
689 #define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */
690 #define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */
691 #define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */
692 #define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */
693 #define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */
694 #define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */
695 #define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */
696 #define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */
697 #define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */
698 #define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */
699 #define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */
701 /* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */
703 /* PPI_CONTROL Masks */
704 #define PORT_EN 0x00000001 /* PPI Port Enable */
705 #define PORT_DIR 0x00000002 /* PPI Port Direction */
706 #define XFR_TYPE 0x0000000C /* PPI Transfer Type */
707 #define PORT_CFG 0x00000030 /* PPI Port Configuration */
708 #define FLD_SEL 0x00000040 /* PPI Active Field Select */
709 #define PACK_EN 0x00000080 /* PPI Packing Mode */
710 #define DMA32 0x00000100 /* PPI 32-bit DMA Enable */
711 #define SKIP_EN 0x00000200 /* PPI Skip Element Enable */
712 #define SKIP_EO 0x00000400 /* PPI Skip Even/Odd Elements */
713 #define DLENGTH 0x00003800 /* PPI Data Length */
714 #define DLEN_8 0x0000 /* Data Length = 8 Bits */
715 #define DLEN_10 0x0800 /* Data Length = 10 Bits */
716 #define DLEN_11 0x1000 /* Data Length = 11 Bits */
717 #define DLEN_12 0x1800 /* Data Length = 12 Bits */
718 #define DLEN_13 0x2000 /* Data Length = 13 Bits */
719 #define DLEN_14 0x2800 /* Data Length = 14 Bits */
720 #define DLEN_15 0x3000 /* Data Length = 15 Bits */
721 #define DLEN_16 0x3800 /* Data Length = 16 Bits */
722 #define DLEN(x) (((x-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */
723 #define POL 0x0000C000 /* PPI Signal Polarities */
724 #define POLC 0x4000 /* PPI Clock Polarity */
725 #define POLS 0x8000 /* PPI Frame Sync Polarity */
727 /* PPI_STATUS Masks */
728 #define FLD 0x00000400 /* Field Indicator */
729 #define FT_ERR 0x00000800 /* Frame Track Error */
730 #define OVR 0x00001000 /* FIFO Overflow Error */
731 #define UNDR 0x00002000 /* FIFO Underrun Error */
732 #define ERR_DET 0x00004000 /* Error Detected Indicator */
733 #define ERR_NCOR 0x00008000 /* Error Not Corrected Indicator */
735 /* ********** DMA CONTROLLER MASKS *********************8 */
737 /*DMAx_CONFIG, MDMA_yy_CONFIG Masks */
738 #define DMAEN 0x00000001 /* Channel Enable */
739 #define WNR 0x00000002 /* Channel Direction (W/R*) */
740 #define WDSIZE_8 0x00000000 /* Word Size 8 bits */
741 #define WDSIZE_16 0x00000004 /* Word Size 16 bits */
742 #define WDSIZE_32 0x00000008 /* Word Size 32 bits */
743 #define DMA2D 0x00000010 /* 2D/1D* Mode */
744 #define RESTART 0x00000020 /* Restart */
745 #define DI_SEL 0x00000040 /* Data Interrupt Select */
746 #define DI_EN 0x00000080 /* Data Interrupt Enable */
747 #define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
748 #define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
749 #define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
750 #define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
751 #define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
752 #define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
753 #define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
754 #define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
755 #define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
756 #define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
757 #define NDSIZE 0x00000900 /* Next Descriptor Size */
758 #define DMAFLOW 0x00007000 /* Flow Control */
759 #define DMAFLOW_STOP 0x0000 /* Stop Mode */
760 #define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
761 #define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
762 #define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
763 #define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
765 #define DMAEN_P 0 /* Channel Enable */
766 #define WNR_P 1 /* Channel Direction (W/R*) */
767 #define DMA2D_P 4 /* 2D/1D* Mode */
768 #define RESTART_P 5 /* Restart */
769 #define DI_SEL_P 6 /* Data Interrupt Select */
770 #define DI_EN_P 7 /* Data Interrupt Enable */
772 /*DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
774 #define DMA_DONE 0x00000001 /* DMA Done Indicator */
775 #define DMA_ERR 0x00000002 /* DMA Error Indicator */
776 #define DFETCH 0x00000004 /* Descriptor Fetch Indicator */
777 #define DMA_RUN 0x00000008 /* DMA Running Indicator */
779 #define DMA_DONE_P 0 /* DMA Done Indicator */
780 #define DMA_ERR_P 1 /* DMA Error Indicator */
781 #define DFETCH_P 2 /* Descriptor Fetch Indicator */
782 #define DMA_RUN_P 3 /* DMA Running Indicator */
784 /*DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
786 #define CTYPE 0x00000040 /* DMA Channel Type Indicator */
787 #define CTYPE_P 6 /* DMA Channel Type Indicator BIT POSITION */
788 #define PCAP8 0x00000080 /* DMA 8-bit Operation Indicator */
789 #define PCAP16 0x00000100 /* DMA 16-bit Operation Indicator */
790 #define PCAP32 0x00000200 /* DMA 32-bit Operation Indicator */
791 #define PCAPWR 0x00000400 /* DMA Write Operation Indicator */
792 #define PCAPRD 0x00000800 /* DMA Read Operation Indicator */
793 #define PMAP 0x00007000 /* DMA Peripheral Map Field */
795 #define PMAP_PPI 0x0000 /* PMAP PPI Port DMA */
796 #define PMAP_SPORT0RX 0x1000 /* PMAP SPORT0 Receive DMA */
797 #define PMAP_SPORT0TX 0x2000 /* PMAP SPORT0 Transmit DMA */
798 #define PMAP_SPORT1RX 0x3000 /* PMAP SPORT1 Receive DMA */
799 #define PMAP_SPORT1TX 0x4000 /* PMAP SPORT1 Transmit DMA */
800 #define PMAP_SPI 0x5000 /* PMAP SPI DMA */
801 #define PMAP_UARTRX 0x6000 /* PMAP UART Receive DMA */
802 #define PMAP_UARTTX 0x7000 /* PMAP UART Transmit DMA */
804 /* ************* GENERAL PURPOSE TIMER MASKS ******************** */
806 /* PWM Timer bit definitions */
808 /* TIMER_ENABLE Register */
809 #define TIMEN0 0x0001
810 #define TIMEN1 0x0002
811 #define TIMEN2 0x0004
813 #define TIMEN0_P 0x00
814 #define TIMEN1_P 0x01
815 #define TIMEN2_P 0x02
817 /* TIMER_DISABLE Register */
818 #define TIMDIS0 0x0001
819 #define TIMDIS1 0x0002
820 #define TIMDIS2 0x0004
822 #define TIMDIS0_P 0x00
823 #define TIMDIS1_P 0x01
824 #define TIMDIS2_P 0x02
826 /* TIMER_STATUS Register */
827 #define TIMIL0 0x0001
828 #define TIMIL1 0x0002
829 #define TIMIL2 0x0004
830 #define TOVF_ERR0 0x0010 /* Timer 0 Counter Overflow */
831 #define TOVF_ERR1 0x0020 /* Timer 1 Counter Overflow */
832 #define TOVF_ERR2 0x0040 /* Timer 2 Counter Overflow */
837 #define TIMIL0_P 0x00
838 #define TIMIL1_P 0x01
839 #define TIMIL2_P 0x02
840 #define TOVF_ERR0_P 0x04
841 #define TOVF_ERR1_P 0x05
842 #define TOVF_ERR2_P 0x06
847 /* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
848 #define TOVL_ERR0 TOVF_ERR0
849 #define TOVL_ERR1 TOVF_ERR1
850 #define TOVL_ERR2 TOVF_ERR2
851 #define TOVL_ERR0_P TOVF_ERR0_P
852 #define TOVL_ERR1_P TOVF_ERR1_P
853 #define TOVL_ERR2_P TOVF_ERR2_P
855 /* TIMERx_CONFIG Registers */
856 #define PWM_OUT 0x0001
857 #define WDTH_CAP 0x0002
858 #define EXT_CLK 0x0003
859 #define PULSE_HI 0x0004
860 #define PERIOD_CNT 0x0008
861 #define IRQ_ENA 0x0010
862 #define TIN_SEL 0x0020
863 #define OUT_DIS 0x0040
864 #define CLK_SEL 0x0080
865 #define TOGGLE_HI 0x0100
866 #define EMU_RUN 0x0200
867 #define ERR_TYP(x) ((x & 0x03) << 14)
869 #define TMODE_P0 0x00
870 #define TMODE_P1 0x01
871 #define PULSE_HI_P 0x02
872 #define PERIOD_CNT_P 0x03
873 #define IRQ_ENA_P 0x04
874 #define TIN_SEL_P 0x05
875 #define OUT_DIS_P 0x06
876 #define CLK_SEL_P 0x07
877 #define TOGGLE_HI_P 0x08
878 #define EMU_RUN_P 0x09
879 #define ERR_TYP_P0 0x0E
880 #define ERR_TYP_P1 0x0F
882 /*/ ****************** PROGRAMMABLE FLAG MASKS ********************* */
884 /* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */
902 /* General Purpose IO (0xFFC00700 - 0xFFC007FF) BIT POSITIONS */
920 /* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS **************** */
923 #define TIMOD 0x00000003 /* Transfer initiation mode and interrupt generation */
924 #define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */
925 #define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */
926 #define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */
927 #define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */
928 #define SZ 0x00000004 /* Send Zero (=0) or last (=1) word when TDBR empty. */
929 #define GM 0x00000008 /* When RDBR full, get more (=1) data or discard (=0) incoming Data */
930 #define PSSE 0x00000010 /* Enable (=1) Slave-Select input for Master. */
931 #define EMISO 0x00000020 /* Enable (=1) MISO pin as an output. */
932 #define SIZE 0x00000100 /* Word length (0 => 8 bits, 1 => 16 bits) */
933 #define LSBF 0x00000200 /* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */
934 #define CPHA 0x00000400 /* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */
935 #define CPOL 0x00000800 /* Clock polarity (0 => active-high, 1 => active-low) */
936 #define MSTR 0x00001000 /* Configures SPI as master (=1) or slave (=0) */
937 #define WOM 0x00002000 /* Open drain (=1) data output enable (for MOSI and MISO) */
938 #define SPE 0x00004000 /* SPI module enable (=1), disable (=0) */
941 #define FLS1 0x00000002 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
942 #define FLS2 0x00000004 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
943 #define FLS3 0x00000008 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
944 #define FLS4 0x00000010 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
945 #define FLS5 0x00000020 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
946 #define FLS6 0x00000040 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
947 #define FLS7 0x00000080 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
948 #define FLG1 0x00000200 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
949 #define FLG2 0x00000400 /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
950 #define FLG3 0x00000800 /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
951 #define FLG4 0x00001000 /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
952 #define FLG5 0x00002000 /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
953 #define FLG6 0x00004000 /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
954 #define FLG7 0x00008000 /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
956 /* SPI_FLG Bit Positions */
957 #define FLS1_P 0x00000001 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
958 #define FLS2_P 0x00000002 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
959 #define FLS3_P 0x00000003 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
960 #define FLS4_P 0x00000004 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
961 #define FLS5_P 0x00000005 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
962 #define FLS6_P 0x00000006 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
963 #define FLS7_P 0x00000007 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
964 #define FLG1_P 0x00000009 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
965 #define FLG2_P 0x0000000A /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
966 #define FLG3_P 0x0000000B /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
967 #define FLG4_P 0x0000000C /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
968 #define FLG5_P 0x0000000D /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
969 #define FLG6_P 0x0000000E /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
970 #define FLG7_P 0x0000000F /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
973 #define SPIF 0x00000001 /* Set (=1) when SPI single-word transfer complete */
974 #define MODF 0x00000002 /* Set (=1) in a master device when some other device tries to become master */
975 #define TXE 0x00000004 /* Set (=1) when transmission occurs with no new data in SPI_TDBR */
976 #define TXS 0x00000008 /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */
977 #define RBSY 0x00000010 /* Set (=1) when data is received with RDBR full */
978 #define RXS 0x00000020 /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full) */
979 #define TXCOL 0x00000040 /* When set (=1), corrupt data may have been transmitted */
982 #define FLG1E 0xFDFF /* Activates SPI_FLOUT1 */
983 #define FLG2E 0xFBFF /* Activates SPI_FLOUT2 */
984 #define FLG3E 0xF7FF /* Activates SPI_FLOUT3 */
985 #define FLG4E 0xEFFF /* Activates SPI_FLOUT4 */
986 #define FLG5E 0xDFFF /* Activates SPI_FLOUT5 */
987 #define FLG6E 0xBFFF /* Activates SPI_FLOUT6 */
988 #define FLG7E 0x7FFF /* Activates SPI_FLOUT7 */
990 /* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */
993 #define AMCKEN 0x00000001 /* Enable CLKOUT */
994 #define AMBEN_NONE 0x00000000 /* All Banks Disabled */
995 #define AMBEN_B0 0x00000002 /* Enable Asynchronous Memory Bank 0 only */
996 #define AMBEN_B0_B1 0x00000004 /* Enable Asynchronous Memory Banks 0 & 1 only */
997 #define AMBEN_B0_B1_B2 0x00000006 /* Enable Asynchronous Memory Banks 0, 1, and 2 */
998 #define AMBEN_ALL 0x00000008 /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */
1000 /* AMGCTL Bit Positions */
1001 #define AMCKEN_P 0x00000000 /* Enable CLKOUT */
1002 #define AMBEN_P0 0x00000001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */
1003 #define AMBEN_P1 0x00000002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */
1004 #define AMBEN_P2 0x00000003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */
1007 #define B0RDYEN 0x00000001 /* Bank 0 RDY Enable, 0=disable, 1=enable */
1008 #define B0RDYPOL 0x00000002 /* Bank 0 RDY Active high, 0=active low, 1=active high */
1009 #define B0TT_1 0x00000004 /* Bank 0 Transition Time from Read to Write = 1 cycle */
1010 #define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */
1011 #define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */
1012 #define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */
1013 #define B0ST_1 0x00000010 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */
1014 #define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */
1015 #define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */
1016 #define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */
1017 #define B0HT_1 0x00000040 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */
1018 #define B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */
1019 #define B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */
1020 #define B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */
1021 #define B0RAT_1 0x00000100 /* Bank 0 Read Access Time = 1 cycle */
1022 #define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */
1023 #define B0RAT_3 0x00000300 /* Bank 0 Read Access Time = 3 cycles */
1024 #define B0RAT_4 0x00000400 /* Bank 0 Read Access Time = 4 cycles */
1025 #define B0RAT_5 0x00000500 /* Bank 0 Read Access Time = 5 cycles */
1026 #define B0RAT_6 0x00000600 /* Bank 0 Read Access Time = 6 cycles */
1027 #define B0RAT_7 0x00000700 /* Bank 0 Read Access Time = 7 cycles */
1028 #define B0RAT_8 0x00000800 /* Bank 0 Read Access Time = 8 cycles */
1029 #define B0RAT_9 0x00000900 /* Bank 0 Read Access Time = 9 cycles */
1030 #define B0RAT_10 0x00000A00 /* Bank 0 Read Access Time = 10 cycles */
1031 #define B0RAT_11 0x00000B00 /* Bank 0 Read Access Time = 11 cycles */
1032 #define B0RAT_12 0x00000C00 /* Bank 0 Read Access Time = 12 cycles */
1033 #define B0RAT_13 0x00000D00 /* Bank 0 Read Access Time = 13 cycles */
1034 #define B0RAT_14 0x00000E00 /* Bank 0 Read Access Time = 14 cycles */
1035 #define B0RAT_15 0x00000F00 /* Bank 0 Read Access Time = 15 cycles */
1036 #define B0WAT_1 0x00001000 /* Bank 0 Write Access Time = 1 cycle */
1037 #define B0WAT_2 0x00002000 /* Bank 0 Write Access Time = 2 cycles */
1038 #define B0WAT_3 0x00003000 /* Bank 0 Write Access Time = 3 cycles */
1039 #define B0WAT_4 0x00004000 /* Bank 0 Write Access Time = 4 cycles */
1040 #define B0WAT_5 0x00005000 /* Bank 0 Write Access Time = 5 cycles */
1041 #define B0WAT_6 0x00006000 /* Bank 0 Write Access Time = 6 cycles */
1042 #define B0WAT_7 0x00007000 /* Bank 0 Write Access Time = 7 cycles */
1043 #define B0WAT_8 0x00008000 /* Bank 0 Write Access Time = 8 cycles */
1044 #define B0WAT_9 0x00009000 /* Bank 0 Write Access Time = 9 cycles */
1045 #define B0WAT_10 0x0000A000 /* Bank 0 Write Access Time = 10 cycles */
1046 #define B0WAT_11 0x0000B000 /* Bank 0 Write Access Time = 11 cycles */
1047 #define B0WAT_12 0x0000C000 /* Bank 0 Write Access Time = 12 cycles */
1048 #define B0WAT_13 0x0000D000 /* Bank 0 Write Access Time = 13 cycles */
1049 #define B0WAT_14 0x0000E000 /* Bank 0 Write Access Time = 14 cycles */
1050 #define B0WAT_15 0x0000F000 /* Bank 0 Write Access Time = 15 cycles */
1051 #define B1RDYEN 0x00010000 /* Bank 1 RDY enable, 0=disable, 1=enable */
1052 #define B1RDYPOL 0x00020000 /* Bank 1 RDY Active high, 0=active low, 1=active high */
1053 #define B1TT_1 0x00040000 /* Bank 1 Transition Time from Read to Write = 1 cycle */
1054 #define B1TT_2 0x00080000 /* Bank 1 Transition Time from Read to Write = 2 cycles */
1055 #define B1TT_3 0x000C0000 /* Bank 1 Transition Time from Read to Write = 3 cycles */
1056 #define B1TT_4 0x00000000 /* Bank 1 Transition Time from Read to Write = 4 cycles */
1057 #define B1ST_1 0x00100000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
1058 #define B1ST_2 0x00200000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
1059 #define B1ST_3 0x00300000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
1060 #define B1ST_4 0x00000000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
1061 #define B1HT_1 0x00400000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
1062 #define B1HT_2 0x00800000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
1063 #define B1HT_3 0x00C00000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
1064 #define B1HT_0 0x00000000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
1065 #define B1RAT_1 0x01000000 /* Bank 1 Read Access Time = 1 cycle */
1066 #define B1RAT_2 0x02000000 /* Bank 1 Read Access Time = 2 cycles */
1067 #define B1RAT_3 0x03000000 /* Bank 1 Read Access Time = 3 cycles */
1068 #define B1RAT_4 0x04000000 /* Bank 1 Read Access Time = 4 cycles */
1069 #define B1RAT_5 0x05000000 /* Bank 1 Read Access Time = 5 cycles */
1070 #define B1RAT_6 0x06000000 /* Bank 1 Read Access Time = 6 cycles */
1071 #define B1RAT_7 0x07000000 /* Bank 1 Read Access Time = 7 cycles */
1072 #define B1RAT_8 0x08000000 /* Bank 1 Read Access Time = 8 cycles */
1073 #define B1RAT_9 0x09000000 /* Bank 1 Read Access Time = 9 cycles */
1074 #define B1RAT_10 0x0A000000 /* Bank 1 Read Access Time = 10 cycles */
1075 #define B1RAT_11 0x0B000000 /* Bank 1 Read Access Time = 11 cycles */
1076 #define B1RAT_12 0x0C000000 /* Bank 1 Read Access Time = 12 cycles */
1077 #define B1RAT_13 0x0D000000 /* Bank 1 Read Access Time = 13 cycles */
1078 #define B1RAT_14 0x0E000000 /* Bank 1 Read Access Time = 14 cycles */
1079 #define B1RAT_15 0x0F000000 /* Bank 1 Read Access Time = 15 cycles */
1080 #define B1WAT_1 0x10000000 /* Bank 1 Write Access Time = 1 cycle */
1081 #define B1WAT_2 0x20000000 /* Bank 1 Write Access Time = 2 cycles */
1082 #define B1WAT_3 0x30000000 /* Bank 1 Write Access Time = 3 cycles */
1083 #define B1WAT_4 0x40000000 /* Bank 1 Write Access Time = 4 cycles */
1084 #define B1WAT_5 0x50000000 /* Bank 1 Write Access Time = 5 cycles */
1085 #define B1WAT_6 0x60000000 /* Bank 1 Write Access Time = 6 cycles */
1086 #define B1WAT_7 0x70000000 /* Bank 1 Write Access Time = 7 cycles */
1087 #define B1WAT_8 0x80000000 /* Bank 1 Write Access Time = 8 cycles */
1088 #define B1WAT_9 0x90000000 /* Bank 1 Write Access Time = 9 cycles */
1089 #define B1WAT_10 0xA0000000 /* Bank 1 Write Access Time = 10 cycles */
1090 #define B1WAT_11 0xB0000000 /* Bank 1 Write Access Time = 11 cycles */
1091 #define B1WAT_12 0xC0000000 /* Bank 1 Write Access Time = 12 cycles */
1092 #define B1WAT_13 0xD0000000 /* Bank 1 Write Access Time = 13 cycles */
1093 #define B1WAT_14 0xE0000000 /* Bank 1 Write Access Time = 14 cycles */
1094 #define B1WAT_15 0xF0000000 /* Bank 1 Write Access Time = 15 cycles */
1097 #define B2RDYEN 0x00000001 /* Bank 2 RDY Enable, 0=disable, 1=enable */
1098 #define B2RDYPOL 0x00000002 /* Bank 2 RDY Active high, 0=active low, 1=active high */
1099 #define B2TT_1 0x00000004 /* Bank 2 Transition Time from Read to Write = 1 cycle */
1100 #define B2TT_2 0x00000008 /* Bank 2 Transition Time from Read to Write = 2 cycles */
1101 #define B2TT_3 0x0000000C /* Bank 2 Transition Time from Read to Write = 3 cycles */
1102 #define B2TT_4 0x00000000 /* Bank 2 Transition Time from Read to Write = 4 cycles */
1103 #define B2ST_1 0x00000010 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
1104 #define B2ST_2 0x00000020 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
1105 #define B2ST_3 0x00000030 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
1106 #define B2ST_4 0x00000000 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
1107 #define B2HT_1 0x00000040 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
1108 #define B2HT_2 0x00000080 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
1109 #define B2HT_3 0x000000C0 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
1110 #define B2HT_0 0x00000000 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
1111 #define B2RAT_1 0x00000100 /* Bank 2 Read Access Time = 1 cycle */
1112 #define B2RAT_2 0x00000200 /* Bank 2 Read Access Time = 2 cycles */
1113 #define B2RAT_3 0x00000300 /* Bank 2 Read Access Time = 3 cycles */
1114 #define B2RAT_4 0x00000400 /* Bank 2 Read Access Time = 4 cycles */
1115 #define B2RAT_5 0x00000500 /* Bank 2 Read Access Time = 5 cycles */
1116 #define B2RAT_6 0x00000600 /* Bank 2 Read Access Time = 6 cycles */
1117 #define B2RAT_7 0x00000700 /* Bank 2 Read Access Time = 7 cycles */
1118 #define B2RAT_8 0x00000800 /* Bank 2 Read Access Time = 8 cycles */
1119 #define B2RAT_9 0x00000900 /* Bank 2 Read Access Time = 9 cycles */
1120 #define B2RAT_10 0x00000A00 /* Bank 2 Read Access Time = 10 cycles */
1121 #define B2RAT_11 0x00000B00 /* Bank 2 Read Access Time = 11 cycles */
1122 #define B2RAT_12 0x00000C00 /* Bank 2 Read Access Time = 12 cycles */
1123 #define B2RAT_13 0x00000D00 /* Bank 2 Read Access Time = 13 cycles */
1124 #define B2RAT_14 0x00000E00 /* Bank 2 Read Access Time = 14 cycles */
1125 #define B2RAT_15 0x00000F00 /* Bank 2 Read Access Time = 15 cycles */
1126 #define B2WAT_1 0x00001000 /* Bank 2 Write Access Time = 1 cycle */
1127 #define B2WAT_2 0x00002000 /* Bank 2 Write Access Time = 2 cycles */
1128 #define B2WAT_3 0x00003000 /* Bank 2 Write Access Time = 3 cycles */
1129 #define B2WAT_4 0x00004000 /* Bank 2 Write Access Time = 4 cycles */
1130 #define B2WAT_5 0x00005000 /* Bank 2 Write Access Time = 5 cycles */
1131 #define B2WAT_6 0x00006000 /* Bank 2 Write Access Time = 6 cycles */
1132 #define B2WAT_7 0x00007000 /* Bank 2 Write Access Time = 7 cycles */
1133 #define B2WAT_8 0x00008000 /* Bank 2 Write Access Time = 8 cycles */
1134 #define B2WAT_9 0x00009000 /* Bank 2 Write Access Time = 9 cycles */
1135 #define B2WAT_10 0x0000A000 /* Bank 2 Write Access Time = 10 cycles */
1136 #define B2WAT_11 0x0000B000 /* Bank 2 Write Access Time = 11 cycles */
1137 #define B2WAT_12 0x0000C000 /* Bank 2 Write Access Time = 12 cycles */
1138 #define B2WAT_13 0x0000D000 /* Bank 2 Write Access Time = 13 cycles */
1139 #define B2WAT_14 0x0000E000 /* Bank 2 Write Access Time = 14 cycles */
1140 #define B2WAT_15 0x0000F000 /* Bank 2 Write Access Time = 15 cycles */
1141 #define B3RDYEN 0x00010000 /* Bank 3 RDY enable, 0=disable, 1=enable */
1142 #define B3RDYPOL 0x00020000 /* Bank 3 RDY Active high, 0=active low, 1=active high */
1143 #define B3TT_1 0x00040000 /* Bank 3 Transition Time from Read to Write = 1 cycle */
1144 #define B3TT_2 0x00080000 /* Bank 3 Transition Time from Read to Write = 2 cycles */
1145 #define B3TT_3 0x000C0000 /* Bank 3 Transition Time from Read to Write = 3 cycles */
1146 #define B3TT_4 0x00000000 /* Bank 3 Transition Time from Read to Write = 4 cycles */
1147 #define B3ST_1 0x00100000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
1148 #define B3ST_2 0x00200000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
1149 #define B3ST_3 0x00300000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
1150 #define B3ST_4 0x00000000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
1151 #define B3HT_1 0x00400000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
1152 #define B3HT_2 0x00800000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
1153 #define B3HT_3 0x00C00000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
1154 #define B3HT_0 0x00000000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
1155 #define B3RAT_1 0x01000000 /* Bank 3 Read Access Time = 1 cycle */
1156 #define B3RAT_2 0x02000000 /* Bank 3 Read Access Time = 2 cycles */
1157 #define B3RAT_3 0x03000000 /* Bank 3 Read Access Time = 3 cycles */
1158 #define B3RAT_4 0x04000000 /* Bank 3 Read Access Time = 4 cycles */
1159 #define B3RAT_5 0x05000000 /* Bank 3 Read Access Time = 5 cycles */
1160 #define B3RAT_6 0x06000000 /* Bank 3 Read Access Time = 6 cycles */
1161 #define B3RAT_7 0x07000000 /* Bank 3 Read Access Time = 7 cycles */
1162 #define B3RAT_8 0x08000000 /* Bank 3 Read Access Time = 8 cycles */
1163 #define B3RAT_9 0x09000000 /* Bank 3 Read Access Time = 9 cycles */
1164 #define B3RAT_10 0x0A000000 /* Bank 3 Read Access Time = 10 cycles */
1165 #define B3RAT_11 0x0B000000 /* Bank 3 Read Access Time = 11 cycles */
1166 #define B3RAT_12 0x0C000000 /* Bank 3 Read Access Time = 12 cycles */
1167 #define B3RAT_13 0x0D000000 /* Bank 3 Read Access Time = 13 cycles */
1168 #define B3RAT_14 0x0E000000 /* Bank 3 Read Access Time = 14 cycles */
1169 #define B3RAT_15 0x0F000000 /* Bank 3 Read Access Time = 15 cycles */
1170 #define B3WAT_1 0x10000000 /* Bank 3 Write Access Time = 1 cycle */
1171 #define B3WAT_2 0x20000000 /* Bank 3 Write Access Time = 2 cycles */
1172 #define B3WAT_3 0x30000000 /* Bank 3 Write Access Time = 3 cycles */
1173 #define B3WAT_4 0x40000000 /* Bank 3 Write Access Time = 4 cycles */
1174 #define B3WAT_5 0x50000000 /* Bank 3 Write Access Time = 5 cycles */
1175 #define B3WAT_6 0x60000000 /* Bank 3 Write Access Time = 6 cycles */
1176 #define B3WAT_7 0x70000000 /* Bank 3 Write Access Time = 7 cycles */
1177 #define B3WAT_8 0x80000000 /* Bank 3 Write Access Time = 8 cycles */
1178 #define B3WAT_9 0x90000000 /* Bank 3 Write Access Time = 9 cycles */
1179 #define B3WAT_10 0xA0000000 /* Bank 3 Write Access Time = 10 cycles */
1180 #define B3WAT_11 0xB0000000 /* Bank 3 Write Access Time = 11 cycles */
1181 #define B3WAT_12 0xC0000000 /* Bank 3 Write Access Time = 12 cycles */
1182 #define B3WAT_13 0xD0000000 /* Bank 3 Write Access Time = 13 cycles */
1183 #define B3WAT_14 0xE0000000 /* Bank 3 Write Access Time = 14 cycles */
1184 #define B3WAT_15 0xF0000000 /* Bank 3 Write Access Time = 15 cycles */
1186 /* ********************** SDRAM CONTROLLER MASKS *************************** */
1189 #define SCTLE 0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */
1190 #define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */
1191 #define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */
1192 #define PFE 0x00000010 /* Enable SDRAM prefetch */
1193 #define PFP 0x00000020 /* Prefetch has priority over AMC requests */
1194 #define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
1195 #define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
1196 #define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
1197 #define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
1198 #define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
1199 #define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
1200 #define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
1201 #define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
1202 #define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
1203 #define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
1204 #define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
1205 #define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
1206 #define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
1207 #define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
1208 #define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
1209 #define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
1210 #define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
1211 #define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
1212 #define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
1213 #define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
1214 #define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
1215 #define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
1216 #define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
1217 #define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
1218 #define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
1219 #define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
1220 #define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
1221 #define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
1222 #define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
1223 #define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
1224 #define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
1225 #define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
1226 #define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
1227 #define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
1228 #define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
1229 #define PUPSD 0x00200000 /*Power-up start delay */
1230 #define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */
1231 #define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */
1232 #define SRFS 0x01000000 /* Start SDRAM self-refresh mode */
1233 #define EBUFE 0x02000000 /* Enable external buffering timing */
1234 #define FBBRW 0x04000000 /* Fast back-to-back read write enable */
1235 #define EMREN 0x10000000 /* Extended mode register enable */
1236 #define TCSR 0x20000000 /* Temp compensated self refresh value 85 deg C */
1237 #define CDDBG 0x40000000 /* Tristate SDRAM controls during bus grant */
1239 /* EBIU_SDBCTL Masks */
1240 #define EBE 0x00000001 /* Enable SDRAM external bank */
1241 #define EBSZ_16 0x00000000 /* SDRAM external bank size = 16MB */
1242 #define EBSZ_32 0x00000002 /* SDRAM external bank size = 32MB */
1243 #define EBSZ_64 0x00000004 /* SDRAM external bank size = 64MB */
1244 #define EBSZ_128 0x00000006 /* SDRAM external bank size = 128MB */
1245 #define EBCAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */
1246 #define EBCAW_9 0x00000010 /* SDRAM external bank column address width = 9 bits */
1247 #define EBCAW_10 0x00000020 /* SDRAM external bank column address width = 9 bits */
1248 #define EBCAW_11 0x00000030 /* SDRAM external bank column address width = 9 bits */
1250 /* EBIU_SDSTAT Masks */
1251 #define SDCI 0x00000001 /* SDRAM controller is idle */
1252 #define SDSRA 0x00000002 /* SDRAM SDRAM self refresh is active */
1253 #define SDPUA 0x00000004 /* SDRAM power up active */
1254 #define SDRS 0x00000008 /* SDRAM is in reset state */
1255 #define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */
1256 #define BGSTAT 0x00000020 /* Bus granted */
1259 #endif /* _DEF_BF532_H */
